From nobody Thu Jun 25 05:47:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AF8EC433FE for ; Tue, 22 Feb 2022 16:33:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234286AbiBVQeU (ORCPT ); Tue, 22 Feb 2022 11:34:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234142AbiBVQdW (ORCPT ); Tue, 22 Feb 2022 11:33:22 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31DCE167F95; Tue, 22 Feb 2022 08:32:51 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 21MGWc3Q113673; Tue, 22 Feb 2022 10:32:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1645547558; bh=M6ARIgneEQH1F/+LZH6mauYppNZEm7uhcajVIp+V8MA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MuMuUEgHEUxlZg62tSMDOKdNubVAJmhh4sFwzgbQdkTx5+2WcibDYZ61Lq2oaP+zR tDgeCF5/nN7ZLQ+M5JlHjDZKVCCMDXOc2ITw3XxdYPxzuHhM2KZkWpQg5xYK2OPXRs B/NjGvJBGnIbkWBBRSafZBv79Ies37Ou0TiGY2u0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 21MGWclj092844 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Feb 2022 10:32:38 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 22 Feb 2022 10:32:38 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 22 Feb 2022 10:32:38 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 21MGWaW3130385; Tue, 22 Feb 2022 10:32:37 -0600 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY Date: Tue, 22 Feb 2022 22:02:29 +0530 Message-ID: <20220222163230.1566-2-r-ravikumar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220222163230.1566-1-r-ravikumar@ti.com> References: <20220222163230.1566-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tomi Valkeinen Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. A slight irregularity in the bindings is the DPTX PHY register block, which is in the MHDP IP, but is needed and mapped by the PHY. Signed-off-by: Tomi Valkeinen Signed-off-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 102 ++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 599861259a30..9e2b212100bb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -786,6 +786,82 @@ #size-cells =3D <2>; }; =20 + serdes_wiz4: wiz@5050000 { + compatible =3D "ti,j721e-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks =3D <&k3_clks 297 9>; + assigned-clock-parents =3D <&k3_clks 297 10>; + assigned-clock-rates =3D <19200000>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + ranges =3D <0x5050000 0x0 0x5050000 0x10000>, + <0xa030a00 0x0 0xa030a00 0x40>; + + wiz4_pll0_refclk: pll0-refclk { + clocks =3D <&k3_clks 297 9>, <&cmn_refclk>; + clock-output-names =3D "wiz4_pll0_refclk"; + #clock-cells =3D <0>; + assigned-clocks =3D <&wiz4_pll0_refclk>; + assigned-clock-parents =3D <&k3_clks 297 9>; + }; + + wiz4_pll1_refclk: pll1-refclk { + clocks =3D <&k3_clks 297 9>, <&cmn_refclk>; + clock-output-names =3D "wiz4_pll1_refclk"; + #clock-cells =3D <0>; + assigned-clocks =3D <&wiz4_pll1_refclk>; + assigned-clock-parents =3D <&k3_clks 297 9>; + }; + + wiz4_refclk_dig: refclk-dig { + clocks =3D <&k3_clks 297 9>, <&cmn_refclk>; + clock-output-names =3D "wiz4_refclk_dig"; + #clock-cells =3D <0>; + assigned-clocks =3D <&wiz4_refclk_dig>; + assigned-clock-parents =3D <&k3_clks 297 9>; + }; + + wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks =3D <&wiz4_refclk_dig>; + #clock-cells =3D <0>; + }; + + wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div { + clocks =3D <&wiz4_pll1_refclk>; + #clock-cells =3D <0>; + }; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x5050000 0x10000>, + <0xa030a00 0x40>; /* DPTX PHY */ + reg-names =3D "torrent_phy", "dptx_phy"; + + resets =3D <&serdes_wiz4 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&wiz4_pll0_refclk>; + clock-names =3D "refclk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + torrent_phy_dp: phy@0 { + reg =3D <0>; + resets =3D <&serdes_wiz4 1>; + cdns,phy-type =3D ; + cdns,num-lanes =3D <4>; + cdns,max-bit-rate =3D <5400>; + #phy-cells =3D <0>; + }; + }; + }; + main_uart0: serial@2800000 { compatible =3D "ti,j721e-uart", "ti,am654-uart"; reg =3D <0x00 0x02800000 0x00 0x100>; @@ -1264,6 +1340,32 @@ }; }; =20 + mhdp: dp-bridge@a000000 { + compatible =3D "ti,j721e-mhdp8546"; + /* + * Note: we do not map DPTX PHY area, as that is handled by + * the PHY driver. + */ + reg =3D <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ + <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + reg-names =3D "mhdptx", "j721e-intg"; + + clocks =3D <&k3_clks 151 36>; + + phys =3D <&torrent_phy_dp>; + phy-names =3D "dpphy"; + + interrupt-parent =3D <&gic500>; + interrupts =3D ; + + power-domains =3D <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + + dp0_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + dss: dss@4a00000 { compatible =3D "ti,j721e-dss"; reg =3D --=20 2.17.1 From nobody Thu Jun 25 05:47:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7392EC433F5 for ; Tue, 22 Feb 2022 16:34:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234301AbiBVQe1 (ORCPT ); Tue, 22 Feb 2022 11:34:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234143AbiBVQdZ (ORCPT ); Tue, 22 Feb 2022 11:33:25 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66586168081; 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Tue, 22 Feb 2022 10:32:41 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 22 Feb 2022 10:32:41 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 21MGWeiR118296; Tue, 22 Feb 2022 10:32:41 -0600 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Date: Tue, 22 Feb 2022 22:02:30 +0530 Message-ID: <20220222163230.1566-3-r-ravikumar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220222163230.1566-1-r-ravikumar@ti.com> References: <20220222163230.1566-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tomi Valkeinen Add the endpoint nodes to describe connection from DSS =3D> MHDP =3D> DisplayPort connector. Also add the required pinmux nodes for hotplug. Signed-off-by: Tomi Valkeinen Signed-off-by: Rahul T R Reviewed-by: Tomi Valkeinen --- .../dts/ti/k3-j721e-common-proc-board.dts | 66 +++++++++++++++++-- 1 file changed, 62 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d7596911b27..fe20c193f299 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -148,6 +148,28 @@ pinctrl-0 =3D <&main_mcan2_gpio_pins_default>; standby-gpios =3D <&main_gpio0 127 GPIO_ACTIVE_HIGH>; }; + + dp_pwr_3v3: fixedregulator-dp-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint =3D <&dp0_out>; + }; + }; + }; }; =20 &main_pmx0 { @@ -190,6 +212,12 @@ >; }; =20 + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ + >; + }; + main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { pinctrl-single,pins =3D < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ @@ -660,6 +688,40 @@ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; =20 +&dss_ports { + port@0 { + reg =3D <0>; + + dpi0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; +}; + +&mhdp { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp0_pins_default>; +}; + +&dp0_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dp0_in: endpoint { + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@4 { + reg =3D <4>; + dp0_out: endpoint { + remote-endpoint =3D <&dp_connector_in>; + }; + }; +}; + &mcasp0 { status =3D "disabled"; }; @@ -845,10 +907,6 @@ status =3D "disabled"; }; =20 -&dss { - status =3D "disabled"; -}; - &icssg0_mdio { status =3D "disabled"; }; --=20 2.17.1