From nobody Sun Sep 22 09:19:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59EEEC433EF for ; Mon, 21 Feb 2022 04:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245726AbiBUEIW (ORCPT ); Sun, 20 Feb 2022 23:08:22 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:38070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245667AbiBUEIA (ORCPT ); Sun, 20 Feb 2022 23:08:00 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34BEA45526; Sun, 20 Feb 2022 20:07:32 -0800 (PST) X-UUID: e0683ef3243e494ab644f18327b0d25d-20220221 X-UUID: e0683ef3243e494ab644f18327b0d25d-20220221 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1962497431; Mon, 21 Feb 2022 12:07:26 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 21 Feb 2022 12:07:24 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 21 Feb 2022 12:07:24 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V2 4/6] spi: mediatek: add spi memory support Date: Mon, 21 Feb 2022 12:07:15 +0800 Message-ID: <20220221040717.3729-5-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220221040717.3729-1-leilk.liu@mediatek.com> References: <20220221040717.3729-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch add the support of spi-mem. Signed-off-by: Leilk Liu --- drivers/spi/spi-mt65xx.c | 310 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 309 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 5fa677a589a4..852fc008329a 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #define SPI_CFG0_REG 0x0000 @@ -75,8 +76,21 @@ #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 =20 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) + +#define PIN_MODE_CFG(x) ((x) / 2) + +#define SPI_CFG3_IPM_PIN_MODE_OFFSET 0 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) +#define SPI_CFG3_IPM_XMODE_EN BIT(4) +#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) +#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 +#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 + +#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) +#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) +#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) + #define MT8173_SPI_MAX_PAD_SEL 3 =20 #define MTK_SPI_PAUSE_INT_STATUS 0x2 @@ -87,6 +101,8 @@ #define MTK_SPI_MAX_FIFO_SIZE 32U #define MTK_SPI_PACKET_SIZE 1024 #define MTK_SPI_IPM_PACKET_SIZE SZ_64K +#define MTK_SPI_IPM_PACKET_LOOP SZ_256 + #define MTK_SPI_32BITS_MASK (0xffffffff) =20 #define DMA_ADDR_EXT_BITS (36) @@ -104,7 +120,8 @@ struct mtk_spi_compatible { bool no_need_unprepare; /* IPM design improve some single mode features */ bool ipm_design; - + /* IPM design that support quad mode */ + bool support_quad; }; =20 struct mtk_spi { @@ -120,6 +137,11 @@ struct mtk_spi { u32 tx_sgl_len, rx_sgl_len; const struct mtk_spi_compatible *dev_comp; u32 spi_clk_hz; + struct completion spimem_done; + bool use_spimem; + struct device *dev; + dma_addr_t tx_dma; + dma_addr_t rx_dma; }; =20 static const struct mtk_spi_compatible mtk_common_compat; @@ -134,6 +156,13 @@ static const struct mtk_spi_compatible ipm_compat_sing= le =3D { .ipm_design =3D true, }; =20 +static const struct mtk_spi_compatible ipm_compat_quad =3D { + .enhance_timing =3D true, + .dma_ext =3D true, + .ipm_design =3D true, + .support_quad =3D true, +}; + static const struct mtk_spi_compatible mt6765_compat =3D { .need_pad_sel =3D true, .must_tx =3D true, @@ -178,6 +207,9 @@ static const struct of_device_id mtk_spi_of_match[] =3D= { { .compatible =3D "mediatek,ipm-spi-single", .data =3D (void *)&ipm_compat_single, }, + { .compatible =3D "mediatek,ipm-spi-quad", + .data =3D (void *)&ipm_compat_quad, + }, { .compatible =3D "mediatek,mt2701-spi", .data =3D (void *)&mtk_common_compat, }, @@ -694,6 +726,13 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *de= v_id) else mdata->state =3D MTK_SPI_IDLE; =20 + /* SPI-MEM ops */ + if (mdata->use_spimem) { + complete(&mdata->spimem_done); + + return IRQ_HANDLED; + } + if (!master->can_dma(master, NULL, trans)) { if (trans->rx_buf) { cnt =3D mdata->xfer_len / 4; @@ -777,6 +816,266 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *d= ev_id) return IRQ_HANDLED; } =20 +static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, + struct spi_mem_op *op) +{ + int opcode_len; + + if (op->data.dir !=3D SPI_MEM_NO_DATA) { + opcode_len =3D 1 + op->addr.nbytes + op->dummy.nbytes; + if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { + op->data.nbytes =3D MTK_SPI_IPM_PACKET_SIZE - opcode_len; + /* force data buffer dma-aligned. */ + op->data.nbytes -=3D op->data.nbytes % 4; + } + } + + return 0; +} + +static bool mtk_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (op->data.buswidth > 4 || op->addr.buswidth > 4 || + op->dummy.buswidth > 4 || op->cmd.buswidth > 4) + return false; + + if (op->addr.nbytes && op->dummy.nbytes && + op->addr.buswidth !=3D op->dummy.buswidth) + return false; + + if (op->addr.nbytes + op->dummy.nbytes > 16) + return false; + + if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { + if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > + MTK_SPI_IPM_PACKET_LOOP || + op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE !=3D 0) + return false; + } + + return true; +} + +static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(master); + + writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), + mdata->base + SPI_TX_SRC_REG); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (mdata->dev_comp->dma_ext) + writel((u32)(mdata->tx_dma >> 32), + mdata->base + SPI_TX_SRC_REG_64); +#endif + + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), + mdata->base + SPI_RX_DST_REG); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (mdata->dev_comp->dma_ext) + writel((u32)(mdata->rx_dma >> 32), + mdata->base + SPI_RX_DST_REG_64); +#endif + } +} + +static int mtk_spi_transfer_wait(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(mem->spi->master); + unsigned long long ms =3D 1; + + if (op->data.dir =3D=3D SPI_MEM_NO_DATA) + ms =3D 8LL * 1000LL * 32; + else + ms =3D 8LL * 1000LL * op->data.nbytes; + do_div(ms, mem->spi->max_speed_hz); + ms +=3D ms + 1000; /* 1s tolerance */ + + if (ms > UINT_MAX) + ms =3D UINT_MAX; + + if (!wait_for_completion_timeout(&mdata->spimem_done, + msecs_to_jiffies(ms))) { + dev_err(mdata->dev, "spi-mem transfer timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mtk_spi_mem_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(mem->spi->master); + u32 reg_val, nio =3D 1, tx_size; + char *tx_tmp_buf, *rx_tmp_buf; + int ret =3D 0; + + mdata->use_spimem =3D true; + reinit_completion(&mdata->spimem_done); + + mtk_spi_reset(mdata); + mtk_spi_hw_init(mem->spi->master, mem->spi); + mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); + + reg_val =3D readl(mdata->base + SPI_CFG3_IPM_REG); + /* opcode byte len */ + reg_val &=3D ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; + reg_val |=3D 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; + + /* addr & dummy byte len */ + reg_val &=3D ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; + if (op->addr.nbytes || op->dummy.nbytes) + reg_val |=3D (op->addr.nbytes + op->dummy.nbytes) << + SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; + + /* data byte len */ + if (op->data.dir =3D=3D SPI_MEM_NO_DATA) { + reg_val |=3D SPI_CFG3_IPM_NODATA_FLAG; + writel(0, mdata->base + SPI_CFG1_REG); + } else { + reg_val &=3D ~SPI_CFG3_IPM_NODATA_FLAG; + mdata->xfer_len =3D op->data.nbytes; + mtk_spi_setup_packet(mem->spi->master); + } + + if (op->addr.nbytes || op->dummy.nbytes) { + if (op->addr.buswidth =3D=3D 1 || op->dummy.buswidth =3D=3D 1) + reg_val |=3D SPI_CFG3_IPM_XMODE_EN; + else + reg_val &=3D ~SPI_CFG3_IPM_XMODE_EN; + } + + if (op->addr.buswidth =3D=3D 2 || + op->dummy.buswidth =3D=3D 2 || + op->data.buswidth =3D=3D 2) + nio =3D 2; + else if (op->addr.buswidth =3D=3D 4 || + op->dummy.buswidth =3D=3D 4 || + op->data.buswidth =3D=3D 4) + nio =3D 4; + + reg_val &=3D ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; + reg_val |=3D PIN_MODE_CFG(nio) << SPI_CFG3_IPM_PIN_MODE_OFFSET; + + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_EN; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_DIR; + else + reg_val &=3D ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; + writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); + + tx_size =3D 1 + op->addr.nbytes + op->dummy.nbytes; + if (op->data.dir =3D=3D SPI_MEM_DATA_OUT) + tx_size +=3D op->data.nbytes; + + tx_size =3D max_t(u32, tx_size, 32); + + tx_tmp_buf =3D kzalloc(tx_size, GFP_KERNEL | GFP_DMA); + if (!tx_tmp_buf) + return -ENOMEM; + + tx_tmp_buf[0] =3D op->cmd.opcode; + + if (op->addr.nbytes) { + int i; + + for (i =3D 0; i < op->addr.nbytes; i++) + tx_tmp_buf[i + 1] =3D op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + } + + if (op->dummy.nbytes) + memset(tx_tmp_buf + op->addr.nbytes + 1, + 0xff, + op->dummy.nbytes); + + if (op->data.nbytes && op->data.dir =3D=3D SPI_MEM_DATA_OUT) + memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, + op->data.buf.out, + op->data.nbytes); + + mdata->tx_dma =3D dma_map_single(mdata->dev, tx_tmp_buf, + tx_size, DMA_TO_DEVICE); + if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { + ret =3D -ENOMEM; + goto err_exit; + } + + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { + rx_tmp_buf =3D kzalloc(op->data.nbytes, + GFP_KERNEL | GFP_DMA); + if (!rx_tmp_buf) { + ret =3D -ENOMEM; + goto unmap_tx_dma; + } + } else { + rx_tmp_buf =3D op->data.buf.in; + } + + mdata->rx_dma =3D dma_map_single(mdata->dev, + rx_tmp_buf, + op->data.nbytes, + DMA_FROM_DEVICE); + if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { + ret =3D -ENOMEM; + goto kfree_rx_tmp_buf; + } + } + + reg_val =3D readl(mdata->base + SPI_CMD_REG); + reg_val |=3D SPI_CMD_TX_DMA; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + reg_val |=3D SPI_CMD_RX_DMA; + writel(reg_val, mdata->base + SPI_CMD_REG); + + mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); + + mtk_spi_enable_transfer(mem->spi->master); + + /* Wait for the interrupt. */ + ret =3D mtk_spi_transfer_wait(mem, op); + if (ret) + goto unmap_rx_dma; + + /* spi disable dma */ + reg_val =3D readl(mdata->base + SPI_CMD_REG); + reg_val &=3D ~SPI_CMD_TX_DMA; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + reg_val &=3D ~SPI_CMD_RX_DMA; + writel(reg_val, mdata->base + SPI_CMD_REG); + +unmap_rx_dma: + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + dma_unmap_single(mdata->dev, mdata->rx_dma, + op->data.nbytes, DMA_FROM_DEVICE); + if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) + memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); + } +kfree_rx_tmp_buf: + if (op->data.dir =3D=3D SPI_MEM_DATA_IN && + !IS_ALIGNED((size_t)op->data.buf.in, 4)) + kfree(rx_tmp_buf); +unmap_tx_dma: + dma_unmap_single(mdata->dev, mdata->tx_dma, + tx_size, DMA_TO_DEVICE); +err_exit: + kfree(tx_tmp_buf); + mdata->use_spimem =3D false; + + return ret; +} + +static const struct spi_controller_mem_ops mtk_spi_mem_ops =3D { + .adjust_op_size =3D mtk_spi_mem_adjust_op_size, + .supports_op =3D mtk_spi_mem_supports_op, + .exec_op =3D mtk_spi_mem_exec_op, +}; + static int mtk_spi_probe(struct platform_device *pdev) { struct spi_master *master; @@ -820,6 +1119,15 @@ static int mtk_spi_probe(struct platform_device *pdev) if (mdata->dev_comp->ipm_design) master->mode_bits |=3D SPI_LOOP; =20 + if (mdata->dev_comp->support_quad) { + master->mem_ops =3D &mtk_spi_mem_ops; + master->mode_bits |=3D SPI_RX_DUAL | SPI_TX_DUAL | + SPI_RX_QUAD | SPI_TX_QUAD; + + mdata->dev =3D &pdev->dev; + init_completion(&mdata->spimem_done); + } + if (mdata->dev_comp->need_pad_sel) { mdata->pad_num =3D of_property_count_u32_elems( pdev->dev.of_node, --=20 2.25.1