From nobody Sun Sep 22 10:24:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83688C433F5 for ; Mon, 21 Feb 2022 04:07:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343529AbiBUEIS (ORCPT ); Sun, 20 Feb 2022 23:08:18 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:37906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245649AbiBUEH6 (ORCPT ); Sun, 20 Feb 2022 23:07:58 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6703045510; Sun, 20 Feb 2022 20:07:31 -0800 (PST) X-UUID: d2a7aa6798d74a8ab54b8309609613c3-20220221 X-UUID: d2a7aa6798d74a8ab54b8309609613c3-20220221 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1248482942; Mon, 21 Feb 2022 12:07:25 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 21 Feb 2022 12:07:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 21 Feb 2022 12:07:23 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 21 Feb 2022 12:07:22 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V2 2/6] spi: mediatek: add IPM single mode design support Date: Mon, 21 Feb 2022 12:07:13 +0800 Message-ID: <20220221040717.3729-3-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220221040717.3729-1-leilk.liu@mediatek.com> References: <20220221040717.3729-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch add the support of IPM single mode design. Signed-off-by: Leilk Liu --- drivers/spi/spi-mt65xx.c | 103 +++++++++++++++++++++++++++++++++------ 1 file changed, 87 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index bbfeb8046c17..5fa677a589a4 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -31,6 +31,7 @@ #define SPI_CFG2_REG 0x0028 #define SPI_TX_SRC_REG_64 0x002c #define SPI_RX_DST_REG_64 0x0030 +#define SPI_CFG3_IPM_REG 0x0040 =20 #define SPI_CFG0_SCK_HIGH_OFFSET 0 #define SPI_CFG0_SCK_LOW_OFFSET 8 @@ -48,6 +49,7 @@ #define SPI_CFG1_CS_IDLE_MASK 0xff #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 +#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) #define SPI_CFG2_SCK_HIGH_OFFSET 0 #define SPI_CFG2_SCK_LOW_OFFSET 16 =20 @@ -68,7 +70,13 @@ #define SPI_CMD_TX_ENDIAN BIT(15) #define SPI_CMD_FINISH_IE BIT(16) #define SPI_CMD_PAUSE_IE BIT(17) +#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) +#define SPI_CMD_IPM_SPIM_LOOP BIT(21) +#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 =20 +#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) +#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) +#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) #define MT8173_SPI_MAX_PAD_SEL 3 =20 #define MTK_SPI_PAUSE_INT_STATUS 0x2 @@ -78,6 +86,7 @@ =20 #define MTK_SPI_MAX_FIFO_SIZE 32U #define MTK_SPI_PACKET_SIZE 1024 +#define MTK_SPI_IPM_PACKET_SIZE SZ_64K #define MTK_SPI_32BITS_MASK (0xffffffff) =20 #define DMA_ADDR_EXT_BITS (36) @@ -93,6 +102,9 @@ struct mtk_spi_compatible { bool dma_ext; /* some IC no need unprepare SPI clk */ bool no_need_unprepare; + /* IPM design improve some single mode features */ + bool ipm_design; + }; =20 struct mtk_spi { @@ -116,6 +128,12 @@ static const struct mtk_spi_compatible mt2712_compat = =3D { .must_tx =3D true, }; =20 +static const struct mtk_spi_compatible ipm_compat_single =3D { + .enhance_timing =3D true, + .dma_ext =3D true, + .ipm_design =3D true, +}; + static const struct mtk_spi_compatible mt6765_compat =3D { .need_pad_sel =3D true, .must_tx =3D true, @@ -157,6 +175,9 @@ static const struct mtk_chip_config mtk_default_chip_in= fo =3D { }; =20 static const struct of_device_id mtk_spi_of_match[] =3D { + { .compatible =3D "mediatek,ipm-spi-single", + .data =3D (void *)&ipm_compat_single, + }, { .compatible =3D "mediatek,mt2701-spi", .data =3D (void *)&mtk_common_compat, }, @@ -275,12 +296,11 @@ static int mtk_spi_set_hw_cs_timing(struct spi_device= *spi) return 0; } =20 -static int mtk_spi_prepare_message(struct spi_master *master, - struct spi_message *msg) +static int mtk_spi_hw_init(struct spi_master *master, + struct spi_device *spi) { u16 cpha, cpol; u32 reg_val; - struct spi_device *spi =3D msg->spi; struct mtk_chip_config *chip_config =3D spi->controller_data; struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 @@ -288,6 +308,15 @@ static int mtk_spi_prepare_message(struct spi_master *= master, cpol =3D spi->mode & SPI_CPOL ? 1 : 0; =20 reg_val =3D readl(mdata->base + SPI_CMD_REG); + if (mdata->dev_comp->ipm_design) { + /* SPI transfer without idle time until packet length done */ + reg_val |=3D SPI_CMD_IPM_NONIDLE_MODE; + if (spi->mode & SPI_LOOP) + reg_val |=3D SPI_CMD_IPM_SPIM_LOOP; + else + reg_val &=3D ~SPI_CMD_IPM_SPIM_LOOP; + } + if (cpha) reg_val |=3D SPI_CMD_CPHA; else @@ -344,18 +373,33 @@ static int mtk_spi_prepare_message(struct spi_master = *master, writel(mdata->pad_sel[spi->chip_select], mdata->base + SPI_PAD_SEL_REG); =20 - /* tick delay */ - reg_val =3D readl(mdata->base + SPI_CFG1_REG); - reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK; - reg_val |=3D ((chip_config->tick_delay & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); - writel(reg_val, mdata->base + SPI_CFG1_REG); + if (mdata->dev_comp->enhance_timing) { + if (mdata->dev_comp->ipm_design) { + reg_val =3D readl(mdata->base + SPI_CMD_REG); + reg_val &=3D ~SPI_CMD_IPM_GET_TICKDLY_MASK; + reg_val |=3D ((chip_config->tick_delay & 0x7) + << SPI_CMD_IPM_GET_TICKDLY_OFFSET); + writel(reg_val, mdata->base + SPI_CMD_REG); + } else { + reg_val =3D readl(mdata->base + SPI_CFG1_REG); + reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK; + reg_val |=3D ((chip_config->tick_delay & 0x7) + << SPI_CFG1_GET_TICK_DLY_OFFSET); + writel(reg_val, mdata->base + SPI_CFG1_REG); + } + } =20 /* set hw cs timing */ mtk_spi_set_hw_cs_timing(spi); return 0; } =20 +static int mtk_spi_prepare_message(struct spi_master *master, + struct spi_message *msg) +{ + return mtk_spi_hw_init(master, msg->spi); +} + static void mtk_spi_set_cs(struct spi_device *spi, bool enable) { u32 reg_val; @@ -377,13 +421,13 @@ static void mtk_spi_set_cs(struct spi_device *spi, bo= ol enable) } =20 static void mtk_spi_prepare_transfer(struct spi_master *master, - struct spi_transfer *xfer) + u32 speed_hz) { u32 div, sck_time, reg_val; struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 - if (xfer->speed_hz < mdata->spi_clk_hz / 2) - div =3D DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz); + if (speed_hz < mdata->spi_clk_hz / 2) + div =3D DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); else div =3D 1; =20 @@ -414,12 +458,24 @@ static void mtk_spi_setup_packet(struct spi_master *m= aster) u32 packet_size, packet_loop, reg_val; struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 - packet_size =3D min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); + if (mdata->dev_comp->ipm_design) + packet_size =3D min_t(u32, + mdata->xfer_len, + MTK_SPI_IPM_PACKET_SIZE); + else + packet_size =3D min_t(u32, + mdata->xfer_len, + MTK_SPI_PACKET_SIZE); + packet_loop =3D mdata->xfer_len / packet_size; =20 reg_val =3D readl(mdata->base + SPI_CFG1_REG); - reg_val &=3D ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); + if (mdata->dev_comp->ipm_design) + reg_val &=3D ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; + else + reg_val &=3D ~SPI_CFG1_PACKET_LENGTH_MASK; reg_val |=3D (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; + reg_val &=3D ~SPI_CFG1_PACKET_LOOP_MASK; reg_val |=3D (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; writel(reg_val, mdata->base + SPI_CFG1_REG); } @@ -514,7 +570,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *mas= ter, mdata->cur_transfer =3D xfer; mdata->xfer_len =3D min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); mdata->num_xfered =3D 0; - mtk_spi_prepare_transfer(master, xfer); + mtk_spi_prepare_transfer(master, xfer->speed_hz); mtk_spi_setup_packet(master); =20 if (xfer->tx_buf) { @@ -547,7 +603,7 @@ static int mtk_spi_dma_transfer(struct spi_master *mast= er, mdata->cur_transfer =3D xfer; mdata->num_xfered =3D 0; =20 - mtk_spi_prepare_transfer(master, xfer); + mtk_spi_prepare_transfer(master, xfer->speed_hz); =20 cmd =3D readl(mdata->base + SPI_CMD_REG); if (xfer->tx_buf) @@ -582,6 +638,19 @@ static int mtk_spi_transfer_one(struct spi_master *mas= ter, struct spi_device *spi, struct spi_transfer *xfer) { + struct mtk_spi *mdata =3D spi_master_get_devdata(spi->master); + u32 reg_val =3D 0; + + /* prepare xfer direction and duplex mode */ + if (mdata->dev_comp->ipm_design) { + if (!xfer->tx_buf || !xfer->rx_buf) { + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_EN; + if (xfer->rx_buf) + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_DIR; + } + writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); + } + if (master->can_dma(master, spi, xfer)) return mtk_spi_dma_transfer(master, spi, xfer); else @@ -748,6 +817,8 @@ static int mtk_spi_probe(struct platform_device *pdev) =20 if (mdata->dev_comp->must_tx) master->flags =3D SPI_MASTER_MUST_TX; + if (mdata->dev_comp->ipm_design) + master->mode_bits |=3D SPI_LOOP; =20 if (mdata->dev_comp->need_pad_sel) { mdata->pad_num =3D of_property_count_u32_elems( --=20 2.25.1