From nobody Sun Jun 28 09:58:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F223C433EF for ; Sun, 20 Feb 2022 11:51:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240930AbiBTLve (ORCPT ); Sun, 20 Feb 2022 06:51:34 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:33844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229924AbiBTLv1 (ORCPT ); Sun, 20 Feb 2022 06:51:27 -0500 Received: from box.trvn.ru (box.trvn.ru [194.87.146.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 413754BFC5; Sun, 20 Feb 2022 03:51:06 -0800 (PST) Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id B254341B13; Sun, 20 Feb 2022 16:50:54 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1645357855; bh=1YlbsxH0JoY8SWFQLXv0f2oen4FfT2iOGdwImk2P+/0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zFJVAxQBsaGmtFTDgKuFvoRNb9sDdKLnFM6KovRPcQ/emsRymMpRDvEHdf+hVi62n wz72T/lSW9dQh3tWNPLxzk3s7fBOeycZl8U4teFai65tSxD01q6Y0fTLd4+Rj+zWet 2mmtFvVPTWaEZ7q3FVM2gpUmMqb+WpeM0SFOwOI/mu5QAeEij05LAdE634yLwoiiUB kMvOe8t7LHjJZaJzirqS40g4I+wQkXFYd6XVobM107MSItmreGQEhMfo3bDpW1AJ0+ lRrF9xMQGR9GALrUN7dZ59WOWLI170cIa7iC8QNdQcCKyYsRd/s9ji8/NigF+eN82V EXnvJkd02A1Yw== From: Nikita Travkin To: thierry.reding@gmail.com, lee.jones@linaro.org Cc: u.kleine-koenig@pengutronix.de, robh+dt@kernel.org, sboyd@kernel.org, krzk@kernel.org, linus.walleij@linaro.org, masneyb@onstation.org, sean.anderson@seco.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin , Krzysztof Kozlowski Subject: [PATCH v6 1/2] dt-bindings: pwm: Document clk based PWM controller Date: Sun, 20 Feb 2022 16:50:29 +0500 Message-Id: <20220220115030.23772-2-nikita@trvn.ru> In-Reply-To: <20220220115030.23772-1-nikita@trvn.ru> References: <20220220115030.23772-1-nikita@trvn.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML devicetree binding for clk based PWM controller Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nikita Travkin -- Changes in v2: - fix the file name. Changes in v4: - Use generic node name in the dt bindings example. Changes in v5: - make compatible required Reviewed-by: Rob Herring --- .../devicetree/bindings/pwm/clk-pwm.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/clk-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documenta= tion/devicetree/bindings/pwm/clk-pwm.yaml new file mode 100644 index 000000000000..ec1768291503 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/clk-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock based PWM controller + +maintainers: + - Nikita Travkin + +description: | + Some systems have clocks that can be exposed to external devices. + (e.g. by muxing them to GPIO pins) + It's often possible to control duty-cycle of such clocks which makes them + suitable for generating PWM signal. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: clk-pwm + + clocks: + description: Clock used to generate the signal. + maxItems: 1 + + "#pwm-cells": + const: 2 + +unevaluatedProperties: false + +required: + - compatible + - clocks + +examples: + - | + pwm { + compatible =3D "clk-pwm"; + #pwm-cells =3D <2>; + clocks =3D <&gcc 0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_clk_flash_default>; + }; --=20 2.34.1 From nobody Sun Jun 28 09:58:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2CA9C433FE for ; Sun, 20 Feb 2022 11:51:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240711AbiBTLvb (ORCPT ); Sun, 20 Feb 2022 06:51:31 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:33846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235340AbiBTLv1 (ORCPT ); Sun, 20 Feb 2022 06:51:27 -0500 Received: from box.trvn.ru (box.trvn.ru [194.87.146.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 412594BFC1; Sun, 20 Feb 2022 03:51:06 -0800 (PST) Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id 739C841C0F; Sun, 20 Feb 2022 16:50:55 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1645357856; bh=UeLE/WMy5E/Koom9vP651Cz6BbnvNerRH7/J6Trfy+g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cb9MMC1NevPniIFhXOkPFspfW07+ht4uIOGhBEjX6Tbg9K/k1toqAOxHx2IBo9hgu a/h0SkZJc51cBCbU2kutHxO84o7bj1pSHurb/iAXwgFu2ng1GuI5FbvKFI/NBwHpRO TrdazRpG2xfprJOz+zAx/+qacIJ2TFoEexz7o/zZJ93Fhz1j8sm3DxZGM+TbCc0+Ql gkvKTf2cm5iRvt0hYvTPrcstiNZO0ipMxvJZvQjLWNsz8idVuPVWdctQEYSD02XizD LbilVcMlJ7zlIexv2+rQgZqNWL6Xago2QJ9Hfwl27X5U4TT6CJU8p6jJacyERm7eEy pY+Ut6/hibY1w== From: Nikita Travkin To: thierry.reding@gmail.com, lee.jones@linaro.org Cc: u.kleine-koenig@pengutronix.de, robh+dt@kernel.org, sboyd@kernel.org, krzk@kernel.org, linus.walleij@linaro.org, masneyb@onstation.org, sean.anderson@seco.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH v6 2/2] pwm: Add clock based PWM output driver Date: Sun, 20 Feb 2022 16:50:30 +0500 Message-Id: <20220220115030.23772-3-nikita@trvn.ru> In-Reply-To: <20220220115030.23772-1-nikita@trvn.ru> References: <20220220115030.23772-1-nikita@trvn.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some systems have clocks exposed to external devices. If the clock controller supports duty-cycle configuration, such clocks can be used as pwm outputs. In fact PWM and CLK subsystems are interfaced with in a similar way and an "opposite" driver already exists (clk-pwm). Add a driver that would enable pwm devices to be used via clk subsystem. Signed-off-by: Nikita Travkin -- Changes in v2: - Address Uwe's review comments: - Round set clk rate up - Add a description with limitations of the driver - Disable and unprepare clock before removing pwmchip Changes in v3: - Use 64bit version of div round up - Address Uwe's review comments: - Reword the limitations to avoid incorrect claims - Move the clk_enabled flag assignment - Drop unnecessary statements Changes in v5: - add missed returns Changes in v6: - Unprepare the clock on error - Drop redundant limitations points --- drivers/pwm/Kconfig | 10 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-clk.c | 139 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+) create mode 100644 drivers/pwm/pwm-clk.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 21e3b05a5153..daa2491a4054 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -140,6 +140,16 @@ config PWM_BRCMSTB To compile this driver as a module, choose M Here: the module will be called pwm-brcmstb.c. =20 +config PWM_CLK + tristate "Clock based PWM support" + depends on HAVE_CLK || COMPILE_TEST + help + Generic PWM framework driver for outputs that can be + muxed to clocks. + + To compile this driver as a module, choose M here: the module + will be called pwm-clk. + config PWM_CLPS711X tristate "CLPS711X PWM support" depends on ARCH_CLPS711X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 708840b7fba8..4a860103c470 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PWM_BCM_KONA) +=3D pwm-bcm-kona.o obj-$(CONFIG_PWM_BCM2835) +=3D pwm-bcm2835.o obj-$(CONFIG_PWM_BERLIN) +=3D pwm-berlin.o obj-$(CONFIG_PWM_BRCMSTB) +=3D pwm-brcmstb.o +obj-$(CONFIG_PWM_CLK) +=3D pwm-clk.o obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o diff --git a/drivers/pwm/pwm-clk.c b/drivers/pwm/pwm-clk.c new file mode 100644 index 000000000000..52c9923368cb --- /dev/null +++ b/drivers/pwm/pwm-clk.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock based PWM controller + * + * Copyright (c) 2021 Nikita Travkin + * + * This is an "adapter" driver that allows PWM consumers to use + * system clocks with duty cycle control as PWM outputs. + * + * Limitations: + * - Due to the fact that exact behavior depends on the underlying + * clock driver, various limitations are possible. + * - Underlying clock may not be able to give 0% or 100% duty cycle + * (constant off or on), exact behavior will depend on the clock. + * - When the PWM is disabled, the clock will be disabled as well, + * line state will depend on the clock. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct pwm_clk_chip { + struct pwm_chip chip; + struct clk *clk; + bool clk_enabled; +}; + +#define to_pwm_clk_chip(_chip) container_of(_chip, struct pwm_clk_chip, ch= ip) + +static int pwm_clk_apply(struct pwm_chip *pwm_chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct pwm_clk_chip *chip =3D to_pwm_clk_chip(pwm_chip); + int ret; + u32 rate; + u64 period =3D state->period; + u64 duty_cycle =3D state->duty_cycle; + + if (!state->enabled) { + if (pwm->state.enabled) { + clk_disable(chip->clk); + chip->clk_enabled =3D false; + } + return 0; + } else if (!pwm->state.enabled) { + ret =3D clk_enable(chip->clk); + if (ret) + return ret; + chip->clk_enabled =3D true; + } + + rate =3D DIV64_U64_ROUND_UP(NSEC_PER_SEC, period); + ret =3D clk_set_rate(chip->clk, rate); + if (ret) + return ret; + + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) + duty_cycle =3D period - duty_cycle; + + return clk_set_duty_cycle(chip->clk, duty_cycle, period); +} + +static const struct pwm_ops pwm_clk_ops =3D { + .apply =3D pwm_clk_apply, + .owner =3D THIS_MODULE, +}; + +static int pwm_clk_probe(struct platform_device *pdev) +{ + struct pwm_clk_chip *chip; + int ret; + + chip =3D devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->clk =3D devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(chip->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), + "Failed to get clock\n"); + + chip->chip.dev =3D &pdev->dev; + chip->chip.ops =3D &pwm_clk_ops; + chip->chip.npwm =3D 1; + + ret =3D clk_prepare(chip->clk); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to prepare clock\n"); + + ret =3D pwmchip_add(&chip->chip); + if (ret < 0) { + clk_unprepare(chip->clk); + return dev_err_probe(&pdev->dev, ret, "Failed to add pwm chip\n"); + } + + platform_set_drvdata(pdev, chip); + return 0; +} + +static int pwm_clk_remove(struct platform_device *pdev) +{ + struct pwm_clk_chip *chip =3D platform_get_drvdata(pdev); + + pwmchip_remove(&chip->chip); + + if (chip->clk_enabled) + clk_disable(chip->clk); + + clk_unprepare(chip->clk); + + return 0; +} + +static const struct of_device_id pwm_clk_dt_ids[] =3D { + { .compatible =3D "clk-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pwm_clk_dt_ids); + +static struct platform_driver pwm_clk_driver =3D { + .driver =3D { + .name =3D "pwm-clk", + .of_match_table =3D pwm_clk_dt_ids, + }, + .probe =3D pwm_clk_probe, + .remove =3D pwm_clk_remove, +}; +module_platform_driver(pwm_clk_driver); + +MODULE_ALIAS("platform:pwm-clk"); +MODULE_AUTHOR("Nikita Travkin "); +MODULE_DESCRIPTION("Clock based PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1