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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:25 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH v8 13/19] drm/mediatek: dpi: Add dpintf support Date: Fri, 18 Feb 2022 15:54:31 +0100 Message-Id: <20220218145437.18563-14-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 164 +++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 38 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +- include/linux/soc/mediatek/mtk-mmsys.h | 2 + 6 files changed, 198 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index be99399faf1bb..c5639ada868f8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL }; =20 +enum TVDPLL_CLK { + TVDPLL_PLL =3D 0, + TVDPLL_D2 =3D 2, + TVDPLL_D4 =3D 4, + TVDPLL_D8 =3D 8, + TVDPLL_D16 =3D 16, +}; + struct mtk_dpi { struct drm_encoder encoder; struct drm_bridge bridge; @@ -71,8 +79,10 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *dpi_ck_cg; struct clk *pixel_clk; struct clk *tvd_clk; + struct clk *pclk_src[5]; int irq; struct drm_display_mode mode; const struct mtk_dpi_conf *conf; @@ -126,6 +136,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; // Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) u32 dimension_mask; @@ -384,6 +395,25 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi= *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } =20 +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, enum mtk_dpi_out_color= _format format) +{ + u32 matrix_sel =3D 0; + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <=3D 720) + matrix_sel =3D 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -391,6 +421,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -398,6 +429,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); @@ -438,6 +470,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_ck_cg); + clk_disable_unprepare(dpi->tvd_clk); } =20 static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -447,12 +481,24 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount !=3D 1) return 0; =20 + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_pixel; + } + ret =3D clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_refcount; } =20 + ret =3D clk_prepare_enable(dpi->dpi_ck_cg); + if (ret) { + dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n", ret); + goto err_ck_cg; + } + ret =3D clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -462,10 +508,11 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); =20 - mtk_dpi_enable(dpi); return 0; =20 err_pixel: + clk_disable_unprepare(dpi->dpi_ck_cg); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; @@ -497,12 +544,21 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, pll_rate =3D clk_get_rate(dpi->tvd_clk); =20 vm.pixelclock =3D pll_rate / factor; - if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + if (dpi->conf->is_dpintf) { + if (factor =3D=3D 1) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[2]); + else if (factor =3D=3D 2) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[3]); + else if (factor =3D=3D 4) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[4]); + else + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[2]); + } else if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -515,9 +571,15 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width =3D vm.hsync_len; - hsync.back_porch =3D vm.hback_porch; - hsync.front_porch =3D vm.hfront_porch; + if (dpi->conf->is_dpintf) { + hsync.sync_width =3D vm.hsync_len / 4; + hsync.back_porch =3D vm.hback_porch / 4; + hsync.front_porch =3D vm.hfront_porch / 4; + } else { + hsync.sync_width =3D vm.hsync_len; + hsync.back_porch =3D vm.hback_porch; + hsync.front_porch =3D vm.hfront_porch; + } hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -559,13 +621,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 + mtk_dpi_enable(dpi); + return 0; } =20 @@ -608,7 +677,6 @@ static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(st= ruct drm_bridge *bridge, u32 *input_fmts; =20 *num_input_fmts =3D 0; - input_fmts =3D kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); if (!input_fmts) @@ -634,15 +702,18 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bri= dge *bridge, if (dpi->conf->num_output_fmts) out_bus_format =3D dpi->conf->output_fmts[0]; =20 - dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", - bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); + dev_info(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); =20 dpi->output_fmt =3D out_bus_format; dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } @@ -687,7 +758,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); =20 - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -801,6 +872,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -810,6 +891,12 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { .c_bottom =3D 0x0010, .c_top =3D 0x0FE0, @@ -817,6 +904,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D= { .y_top =3D 0x0FE0, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpintf_limit =3D { + .c_bottom =3D 0x0000, + .c_top =3D 0xFFF, + .y_bottom =3D 0x0000, + .y_top =3D 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -882,6 +976,19 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .limit =3D &mtk_dpi_limit, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .limit =3D &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -929,7 +1036,18 @@ static int mtk_dpi_probe(struct platform_device *pdev) if (IS_ERR(dpi->engine_clk)) { ret =3D PTR_ERR(dpi->engine_clk); if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "Failed to get engine clock: %d\n", ret); + dev_err(dev, "Failed to get engine clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg =3D devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret =3D PTR_ERR(dpi->dpi_ck_cg); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", + ret); =20 return ret; } @@ -952,6 +1070,11 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; } =20 + dpi->pclk_src[1] =3D devm_clk_get(dev, "TVDPLL_D2"); + dpi->pclk_src[2] =3D devm_clk_get(dev, "TVDPLL_D4"); + dpi->pclk_src[3] =3D devm_clk_get(dev, "TVDPLL_D8"); + dpi->pclk_src[4] =3D devm_clk_get(dev, "TVDPLL_D16"); + dpi->irq =3D platform_get_irq(pdev, 0); if (dpi->irq <=3D 0) return -EINVAL; @@ -1004,6 +1127,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe16627..91b32dfffced2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,15 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP BIT(1) #define CH_SWAP_MASK (0x7 << 0) +#define DPINTF_CH_SWAP_MASK (0x7 << 1) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 #define SWAP_BRG 0x02 @@ -80,8 +85,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +100,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +230,29 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL BIT(0) +#define INT_MATRIX_SEL_MASK (0x1F << 0) +#define RGB_TO_JPEG 0x00 +#define RGB_TO_FULL709 0x01 +#define RGB_TO_BT601 0x02 +#define RGB_TO_BT709 0x03 +#define JPEG_TO_RGB 0x04 +#define FULL709_TO_RGB 0x05 +#define BT601_TO_RGB 0x06 +#define BT709_TO_RGB 0x07 +#define JPEG_TO_BT601 0x08 +#define JPEG_TO_BT709 0x09 +#define BT601_TO_JPEG 0xA +#define BT709_TO_JPEG 0xB +#define BT709_TO_BT601 0xC +#define BT601_TO_BT709 0xD +#define JPEG_TO_CERGB 0x14 +#define FULL709_TO_CERGB 0x15 +#define BT601_TO_CERGB 0x16 +#define BT709_TO_CERGB 0x17 +#define RGB_TO_CERGB 0x1C +#define MATRIX_BIT BIT(8) +#define EXT_MATRIX_EN BIT(12) #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index b4b682bc19913..e8bd6fd4a63d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -351,6 +351,11 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_CO= MP_TYPE_MAX] =3D { [MTK_DISP_WDMA] =3D "wdma", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", + [MTK_DP_INTF] =3D "dp-intf", + [MTK_DISP_PWM] =3D "pwm", + [MTK_DISP_MUTEX] =3D "mutex", + [MTK_DISP_OD] =3D "od", + [MTK_DISP_BLS] =3D "bls", }; =20 struct mtk_ddp_comp_match { @@ -369,6 +374,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_ID_MAX] =3D { [DDP_COMPONENT_DITHER] =3D { MTK_DISP_DITHER, 0, &ddp_dither }, [DDP_COMPONENT_DPI0] =3D { MTK_DPI, 0, &ddp_dpi }, [DDP_COMPONENT_DPI1] =3D { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -513,6 +520,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 4c6a986623051..deda70df1d6d9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 56ff8c57ef8fd..e00ab6410db74 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -511,6 +511,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -611,7 +613,8 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_RDMA || comp_type =3D=3D MTK_DPI || - comp_type =3D=3D MTK_DSI) { + comp_type =3D=3D MTK_DPI || + comp_type =3D=3D MTK_DP_INTF) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 4bba275e235ac..56ed2fa5f59e8 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -19,6 +19,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DITHER, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, --=20 2.34.1