From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D25BBC433F5 for ; Fri, 18 Feb 2022 14:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236378AbiBRO4c (ORCPT ); Fri, 18 Feb 2022 09:56:32 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236302AbiBRO40 (ORCPT ); Fri, 18 Feb 2022 09:56:26 -0500 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DB2C57B3B for ; Fri, 18 Feb 2022 06:56:00 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id k1so15027129wrd.8 for ; Fri, 18 Feb 2022 06:56:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qC+RbOnlbAMYT0RkhfvSIqXlBo3fNavEyqmQsnLiR2Q=; b=CB/gthuBR1PKlTX0iRK6AGpgmej1LoRD8khuOAy0FQB9eCSE8iJkQM4NYE1ZysOiKs la2wmI5DNqHmk3Wie4KVwcRAjSuR3pv9v0Z3NBZHUVKejZwAY0Y78WkhHLlnXLYHPDIv KiAERdi2FrteWdUGKvtFGAAT71x4pk+S1RHGgB1i/atRB3wMMCKZVkDFzFbER0ZMu+O4 VATNEmRSJkbX/ZDl4zvF+/q0Cl8dwfUwyt24KzEVU8MVMBpgeCCsQTzOW3z1fLhqK7CM WOhVK1BhA0a2HUW0Pn8hKI2l4dGz92rXj1d/SpDEDofgbA1bFqHzXEVn6guVSxM93lv7 SjxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qC+RbOnlbAMYT0RkhfvSIqXlBo3fNavEyqmQsnLiR2Q=; b=3rY10/dODCRa0rdQWewX8icdMyb1v264MmNfsFjFV1bR35hGlU/TWmMOnPKagoIKo5 DzzfBsEeOnJOqEsZs3nnNG2mxVd9GnNenYNy15/igwnnGxQWQQA+VkpvrjoGFKjdi9HH SP7r573KBSuVvsr5Un6mSIRy3ZGORYrxvbgUcw8B1DDYEgsxityHMyuk2oCqq695UiFP bYCja6BYuiEhnmJAqLP+19zTJTCNyj2cDU/YtTa0A5755QGfYCsXIsWaonooND+XLoIu PhNDvsHkJPGVErtvPCwoKNFTkoSJ+RRGpo587FJxZKOEtycG2hQu9e6089mxsYEhSLgI PQqA== X-Gm-Message-State: AOAM530kjanO9CIoJ0fuhOfEACR2ZKd5v3jxNMvpBDZDT1mmhgvotIg9 n7nWPgTV9uaFXepOcNbLwiRzcw== X-Google-Smtp-Source: ABdhPJwNBdk3NS5ZflKP/t4iGuuUk373NB0fBIlAS30h710cFUX/Rlxqs4tq3A739PN3fuS29Ive5g== X-Received: by 2002:a05:6000:257:b0:1e3:3a1b:d4ca with SMTP id m23-20020a056000025700b001e33a1bd4camr6304391wrz.112.1645196158903; Fri, 18 Feb 2022 06:55:58 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:55:58 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann , Rob Herring Subject: [PATCH v8 01/19] dt-bindings: mediatek,dpi: Add DP_INTF compatible Date: Fri, 18 Feb 2022 15:54:19 +0100 Message-Id: <20220218145437.18563-2-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann DP_INTF is similar to DPI but does not have the exact same feature set or register layouts. DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reviewed-by: Rob Herring --- .../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index dd2896a40ff08..53acf9a84f7fb 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: mediatek DPI Controller Device Tree Bindings +title: mediatek DPI/DP_INTF Controller Device Tree Bindings =20 maintainers: - CK Hu - Jitao shi =20 description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The Mediatek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data= on a + parallel output bus. =20 properties: compatible: @@ -23,6 +23,7 @@ properties: - mediatek,mt8173-dpi - mediatek,mt8183-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dpintf =20 reg: maxItems: 1 @@ -54,7 +55,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of= an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip. =20 required: - compatible --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94C71C43219 for ; Fri, 18 Feb 2022 14:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236370AbiBRO4h (ORCPT ); Fri, 18 Feb 2022 09:56:37 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236322AbiBRO41 (ORCPT ); Fri, 18 Feb 2022 09:56:27 -0500 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AD3458E7A for ; Fri, 18 Feb 2022 06:56:02 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id d27so15030081wrc.6 for ; Fri, 18 Feb 2022 06:56:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8f2hof1aQ6lwVFmupuo9jzO+yiBIvX9J29TbA0gSLWY=; b=g5BxrjBH3TULbbsg0hXkjFu7gK33jq2Gb4PAaYmUct5j3CMtMNvfFTKLgLG6VSzQuj D1HyPjn8TiRIrUhKIyFVjvj0V7vIvmfBETUGA0X3CKjwlB48bZhPpVY01UQ1YyC35PzH fFwja52bRYhdU2AyTxVLM43JlBDYbW4Zc4nCw/hvEMjWUonqPnhJDyHbMlE3BTOLCKr4 9EvFI186fmfi5et2vXSryQscGWaaf57p2erQolFts798qbDdxny9yql/4pgSjUCl8Gz8 J3rCMjX8VJSsWGHZyohL1kraDRkPmdM35wmHGfpxQ7xKwmIpLfBdR4E/I6Us4EOb7x0L nPMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8f2hof1aQ6lwVFmupuo9jzO+yiBIvX9J29TbA0gSLWY=; b=LYdetRbVVILZSDUr0tGSrg5L2rHGuzqOgJZEb1fguwr3Xfa4qHzsZMFEABe6cl4SY7 EZ6Ir7QyOSI4eMGomXkd/6hR8br0vyi5PTKS/qsaklqHtnT5czoeHAsiheE+HAij6kip 417D+YrysGY8Mf7B70Ak4/aFUQz7Rg7a/8yXcIw/Xac8j9LljDYcBUvK6F2yxH/nDULF WZ9FozF0BzMRbalE7jDGIT7ZTOI28O4yoQS9EZbvQdXA871r5k0oQujWDQ2+msMYMvlf 9EFvorZFYjurndxRANsPKZqg4uNkkogZopYBefK3nhTJCj2d+Mzukn9Is5/RTdbWMyB4 frEA== X-Gm-Message-State: AOAM530S4fgmdW0B3MTu73mx0uxYYxstPz+1iqGEnXSdu8p1EeVVLyhy yEAKkJruPYb6l616LKVI96O81A== X-Google-Smtp-Source: ABdhPJyh9duhvScQ+K+GxiAh+adrwEeS9AEjb/vcfumx/8LoyXD8GON1VKujIsjJufeghUVk9wYrfw== X-Received: by 2002:adf:e7d1:0:b0:1e6:b9ba:fa1 with SMTP id e17-20020adfe7d1000000b001e6b9ba0fa1mr6306132wrn.269.1645196161044; Fri, 18 Feb 2022 06:56:01 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:00 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann , Rob Herring Subject: [PATCH v8 02/19] dt-bindings: mediatek,dp: Add Display Port binding Date: Fri, 18 Feb 2022 15:54:20 +0100 Message-Id: <20220218145437.18563-3-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This controller is present on several mediatek hardware. Currently mt8195 and mt8395 have this controller without a functional difference, so only one compatible field is added. The controller can have two forms, as a normal display port and as an embedded display port. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reviewed-by: Rob Herring --- .../display/mediatek/mediatek,dp.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 0000000000000..068b11d766e21 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Display Port Controller + +maintainers: + - CK Hu + - Jitao shi + +description: | + Device tree bindings for the Mediatek (embedded) Display Port controller + present on some Mediatek SoCs. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-tx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: faxi clock + + clock-names: + items: + - const: faxi + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the controller + +required: + - compatible + - reg + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + #include + edp_tx: edp_tx@1c500000 { + compatible =3D "mediatek,mt8195-dp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_pin>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edp_in: endpoint { + remote-endpoint =3D <&dp_intf0_out>; + }; + }; + port@1 { + reg =3D <1>; + edp_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + }; --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DBACC433F5 for ; Fri, 18 Feb 2022 14:56:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236463AbiBRO4l (ORCPT ); Fri, 18 Feb 2022 09:56:41 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232520AbiBRO42 (ORCPT ); Fri, 18 Feb 2022 09:56:28 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F9E557B1A for ; Fri, 18 Feb 2022 06:56:04 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id i14so14999406wrc.10 for ; Fri, 18 Feb 2022 06:56:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nJkHxY5AR6xqJWj38hKMvv+Z6LskhPZHMXhRMUaTZBg=; b=d4/A7tapqhoj+nKQknbI9myUskve33mE681HrsO26zPtt277c7xD5xX1OUlmAVlFMM GazLRWwYi7bBKTz0B+bjiXXoNTZPLzZ6xgpE/oHg8wA+lSQYCx4M33ob2H0UmVjv7HyZ Hv3bJhIlhPfm0Yo9043I6dnA8OZ4xd38JXmZwzeziS7hSM8e6qmSv8n0s81VklGSqHX9 vadFGHdH+6mdVgHOCY8KY/dF7owTVl4GJTmNe+rdf+deBJWkw2N9SlRpAwhVHJ1I87H6 ExctPr4MqPcB5h6o47uN6YRYlXtxsK3BPfBQpkMbqDG3w12PaIbJTsy1tUCEImY8HjP1 GaHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nJkHxY5AR6xqJWj38hKMvv+Z6LskhPZHMXhRMUaTZBg=; b=AdJekj9/D8YV5IiAsLj41gWGhqoEuiyUcDbPijEfIppvAgjuRUz9WpuEmBpHAYE1LE Zt3mpzhM06pzrc6VffAfXjDW8kfyIB7s/J6KxkQ51abUAvCZesEeetBGYTT6bepC9crb nFMX2+Rt5GuluZPqLlBgQf0r09n4yS42+BiEdEQczNG4Isft1+HG0DLPiqC3oJiPpvw2 wWurQ1GoxEI8Q39HHYNDnG80QS7HSWFcgR5WKV645qpQ/U2M9vFqdsXKUH8Ri8m3c3N5 cS1zG8KoBPQ6Kji7+d00hEv2fJa9oqkRUnHBdaPNN3Q8/8az9oKciWeaCAiNbOIhWSJR WjBA== X-Gm-Message-State: AOAM53313n5X5HTnH0PwqmOOppIaFNI5gm6fnT8UsCpagpmVchpUVBm6 W/eF9RQBEE4hUgeN7IcFX+3ZuQ== X-Google-Smtp-Source: ABdhPJzKg+0QXkil1m7jx6gI2ctEKlAP5e/CL5A6ueJGTjphI0RFc7JztgkWPfSY1UibxXF5qSrFxg== X-Received: by 2002:adf:8170:0:b0:1e0:6087:9d42 with SMTP id 103-20020adf8170000000b001e060879d42mr6297395wrm.217.1645196163141; Fri, 18 Feb 2022 06:56:03 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:02 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH v8 03/19] drm/edid: Add cea_sad helpers for freq/length Date: Fri, 18 Feb 2022 15:54:21 +0100 Message-Id: <20220218145437.18563-4-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This patch adds two helper functions that extract the frequency and word length from a struct cea_sad. For these helper functions new defines are added that help translate the 'freq' and 'byte2' fields into real numbers. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/drm_edid.c | 74 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 18 ++++++++-- 2 files changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 12893e7be89bb..500279a82167a 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -4747,6 +4747,80 @@ int drm_edid_to_speaker_allocation(struct edid *edid= , u8 **sadb) } EXPORT_SYMBOL(drm_edid_to_speaker_allocation); =20 +/** + * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad frequency field and returns the sample rate in Hz. + * + * Return: Sample rate in Hz or a negative errno if parsing failed. + */ +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad) +{ + switch (sad->freq) { + case DRM_CEA_SAD_FREQ_32KHZ: + return 32000; + case DRM_CEA_SAD_FREQ_44KHZ: + return 44100; + case DRM_CEA_SAD_FREQ_48KHZ: + return 48000; + case DRM_CEA_SAD_FREQ_88KHZ: + return 88200; + case DRM_CEA_SAD_FREQ_96KHZ: + return 96000; + case DRM_CEA_SAD_FREQ_176KHZ: + return 176400; + case DRM_CEA_SAD_FREQ_192KHZ: + return 192000; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_sample_rate); + +static bool drm_cea_sad_is_uncompressed(const struct cea_sad *sad) +{ + switch (sad->format) { + case HDMI_AUDIO_CODING_TYPE_STREAM: + case HDMI_AUDIO_CODING_TYPE_PCM: + return true; + default: + return false; + } +} + +/** + * drm_cea_sad_get_uncompressed_word_length - Extract word length + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad byte2 field and returns the word length for an + * uncompressed stream. + * + * Note: This function may only be called for uncompressed audio. + * + * Return: Word length in bits or a negative errno if parsing failed. + */ +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad) +{ + if (!drm_cea_sad_is_uncompressed(sad)) { + DRM_WARN("Unable to get the uncompressed word length for a compressed fo= rmat: %u\n", + sad->format); + return -EINVAL; + } + + switch (sad->byte2) { + case DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT: + return 16; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT: + return 20; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT: + return 24; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length); + /** * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay * @connector: connector associated with the HDMI/DP sink diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 18f6c700f6d02..a30452b313979 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -361,12 +361,24 @@ struct edid { =20 /* Short Audio Descriptor */ struct cea_sad { - u8 format; + u8 format; /* See HDMI_AUDIO_CODING_TYPE_* */ u8 channels; /* max number of channels - 1 */ - u8 freq; + u8 freq; /* See CEA_SAD_FREQ_* */ u8 byte2; /* meaning depends on format */ }; =20 +#define DRM_CEA_SAD_FREQ_32KHZ BIT(0) +#define DRM_CEA_SAD_FREQ_44KHZ BIT(1) +#define DRM_CEA_SAD_FREQ_48KHZ BIT(2) +#define DRM_CEA_SAD_FREQ_88KHZ BIT(3) +#define DRM_CEA_SAD_FREQ_96KHZ BIT(4) +#define DRM_CEA_SAD_FREQ_176KHZ BIT(5) +#define DRM_CEA_SAD_FREQ_192KHZ BIT(6) + +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2) + struct drm_encoder; struct drm_connector; struct drm_connector_state; @@ -374,6 +386,8 @@ struct drm_display_mode; =20 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad); +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad); int drm_av_sync_delay(struct drm_connector *connector, const struct drm_display_mode *mode); =20 --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54C4CC433FE for ; Fri, 18 Feb 2022 14:56:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236412AbiBRO4v (ORCPT ); Fri, 18 Feb 2022 09:56:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236336AbiBRO4c (ORCPT ); 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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:05 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH v8 04/19] video/hdmi: Add audio_infoframe packing for DP Date: Fri, 18 Feb 2022 15:54:22 +0100 Message-Id: <20220218145437.18563-5-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann Similar to HDMI, DP uses audio infoframes as well which are structured very similar to the HDMI ones. This patch adds a helper function to pack the HDMI audio infoframe for DP, called hdmi_audio_infoframe_pack_for_dp(). hdmi_audio_infoframe_pack_only() is split into two parts. One of them packs the payload only and can be used for HDMI and DP. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/video/hdmi.c | 83 ++++++++++++++++++++++++++++--------- include/drm/drm_dp_helper.h | 2 + include/linux/hdmi.h | 7 +++- 3 files changed, 72 insertions(+), 20 deletions(-) diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index 947be761dfa40..63e74d9fd210e 100644 --- a/drivers/video/hdmi.c +++ b/drivers/video/hdmi.c @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ =20 +#include #include #include #include @@ -381,12 +382,34 @@ static int hdmi_audio_infoframe_check_only(const stru= ct hdmi_audio_infoframe *fr * * Returns 0 on success or a negative error code on failure. */ -int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame) +int hdmi_audio_infoframe_check(const struct hdmi_audio_infoframe *frame) { return hdmi_audio_infoframe_check_only(frame); } EXPORT_SYMBOL(hdmi_audio_infoframe_check); =20 +static void +hdmi_audio_infoframe_pack_payload(const struct hdmi_audio_infoframe *frame, + u8 *buffer) +{ + u8 channels; + + if (frame->channels >=3D 2) + channels =3D frame->channels - 1; + else + channels =3D 0; + + buffer[0] =3D ((frame->coding_type & 0xf) << 4) | (channels & 0x7); + buffer[1] =3D ((frame->sample_frequency & 0x7) << 2) | + (frame->sample_size & 0x3); + buffer[2] =3D frame->coding_type_ext & 0x1f; + buffer[3] =3D frame->channel_allocation; + buffer[4] =3D (frame->level_shift_value & 0xf) << 3; + + if (frame->downmix_inhibit) + buffer[4] |=3D BIT(7); +} + /** * hdmi_audio_infoframe_pack_only() - write HDMI audio infoframe to binary= buffer * @frame: HDMI audio infoframe @@ -404,7 +427,6 @@ EXPORT_SYMBOL(hdmi_audio_infoframe_check); ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *= frame, void *buffer, size_t size) { - unsigned char channels; u8 *ptr =3D buffer; size_t length; int ret; @@ -420,28 +442,13 @@ ssize_t hdmi_audio_infoframe_pack_only(const struct h= dmi_audio_infoframe *frame, =20 memset(buffer, 0, size); =20 - if (frame->channels >=3D 2) - channels =3D frame->channels - 1; - else - channels =3D 0; - ptr[0] =3D frame->type; ptr[1] =3D frame->version; ptr[2] =3D frame->length; ptr[3] =3D 0; /* checksum */ =20 - /* start infoframe payload */ - ptr +=3D HDMI_INFOFRAME_HEADER_SIZE; - - ptr[0] =3D ((frame->coding_type & 0xf) << 4) | (channels & 0x7); - ptr[1] =3D ((frame->sample_frequency & 0x7) << 2) | - (frame->sample_size & 0x3); - ptr[2] =3D frame->coding_type_ext & 0x1f; - ptr[3] =3D frame->channel_allocation; - ptr[4] =3D (frame->level_shift_value & 0xf) << 3; - - if (frame->downmix_inhibit) - ptr[4] |=3D BIT(7); + hdmi_audio_infoframe_pack_payload(frame, + ptr + HDMI_INFOFRAME_HEADER_SIZE); =20 hdmi_infoframe_set_checksum(buffer, length); =20 @@ -479,6 +486,44 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_in= foframe *frame, } EXPORT_SYMBOL(hdmi_audio_infoframe_pack); =20 +/** + * hdmi_audio_infoframe_pack_for_dp - Pack a HDMI Audio infoframe for + * displayport + * + * @frame HDMI Audio infoframe + * @sdp secondary data packet for display port. This is filled with the + * appropriate data + * @dp_version Display Port version to be encoded in the header + * + * Packs a HDMI Audio Infoframe to be sent over Display Port. This function + * fills the secondary data packet to be used for Display Port. + * + * Return: Number of total written bytes or a negative errno on failure. + */ +ssize_t +hdmi_audio_infoframe_pack_for_dp(const struct hdmi_audio_infoframe *frame, + struct dp_sdp *sdp, u8 dp_version) +{ + int ret; + + ret =3D hdmi_audio_infoframe_check(frame); + if (ret) + return ret; + + memset(sdp->db, 0, sizeof(sdp->db)); + + // Secondary-data packet header + sdp->sdp_header.HB0 =3D 0; + sdp->sdp_header.HB1 =3D frame->type; + sdp->sdp_header.HB2 =3D DP_SDP_AUDIO_INFOFRAME_HB2; + sdp->sdp_header.HB3 =3D (dp_version & 0x3f) << 2; + + hdmi_audio_infoframe_pack_payload(frame, sdp->db); + + return frame->length + 4; +} +EXPORT_SYMBOL(hdmi_audio_infoframe_pack_for_dp); + /** * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe * @frame: HDMI vendor infoframe diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 30359e434c3f3..707927e3e773a 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1567,6 +1567,8 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw); #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ /* 0x80+ CEA-861 infoframe types */ =20 +#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b + /** * struct dp_sdp_header - DP secondary data packet header * @HB0: Secondary Data Packet ID diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index c8ec982ff4984..2f4dcc8d060e3 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -336,7 +336,12 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_in= foframe *frame, void *buffer, size_t size); ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *= frame, void *buffer, size_t size); -int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame); +int hdmi_audio_infoframe_check(const struct hdmi_audio_infoframe *frame); + +struct dp_sdp; +ssize_t +hdmi_audio_infoframe_pack_for_dp(const struct hdmi_audio_infoframe *frame, + struct dp_sdp *sdp, u8 dp_version); =20 enum hdmi_3d_structure { HDMI_3D_STRUCTURE_INVALID =3D -1, --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58ACDC433EF for ; Fri, 18 Feb 2022 14:56:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236451AbiBRO46 (ORCPT ); Fri, 18 Feb 2022 09:56:58 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236335AbiBRO4c (ORCPT ); Fri, 18 Feb 2022 09:56:32 -0500 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6F2D580DF for ; Fri, 18 Feb 2022 06:56:09 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id u1so15005411wrg.11 for ; Fri, 18 Feb 2022 06:56:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rl9GJMwANTs4ZJlwlTLAUM9iGOwBbNwdWImM77zNitM=; b=Hq1ej1mQ2MMxf1bH4FLzvR7tpbxNj+Ol/3YFedobT9BlNZW3XGnLfALtYMiNcrFzvx 6wfzxXM7ZKIwy8BWbif2XP0qliiTiU2SwVHwOoJ0MqJE6DuHFSclcfH5h4QjN8UtDm8T IIaoAVlt8blotwG4zd4GBZQgaMwNFiq47JQGj0VDHJmeFcNcGBTyYfvmV4e0IQKILwBT YihSV6M8YUNaWuEcTz5iv2sOHevL3jcuTZNiVFYuLPZHhY6LtP5DRie4iwTinXqSZKgv Mnorce5EopmKWsKgTqFd7XpUdJOS75xN0MyOPsv4qcw3iMagdkdhheMdVHy6NhAu549X 1/5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rl9GJMwANTs4ZJlwlTLAUM9iGOwBbNwdWImM77zNitM=; b=CVCQpjnvk/ci5Omky+U+XmCNDOkRpjn3PnV/XKfyqUiZbz6fkyhYMAXcUHf+NFdsI8 o0+Iewt0lpshB86L8KbnjqD+Ciq+rsLTs9JRNrmCoYfVTqgaz8HGZhPkAtI6NVIz87iq zqXxwsWOG7aoRzqJRAiShGtZPFwnQUdhXpX550TmexOxwKOJCeT9dsrwh8YZoLQKtqOD kX0E+QQh0RrnSMt5Gp99D66at4tppSvCFx4QzqTyGHGub7Pau1KWGtrhzwUU3giEE/rm VXuP423Cmmb7FOB1cqiigOHESSgAVpwBbEfNxRQIaBi0zFr33py+PkuM5USW3MMzNRTi 8kJA== X-Gm-Message-State: AOAM5308vrkUQYGp1d/zAsceyMiUYOsG+S5bV4dAIWv5KeJU8iXm2b0i v+0BlfM7/+TQgUnpXrIqErbj5A== X-Google-Smtp-Source: ABdhPJzLbEEfYgSHqBNDUq8sOQOCufmyh+U/0S0P0s5vcWkm4sqUVe7KIKtrF43MUbMyX5wJmXLcDQ== X-Received: by 2002:adf:ec07:0:b0:1e3:1ef2:5ff6 with SMTP id x7-20020adfec07000000b001e31ef25ff6mr6336681wrn.255.1645196168227; Fri, 18 Feb 2022 06:56:08 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:07 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 05/19] drm/mediatek: dpi: move dpi limits to board config Date: Fri, 18 Feb 2022 15:54:23 +0100 Message-Id: <20220218145437.18563-6-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dpi limits to the board config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4554e2de14309..4746eb3425674 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + const struct mtk_dpi_yc_limit *limit; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi= , u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } =20 -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit =3D dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); =20 - limit.c_bottom =3D 0x0010; - limit.c_top =3D 0x0FE0; - limit.y_bottom =3D 0x0010; - limit.y_top =3D 0x0FE0; - dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol =3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); =20 - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { + .c_bottom =3D 0x0010, + .c_top =3D 0x0FE0, + .y_bottom =3D 0x0010, + .y_top =3D 0x0FE0, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt2701_conf =3D { @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8183_conf =3D { @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8192_conf =3D { @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static int mtk_dpi_probe(struct platform_device *pdev) --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7FA7C433FE for ; Fri, 18 Feb 2022 14:56:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236482AbiBRO5C (ORCPT ); Fri, 18 Feb 2022 09:57:02 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236404AbiBRO4f (ORCPT ); Fri, 18 Feb 2022 09:56:35 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A78E858396 for ; Fri, 18 Feb 2022 06:56:11 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id i14so14999902wrc.10 for ; Fri, 18 Feb 2022 06:56:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=74eAjite1YksdGIU0aBC39Xndc2WIe2LazK2htC4zfk=; b=HoHQ/qui2T0BIpjk7uFcqqXA+59MESDkpbd4jX3EgaODmxpm8DiFx/ESXwZGyAm7RE +1bDYwDbtRQvInmytiZG0dsjPa/vfLvQs5U0w4A6CEGcMhHpe6uzZ3Z9WYSOwdDEaAXU Mm9G3C9lRiGVfEZ1jPX8BOq7Ja0JI7eqCXiURCVkjJ0au1AaTH1Pw2rxE/iVn4LA/yUw LK9M/DKvTdp/QUh+o/X0uigtfJ5viGx5t4yWya9hNiGWRmnkP8EWfwQ/SQKai9Nv3KQO dnDCiiHMZlTp1gMZC6jXc+5E/BKtvoaERTnqf+OUCAEUXWSMC+D2HYRqWaVuQw6YgWrO lDdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=74eAjite1YksdGIU0aBC39Xndc2WIe2LazK2htC4zfk=; b=J4l9odazNPP8Xj51JePNF1lE0aRYDPqj9SXNgBzqX+hVkeqz6zO+sh/H+8uO0utzZa QJXL1hAsgDh7iCtFL9hF50XTLSCYm0WQeH3AkkuopRGszLHICTMG8srjFTFnlt9DgCON gwxvxtxBrR04FcX5Dke6w4hCAurGAX4p2wJ9bdb7wYPCPdt9H6ASXpfCz5U5WQmu1Wv0 b9mcpT41veupsnq7LalEcbHAXLMzC+pE4oSSR9tYK1xItbAkSh3YvLFVM6ilctYUcLIg sS8BV0QFnkGGmeXksmybZ4zNZCqOxVtUy1qsWu5bRdmsZvc0FpksaqjINbohIWdujnC3 oQww== X-Gm-Message-State: AOAM5331Sr6YQLiTXmBmCxPfN3zJPArBC6JBo6+xEaTwwGY2GmIlGFJd 2U7qzG6jAHauL4r7uER6kTg56g== X-Google-Smtp-Source: ABdhPJykBR0WcjKdOJgGeDVbCzSmsQ2DzFr1mKmqIp5hyqDnSRTrae+KtQ1kIOkfZyByjJW30hC/7g== X-Received: by 2002:adf:9f45:0:b0:1e3:20e8:489a with SMTP id f5-20020adf9f45000000b001e320e8489amr6109613wrg.602.1645196170187; Fri, 18 Feb 2022 06:56:10 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:09 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 06/19] drm/mediatek: dpi: implement a CK/DE pol toggle in board config Date: Fri, 18 Feb 2022 15:54:24 +0100 Message-Id: <20220218145437.18563-7-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support boards without CK/DE pol support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4746eb3425674..545a1337cc899 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -211,13 +212,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask; =20 - pol =3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL)= | + mask =3D HSYNC_POL | VSYNC_POL; + pol =3D (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_PO= L) | (dpi_pol->vsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |=3D CK_POL | DE_POL; + pol |=3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); } =20 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -799,6 +807,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -809,6 +818,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -818,6 +828,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -827,6 +838,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62B5AC43217 for ; Fri, 18 Feb 2022 14:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234116AbiBRO5Y (ORCPT ); Fri, 18 Feb 2022 09:57:24 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236435AbiBRO4f (ORCPT ); Fri, 18 Feb 2022 09:56:35 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF192580CF for ; Fri, 18 Feb 2022 06:56:13 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id u2so13887637wrw.1 for ; Fri, 18 Feb 2022 06:56:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=05D+3SKZ7tKyXIjmuWnmBbAFic5DyC5nxoFhcmxTYHM=; b=XRVLtCA6bB2RENQ6zCTV2QK0fMPPuWQMd9PHjYs2TWXZ+/XIHN7/vUE0nW/8Sudo5L ixxyQe/plaAI+6zg7JFobruNHFdn+qRcrRo2T7p0v5CdmK+tfhqNcOgS35lwdQah+ds+ OQlk8nTP78vlPGMuwezHTJ1e4Eyomy7OMzZ6YfSwoSPzmPqobc5TfETm/nZu+Vw8TRDt q/NFNvbHzBv4sDjyf6VrG0aEFY3xjvydfdTo1eA496dSKUVmSLEV1LX2+kS0i4Z7of/B dEoOd1OZvv2mWWmmtF/J1GgEi3cGWh8Jw7oqBWBb/tLB1/DUOSWTLShdrc5bWKCbsH0K PL1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=05D+3SKZ7tKyXIjmuWnmBbAFic5DyC5nxoFhcmxTYHM=; b=FyvISIrhMUtzjhhGKrz+WGbzanWb+d56XPfoYsvMKnyP27jDiuf67bRoemshtuvLlV 2lSa4r4uz0X1o7H4mCzxOFi9F2bVKTWK2GFJVjuXf7h30K2Tp8wfGCAWN10S62Rm/B5Z REgE5D4BuQGejrkcUgktG01BqB5rb08GWVdI0V9H7mTR2Qsaa/bevXLW6qOfFWenXHir 769YDaOtLiQ1HyRrZwlfPv5N5cgotRnK9xVcy2kPKNv9KDppvDvypabJxEgd0olesVcJ KfndQ72eviPBRI/hr8D+CRQRmszaaqGYsG4eLKciGdzGfgJN2gb3b4YJOkG2HeqprsZ5 wKOQ== X-Gm-Message-State: AOAM530Zk6wUk/X81RcWZXxLdjV1OkzRUmDlMZkvKryT+P9K+H5SGuBs 46hOjdjvjZkUC9jtIzBsUVby/Q== X-Google-Smtp-Source: ABdhPJxzIJ4HeICGEQlbgAY6RhWstXxhrG+4xKFtg/DzjbljouSlndT3aFcLqryjNnjrzZMMpbND/w== X-Received: by 2002:a05:6000:257:b0:1e3:3a1b:d4ca with SMTP id m23-20020a056000025700b001e33a1bd4camr6305144wrz.112.1645196172298; Fri, 18 Feb 2022 06:56:12 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:11 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 07/19] drm/mediatek: dpi: implement a swap_input toggle in board config Date: Fri, 18 Feb 2022 15:54:25 +0100 Message-Id: <20220218145437.18563-8-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support boards without swap_input support Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 545a1337cc899..454f8563efae4 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -378,18 +379,21 @@ static void mtk_dpi_config_color_format(struct mtk_dp= i *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -808,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -819,6 +824,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +835,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +846,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B21E9C433FE for ; Fri, 18 Feb 2022 14:57:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236542AbiBRO5O (ORCPT ); Fri, 18 Feb 2022 09:57:14 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236443AbiBRO4f (ORCPT ); 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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:14 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 08/19] drm/mediatek: dpi: move dimension mask to board config Date: Fri, 18 Feb 2022 15:54:26 +0100 Message-Id: <20220218145437.18563-9-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dimension mask to the board config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 454f8563efae4..8ca3455ed64ee 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,8 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + // Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) + u32 dimension_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -156,30 +158,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); } =20 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } =20 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -813,6 +815,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -825,6 +828,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -847,6 +852,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; 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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:16 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 09/19] drm/mediatek: dpi: move dimension_mask to board config Date: Fri, 18 Feb 2022 15:54:27 +0100 Message-Id: <20220218145437.18563-10-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dimension mask to board config Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 8ca3455ed64ee..0d3acd08ea358 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_conf { bool swap_input_support; // Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) u32 dimension_mask; + // Mask used for HSIZE and VSIZE (no shift) + u32 hvsize_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -243,8 +245,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *d= pi, bool inter) =20 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 hei= ght) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); } =20 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -816,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -841,6 +847,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +860,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; 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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:18 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 10/19] drm/mediatek: dpi: move swap_shift to board config Date: Fri, 18 Feb 2022 15:54:28 +0100 Message-Id: <20220218145437.18563-11-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the swap shift value to board config Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 0d3acd08ea358..ec221e24e0fee 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_conf { u32 dimension_mask; // Mask used for HSIZE and VSIZE (no shift) u32 hvsize_mask; + u32 channel_swap_shift; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -349,7 +350,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, break; } =20 - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, + CH_SWAP_MASK << dpi->conf->channel_swap_shift); } =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -821,6 +823,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -835,6 +838,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -848,6 +852,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -861,6 +866,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19408C433EF for ; Fri, 18 Feb 2022 14:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236514AbiBRO6X (ORCPT ); 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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:20 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 11/19] drm/mediatek: dpi: move the yuv422_en_bit to board config Date: Fri, 18 Feb 2022 15:54:29 +0100 Message-Id: <20220218145437.18563-12-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the yuv422 en bit to board config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index ec221e24e0fee..fcf88dcd8b89d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_conf { // Mask used for HSIZE and VSIZE (no shift) u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -356,7 +357,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -824,6 +826,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +842,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +857,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -867,6 +872,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AACACC433F5 for ; Fri, 18 Feb 2022 14:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236251AbiBRO5n (ORCPT ); Fri, 18 Feb 2022 09:57:43 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236585AbiBRO46 (ORCPT ); Fri, 18 Feb 2022 09:56:58 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E30C9EBADB for ; Fri, 18 Feb 2022 06:56:24 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id x5so10181024wrg.13 for ; Fri, 18 Feb 2022 06:56:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4n+TZK7KbEUWOxLwDOr/TfxysKvgpkHmktiIGYd/K7I=; b=AYIJhoYSI/uBVyX7bKr0EN1LMOI9DxVA+XSltqNaOrt2mARRYDaY5J64JbYiCTP7IZ VKDnRnXSySg9ti8q2Gdd3ZT0Wyy7ynM+UAAvTdKD8U0Tlw/rdFU0Ax+Bl31KHyQvR6J+ ApEGo756/YXVILQcaJjKh6mpjgrnE6hH2BcxMa0PSZfAbZ1ii4qMye2ff32XGm+aMqWW I4JiP+ajubHk33IS1IZ3S8JjYTWhjCMn2KKcc8E9C8JUJwyz2G0tABN5GfQXUKJTkUEx lSLU6qH/VrjTJXGL8HJZcnUdu8gPP2xdjRyeQv76DPON8zKmYDxfu3kR4iYgimxYtDmD 9uRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4n+TZK7KbEUWOxLwDOr/TfxysKvgpkHmktiIGYd/K7I=; b=1BjisvhGpLq18m/7R6GTQO1AHK3PGwnSbklir12wM07NdyzbZtOhwMvxvypuQmjB8d nQJ2V758p9oqycuc+ZLyWAFhOg6nrGvGmVXCbn3Yk7A0eulEFuYqX7DJ1uFYjQUzUmDh tIYOmdsGZIzmAEC4AhMBDA90mV+xya9KXydUEE+NwBC6IDEA7HgI4SQRl0d0nOe1noHh E6t+qh7wK5rptEBnMtEynB9zghVOL0WtWJOM//oym+o1WdiFJQeq2zIFTDE6bg98MEBP qnKjjMo2vdRiuZWRpQIPa3jCYkpSqO5V+9ji7PLZcLx2c2d61tpCFAHT6Dd+uZiJMuN+ iUSA== X-Gm-Message-State: AOAM533Wbq04suJ9Bu4ld6SNcZc1owtiXn9W0DeyWZaUEiH1NU/FbDPV 9+JJon5HrVKHYqiv8MNRYMt5aA== X-Google-Smtp-Source: ABdhPJxA3E5twbEB2QJP6JHl07PRCaBz7TlkWHIbHPK96lIV8OG5te3hJNfKAZY7HiAKl5ltEPTi9Q== X-Received: by 2002:a05:6000:1a8c:b0:1e8:88ae:f908 with SMTP id f12-20020a0560001a8c00b001e888aef908mr6354423wry.532.1645196183454; Fri, 18 Feb 2022 06:56:23 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:23 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v8 12/19] drm/mediatek: dpi: move the csc_enable bit to board config Date: Fri, 18 Feb 2022 15:54:30 +0100 Message-Id: <20220218145437.18563-13-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the csc_enable bit to board config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index fcf88dcd8b89d..be99399faf1bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -133,6 +133,7 @@ struct mtk_dpi_conf { u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; + u32 csc_enable_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -363,7 +364,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi= *dpi, bool enable) =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); } =20 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -827,6 +829,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -843,6 +846,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -858,6 +862,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -873,6 +878,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B421FC433F5 for ; Fri, 18 Feb 2022 14:57:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236460AbiBRO6C (ORCPT ); Fri, 18 Feb 2022 09:58:02 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:52220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236486AbiBRO5C (ORCPT ); Fri, 18 Feb 2022 09:57:02 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F1E4B8B44 for ; Fri, 18 Feb 2022 06:56:27 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id k1so15029363wrd.8 for ; Fri, 18 Feb 2022 06:56:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z+CyanyxNzfsttxUn3F/dqOxuTwcblHV88TsdjsGQ8g=; b=qYqwJvoujRk2EBe65c5EsTZc86HUCGX77wz9ae8JBytiSO9rxBHEWWvOLIf4xbKBce Lv84f4LQMARD/Wd6ezyrmcTabTrOtmTPI1XszBJ25DGK9LSIlyTe5FuRF1+zxNSZNo7D 5TcSKtu1alA1mU1908wUFHYgNTLcSi6jiqjXRkEykj2iflAhw5RGDYtPR6uG8E5C0gJv PPenJRh2LPqR1f6vVXg+U+mODeYLELWCQavh8JRwJQ3W+Bwj8yrXew7wzzhywCMzCBPr bH1PiCOOaxGqSpnJYuZFLvnWVg0leiqsDqy/TUBefT0ElfA7Qu6/sjy3N6Hvf0gNhAkX QumQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z+CyanyxNzfsttxUn3F/dqOxuTwcblHV88TsdjsGQ8g=; b=TVjYt5merDJzRya00+utdYG4WEAi8YxBM1eZVH1XXVztVNqw+ouF4h9dot8khehCg/ yy/fPFPafxMclHCNEBb64bcYUViBxnOAuLL8cK+R72Q08svMIHHi5qJhstYCU0Q6V35C CCGXM2LcWhMyDM2NbKBSBvP1a0qyyUYmyHSNsQiYuEZDvFf8HjmEBv2IEc8RftDUY0R2 LmWqgWeYrjuq8Sg04+KQtszFmhlinl0ohzx3wmHkQQnsk7YyZbvJu4avaOyjlYk3lPb5 DIUfbOo33Yk5YWhwa7oQ95qvFBVCWR8k/7REOG/w3VhV44kdzGtc2TksW1Nj9e2M6kms wsKA== X-Gm-Message-State: AOAM533kbquF6IszaWoGJWN4I5NuF6jB+vUdx0IGQxkueUdL58dm3FR1 zfBmLCj3aT0HlZkw7RGwINr9fw== X-Google-Smtp-Source: ABdhPJxs7nxM6cFPO7E+zSl70tOgivGEwYl0sfgsEyIcTHcHpVoPO6BFogpwFT5VPMN/W3eVTuOrnQ== X-Received: by 2002:adf:c409:0:b0:1e7:be44:8dfa with SMTP id v9-20020adfc409000000b001e7be448dfamr6598796wrf.617.1645196185665; Fri, 18 Feb 2022 06:56:25 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:25 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH v8 13/19] drm/mediatek: dpi: Add dpintf support Date: Fri, 18 Feb 2022 15:54:31 +0100 Message-Id: <20220218145437.18563-14-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 164 +++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 38 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +- include/linux/soc/mediatek/mtk-mmsys.h | 2 + 6 files changed, 198 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index be99399faf1bb..c5639ada868f8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL }; =20 +enum TVDPLL_CLK { + TVDPLL_PLL =3D 0, + TVDPLL_D2 =3D 2, + TVDPLL_D4 =3D 4, + TVDPLL_D8 =3D 8, + TVDPLL_D16 =3D 16, +}; + struct mtk_dpi { struct drm_encoder encoder; struct drm_bridge bridge; @@ -71,8 +79,10 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *dpi_ck_cg; struct clk *pixel_clk; struct clk *tvd_clk; + struct clk *pclk_src[5]; int irq; struct drm_display_mode mode; const struct mtk_dpi_conf *conf; @@ -126,6 +136,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; // Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) u32 dimension_mask; @@ -384,6 +395,25 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi= *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } =20 +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, enum mtk_dpi_out_color= _format format) +{ + u32 matrix_sel =3D 0; + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <=3D 720) + matrix_sel =3D 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -391,6 +421,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -398,6 +429,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); @@ -438,6 +470,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_ck_cg); + clk_disable_unprepare(dpi->tvd_clk); } =20 static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -447,12 +481,24 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount !=3D 1) return 0; =20 + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_pixel; + } + ret =3D clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_refcount; } =20 + ret =3D clk_prepare_enable(dpi->dpi_ck_cg); + if (ret) { + dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n", ret); + goto err_ck_cg; + } + ret =3D clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -462,10 +508,11 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); =20 - mtk_dpi_enable(dpi); return 0; =20 err_pixel: + clk_disable_unprepare(dpi->dpi_ck_cg); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; @@ -497,12 +544,21 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, pll_rate =3D clk_get_rate(dpi->tvd_clk); =20 vm.pixelclock =3D pll_rate / factor; - if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + if (dpi->conf->is_dpintf) { + if (factor =3D=3D 1) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[2]); + else if (factor =3D=3D 2) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[3]); + else if (factor =3D=3D 4) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[4]); + else + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[2]); + } else if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -515,9 +571,15 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width =3D vm.hsync_len; - hsync.back_porch =3D vm.hback_porch; - hsync.front_porch =3D vm.hfront_porch; + if (dpi->conf->is_dpintf) { + hsync.sync_width =3D vm.hsync_len / 4; + hsync.back_porch =3D vm.hback_porch / 4; + hsync.front_porch =3D vm.hfront_porch / 4; + } else { + hsync.sync_width =3D vm.hsync_len; + hsync.back_porch =3D vm.hback_porch; + hsync.front_porch =3D vm.hfront_porch; + } hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -559,13 +621,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 + mtk_dpi_enable(dpi); + return 0; } =20 @@ -608,7 +677,6 @@ static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(st= ruct drm_bridge *bridge, u32 *input_fmts; =20 *num_input_fmts =3D 0; - input_fmts =3D kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); if (!input_fmts) @@ -634,15 +702,18 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bri= dge *bridge, if (dpi->conf->num_output_fmts) out_bus_format =3D dpi->conf->output_fmts[0]; =20 - dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", - bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); + dev_info(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); =20 dpi->output_fmt =3D out_bus_format; dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } @@ -687,7 +758,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); =20 - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -801,6 +872,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -810,6 +891,12 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { .c_bottom =3D 0x0010, .c_top =3D 0x0FE0, @@ -817,6 +904,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D= { .y_top =3D 0x0FE0, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpintf_limit =3D { + .c_bottom =3D 0x0000, + .c_top =3D 0xFFF, + .y_bottom =3D 0x0000, + .y_top =3D 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -882,6 +976,19 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .limit =3D &mtk_dpi_limit, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .limit =3D &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -929,7 +1036,18 @@ static int mtk_dpi_probe(struct platform_device *pdev) if (IS_ERR(dpi->engine_clk)) { ret =3D PTR_ERR(dpi->engine_clk); if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "Failed to get engine clock: %d\n", ret); + dev_err(dev, "Failed to get engine clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg =3D devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret =3D PTR_ERR(dpi->dpi_ck_cg); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", + ret); =20 return ret; } @@ -952,6 +1070,11 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; } =20 + dpi->pclk_src[1] =3D devm_clk_get(dev, "TVDPLL_D2"); + dpi->pclk_src[2] =3D devm_clk_get(dev, "TVDPLL_D4"); + dpi->pclk_src[3] =3D devm_clk_get(dev, "TVDPLL_D8"); + dpi->pclk_src[4] =3D devm_clk_get(dev, "TVDPLL_D16"); + dpi->irq =3D platform_get_irq(pdev, 0); if (dpi->irq <=3D 0) return -EINVAL; @@ -1004,6 +1127,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe16627..91b32dfffced2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,15 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP BIT(1) #define CH_SWAP_MASK (0x7 << 0) +#define DPINTF_CH_SWAP_MASK (0x7 << 1) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 #define SWAP_BRG 0x02 @@ -80,8 +85,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +100,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +230,29 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL BIT(0) +#define INT_MATRIX_SEL_MASK (0x1F << 0) +#define RGB_TO_JPEG 0x00 +#define RGB_TO_FULL709 0x01 +#define RGB_TO_BT601 0x02 +#define RGB_TO_BT709 0x03 +#define JPEG_TO_RGB 0x04 +#define FULL709_TO_RGB 0x05 +#define BT601_TO_RGB 0x06 +#define BT709_TO_RGB 0x07 +#define JPEG_TO_BT601 0x08 +#define JPEG_TO_BT709 0x09 +#define BT601_TO_JPEG 0xA +#define BT709_TO_JPEG 0xB +#define BT709_TO_BT601 0xC +#define BT601_TO_BT709 0xD +#define JPEG_TO_CERGB 0x14 +#define FULL709_TO_CERGB 0x15 +#define BT601_TO_CERGB 0x16 +#define BT709_TO_CERGB 0x17 +#define RGB_TO_CERGB 0x1C +#define MATRIX_BIT BIT(8) +#define EXT_MATRIX_EN BIT(12) #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index b4b682bc19913..e8bd6fd4a63d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -351,6 +351,11 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_CO= MP_TYPE_MAX] =3D { [MTK_DISP_WDMA] =3D "wdma", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", + [MTK_DP_INTF] =3D "dp-intf", + [MTK_DISP_PWM] =3D "pwm", + [MTK_DISP_MUTEX] =3D "mutex", + [MTK_DISP_OD] =3D "od", + [MTK_DISP_BLS] =3D "bls", }; =20 struct mtk_ddp_comp_match { @@ -369,6 +374,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_ID_MAX] =3D { [DDP_COMPONENT_DITHER] =3D { MTK_DISP_DITHER, 0, &ddp_dither }, [DDP_COMPONENT_DPI0] =3D { MTK_DPI, 0, &ddp_dpi }, [DDP_COMPONENT_DPI1] =3D { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -513,6 +520,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 4c6a986623051..deda70df1d6d9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 56ff8c57ef8fd..e00ab6410db74 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -511,6 +511,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -611,7 +613,8 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_RDMA || comp_type =3D=3D MTK_DPI || - comp_type =3D=3D MTK_DSI) { + comp_type =3D=3D MTK_DPI || + comp_type =3D=3D MTK_DP_INTF) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 4bba275e235ac..56ed2fa5f59e8 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -19,6 +19,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DITHER, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1FF1C433EF for ; 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[2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:27 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH v8 14/19] phy: phy-mtk-dp: Add driver for DP phy Date: Fri, 18 Feb 2022 15:54:32 +0100 Message-Id: <20220218145437.18563-15-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This is a new driver that supports the integrated DisplayPort phy for mediatek SoCs, especially the mt8195. The phy is integrated into the DisplayPort controller and will be created by the mtk-dp driver. This driver expects a struct regmap to be able to work on the same registers as the DisplayPort controller. It sets the device data to be the struct phy so that the DisplayPort controller can easily work with it. The driver does not have any devicetree bindings because the datasheet does not list the controller and the phy as distinct units. The interaction with the controller can be covered by the configure callback of the phy framework and its displayport parameters. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 8 ++ drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-dp.c | 199 ++++++++++++++++++++++++++++++ 4 files changed, 209 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-dp.c diff --git a/MAINTAINERS b/MAINTAINERS index fca970a46e77a..33a05d396dd03 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6467,6 +6467,7 @@ L: linux-mediatek@lists.infradead.org (moderated for = non-subscribers) S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ +F: drivers/phy/mediatek/phy-mtk-dp.c F: drivers/phy/mediatek/phy-mtk-hdmi* F: drivers/phy/mediatek/phy-mtk-mipi* =20 diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 55f8e6c048ab3..f7ec860590492 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -55,3 +55,11 @@ config PHY_MTK_MIPI_DSI select GENERIC_PHY help Support MIPI DSI for Mediatek SoCs. + +config PHY_MTK_DP + tristate "MediaTek DP-PHY Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Support DisplayPort PHY for Mediatek SoCs. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index ace660fbed3a1..4ba1e06504346 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -3,6 +3,7 @@ # Makefile for the phy drivers. # =20 +obj-$(CONFIG_PHY_MTK_DP) +=3D phy-mtk-dp.o obj-$(CONFIG_PHY_MTK_TPHY) +=3D phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) +=3D phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) +=3D phy-mtk-xsphy.o diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c new file mode 100644 index 0000000000000..2841dd3f22543 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 BayLibre + * Author: Markus Schneider-Pargmann + */ + +#include +#include +#include +#include +#include +#include + +#define PHY_OFFSET 0x1000 + +#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x014) +#define TPLL_SSC_EN BIT(3) + +#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x03C) +#define BIT_RATE_RBR 0 +#define BIT_RATE_HBR 1 +#define BIT_RATE_HBR2 2 +#define BIT_RATE_HBR3 3 + +#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x038) +#define DP_GLB_SW_RST_PHYD BIT(0) + +#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) +#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) +#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) +#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438) +#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT 0x10 +#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (0x14 << 8) +#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT (0x18 << 16) +#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT (0x20 << 24) +#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT 0x18 +#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT (0x1e << 8) +#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (0x24 << 16) +#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT (0x20 << 24) +#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT 0x28 +#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT (0x30 << 8) +#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0x00 +#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT (0x04 << 8) +#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT (0x08 << 16) +#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT (0x10 << 24) +#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0x00 +#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT (0x06 << 8) +#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT (0x0c << 16) +#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT (0x00 << 24) +#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT 0x08 +#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT (0x00 << 8) +#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) + +struct mtk_dp_phy { + struct regmap *regs; +}; + +static int mtk_dp_phy_init(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + u32 driving_params[] =3D { + DRIVING_PARAM_3_DEFAULT, + DRIVING_PARAM_4_DEFAULT, + DRIVING_PARAM_5_DEFAULT, + DRIVING_PARAM_6_DEFAULT, + DRIVING_PARAM_7_DEFAULT, + DRIVING_PARAM_8_DEFAULT + }; + + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + + return 0; +} + +static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts = *opts) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + u32 val; + + if (opts->dp.set_rate) { + switch (opts->dp.link_rate) { + default: + dev_err(&phy->dev, + "Implementation error, unknown linkrate %x\n", + opts->dp.link_rate); + return -EINVAL; + case 1620: + val =3D BIT_RATE_RBR; + break; + case 2700: + val =3D BIT_RATE_HBR; + break; + case 5400: + val =3D BIT_RATE_HBR2; + break; + case 8100: + val =3D BIT_RATE_HBR3; + break; + } + regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); + } + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, + TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); + + return 0; +} + +static int mtk_dp_phy_reset(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 0); + usleep_range(50, 200); + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 1); + + return 0; +} + +static const struct phy_ops mtk_dp_phy_dev_ops =3D { + .init =3D mtk_dp_phy_init, + .configure =3D mtk_dp_phy_configure, + .reset =3D mtk_dp_phy_reset, + .owner =3D THIS_MODULE, +}; + +static int mtk_dp_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_dp_phy *dp_phy; + struct phy *phy; + + dp_phy =3D devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); + if (!dp_phy) + return -ENOMEM; + + dp_phy->regs =3D *(struct regmap **)dev->platform_data; + if (!dp_phy->regs) { + dev_err(dev, "No data passed, requires struct regmap**\n"); + return -EINVAL; + } + + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create DP PHY: %ld\n", PTR_ERR(phy)); + return PTR_ERR(phy); + } + phy_set_drvdata(phy, dp_phy); + + if (!dev->of_node) + phy_create_lookup(phy, "dp", dev_name(dev)); + + return 0; +} + +struct platform_driver mtk_dp_phy_driver =3D { + .probe =3D mtk_dp_phy_probe, + .driver =3D { + .name =3D "mediatek-dp-phy", + }, +}; +module_platform_driver(mtk_dp_phy_driver); + +MODULE_AUTHOR("Markus Schneider-Pargmann "); +MODULE_DESCRIPTION("MediaTek DP PHY Driver"); +MODULE_LICENSE("GPL v2"); --=20 2.34.1 From nobody Sun Sep 22 07:48:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94120C433EF for ; Fri, 18 Feb 2022 14:57:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235317AbiBRO57 (ORCPT ); Fri, 18 Feb 2022 09:57:59 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:53062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236636AbiBRO5Y (ORCPT ); Fri, 18 Feb 2022 09:57:24 -0500 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50B91DF22 for ; Fri, 18 Feb 2022 06:56:32 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id az26-20020a05600c601a00b0037c078db59cso6590817wmb.4 for ; Fri, 18 Feb 2022 06:56:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pNtYQ1NW9bgMsck7uEE80Ot9MecVkmXTw0bgiCTpcoM=; b=nSBiQn7Mfd16j/2beXMfkG2ybwxldftfXm3yzgNGqw8ezPhXtxOpTekhI4WyHbu1DC SOWFFQVM4op6Q0kr0NOcDgtIsgT/uvgDWuMwFcydZsXTVfCumgpANUzeREXjQO3/rO/k OHFeApylTQR/qY2+W7ceqrOyqHR2E10MbSrlXTT90EjhDfFjbsO87mB0/1TlfzTz4qsc t+NfqWnNQzJpjWK1t7JAetvmLVRceKpBeIl7GPHehci9Ps0GZcNuAWY8PZwjx/m5Yn9o OdG4xjVzInM7pqN/pF2tJLNn2jtsf1eevn4zMJMdM0PVX8t6w0V+CCJ2Irrc6IYKu7Tg NpCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pNtYQ1NW9bgMsck7uEE80Ot9MecVkmXTw0bgiCTpcoM=; b=ysqtGbno5a+CID+k1PVI+Om/PVTqkRlajoaVDaFLUafDGO3s/Uq6jZE+Tve85bSJPX J8fDdyuF7Jv0eLzUX16CedpSkuSy/+ODJBBJwl3+0gXeMbK/P1yvlx7t/HJ2EX2tWApx dWv+Kicg32OIeHUBphtbMCcFj2fr0tbQrU6Os14LDj5pDHci1kk00eFP1fssAK+F8nRW Fk5E2ZvA5piPCp+uSzOzzWDWqnvczZFVYWkvPiLrevwmgziMlcJ5cny4juDooJh9KhIL lFWAgJnkQEgZxaojAu+LmujY+DBlTbMyogP2yzpZ0rjqVPpelf/TjLfsxP2IDvVUxTKu YOaQ== X-Gm-Message-State: AOAM531xdUhUwu2OaBjNKNCXs/FQ409JW+5B5+hnU7kc3btVkYL1uS2t smjqRbiKv0A3Ra/aTQ2BLjPybA== X-Google-Smtp-Source: ABdhPJyvo+b5+QA2e8LIHv0Uf/gFIz15SR24+HMRZDjiBiDxgzTHtblAHhPCc+vMlxpJTgB6NaMlrg== X-Received: by 2002:a05:600c:4f83:b0:37c:d057:3efe with SMTP id n3-20020a05600c4f8300b0037cd0573efemr10819492wmq.143.1645196190327; Fri, 18 Feb 2022 06:56:30 -0800 (PST) Received: from localhost.localdomain (2a02-8440-6241-3b28-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6241:3b28:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id b10sm47431454wrd.8.2022.02.18.06.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 06:56:29 -0800 (PST) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, Markus Schneider-Pargmann , kernel test robot Subject: [PATCH v8 15/19] drm/mediatek: Add mt8195 Embedded DisplayPort driver Date: Fri, 18 Feb 2022 15:54:33 +0100 Message-Id: <20220218145437.18563-16-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218145437.18563-1-granquet@baylibre.com> References: <20220218145437.18563-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. It supports the mt8195, the embedded DisplayPort units. It offers hot-plug-detection and DisplayPort 1.4 with up to 4 lanes. The driver creates a child device for the phy. The child device will never exist without the parent being active. As they are sharing a register range, the parent passes a regmap pointer to the child so that both can work with the same register range. The phy driver sets device data that is read by the parent to get the phy device that can be used to control the phy properties. This driver is based on an initial version by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reported-by: kernel test robot --- drivers/gpu/drm/mediatek/Kconfig | 7 + drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_dp.c | 2358 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dp_reg.h | 568 ++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 2937 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kc= onfig index 2976d21e9a34a..029b94c716131 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -28,3 +28,10 @@ config DRM_MEDIATEK_HDMI select PHY_MTK_HDMI help DRM/KMS HDMI driver for Mediatek SoCs + +config MTK_DPTX_SUPPORT + tristate "DRM DPTX Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select PHY_MTK_DP + help + DRM/KMS Display Port driver for Mediatek SoCs. diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index 29098d7c8307c..d86a6406055e6 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -21,3 +21,5 @@ mediatek-drm-hdmi-objs :=3D mtk_cec.o \ mtk_hdmi_ddc.o =20 obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mediatek-drm-hdmi.o + +obj-$(CONFIG_MTK_DPTX_SUPPORT) +=3D mtk_dp.o diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c new file mode 100644 index 0000000000000..5b60293ecc0d3 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -0,0 +1,2358 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2021 BayLibre + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include