From nobody Sat Jun 27 23:19:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0775C433EF for ; Fri, 18 Feb 2022 12:16:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235070AbiBRMRO (ORCPT ); Fri, 18 Feb 2022 07:17:14 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:58768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233930AbiBRMRM (ORCPT ); Fri, 18 Feb 2022 07:17:12 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8D0828ADBB; Fri, 18 Feb 2022 04:16:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645186613; x=1676722613; h=from:to:cc:subject:date:message-id:mime-version; bh=jo9RXuWk9+zTcvMEjwT0ZCRUnTvpVEE6zSwU3xjPQ/I=; b=bTzBfVL/REsG68T8FJQOCPHWo4buHalbltTLn5vnlhFxmIkMpxmA1o+A /buWD0Uo2lMOt3SUsKipEh9pHUBvoH32xW0AfKBRtA9y2to2SRSHTzkYG J9zDaq9B4zC0J+8Hn6KfFmKem8N5oQ+Om4oPEIAHQvEgPBYGq21mEC2mR hIulpvsiVhiVpNS27XShj3y/ZgaJBaN/fG9U/oobGQv9tEFly8DH3Fsys Z+g+T3rNr9b37LpPdH3knfclG3K3AVMImGD3ts+lFiP/ks1u7PPknwKdh rQQcv5GIxziLr2d3oSGl1S3vy8ur69ZSuP1CqYlMfyldoAZTQP7ba5gtk Q==; X-IronPort-AV: E=Sophos;i="5.88,378,1635231600"; d="scan'208";a="149211524" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2022 05:16:52 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 18 Feb 2022 05:16:52 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 18 Feb 2022 05:16:47 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , , , Subject: [PATCH v6] ARM: dts: add DT for lan966 SoC and 2-port board pcb8291 Date: Fri, 18 Feb 2022 17:46:41 +0530 Message-ID: <20220218121641.26472-1-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds basic DT for Microchip lan966x SoC and associated board pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG and MCAN0. Signed-off-by: Kavyasree Kotagiri --- v5 -> v6: - Renamed dts file to lan966x-pcb8291.dts file. - Disabled optional watchdog in dtsi file and enabled it in dts file. v4 -> v5: - Modified AES, SHA, TRNG node names as per generic names recommended. v3 -> v4: - Removed character 'x' from compatible string. - Removed memory node as handled by bootloader. - Renamed flexcom3 usart0 to usart3 - Added /chosen and /aliases nodes in dts file. v2 -> v3: - Enabling trng in dtsi itself. - Removed "status=3Dokay" dma0. - Add gpio pin settings for can0(missed adding this in previous version) v1 -> v2: - Moved flx3 usart0 node to dtsi file. - Removed status=3D"okay" for dma0 to maintain consistency across nodes (which means enabling dma0 by default) arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/lan966x-pcb8291.dts | 64 +++++++ arch/arm/boot/dts/lan966x.dtsi | 238 ++++++++++++++++++++++++++ 3 files changed, 304 insertions(+) create mode 100644 arch/arm/boot/dts/lan966x-pcb8291.dts create mode 100644 arch/arm/boot/dts/lan966x.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..c17a7308ff44 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) +=3D \ dtb-$(CONFIG_SOC_IMX7ULP) +=3D \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_LAN966) +=3D \ + lan966x-pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) +=3D \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan9= 66x-pcb8291.dts new file mode 100644 index 000000000000..3281af90ac6d --- /dev/null +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8291.dts - Device Tree file for PCB8291 + */ +/dts-v1/; +#include "lan966x.dtsi" + +/ { + model =3D "Microchip EVB - LAN9662"; + compatible =3D "microchip,lan9662-pcb8291", "microchip,lan9662", "microch= ip,lan966"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + serial0 =3D &usart3; + }; +}; + +&gpio { + fc_shrd7_pins: fc_shrd7-pins { + pins =3D "GPIO_49"; + function =3D "fc_shrd7"; + }; + + fc_shrd8_pins: fc_shrd8-pins { + pins =3D "GPIO_54"; + function =3D "fc_shrd8"; + }; + + fc3_b_pins: fcb3-spi-pins { + /* SCK, RXD, TXD */ + pins =3D "GPIO_51", "GPIO_52", "GPIO_53"; + function =3D "fc3_b"; + }; + + can0_b_pins: can0_b_pins { + /* RX, TX */ + pins =3D "GPIO_35", "GPIO_36"; + function =3D "can0_b"; + }; +}; + +&can0 { + pinctrl-0 =3D <&can0_b_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&flx3 { + atmel,flexcom-mode =3D ; + status =3D "okay"; + + usart3: serial@200 { + pinctrl-0 =3D <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + }; +}; + +&watchdog { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi new file mode 100644 index 000000000000..10ffe78110ff --- /dev/null +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Kavyasree Kotagiri + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + model =3D "Microchip LAN966 family SoC"; + compatible =3D "microchip,lan966"; + interrupt-parent =3D <&gic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + clock-frequency =3D <600000000>; + reg =3D <0x0>; + }; + }; + + clocks { + sys_clk: sys_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <162500000>; + }; + + cpu_clk: cpu_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <600000000>; + }; + + ddr_clk: ddr_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <300000000>; + }; + + nic_clk: nic_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + }; + }; + + clks: clock-controller@e00c00a8 { + compatible =3D "microchip,lan966x-gck"; + #clock-cells =3D <1>; + clocks =3D <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names =3D "cpu", "ddr", "sys"; + reg =3D <0xe00c00a8 0x38>; + }; + + timer { + compatible =3D "arm,armv7-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + clock-frequency =3D <37500000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + flx0: flexcom@e0040000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xe0040000 0x100>; + clocks =3D <&clks GCK_ID_FLEXCOM0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0040000 0x800>; + status =3D "disabled"; + }; + + flx1: flexcom@e0044000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xe0044000 0x100>; + clocks =3D <&clks GCK_ID_FLEXCOM1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0044000 0x800>; + status =3D "disabled"; + }; + + trng: rng@e0048000 { + compatible =3D "atmel,at91sam9g45-trng"; + reg =3D <0xe0048000 0x100>; + clocks =3D <&nic_clk>; + }; + + aes: crypto@e004c000 { + compatible =3D "atmel,at91sam9g46-aes"; + reg =3D <0xe004c000 0x100>; + interrupts =3D ; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(13)>, + <&dma0 AT91_XDMAC_DT_PERID(12)>; + dma-names =3D "rx", "tx"; + clocks =3D <&nic_clk>; + clock-names =3D "aes_clk"; + }; + + flx2: flexcom@e0060000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xe0060000 0x100>; + clocks =3D <&clks GCK_ID_FLEXCOM2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0060000 0x800>; + status =3D "disabled"; + }; + + flx3: flexcom@e0064000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xe0064000 0x100>; + clocks =3D <&clks GCK_ID_FLEXCOM3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0064000 0x800>; + status =3D "disabled"; + + usart3: serial@200 { + compatible =3D "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + clocks =3D <&nic_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + }; + + dma0: dma-controller@e0068000 { + compatible =3D "microchip,sama7g5-dma"; + reg =3D <0xe0068000 0x1000>; + interrupts =3D ; + #dma-cells =3D <1>; + clocks =3D <&nic_clk>; + clock-names =3D "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible =3D "atmel,at91sam9g46-sha"; + reg =3D <0xe006c000 0xec>; + interrupts =3D ; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(14)>; + dma-names =3D "tx"; + clocks =3D <&nic_clk>; + clock-names =3D "sha_clk"; + }; + + flx4: flexcom@e0070000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xe0070000 0x100>; + clocks =3D <&clks GCK_ID_FLEXCOM4>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0070000 0x800>; + status =3D "disabled"; + }; + + timer0: timer@e008c000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xe008c000 0x400>; + clocks =3D <&nic_clk>; + clock-names =3D "timer"; + interrupts =3D ; + }; + + watchdog: watchdog@e0090000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0xe0090000 0x1000>; + interrupts =3D ; + clocks =3D <&nic_clk>; + status =3D "disabled"; + }; + + can0: can@e081c000 { + compatible =3D "bosch,m_can"; + reg =3D <0xe081c000 0xfc>, <0x00100000 0x4000>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + clocks =3D <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&clks GCK_ID_MCAN0>; + assigned-clock-rates =3D <40000000>; + bosch,mram-cfg =3D <0x0 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + gpio: pinctrl@e2004064 { + compatible =3D "microchip,lan966x-pinctrl"; + reg =3D <0xe2004064 0xb4>, + <0xe2010024 0x138>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&gpio 0 0 78>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + gic: interrupt-controller@e8c11000 { + compatible =3D "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells =3D <3>; + interrupts =3D ; + interrupt-controller; + reg =3D <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>, + <0xe8c14000 0x2000>, + <0xe8c16000 0x2000>; + }; + }; +}; --=20 2.17.1