From nobody Sun Sep 22 09:38:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D60BC433EF for ; Fri, 18 Feb 2022 09:18:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233451AbiBRJSr (ORCPT ); Fri, 18 Feb 2022 04:18:47 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233324AbiBRJRX (ORCPT ); Fri, 18 Feb 2022 04:17:23 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53F671A3AE; Fri, 18 Feb 2022 01:17:00 -0800 (PST) X-UUID: 62b20fe046c7480682628e4aee4377f7-20220218 X-UUID: 62b20fe046c7480682628e4aee4377f7-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1862070054; Fri, 18 Feb 2022 17:16:58 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:56 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes Date: Fri, 18 Feb 2022 17:16:32 +0800 Message-ID: <20220218091633.9368-23-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add gce info for display nodes. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 1f1555fd18f5..df884c48669e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1226,6 +1226,9 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8192-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; #clock-cells =3D <1>; }; =20 @@ -1234,6 +1237,8 @@ reg =3D <0 0x14001000 0 0x1000>; interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events =3D , + ; }; =20 smi_common: smi@14002000 { @@ -1275,6 +1280,7 @@ iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; }; =20 ovl_2l0: ovl@14006000 { @@ -1285,6 +1291,7 @@ clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; }; =20 rdma0: rdma@14007000 { @@ -1296,6 +1303,7 @@ mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <5120>; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; }; =20 color0: color@14009000 { @@ -1305,6 +1313,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; =20 ccorr0: ccorr@1400a000 { @@ -1313,6 +1322,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; =20 aal0: aal@1400b000 { @@ -1321,6 +1331,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; =20 gamma0: gamma@1400c000 { @@ -1330,6 +1341,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; =20 postmask0: postmask@1400d000 { @@ -1339,6 +1351,7 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; iommus =3D <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; =20 dither0: dither@1400e000 { @@ -1348,6 +1361,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 dsi0: dsi@14010000 { @@ -1371,6 +1385,7 @@ clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; =20 rdma4: rdma@14015000 { @@ -1381,6 +1396,7 @@ clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; mediatek,rdma-fifo-size =3D <2048>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; =20 dpi0: dpi@14016000 { --=20 2.18.0