From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77786C433EF for ; Fri, 18 Feb 2022 09:17:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233322AbiBRJRc (ORCPT ); Fri, 18 Feb 2022 04:17:32 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233204AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74FEB10FC7; Fri, 18 Feb 2022 01:16:45 -0800 (PST) X-UUID: c669cd9a74da4a49a946962a501f6aa2-20220218 X-UUID: c669cd9a74da4a49a946962a501f6aa2-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1132822781; Fri, 18 Feb 2022 17:16:38 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:37 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller Date: Fri, 18 Feb 2022 17:16:11 +0800 Message-ID: <20220218091633.9368-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power domains controller node for SoC mt8192. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index c1d4030e7e4b..f10a9c75b20c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -301,6 +302,206 @@ #interrupt-cells =3D <2>; }; =20 + scpsys: syscon@10006000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0 0x10006000 0 0x1000>; + #power-domain-cells =3D <1>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8192-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domain of the SoC */ + power-domain@MT8192_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>; + clock-names =3D "audio", "audio1", "audio2"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CONN { + reg =3D ; + clocks =3D <&infracfg CLK_INFRA_PMIC_CONN>; + clock-names =3D "conn"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MFG_PLL_SEL>; + clock-names =3D "mfg"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG1 { + reg =3D ; + mediatek,infracfg =3D <&infracfg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG2 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG3 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG4 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG5 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG6 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_DISP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_DISP_SEL>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names =3D "disp", "disp-0", "disp-1", "disp-2", + "disp-3"; + mediatek,infracfg =3D <&infracfg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8192_POWER_DOMAIN_IPE { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_IPE_SEL>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + clock-names =3D "ipe", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_IMG1_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names =3D "isp", "isp-0", "isp-1"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP2 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_IMG2_SEL>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + clock-names =3D "isp2", "isp2-0", "isp2-1"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MDP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MDP_SEL>, + <&mdpsys CLK_MDP_SMI0>; + clock-names =3D "mdp", "mdp-0"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VENC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_VENC_SEL>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names =3D "venc", "venc-0"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VDEC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names =3D "vdec", "vdec-0", "vdec-1", "vdec-2"; + mediatek,infracfg =3D <&infracfg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8192_POWER_DOMAIN_VDEC2 { + reg =3D ; + clocks =3D <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names =3D "vdec2-0", "vdec2-1", + "vdec2-2"; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CAM_SEL>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + clock-names =3D "cam", "cam-0", "cam-1", "cam-2", + "cam-3"; + mediatek,infracfg =3D <&infracfg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { + reg =3D ; + clocks =3D <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names =3D "cam_rawa-0"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { + reg =3D ; + clocks =3D <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names =3D "cam_rawb-0"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { + reg =3D ; + clocks =3D <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names =3D "cam_rawc-0"; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible =3D "mediatek,mt8192-wdt"; reg =3D <0 0x10007000 0 0x100>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61D46C433EF for ; Fri, 18 Feb 2022 09:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233331AbiBRJR2 (ORCPT ); Fri, 18 Feb 2022 04:17:28 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233189AbiBRJRE (ORCPT ); Fri, 18 Feb 2022 04:17:04 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E437DF6C; Fri, 18 Feb 2022 01:16:42 -0800 (PST) X-UUID: d5d5884ceb6a406193bdb7633dc466e5-20220218 X-UUID: d5d5884ceb6a406193bdb7633dc466e5-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1739811868; Fri, 18 Feb 2022 17:16:40 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:38 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 02/23] arm64: dts: mt8192: Add pwrap node Date: Fri, 18 Feb 2022 17:16:12 +0800 Message-ID: <20220218091633.9368-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pwrap node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index f10a9c75b20c..f58a13b10916 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names =3D "clk13m"; }; =20 + pwrap: pwrap@10026000 { + compatible =3D "mediatek,mt6873-pwrap"; + reg =3D <0 0x10026000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names =3D "spi", "wrap"; + assigned-clocks =3D <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECECC43219 for ; Fri, 18 Feb 2022 09:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233221AbiBRJRL (ORCPT ); Fri, 18 Feb 2022 04:17:11 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231174AbiBRJRE (ORCPT ); Fri, 18 Feb 2022 04:17:04 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CCD410FC3; Fri, 18 Feb 2022 01:16:44 -0800 (PST) X-UUID: a839d78433cf4f749193635138fe89aa-20220218 X-UUID: a839d78433cf4f749193635138fe89aa-20220218 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1573464550; Fri, 18 Feb 2022 17:16:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:39 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 03/23] arm64: dts: mt8192: Add spmi node Date: Fri, 18 Feb 2022 17:16:13 +0800 Message-ID: <20220218091633.9368-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add spmi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index f58a13b10916..8635c8a53472 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -535,6 +535,23 @@ assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; }; =20 + spmi: spmi@10027000 { + compatible =3D "mediatek,mt6873-spmi"; + reg =3D <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names =3D "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks =3D <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73946C433FE for ; Fri, 18 Feb 2022 09:17:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233260AbiBRJRP (ORCPT ); Fri, 18 Feb 2022 04:17:15 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233188AbiBRJRE (ORCPT ); Fri, 18 Feb 2022 04:17:04 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC3C610FD9; Fri, 18 Feb 2022 01:16:47 -0800 (PST) X-UUID: ea24ec52d4c949aebf453e56e417182b-20220218 X-UUID: ea24ec52d4c949aebf453e56e417182b-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 681940819; Fri, 18 Feb 2022 17:16:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:40 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node Date: Fri, 18 Feb 2022 17:16:14 +0800 Message-ID: <20220218091633.9368-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add gce node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 8635c8a53472..f92d8d7afa5d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; #include +#include #include #include #include @@ -552,6 +553,15 @@ #size-cells =3D <0>; }; =20 + gce: mailbox@10228000 { + compatible =3D "mediatek,mt8192-gce"; + reg =3D <0 0x10228000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <3>; + clocks =3D <&infracfg CLK_INFRA_GCE>; + clock-names =3D "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89589C433FE for ; Fri, 18 Feb 2022 09:17:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233391AbiBRJRi (ORCPT ); Fri, 18 Feb 2022 04:17:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233206AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF90610FD3; Fri, 18 Feb 2022 01:16:46 -0800 (PST) X-UUID: cc8e84ada6ee4ed1b0682d9c0650bae8-20220218 X-UUID: cc8e84ada6ee4ed1b0682d9c0650bae8-20220218 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1367642337; Fri, 18 Feb 2022 17:16:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:41 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 05/23] arm64: dts: mt8192: Add SCP node Date: Fri, 18 Feb 2022 17:16:15 +0800 Message-ID: <20220218091633.9368-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SCP node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index f92d8d7afa5d..61aadd7bd397 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -706,6 +706,18 @@ status =3D "disabled"; }; =20 + scp: scp@10500000 { + compatible =3D "mediatek,mt8192-scp"; + reg =3D <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names =3D "sram", "l1tcm", "cfg"; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_SCPSYS>; + clock-names =3D "main"; + status =3D "disabled"; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB1CCC4332F for ; Fri, 18 Feb 2022 09:17:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233265AbiBRJRS (ORCPT ); Fri, 18 Feb 2022 04:17:18 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233191AbiBRJRE (ORCPT ); Fri, 18 Feb 2022 04:17:04 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EC8610FD0; Fri, 18 Feb 2022 01:16:45 -0800 (PST) X-UUID: 51e70bfc7d81466a93378d5b037a31d9-20220218 X-UUID: 51e70bfc7d81466a93378d5b037a31d9-20220218 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 94939064; Fri, 18 Feb 2022 17:16:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:42 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node Date: Fri, 18 Feb 2022 17:16:16 +0800 Message-ID: <20220218091633.9368-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 61aadd7bd397..ce18d692175f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -875,6 +875,31 @@ #clock-cells =3D <1>; }; =20 + u3phy0: usb-phy@11e40000 { + compatible =3D "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "okay"; + + u2port0: usb-phy@11e40000 { + reg =3D <0 0x11e40000 0 0x700>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + status =3D "okay"; + }; + + u3port0: usb-phy@11e40700 { + reg =3D <0 0x11e40700 0 0x900>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + status =3D "okay"; + }; + }; + i2c0: i2c@11f00000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11f00000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06FCDC433EF for ; Fri, 18 Feb 2022 09:17:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233308AbiBRJRz (ORCPT ); Fri, 18 Feb 2022 04:17:55 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233210AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BE359FEC; Fri, 18 Feb 2022 01:16:47 -0800 (PST) X-UUID: 86e917ff7ed84f6db4a002e8c7d860fc-20220218 X-UUID: 86e917ff7ed84f6db4a002e8c7d860fc-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1594865135; Fri, 18 Feb 2022 17:16:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:43 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 07/23] arm64: dts: mt8192: Add xhci node Date: Fri, 18 Feb 2022 17:16:17 +0800 Message-ID: <20220218091633.9368-8-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index ce18d692175f..08c7c1c772f5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include =20 / { @@ -718,6 +719,30 @@ status =3D "disabled"; }; =20 + xhci: xhci@11200000 { + compatible =3D "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "host"; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names =3D "sys_ck", "xhci_ck", "ref_ck"; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg 0x420 102>; + #address-cells =3D <2>; + #size-cells =3D <2>; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97B4DC433EF for ; Fri, 18 Feb 2022 09:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233301AbiBRJRW (ORCPT ); Fri, 18 Feb 2022 04:17:22 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233193AbiBRJRG (ORCPT ); Fri, 18 Feb 2022 04:17:06 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CBF810FE5; Fri, 18 Feb 2022 01:16:48 -0800 (PST) X-UUID: dce69bfac27c49e7b5243bfa4ba95afc-20220218 X-UUID: dce69bfac27c49e7b5243bfa4ba95afc-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1732226255; Fri, 18 Feb 2022 17:16:44 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:44 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 08/23] arm64: dts: mt8192: Add audio-related nodes Date: Fri, 18 Feb 2022 17:16:18 +0800 Message-ID: <20220218091633.9368-9-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add audio-related nodes in audsys for mt8192 SoC. Move audsys node in ascending order. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++- 1 file changed, 129 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 08c7c1c772f5..f93fe3779161 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -743,6 +743,135 @@ #size-cells =3D <2>; }; =20 + audsys: syscon@11210000 { + compatible =3D "mediatek,mt8192-audsys", "syscon"; + reg =3D <0 0x11210000 0 0x2000>; + #clock-cells =3D <1>; + + afe: mt8192-afe-pcm { + compatible =3D "mediatek,mt8192-audio"; + interrupts =3D ; + resets =3D <&watchdog 17>; + reset-names =3D "audiosys"; + mediatek,apmixedsys =3D <&apmixedsys>; + mediatek,infracfg =3D <&infracfg>; + mediatek,topckgen =3D <&topckgen>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_AUDIO>; + clocks =3D <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&audsys CLK_AUD_ADC>, + <&audsys CLK_AUD_ADDA6_ADC>, + <&audsys CLK_AUD_22M>, + <&audsys CLK_AUD_24M>, + <&audsys CLK_AUD_APLL_TUNER>, + <&audsys CLK_AUD_APLL2_TUNER>, + <&audsys CLK_AUD_TDM>, + <&audsys CLK_AUD_TML>, + <&audsys CLK_AUD_NLE>, + <&audsys CLK_AUD_DAC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES_TML>, + <&audsys CLK_AUD_ADDA6_ADC_HIRES>, + <&audsys CLK_AUD_3RD_DAC>, + <&audsys CLK_AUD_3RD_DAC_PREDIS>, + <&audsys CLK_AUD_3RD_DAC_TML>, + <&audsys CLK_AUD_3RD_DAC_HIRES>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_MAINPLL_D4_D4>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&topckgen CLK_TOP_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&topckgen CLK_TOP_APLL12_DIV5>, + <&topckgen CLK_TOP_APLL12_DIV6>, + <&topckgen CLK_TOP_APLL12_DIV7>, + <&topckgen CLK_TOP_APLL12_DIV8>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_AUDIO_H_SEL>, + <&clk26m>; + clock-names =3D "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adda6_adc_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_tdm_clk", + "aud_tml_clk", + "aud_nle", + "aud_dac_hires_clk", + "aud_adc_hires_clk", + "aud_adc_hires_tml", + "aud_adda6_adc_hires_clk", + "aud_3rd_dac_clk", + "aud_3rd_dac_predis_clk", + "aud_3rd_dac_tml", + "aud_3rd_dac_hires_clk", + "aud_infra_clk", + "aud_infra_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d4_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d4", + "top_mux_aud_eng2", + "top_apll2_d4", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_i2s6_m_sel", + "top_i2s7_m_sel", + "top_i2s8_m_sel", + "top_i2s9_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_apll12_div5", + "top_apll12_div6", + "top_apll12_div7", + "top_apll12_div8", + "top_apll12_div9", + "top_mux_audio_h", + "top_clk26m_clk"; + }; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; @@ -758,12 +887,6 @@ status =3D "disable"; }; =20 - audsys: clock-controller@11210000 { - compatible =3D "mediatek,mt8192-audsys", "syscon"; - reg =3D <0 0x11210000 0 0x1000>; - #clock-cells =3D <1>; - }; - i2c3: i2c@11cb0000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11cb0000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D340C433EF for ; Fri, 18 Feb 2022 09:17:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233303AbiBRJRl (ORCPT ); Fri, 18 Feb 2022 04:17:41 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233209AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0AFF11175; Fri, 18 Feb 2022 01:16:50 -0800 (PST) X-UUID: 8c74edc5be4d4c7cbc3def0e3364168e-20220218 X-UUID: 8c74edc5be4d4c7cbc3def0e3364168e-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1013492680; Fri, 18 Feb 2022 17:16:46 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:45 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:45 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node Date: Fri, 18 Feb 2022 17:16:19 +0800 Message-ID: <20220218091633.9368-10-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" add infracfg_rst node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index f93fe3779161..a935a22babbb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -267,10 +268,23 @@ #clock-cells =3D <1>; }; =20 - infracfg: syscon@10001000 { - compatible =3D "mediatek,mt8192-infracfg", "syscon"; + infracfg: infracfg@10001000 { + compatible =3D "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + + infracfg_rst: reset-controller { + compatible =3D "ti,syscon-reset"; + #reset-cells =3D <1>; + + ti,reset-bits =3D < + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: l= vts_ap */ + 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1:= lvts_mcu */ + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2:= pcie phy */ + 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: p= cie top */ + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: s= vs */ + >; + }; }; =20 pericfg: syscon@10003000 { --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50896C433F5 for ; Fri, 18 Feb 2022 09:17:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233281AbiBRJRv (ORCPT ); Fri, 18 Feb 2022 04:17:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233208AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0CB71117E; Fri, 18 Feb 2022 01:16:50 -0800 (PST) X-UUID: cf2f7da9140d4f098cc3b515a4a63132-20220218 X-UUID: cf2f7da9140d4f098cc3b515a4a63132-20220218 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1742451437; Fri, 18 Feb 2022 17:16:47 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:45 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 10/23] arm64: dts: mt8192: Add PCIe node Date: Fri, 18 Feb 2022 17:16:20 +0800 Message-ID: <20220218091633.9368-11-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a935a22babbb..4533c794effc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -886,6 +886,44 @@ }; }; =20 + pcie: pcie@11230000 { + compatible =3D "mediatek,mt8192-pcie"; + device_type =3D "pci"; + reg =3D <0 0x11230000 0 0x2000>; + reg-names =3D "pcie-mac"; + #address-cells =3D <3>; + #size-cells =3D <2>; + clocks =3D <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>, + <&infracfg CLK_INFRA_PCIE_PL_P_250M>; + clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", + "obff_ck0", "axi_ck0", "pipe_ck0"; + assigned-clocks =3D <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D6_D4>; + resets =3D <&infracfg_rst 2>, + <&infracfg_rst 3>; + reset-names =3D "phy", "mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F1F9C433F5 for ; Fri, 18 Feb 2022 09:17:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233340AbiBRJR6 (ORCPT ); Fri, 18 Feb 2022 04:17:58 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233218AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D3DE11C24; Fri, 18 Feb 2022 01:16:51 -0800 (PST) X-UUID: 57bca648af1f4ba3808584a3d836b386-20220218 X-UUID: 57bca648af1f4ba3808584a3d836b386-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 468450769; Fri, 18 Feb 2022 17:16:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:46 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 11/23] arm64: dts: mt8192: Correct nor_flash status of mt8192 Date: Fri, 18 Feb 2022 17:16:21 +0800 Message-ID: <20220218091633.9368-12-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Correct nor_flash status of mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 4533c794effc..f51fd0f6c356 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -936,7 +936,7 @@ assigned-clock-parents =3D <&clk26m>; #address-cells =3D <1>; #size-cells =3D <0>; - status =3D "disable"; + status =3D "disabled"; }; =20 i2c3: i2c@11cb0000 { --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AB59C433F5 for ; Fri, 18 Feb 2022 09:17:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233129AbiBRJSF (ORCPT ); Fri, 18 Feb 2022 04:18:05 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233220AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6579211C29; Fri, 18 Feb 2022 01:16:52 -0800 (PST) X-UUID: 87846e3da7314d85821a6381634438b1-20220218 X-UUID: 87846e3da7314d85821a6381634438b1-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 189519421; Fri, 18 Feb 2022 17:16:49 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:47 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 12/23] arm64: dts: mt8192: Add efuse node Date: Fri, 18 Feb 2022 17:16:22 +0800 Message-ID: <20220218091633.9368-13-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add efuse node for mt8192 SoC Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index f51fd0f6c356..094805db395b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -939,6 +939,20 @@ status =3D "disabled"; }; =20 + efuse: efuse@11c10000 { + compatible =3D "mediatek,efuse"; + reg =3D <0 0x11c10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_e_data1: data1 { + reg =3D <0x1C0 0x58>; + }; + svs_calibration: calib@580 { + reg =3D <0x580 0x68>; + }; + }; + i2c3: i2c@11cb0000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11cb0000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D94BAC433FE for ; Fri, 18 Feb 2022 09:17:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233358AbiBRJSK (ORCPT ); Fri, 18 Feb 2022 04:18:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233232AbiBRJRM (ORCPT ); Fri, 18 Feb 2022 04:17:12 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CADC10FD0; Fri, 18 Feb 2022 01:16:54 -0800 (PST) X-UUID: fae9cd7c560b4e168fd4f3cab55fe57e-20220218 X-UUID: fae9cd7c560b4e168fd4f3cab55fe57e-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1348336215; Fri, 18 Feb 2022 17:16:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:48 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes Date: Fri, 18 Feb 2022 17:16:23 +0800 Message-ID: <20220218091633.9368-14-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mmc nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++--- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 094805db395b..cfc2db501108 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1154,10 +1154,38 @@ #clock-cells =3D <1>; }; =20 - msdc: clock-controller@11f60000 { - compatible =3D "mediatek,mt8192-msdc"; - reg =3D <0 0x11f60000 0 0x1000>; - #clock-cells =3D <1>; + mmc0: mmc@11f60000 { + compatible =3D "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11f60000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>; + clock-names =3D "source", "hclk", "source_cg", "sys_cg", + "axi_cg", "ahb_cg", "pclk_cg"; + status =3D "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible =3D "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11f70000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>; + clock-names =3D "source", "hclk", "source_cg", "sys_cg", + "axi_cg", "ahb_cg", "pclk_cg"; + status =3D "disabled"; }; =20 mfgcfg: clock-controller@13fbf000 { --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B779DC433F5 for ; Fri, 18 Feb 2022 09:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233366AbiBRJSB (ORCPT ); Fri, 18 Feb 2022 04:18:01 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233195AbiBRJRK (ORCPT ); Fri, 18 Feb 2022 04:17:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6907512628; Fri, 18 Feb 2022 01:16:53 -0800 (PST) X-UUID: ed695d1ebde8408181d8632c57bf6e3a-20220218 X-UUID: ed695d1ebde8408181d8632c57bf6e3a-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 403941676; Fri, 18 Feb 2022 17:16:50 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:49 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node Date: Fri, 18 Feb 2022 17:16:24 +0800 Message-ID: <20220218091633.9368-15-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index cfc2db501108..f5e5af949f19 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1114,6 +1114,16 @@ }; }; =20 + mipi_tx0: mipi-dphy@11e50000 { + compatible =3D "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11e50000 0 0x1000>; + clocks =3D <&apmixedsys CLK_APMIXED_MIPID26M>; + clock-names =3D "ref_clk"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + }; + i2c0: i2c@11f00000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11f00000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62EB1C433F5 for ; Fri, 18 Feb 2022 09:18:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233463AbiBRJSQ (ORCPT ); Fri, 18 Feb 2022 04:18:16 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233226AbiBRJRM (ORCPT ); Fri, 18 Feb 2022 04:17:12 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D324412748; Fri, 18 Feb 2022 01:16:53 -0800 (PST) X-UUID: d720707021ec4b6d8d1a3f6c79e9cba5-20220218 X-UUID: d720707021ec4b6d8d1a3f6c79e9cba5-20220218 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 15230339; Fri, 18 Feb 2022 17:16:52 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:50 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes Date: Fri, 18 Feb 2022 17:16:25 +0800 Message-ID: <20220218091633.9368-16-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add m4u and smi nodes for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index f5e5af949f19..40887120fdb3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -1210,24 +1211,114 @@ #clock-cells =3D <1>; }; =20 + smi_common: smi@14002000 { + compatible =3D "mediatek,mt8192-smi-common"; + reg =3D <0 0x14002000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names =3D "apb", "smi", "gals0", "gals1"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,larb-id =3D <0>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,larb-id =3D <1>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + iommu0: m4u@1401d000 { + compatible =3D "mediatek,mt8192-m4u"; + reg =3D <0 0x1401d000 0 0x1000>; + mediatek,larbs =3D <&larb0 &larb1 &larb2 + &larb4 &larb5 &larb7 + &larb9 &larb11 &larb13 + &larb14 &larb16 &larb17 + &larb18 &larb19 &larb20>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_SMI_IOMMU>; + clock-names =3D "bclk"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells =3D <1>; + }; + imgsys: clock-controller@15020000 { compatible =3D "mediatek,mt8192-imgsys"; reg =3D <0 0x15020000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb9: larb@1502e000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1502e000 0 0x1000>; + mediatek,larb-id =3D <9>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP>; + }; + imgsys2: clock-controller@15820000 { compatible =3D "mediatek,mt8192-imgsys2"; reg =3D <0 0x15820000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb11: larb@1582e000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1582e000 0 0x1000>; + mediatek,larb-id =3D <11>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1600d000 0 0x1000>; + mediatek,larb-id =3D <5>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + vdecsys_soc: clock-controller@1600f000 { compatible =3D "mediatek,mt8192-vdecsys_soc"; reg =3D <0 0x1600f000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb4: larb@1602e000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1602e000 0 0x1000>; + mediatek,larb-id =3D <4>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + vdecsys: clock-controller@1602f000 { compatible =3D "mediatek,mt8192-vdecsys"; reg =3D <0 0x1602f000 0 0x1000>; @@ -1240,12 +1331,79 @@ #clock-cells =3D <1>; }; =20 + larb7: larb@17010000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x17010000 0 0x1000>; + mediatek,larb-id =3D <7>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8192-camsys"; reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb13: larb@1a001000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a001000 0 0x1000>; + mediatek,larb-id =3D <13>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a002000 0 0x1000>; + mediatek,larb-id =3D <14>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a00f000 0 0x1000>; + mediatek,larb-id =3D <16>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names =3D "apb", "smi"; + mediatek,smi-id =3D <16>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a010000 0 0x1000>; + mediatek,larb-id =3D <17>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a011000 0 0x1000>; + mediatek,larb-id =3D <18>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible =3D "mediatek,mt8192-camsys_rawa"; reg =3D <0 0x1a04f000 0 0x1000>; @@ -1270,10 +1428,43 @@ #clock-cells =3D <1>; }; =20 + larb20: larb@1b00f000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1b00f000 0 0x1000>; + mediatek,larb-id =3D <20>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1b10f000 0 0x1000>; + mediatek,larb-id =3D <19>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_IPE>; + }; + mdpsys: clock-controller@1f000000 { compatible =3D "mediatek,mt8192-mdpsys"; reg =3D <0 0x1f000000 0 0x1000>; #clock-cells =3D <1>; }; + + larb2: larb@1f002000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1f002000 0 0x1000>; + mediatek,larb-id =3D <2>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; + }; }; }; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1817C433F5 for ; Fri, 18 Feb 2022 09:17:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233380AbiBRJSN (ORCPT ); Fri, 18 Feb 2022 04:18:13 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233237AbiBRJRM (ORCPT ); Fri, 18 Feb 2022 04:17:12 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B9B610FF4; Fri, 18 Feb 2022 01:16:54 -0800 (PST) X-UUID: 93edd37a171b480d82978a523621782a-20220218 X-UUID: 93edd37a171b480d82978a523621782a-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 884860929; Fri, 18 Feb 2022 17:16:52 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:51 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 16/23] arm64: dts: mt8192: Add H264 venc device node Date: Fri, 18 Feb 2022 17:16:26 +0800 Message-ID: <20220218091633.9368-17-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds H264 venc node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 40887120fdb3..936aa788664f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1342,6 +1342,29 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_VENC>; }; =20 + vcodec_enc: vcodec@0x17020000 { + compatible =3D "mediatek,mt8192-vcodec-enc"; + reg =3D <0 0x17020000 0 0x2000>; + iommus =3D <&iommu0 M4U_PORT_L7_VENC_RCPU>, + <&iommu0 M4U_PORT_L7_VENC_REC>, + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; + interrupts =3D ; + mediatek,scp =3D <&scp>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VENC>; + clocks =3D <&vencsys CLK_VENC_SET1_VENC>; + clock-names =3D "venc-set1"; + assigned-clocks =3D <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8192-camsys"; reg =3D <0 0x1a000000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37225C433F5 for ; Fri, 18 Feb 2022 09:18:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232880AbiBRJS0 (ORCPT ); Fri, 18 Feb 2022 04:18:26 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233248AbiBRJRN (ORCPT ); Fri, 18 Feb 2022 04:17:13 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFE4D9FEC; Fri, 18 Feb 2022 01:16:56 -0800 (PST) X-UUID: cc028a83800b49e99bc316c9ab689c23-20220218 X-UUID: cc028a83800b49e99bc316c9ab689c23-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 21078361; Fri, 18 Feb 2022 17:16:52 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:52 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes Date: Fri, 18 Feb 2022 17:16:27 +0800 Message-ID: <20220218091633.9368-18-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 936aa788664f..543a80252ce5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1291,6 +1291,64 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; }; =20 + vcodec_dec: vcodec_dec@16000000 { + compatible =3D "mediatek,mt8192-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + mediatek,scp =3D <&scp>; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + }; + + vcodec_lat: vcodec_lat@0x16010000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x16010000 0 0x800>; /* VDEC_MISC */ + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec= ", + "vdec-top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec_core@0x16025000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec= ", + "vdec-top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + larb5: larb@1600d000 { compatible =3D "mediatek,mt8192-smi-larb"; reg =3D <0 0x1600d000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F71FC433EF for ; Fri, 18 Feb 2022 09:18:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233485AbiBRJSX (ORCPT ); Fri, 18 Feb 2022 04:18:23 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233267AbiBRJRP (ORCPT ); Fri, 18 Feb 2022 04:17:15 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9487111C24; Fri, 18 Feb 2022 01:16:57 -0800 (PST) X-UUID: 4cf62379aeb949e08644145c6d69fcec-20220218 X-UUID: 4cf62379aeb949e08644145c6d69fcec-20220218 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1864312812; Fri, 18 Feb 2022 17:16:54 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:53 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 18/23] arm64: dts: mt8192: Add dpi node Date: Fri, 18 Feb 2022 17:16:28 +0800 Message-ID: <20220218091633.9368-19-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 543a80252ce5..55bcbf72a366 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1242,6 +1242,16 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 + dpi0: dpi@14016000 { + compatible =3D "mediatek,mt8192-dpi"; + reg =3D <0 0x14016000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names =3D "pixel", "engine", "pll"; + }; + iommu0: m4u@1401d000 { compatible =3D "mediatek,mt8192-m4u"; reg =3D <0 0x1401d000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A97B3C433F5 for ; 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Fri, 18 Feb 2022 17:16:54 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:54 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 19/23] arm64: dts: mt8192: Add i2c aliases Date: Fri, 18 Feb 2022 17:16:29 +0800 Message-ID: <20220218091633.9368-20-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add i2c aliases for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 55bcbf72a366..e3314cdc7c1a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -21,6 +21,19 @@ #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + i2c9 =3D &i2c9; + }; + clk26m: oscillator0 { compatible =3D "fixed-clock"; #clock-cells =3D <0>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A251FC433FE for ; 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Fri, 18 Feb 2022 17:16:55 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:54 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes Date: Fri, 18 Feb 2022 17:16:30 +0800 Message-ID: <20220218091633.9368-21-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index e3314cdc7c1a..026f2d8141b0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -32,6 +32,11 @@ i2c7 =3D &i2c7; i2c8 =3D &i2c8; i2c9 =3D &i2c9; + ovl0 =3D &ovl0; + ovl-2l0 =3D &ovl_2l0; + ovl-2l2 =3D &ovl_2l2; + rdma0 =3D &rdma0; + rdma4 =3D &rdma4; }; =20 clk26m: oscillator0 { @@ -1224,6 +1229,13 @@ #clock-cells =3D <1>; }; =20 + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8192-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + }; + smi_common: smi@14002000 { compatible =3D "mediatek,mt8192-smi-common"; reg =3D <0 0x14002000 0 0x1000>; @@ -1255,6 +1267,109 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 + ovl0: ovl@14005000 { + compatible =3D "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + ovl_2l0: ovl@14006000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14006000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8192-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + iommus =3D <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,larb =3D <&larb0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + color0: color@14009000 { + compatible =3D "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400a000 { + compatible =3D "mediatek,mt8192-disp-ccorr"; + reg =3D <0 0x1400a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@1400b000 { + compatible =3D "mediatek,mt8192-disp-aal"; + reg =3D <0 0x1400b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@1400c000 { + compatible =3D "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x1400c000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + postmask0: postmask@1400d000 { + compatible =3D "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400d000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + iommus =3D <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + }; + + dither0: dither@1400e000 { + compatible =3D "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x1400e000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + }; + + ovl_2l2: ovl@14014000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + }; + + rdma4: rdma@14015000 { + compatible =3D "mediatek,mt8192-disp-rdma"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; + iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size =3D <2048>; + }; + dpi0: dpi@14016000 { compatible =3D "mediatek,mt8192-dpi"; reg =3D <0 0x14016000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ED95C433F5 for ; Fri, 18 Feb 2022 09:18:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233469AbiBRJS7 (ORCPT ); Fri, 18 Feb 2022 04:18:59 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233188AbiBRJRR (ORCPT ); Fri, 18 Feb 2022 04:17:17 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F91E10FF9; Fri, 18 Feb 2022 01:16:59 -0800 (PST) X-UUID: 9c929ed809f443ac99cb348187ab6c65-20220218 X-UUID: 9c929ed809f443ac99cb348187ab6c65-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 70572379; Fri, 18 Feb 2022 17:16:56 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:55 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 21/23] arm64: dts: mt8192: Add dsi node Date: Fri, 18 Feb 2022 17:16:31 +0800 Message-ID: <20220218091633.9368-22-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dsi ndoe for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 026f2d8141b0..1f1555fd18f5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1350,6 +1350,19 @@ clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; }; =20 + dsi0: dsi@14010000 { + compatible =3D "mediatek,mt8183-dsi"; + reg =3D <0 0x14010000 0 0x1000>; + interrupts =3D ; + mediatek,syscon-dsi =3D <&mmsys 0x140>; + clocks =3D <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + }; + ovl_2l2: ovl@14014000 { compatible =3D "mediatek,mt8192-disp-ovl-2l"; reg =3D <0 0x14014000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D60BC433EF for ; Fri, 18 Feb 2022 09:18:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233451AbiBRJSr (ORCPT ); Fri, 18 Feb 2022 04:18:47 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233324AbiBRJRX (ORCPT ); Fri, 18 Feb 2022 04:17:23 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53F671A3AE; Fri, 18 Feb 2022 01:17:00 -0800 (PST) X-UUID: 62b20fe046c7480682628e4aee4377f7-20220218 X-UUID: 62b20fe046c7480682628e4aee4377f7-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1862070054; Fri, 18 Feb 2022 17:16:58 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:56 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 22/23] arm64: dts: mt8192: Add gce info for display nodes Date: Fri, 18 Feb 2022 17:16:32 +0800 Message-ID: <20220218091633.9368-23-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add gce info for display nodes. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 1f1555fd18f5..df884c48669e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1226,6 +1226,9 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8192-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; #clock-cells =3D <1>; }; =20 @@ -1234,6 +1237,8 @@ reg =3D <0 0x14001000 0 0x1000>; interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events =3D , + ; }; =20 smi_common: smi@14002000 { @@ -1275,6 +1280,7 @@ iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; }; =20 ovl_2l0: ovl@14006000 { @@ -1285,6 +1291,7 @@ clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; }; =20 rdma0: rdma@14007000 { @@ -1296,6 +1303,7 @@ mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <5120>; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; }; =20 color0: color@14009000 { @@ -1305,6 +1313,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; =20 ccorr0: ccorr@1400a000 { @@ -1313,6 +1322,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; =20 aal0: aal@1400b000 { @@ -1321,6 +1331,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; =20 gamma0: gamma@1400c000 { @@ -1330,6 +1341,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; =20 postmask0: postmask@1400d000 { @@ -1339,6 +1351,7 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; iommus =3D <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; =20 dither0: dither@1400e000 { @@ -1348,6 +1361,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 dsi0: dsi@14010000 { @@ -1371,6 +1385,7 @@ clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; =20 rdma4: rdma@14015000 { @@ -1381,6 +1396,7 @@ clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; mediatek,rdma-fifo-size =3D <2048>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; =20 dpi0: dpi@14016000 { --=20 2.18.0 From nobody Sun Sep 22 07:46:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 199B4C433F5 for ; Fri, 18 Feb 2022 09:18:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232573AbiBRJSz (ORCPT ); Fri, 18 Feb 2022 04:18:55 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233314AbiBRJRZ (ORCPT ); Fri, 18 Feb 2022 04:17:25 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 020201D334; Fri, 18 Feb 2022 01:17:05 -0800 (PST) X-UUID: 0d04cbee63d6418d80cc3d063b58a05a-20220218 X-UUID: 0d04cbee63d6418d80cc3d063b58a05a-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1942008424; Fri, 18 Feb 2022 17:17:00 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:58 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node Date: Fri, 18 Feb 2022 17:16:33 +0800 Message-ID: <20220218091633.9368-24-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index df884c48669e..c0fc723fdf0a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -642,6 +642,16 @@ status =3D "disabled"; }; =20 + pwm0: pwm@1100e000 { + compatible =3D "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + #pwm-cells =3D <2>; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names =3D "main", "mm"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; --=20 2.18.0