From nobody Sun Jun 28 00:17:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A71CC433FE for ; Thu, 17 Feb 2022 18:08:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243990AbiBQSI1 (ORCPT ); Thu, 17 Feb 2022 13:08:27 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:33190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239522AbiBQSIZ (ORCPT ); Thu, 17 Feb 2022 13:08:25 -0500 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8418615DB28; Thu, 17 Feb 2022 10:08:10 -0800 (PST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21HFRgDa025670; Thu, 17 Feb 2022 10:08:05 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=8jG0tqM0e9p6vsriO0mMsEIgAm5bCPAtrYKjjQkIC3k=; b=Zid9lCd/kOQrOmDpisLc+w2PFH2QeAv8Vd4SNUiNfo8fiFmwksSRmbB2aMntUf74RopT SEDsPihdy3HUhTN26iW60Ucgbc1nxj0jFCY9aUUtladXsz4E3Frgv2MNsovv8rhaQvFP 2qdouLv2MruXJ5UrV5ePEJzq80hdYC0RYlatk+v6EMvTeTKiOYLlGB8YWeC9/8Td13it 0vd/dQrlmV6RNE689ofz9ZribAosvjCRfDnYgtDqgaSenzUuFO1Lh3mi+0j/n3rED7bw 0DIX3PXuAEWLpwpbCtr/wYWw+oNAmdcekKoM7kEl0l9lZdfMdAX0wJ0LIV+r+P55cOfm qg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e9kktt4f1-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 10:08:05 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 17 Feb 2022 10:08:03 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 17 Feb 2022 10:08:03 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 91E873F70F6; Thu, 17 Feb 2022 10:05:02 -0800 (PST) From: Rakesh Babu Saladi To: , , , , , , , CC: Harman Kalra , Rakesh Babu Saladi Subject: [net-next PATCH 1/3] octeontx2-af: Sending tsc value to the userspace Date: Thu, 17 Feb 2022 23:34:48 +0530 Message-ID: <20220217180450.21721-2-rsaladi2@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220217180450.21721-1-rsaladi2@marvell.com> References: <20220217180450.21721-1-rsaladi2@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7viX9QoLE_bdUrflCwdPygosvPotoUkO X-Proofpoint-GUID: 7viX9QoLE_bdUrflCwdPygosvPotoUkO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_06,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Harman Kalra This patch updates the existing PTP_OP_GET_CLOCK mbox message to return timestamp counter value, tsc (cntvct_el0 or pmccntr_el0) along with the PTP HI clock value. In some debugging scenarios user might need to read the PTP HI clock value in the fastpath, so as to know how many ticks have been spent till point from the reception of the packet, as packet reception tick value is already appended to the packet by CGX. If directly PTP_OP_GET_CLOCK mbox message is sent every time user wants to record PTP HI clock value, it will bring down the performance to a great extent as mbox is a very expensive process. To handle this PTP HI clock can be derived from timestamp counter (tsc, which could be running at 100MHz or system freq) using two parameters freq multiplier (ratio of frequencies of PTP HI clock and tsc) and clock delta (by how much tsc is lagging from PTP HI clock). During configuration stage these parameters are calculated freq_mult =3D (freq of PTP HI clock)/(freq of tsc counter) clk_delta =3D (PTP_HI clock value / freq_mult) - (tsc val) these PTP_HI val and tsc value are receieved by calling PTP_OP_GET_CLOCK. Purpose of returing tsc at the same time with PTP_HI value is to avoid mbox propagation delay. Now whenever user wants to know PTP HI clock, it can be derived from tsc counter and returned: PTP_HI val =3D (tsc value + clk_delta) * freq_mult Signed-off-by: Harman Kalra Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Rakesh Babu Saladi --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 2 ++ .../net/ethernet/marvell/octeontx2/af/ptp.c | 25 ++++++++++++++++--- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 550cb11197bf..2be11062ec33 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1451,12 +1451,14 @@ struct ptp_req { struct mbox_msghdr hdr; u8 op; s64 scaled_ppm; + u8 is_pmu; u64 thresh; }; struct ptp_rsp { struct mbox_msghdr hdr; u64 clk; + u64 tsc; }; struct set_vf_perm { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/= ethernet/marvell/octeontx2/af/ptp.c index e682b7bfde64..211c375446f4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c @@ -114,10 +114,28 @@ static int ptp_adjfine(struct ptp *ptp, long scaled_p= pm) return 0; } -static int ptp_get_clock(struct ptp *ptp, u64 *clk) +static inline u64 get_tsc(bool is_pmu) +{ +#if defined(CONFIG_ARM64) + return is_pmu ? read_sysreg(pmccntr_el0) : read_sysreg(cntvct_el0); +#else + return 0; +#endif +} + +static int ptp_get_clock(struct ptp *ptp, bool is_pmu, u64 *clk, u64 *tsc) { /* Return the current PTP clock */ - *clk =3D readq(ptp->reg_base + PTP_CLOCK_HI); + u64 end, start; + u8 retries =3D 0; + + do { + start =3D get_tsc(0); + *tsc =3D get_tsc(is_pmu); + *clk =3D readq(ptp->reg_base + PTP_CLOCK_HI); + end =3D get_tsc(0); + retries++; + } while (((end - start) > 50) && retries < 5); return 0; } @@ -297,7 +315,8 @@ int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp= _req *req, err =3D ptp_adjfine(rvu->ptp, req->scaled_ppm); break; case PTP_OP_GET_CLOCK: - err =3D ptp_get_clock(rvu->ptp, &rsp->clk); + err =3D ptp_get_clock(rvu->ptp, req->is_pmu, &rsp->clk, + &rsp->tsc); break; case PTP_OP_GET_TSTMP: err =3D ptp_get_tstmp(rvu->ptp, &rsp->clk); -- 2.17.1 From nobody Sun Jun 28 00:17:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C71FC433EF for ; Thu, 17 Feb 2022 18:44:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244608AbiBQSoR (ORCPT ); Thu, 17 Feb 2022 13:44:17 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244619AbiBQSoM (ORCPT ); Thu, 17 Feb 2022 13:44:12 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7A933B030; Thu, 17 Feb 2022 10:43:54 -0800 (PST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21HGH43j014913; Thu, 17 Feb 2022 10:43:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=jEc+Xgh/pv009ONqoZO13Cf6KkRQGdrEOXdOnrn/VHI=; b=VsNd2XF4s14a0Y/FCRFQQzchblCVDwuWPbtokk7HV0fkOUf+gX38yNmL1skJZer4Jem3 Fa2DZFpkj/Vw5Rm6+2DQjQhxwfUUhpbj/ZzJa+c25yQnLFtQQ24YWXU8SSAjp6CnINUU 5OJVVsxWTMMO+3222yZcetyew8ZEC80Ss1EiLfVD8IoYrOON1Pk4qYji0kTJDfx6ggVb b/3lApIi4uHyeapeF+V6mfkInaICOiAM4hRXHcPgjLS1VmD7fOBxRgHFdQm/y3rB5yBG dbD5aGKmJnn0B/o49Z6Bg7ZOXutmc0/pn4/j6j+5oiZG1fAWZYJ+Xgug98AzmWo2CUee ZA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3e9sqrgqtf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 10:43:52 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Feb 2022 10:08:10 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 17 Feb 2022 10:08:08 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id F260B3F7108; Thu, 17 Feb 2022 10:05:05 -0800 (PST) From: Rakesh Babu Saladi To: , , , , , , , CC: Naveen Mamindlapalli , Rakesh Babu Saladi Subject: [net-next PATCH 2/3] octeontx2-pf: cn10k: add support for new ptp timestamp format Date: Thu, 17 Feb 2022 23:34:49 +0530 Message-ID: <20220217180450.21721-3-rsaladi2@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220217180450.21721-1-rsaladi2@marvell.com> References: <20220217180450.21721-1-rsaladi2@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: PNsgHLgimsjzyrzes_dMT_KTwd3jDC-u X-Proofpoint-GUID: PNsgHLgimsjzyrzes_dMT_KTwd3jDC-u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_07,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Naveen Mamindlapalli The cn10k hardware ptp timestamp format has been modified primarily to support 1-step ptp clock. The 64-bit timestamp used by hardware is split into two 32-bit fields, the upper one holds seconds, the lower one nanoseconds. A new register (PTP_CLOCK_SEC) has been added that returns the current seconds value. The nanoseconds register PTP_CLOCK_HI resets after every second. The cn10k RPM block provides Rx/Tx timestamps to the NIX block using the new timestamp format. The software can read the current timestamp in nanoseconds by reading both PTP_CLOCK_SEC & PTP_CLOCK_HI registers. This patch provides support for new timestamp format. Signed-off-by: Naveen Mamindlapalli Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Rakesh Babu Saladi --- .../net/ethernet/marvell/octeontx2/af/ptp.c | 44 ++++++++++++++++++- .../net/ethernet/marvell/octeontx2/af/ptp.h | 2 + .../marvell/octeontx2/nic/otx2_common.h | 3 ++ .../ethernet/marvell/octeontx2/nic/otx2_ptp.c | 8 ++++ .../ethernet/marvell/octeontx2/nic/otx2_ptp.h | 15 +++++++ .../marvell/octeontx2/nic/otx2_txrx.c | 6 ++- 6 files changed, 75 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/= ethernet/marvell/octeontx2/af/ptp.c index 211c375446f4..6f5e1a5d957f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c @@ -25,6 +25,9 @@ #define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP 0xB600 #define PCI_DEVID_OCTEONTX2_RST 0xA085 #define PCI_DEVID_CN10K_PTP 0xA09E +#define PCI_SUBSYS_DEVID_CN10K_A_PTP 0xB900 +#define PCI_SUBSYS_DEVID_CNF10K_A_PTP 0xBA00 +#define PCI_SUBSYS_DEVID_CNF10K_B_PTP 0xBC00 =20 #define PCI_PTP_BAR_NO 0 =20 @@ -46,10 +49,43 @@ #define PTP_CLOCK_HI 0xF10ULL #define PTP_CLOCK_COMP 0xF18ULL #define PTP_TIMESTAMP 0xF20ULL +#define PTP_CLOCK_SEC 0xFD0ULL =20 static struct ptp *first_ptp_block; static const struct pci_device_id ptp_id_table[]; =20 +static bool is_ptp_tsfmt_sec_nsec(struct ptp *ptp) +{ + if (ptp->pdev->subsystem_device =3D=3D PCI_SUBSYS_DEVID_CN10K_A_PTP || + ptp->pdev->subsystem_device =3D=3D PCI_SUBSYS_DEVID_CNF10K_A_PTP) + return true; + return false; +} + +static u64 read_ptp_tstmp_sec_nsec(struct ptp *ptp) +{ + u64 sec, sec1, nsec; + unsigned long flags; + + spin_lock_irqsave(&ptp->ptp_lock, flags); + sec =3D readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; + nsec =3D readq(ptp->reg_base + PTP_CLOCK_HI); + sec1 =3D readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; + /* check nsec rollover */ + if (sec1 > sec) { + nsec =3D readq(ptp->reg_base + PTP_CLOCK_HI); + sec =3D sec1; + } + spin_unlock_irqrestore(&ptp->ptp_lock, flags); + + return sec * NSEC_PER_SEC + nsec; +} + +static u64 read_ptp_tstmp_nsec(struct ptp *ptp) +{ + return readq(ptp->reg_base + PTP_CLOCK_HI); +} + struct ptp *ptp_get(void) { struct ptp *ptp =3D first_ptp_block; @@ -132,7 +168,7 @@ static int ptp_get_clock(struct ptp *ptp, bool is_pmu, = u64 *clk, u64 *tsc) do { start =3D get_tsc(0); *tsc =3D get_tsc(is_pmu); - *clk =3D readq(ptp->reg_base + PTP_CLOCK_HI); + *clk =3D ptp->read_ptp_tstmp(ptp); end =3D get_tsc(0); retries++; } while (((end - start) > 50) && retries < 5); @@ -232,6 +268,12 @@ static int ptp_probe(struct pci_dev *pdev, if (!first_ptp_block) first_ptp_block =3D ptp; =20 + spin_lock_init(&ptp->ptp_lock); + if (is_ptp_tsfmt_sec_nsec(ptp)) + ptp->read_ptp_tstmp =3D &read_ptp_tstmp_sec_nsec; + else + ptp->read_ptp_tstmp =3D &read_ptp_tstmp_nsec; + return 0; =20 error_free: diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.h b/drivers/net/= ethernet/marvell/octeontx2/af/ptp.h index 1b81a0493cd3..95a955159f40 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.h @@ -15,6 +15,8 @@ struct ptp { struct pci_dev *pdev; void __iomem *reg_base; + u64 (*read_ptp_tstmp)(struct ptp *ptp); + spinlock_t ptp_lock; /* lock */ u32 clock_rate; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 7724f17ec31f..65e31a2210d9 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -275,6 +276,8 @@ struct otx2_ptp { u64 thresh; =20 struct ptp_pin_desc extts_config; + u64 (*convert_rx_ptp_tstmp)(u64 timestamp); + u64 (*convert_tx_ptp_tstmp)(u64 timestamp); }; =20 #define OTX2_HW_TIMESTAMP_LEN 8 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c b/driver= s/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c index 61c20907315f..fdc2c9315b91 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c @@ -294,6 +294,14 @@ int otx2_ptp_init(struct otx2_nic *pfvf) goto error; } =20 + if (is_dev_otx2(pfvf->pdev)) { + ptp_ptr->convert_rx_ptp_tstmp =3D &otx2_ptp_convert_rx_timestamp; + ptp_ptr->convert_tx_ptp_tstmp =3D &otx2_ptp_convert_tx_timestamp; + } else { + ptp_ptr->convert_rx_ptp_tstmp =3D &cn10k_ptp_convert_timestamp; + ptp_ptr->convert_tx_ptp_tstmp =3D &cn10k_ptp_convert_timestamp; + } + pfvf->ptp =3D ptp_ptr; =20 error: diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.h b/driver= s/net/ethernet/marvell/octeontx2/nic/otx2_ptp.h index 6ff284211d7b..7ff41927ceaf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.h @@ -8,6 +8,21 @@ #ifndef OTX2_PTP_H #define OTX2_PTP_H =20 +static inline u64 otx2_ptp_convert_rx_timestamp(u64 timestamp) +{ + return be64_to_cpu(*(__be64 *)×tamp); +} + +static inline u64 otx2_ptp_convert_tx_timestamp(u64 timestamp) +{ + return timestamp; +} + +static inline u64 cn10k_ptp_convert_timestamp(u64 timestamp) +{ + return ((timestamp >> 32) * NSEC_PER_SEC) + (timestamp & 0xFFFFFFFFUL); +} + int otx2_ptp_init(struct otx2_nic *pfvf); void otx2_ptp_destroy(struct otx2_nic *pfvf); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c index 7c4068c5d1ac..c26de15b2ac3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c @@ -148,6 +148,7 @@ static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { timestamp =3D ((u64 *)sq->timestamps->base)[snd_comp->sqe_id]; if (timestamp !=3D 1) { + timestamp =3D pfvf->ptp->convert_tx_ptp_tstmp(timestamp); err =3D otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); if (!err) { memset(&ts, 0, sizeof(ts)); @@ -167,14 +168,15 @@ static void otx2_snd_pkt_handler(struct otx2_nic *pfv= f, static void otx2_set_rxtstamp(struct otx2_nic *pfvf, struct sk_buff *skb, void *data) { - u64 tsns; + u64 timestamp, tsns; int err; =20 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)) return; =20 + timestamp =3D pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data); /* The first 8 bytes is the timestamp */ - err =3D otx2_ptp_tstamp2time(pfvf, be64_to_cpu(*(__be64 *)data), &tsns); + err =3D otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); if (err) return; =20 --=20 2.17.1 From nobody Sun Jun 28 00:17:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6ACCC433F5 for ; Thu, 17 Feb 2022 18:44:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244614AbiBQSoU (ORCPT ); Thu, 17 Feb 2022 13:44:20 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244600AbiBQSoP (ORCPT ); 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Thu, 17 Feb 2022 10:43:55 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Feb 2022 10:08:09 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 17 Feb 2022 10:08:08 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 5FB7D3F70D5; Thu, 17 Feb 2022 10:05:09 -0800 (PST) From: Rakesh Babu Saladi To: , , , , , , , CC: Naveen Mamindlapalli , Rakesh Babu Saladi Subject: [net-next PATCH 3/3] octeontx2-af: cn10k: add workaround for ptp errata Date: Thu, 17 Feb 2022 23:34:50 +0530 Message-ID: <20220217180450.21721-4-rsaladi2@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220217180450.21721-1-rsaladi2@marvell.com> References: <20220217180450.21721-1-rsaladi2@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xRhkokcY11xajeDqqmiJrc8ZPqTNkUo3 X-Proofpoint-GUID: xRhkokcY11xajeDqqmiJrc8ZPqTNkUo3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_07,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Naveen Mamindlapalli This patch adds workaround for PTP errata given below. 1. At the time of 1 sec rollover of nano-second counter, the nano-second counter is set to 0. However, it should be set to (existing counter_value - 10^9). This leads to an accumulating error in the timestamp value with each sec rollover. 2. Additionally, the nano-second counter currently is rolling over at 'h3B9A_C9FF. It should roll over at 'h3B9A_CA00. The workaround for issue #1 is to speed up the ptp clock by adjusting PTP_CLOCK_COMP register to the desired value to compensate for the nanoseconds lost per each second. The workaround for issue #2 is to slow down the ptp clock such that the rollover occurs at ~1sec. Signed-off-by: Naveen Mamindlapalli Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Rakesh Babu Saladi --- .../net/ethernet/marvell/octeontx2/af/ptp.c | 87 +++++++++++++++++-- 1 file changed, 80 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/= ethernet/marvell/octeontx2/af/ptp.c index 6f5e1a5d957f..faf8f34421f3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c @@ -51,9 +51,19 @@ #define PTP_TIMESTAMP 0xF20ULL #define PTP_CLOCK_SEC 0xFD0ULL =20 +#define CYCLE_MULT 1000 + static struct ptp *first_ptp_block; static const struct pci_device_id ptp_id_table[]; =20 +static bool cn10k_ptp_errata(struct ptp *ptp) +{ + if (ptp->pdev->subsystem_device =3D=3D PCI_SUBSYS_DEVID_CN10K_A_PTP || + ptp->pdev->subsystem_device =3D=3D PCI_SUBSYS_DEVID_CNF10K_A_PTP) + return true; + return false; +} + static bool is_ptp_tsfmt_sec_nsec(struct ptp *ptp) { if (ptp->pdev->subsystem_device =3D=3D PCI_SUBSYS_DEVID_CN10K_A_PTP || @@ -86,6 +96,58 @@ static u64 read_ptp_tstmp_nsec(struct ptp *ptp) return readq(ptp->reg_base + PTP_CLOCK_HI); } =20 +static u64 ptp_calc_adjusted_comp(u64 ptp_clock_freq) +{ + u64 comp, adj =3D 0, cycles_per_sec, ns_drift =3D 0; + u32 ptp_clock_nsec, cycle_time; + int cycle; + + /* Errata: + * Issue #1: At the time of 1 sec rollover of the nano-second counter, + * the nano-second counter is set to 0. However, it should be set to + * (existing counter_value - 10^9). + * + * Issue #2: The nano-second counter rolls over at 0x3B9A_C9FF. + * It should roll over at 0x3B9A_CA00. + */ + + /* calculate ptp_clock_comp value */ + comp =3D ((u64)1000000000ULL << 32) / ptp_clock_freq; + /* use CYCLE_MULT to avoid accuracy loss due to integer arithmetic */ + cycle_time =3D NSEC_PER_SEC * CYCLE_MULT / ptp_clock_freq; + /* cycles per sec */ + cycles_per_sec =3D ptp_clock_freq; + + /* check whether ptp nanosecond counter rolls over early */ + cycle =3D cycles_per_sec - 1; + ptp_clock_nsec =3D (cycle * comp) >> 32; + while (ptp_clock_nsec < NSEC_PER_SEC) { + if (ptp_clock_nsec =3D=3D 0x3B9AC9FF) + goto calc_adj_comp; + cycle++; + ptp_clock_nsec =3D (cycle * comp) >> 32; + } + /* compute nanoseconds lost per second when nsec counter rolls over */ + ns_drift =3D ptp_clock_nsec - NSEC_PER_SEC; + /* calculate ptp_clock_comp adjustment */ + if (ns_drift > 0) { + adj =3D comp * ns_drift; + adj =3D adj / 1000000000ULL; + } + /* speed up the ptp clock to account for nanoseconds lost */ + comp +=3D adj; + return comp; + +calc_adj_comp: + /* slow down the ptp clock to not rollover early */ + adj =3D comp * cycle_time; + adj =3D adj / 1000000000ULL; + adj =3D adj / CYCLE_MULT; + comp -=3D adj; + + return comp; +} + struct ptp *ptp_get(void) { struct ptp *ptp =3D first_ptp_block; @@ -113,8 +175,8 @@ void ptp_put(struct ptp *ptp) static int ptp_adjfine(struct ptp *ptp, long scaled_ppm) { bool neg_adj =3D false; - u64 comp; - u64 adj; + u32 freq, freq_adj; + u64 comp, adj; s64 ppb; =20 if (scaled_ppm < 0) { @@ -136,15 +198,22 @@ static int ptp_adjfine(struct ptp *ptp, long scaled_p= pm) * where tbase is the basic compensation value calculated * initialy in the probe function. */ - comp =3D ((u64)1000000000ull << 32) / ptp->clock_rate; /* convert scaled_ppm to ppb */ ppb =3D 1 + scaled_ppm; ppb *=3D 125; ppb >>=3D 13; - adj =3D comp * ppb; - adj =3D div_u64(adj, 1000000000ull); - comp =3D neg_adj ? comp - adj : comp + adj; =20 + if (cn10k_ptp_errata(ptp)) { + /* calculate the new frequency based on ppb */ + freq_adj =3D (ptp->clock_rate * ppb) / 1000000000ULL; + freq =3D neg_adj ? ptp->clock_rate + freq_adj : ptp->clock_rate - freq_a= dj; + comp =3D ptp_calc_adjusted_comp(freq); + } else { + comp =3D ((u64)1000000000ull << 32) / ptp->clock_rate; + adj =3D comp * ppb; + adj =3D div_u64(adj, 1000000000ull); + comp =3D neg_adj ? comp - adj : comp + adj; + } writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); =20 return 0; @@ -220,7 +289,11 @@ void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_= freq, u32 extts) writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_HI_INCR); writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_LO_INCR); =20 - clock_comp =3D ((u64)1000000000ull << 32) / ptp->clock_rate; + if (cn10k_ptp_errata(ptp)) + clock_comp =3D ptp_calc_adjusted_comp(ptp->clock_rate); + else + clock_comp =3D ((u64)1000000000ull << 32) / ptp->clock_rate; + /* Initial compensation value to start the nanosecs counter */ writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); } --=20 2.17.1