From nobody Sun Jun 28 00:17:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1BE0C433FE for ; Thu, 17 Feb 2022 14:49:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242148AbiBQOts (ORCPT ); Thu, 17 Feb 2022 09:49:48 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:38834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242108AbiBQOti (ORCPT ); Thu, 17 Feb 2022 09:49:38 -0500 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F302321F5E5; Thu, 17 Feb 2022 06:49:23 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21HDwSUO011767; Thu, 17 Feb 2022 15:48:51 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=fXiYuBUyotv54LQyPZgnEfOt06j2LWRZLDd1yz76l+0=; b=CE2j31jMzdXDLas38K2WwBQENXRIjAz4ciT3WqcFGs71po+NsTUwTpWiUO9dr1n1kmX6 kKvLcKAoXV53hUUpoBbsUTW4XQmyGlQhBwhFQbWNhZH0bN4xSDzeT5L76WhFaiFixkZZ yQ4+seqcu7Y3jiXCvV6PqbAC83LHhaJegA091FLMmw+ngqwQaYEfxiOjvDMxljeCXJXZ INa0M9vHMv1++EJzb+5xl1+U0XtKuTpZu2ZtbGw4FsQqUMKAH/j1SMbrHm1N+TN1HZuD axOOSmHBG5vJWB1PvfZr5LDCpLzyNmsXd/sFmeXCpToIcAPwM1tSKMwehgsDmnqnrgL9 Bg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3e9de2uwpe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 15:48:51 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F0F3810002A; Thu, 17 Feb 2022 15:48:49 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E71DF2278A1; Thu, 17 Feb 2022 15:48:49 +0100 (CET) Received: from localhost (10.75.127.48) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Thu, 17 Feb 2022 15:48:49 +0100 From: Christophe Kerello To: , , , , , CC: , , , , , Christophe Kerello , Rob Herring Subject: [PATCH v3 1/4] dt-binding: mtd: nand: Document the wp-gpios property Date: Thu, 17 Feb 2022 15:47:52 +0100 Message-ID: <20220217144755.270679-2-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217144755.270679-1-christophe.kerello@foss.st.com> References: <20220217144755.270679-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_05,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" A few drivers use this property to describe the GPIO pin used to protect the NAND during program/erase operations. Signed-off-by: Christophe Kerello Acked-by: Rob Herring --- Changes in v2: - add Rob Acked-by. Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/D= ocumentation/devicetree/bindings/mtd/nand-controller.yaml index bd217e6f5018..53b21aed0ac5 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -154,6 +154,13 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. =20 + wp-gpios: + description: + Contains one GPIO descriptor for the Write Protect pin. + Active state refers to the NAND Write Protect state and should be + set to GPIOD_ACTIVE_LOW unless the signal is inverted. + maxItems: 1 + secure-regions: $ref: /schemas/types.yaml#/definitions/uint64-matrix description: --=20 2.25.1 From nobody Sun Jun 28 00:17:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B90DCC433F5 for ; Thu, 17 Feb 2022 14:49:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241828AbiBQOth (ORCPT ); Thu, 17 Feb 2022 09:49:37 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:38392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242086AbiBQOtc (ORCPT ); Thu, 17 Feb 2022 09:49:32 -0500 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3F1220576C; Thu, 17 Feb 2022 06:49:17 -0800 (PST) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21HDFUgu030673; Thu, 17 Feb 2022 15:48:55 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=vJYKJrfoZTOxidHtgmggToIXf7luT4gK50tpphfihR8=; b=MVIuaMSlk+h1JIRlIGwQ/g3wHqNP3eZtFFyqQnxguYKVpJQ2bMszSyDwdPtpdmuDjsl5 /beXi/qmfOp1pti1uSERSLm6P/0awiANcFztdGNBuXqBymWGJfz71hQxzy0aCMOQ0FuU H13CuEfrsar5zckXQBFNWvNbyKieYpXdmrvvlaJZA0/K4k4CIGq85VB6tcE7Bbez6vRc r9Dytxf8PxDPKjJ32Yy0AyJO7xau8PCIDajgxLhhRsFuUbS986EiOc7xZ2SioZmasiOO XHB216d8OXpliFcVbuhwT2yghTYN78I0qi0EbyM188X7nh9d4u5ZcTEZrD9jfyUC1Gap GA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3e9k06a45x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 15:48:55 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CC5D610002A; Thu, 17 Feb 2022 15:48:54 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C28CC2278A1; Thu, 17 Feb 2022 15:48:54 +0100 (CET) Received: from localhost (10.75.127.50) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Thu, 17 Feb 2022 15:48:54 +0100 From: Christophe Kerello To: , , , , , CC: , , , , , Christophe Kerello Subject: [PATCH v3 2/4] mtd: rawnand: stm32_fmc2: Add NAND Write Protect support Date: Thu, 17 Feb 2022 15:47:53 +0100 Message-ID: <20220217144755.270679-3-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217144755.270679-1-christophe.kerello@foss.st.com> References: <20220217144755.270679-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_05,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds the support of the WP# signal. WP will be disabled in probe/resume callbacks and will be enabled in remove/suspend callbacks. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 40 +++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/= stm32_fmc2_nand.c index 97b4e02e43e4..87c1c7dd97eb 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,7 @@ struct stm32_fmc2_timings { =20 struct stm32_fmc2_nand { struct nand_chip chip; + struct gpio_desc *wp_gpio; struct stm32_fmc2_timings timings; int ncs; int cs_used[FMC2_MAX_CE]; @@ -1747,6 +1749,18 @@ static const struct nand_controller_ops stm32_fmc2_n= fc_controller_ops =3D { .setup_interface =3D stm32_fmc2_nfc_setup_interface, }; =20 +static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand) +{ + if (nand->wp_gpio) + gpiod_set_value(nand->wp_gpio, 1); +} + +static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand) +{ + if (nand->wp_gpio) + gpiod_set_value(nand->wp_gpio, 0); +} + static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, struct device_node *dn) { @@ -1785,6 +1799,18 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_f= mc2_nfc *nfc, nand->cs_used[i] =3D cs; } =20 + nand->wp_gpio =3D devm_gpiod_get_from_of_node(nfc->dev, dn, + "wp-gpios", 0, + GPIOD_OUT_HIGH, "wp"); + if (IS_ERR(nand->wp_gpio)) { + ret =3D PTR_ERR(nand->wp_gpio); + if (ret !=3D -ENOENT) + return dev_err_probe(nfc->dev, ret, + "failed to request WP GPIO\n"); + + nand->wp_gpio =3D NULL; + } + nand_set_flash_node(&nand->chip, dn); =20 return 0; @@ -1956,10 +1982,12 @@ static int stm32_fmc2_nfc_probe(struct platform_dev= ice *pdev) chip->options |=3D NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA; =20 + stm32_fmc2_nfc_wp_disable(nand); + /* Scan to find existence of the device */ ret =3D nand_scan(chip, nand->ncs); if (ret) - goto err_release_dma; + goto err_wp_enable; =20 ret =3D mtd_device_register(mtd, NULL, 0); if (ret) @@ -1972,6 +2000,9 @@ static int stm32_fmc2_nfc_probe(struct platform_devic= e *pdev) err_nand_cleanup: nand_cleanup(chip); =20 +err_wp_enable: + stm32_fmc2_nfc_wp_enable(nand); + err_release_dma: if (nfc->dma_ecc_ch) dma_release_channel(nfc->dma_ecc_ch); @@ -2012,15 +2043,20 @@ static int stm32_fmc2_nfc_remove(struct platform_de= vice *pdev) =20 clk_disable_unprepare(nfc->clk); =20 + stm32_fmc2_nfc_wp_enable(nand); + return 0; } =20 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev) { struct stm32_fmc2_nfc *nfc =3D dev_get_drvdata(dev); + struct stm32_fmc2_nand *nand =3D &nfc->nand; =20 clk_disable_unprepare(nfc->clk); =20 + stm32_fmc2_nfc_wp_enable(nand); + pinctrl_pm_select_sleep_state(dev); =20 return 0; @@ -2042,6 +2078,8 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struc= t device *dev) =20 stm32_fmc2_nfc_init(nfc); =20 + stm32_fmc2_nfc_wp_disable(nand); + for (chip_cs =3D 0; chip_cs < FMC2_MAX_CE; chip_cs++) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; --=20 2.25.1 From nobody Sun Jun 28 00:17:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70B6BC4321E for ; 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Thu, 17 Feb 2022 15:48:59 +0100 From: Christophe Kerello To: , , , , , CC: , , , , , Christophe Kerello , Subject: [PATCH v3 3/4] nvmem: core: Fix a conflict between MTD and NVMEM on wp-gpios property Date: Thu, 17 Feb 2022 15:47:54 +0100 Message-ID: <20220217144755.270679-4-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217144755.270679-1-christophe.kerello@foss.st.com> References: <20220217144755.270679-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_05,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wp-gpios property can be used on NVMEM nodes and the same property can be also used on MTD NAND nodes. In case of the wp-gpios property is defined at NAND level node, the GPIO management is done at NAND driver level. Write protect is disabled when the driver is probed or resumed and is enabled when the driver is released or suspended. When no partitions are defined in the NAND DT node, then the NAND DT node will be passed to NVMEM framework. If wp-gpios property is defined in this node, the GPIO resource is taken twice and the NAND controller driver fails to probe. It would be possible to set config->wp_gpio at MTD level before calling nvmem_register function but NVMEM framework will toggle this GPIO on each write when this GPIO should only be controlled at NAND level driver to ensure that the Write Protect has not been enabled. A way to fix this conflict is to add a new boolean flag in nvmem_config named ignore_wp. In case ignore_wp is set, the GPIO resource will be managed by the provider. Fixes: 2a127da461a9 ("nvmem: add support for the write-protect pin") Signed-off-by: Christophe Kerello Cc: stable@vger.kernel.org --- Changes in v3: - add a fixes tag. - rename skip_wp_gpio by ignore_wp in nvmen_config. Changes in v2: - rework the proposal done to fix a conflict between MTD and NVMEM on wp-gpios property. drivers/nvmem/core.c | 2 +- include/linux/nvmem-provider.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 23a38dcf0fc4..9fd1602b539d 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -771,7 +771,7 @@ struct nvmem_device *nvmem_register(const struct nvmem_= config *config) =20 if (config->wp_gpio) nvmem->wp_gpio =3D config->wp_gpio; - else + else if (!config->ignore_wp) nvmem->wp_gpio =3D gpiod_get_optional(config->dev, "wp", GPIOD_OUT_HIGH); if (IS_ERR(nvmem->wp_gpio)) { diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index 98efb7b5660d..c9a3ac9efeaa 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -70,7 +70,8 @@ struct nvmem_keepout { * @word_size: Minimum read/write access granularity. * @stride: Minimum read/write access stride. * @priv: User context passed to read/write callbacks. - * @wp-gpio: Write protect pin + * @wp-gpio: Write protect pin + * @ignore_wp: Write Protect pin is managed by the provider. * * Note: A default "nvmem" name will be assigned to the device if * no name is specified in its configuration. In such case "" is @@ -92,6 +93,7 @@ struct nvmem_config { enum nvmem_type type; bool read_only; bool root_only; + bool ignore_wp; struct device_node *of_node; bool no_of_node; nvmem_reg_read_t reg_read; --=20 2.25.1 From nobody Sun Jun 28 00:17:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23FD8C433F5 for ; Thu, 17 Feb 2022 14:49:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242155AbiBQOtv (ORCPT ); Thu, 17 Feb 2022 09:49:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:38936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242122AbiBQOtj (ORCPT ); Thu, 17 Feb 2022 09:49:39 -0500 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0145721FC69; Thu, 17 Feb 2022 06:49:24 -0800 (PST) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21HBatfR010860; Thu, 17 Feb 2022 15:49:03 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=uDBTaIhKiAzA8mTM+6OWIIjO0uszxvkCNaIBSKJuIPE=; b=cepx7Q01ybZURJgeAHcz2UECpj/Q9EsgWS4PVaF5dwaGrgoTsMzL7htjFyB8m5ejX1p8 WYvFMuaT/HJ4DGehMlTtL2aL7b9uLABGuhnaOQKtTOFaEgfK3wCgcrmRv63SmM8M8X2+ UBFI8SXObppvaFqdXNYtJFiUj0sxBOiaZTIcaiY/WuaszmB/Nz+ug0JikV48mz6xPDjX 9aVWlxV/5GxkL/GK41YpNhQVK9Fpwkjn2+rx8cyyaOwUvuyjwOt5lqc8Tkzwez3SgJJn T0pywHZdKhQeZZXieE7c5ZTGQWGFwLnW0pQLRJotZ/CnJ0LosPOU439bOoa3YfsGULWZ +Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3e9hvgjmpp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 15:49:03 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 509B710002A; Thu, 17 Feb 2022 15:49:03 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4722E2278A1; Thu, 17 Feb 2022 15:49:03 +0100 (CET) Received: from localhost (10.75.127.50) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Thu, 17 Feb 2022 15:49:02 +0100 From: Christophe Kerello To: , , , , , CC: , , , , , Christophe Kerello , Subject: [PATCH v3 4/4] mtd: core: Fix a conflict between MTD and NVMEM on wp-gpios property Date: Thu, 17 Feb 2022 15:47:55 +0100 Message-ID: <20220217144755.270679-5-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217144755.270679-1-christophe.kerello@foss.st.com> References: <20220217144755.270679-1-christophe.kerello@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_05,2022-02-17_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wp-gpios property can be used on NVMEM nodes and the same property can be also used on MTD NAND nodes. In case of the wp-gpios property is defined at NAND level node, the GPIO management is done at NAND driver level. Write protect is disabled when the driver is probed or resumed and is enabled when the driver is released or suspended. When no partitions are defined in the NAND DT node, then the NAND DT node will be passed to NVMEM framework. If wp-gpios property is defined in this node, the GPIO resource is taken twice and the NAND controller driver fails to probe. A new Boolean flag named ignore_wp has been added in nvmem_config. In case ignore_wp is set, it means that the GPIO is handled by the provider. Lets set this flag in MTD layer to avoid the conflict on wp_gpios property. Fixes: 2a127da461a9 ("nvmem: add support for the write-protect pin") Signed-off-by: Christophe Kerello Cc: stable@vger.kernel.org Acked-by: Miquel Raynal --- Changes in v3: - add a fixes tag - rename skip_wp_gpio by ignore_wp in nvmen_config. drivers/mtd/mtdcore.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 70f492dce158..eef87b28d6c8 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -546,6 +546,7 @@ static int mtd_nvmem_add(struct mtd_info *mtd) config.stride =3D 1; config.read_only =3D true; config.root_only =3D true; + config.ignore_wp =3D true; config.no_of_node =3D !of_device_is_compatible(node, "nvmem-cells"); config.priv =3D mtd; =20 @@ -833,6 +834,7 @@ static struct nvmem_device *mtd_otp_nvmem_register(stru= ct mtd_info *mtd, config.owner =3D THIS_MODULE; config.type =3D NVMEM_TYPE_OTP; config.root_only =3D true; + config.ignore_wp =3D true; config.reg_read =3D reg_read; config.size =3D size; config.of_node =3D np; --=20 2.25.1