From nobody Sun Sep 22 09:26:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3AFCC433F5 for ; Thu, 17 Feb 2022 13:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239969AbiBQNnO (ORCPT ); Thu, 17 Feb 2022 08:43:14 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241106AbiBQNmn (ORCPT ); Thu, 17 Feb 2022 08:42:43 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71C6A26AC4; Thu, 17 Feb 2022 05:42:27 -0800 (PST) X-UUID: 9287c66b22a8421bac5ded8cc04bb237-20220217 X-UUID: 9287c66b22a8421bac5ded8cc04bb237-20220217 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1550400994; Thu, 17 Feb 2022 21:42:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 17 Feb 2022 21:42:23 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 21:42:22 +0800 From: Jiaxin Yu To: CC: , , , , , , , , , , , , , , , , Jiaxin Yu Subject: [v2 11/17] ASoC: mediatek: mt8186: support gpio control in platform driver Date: Thu, 17 Feb 2022 21:41:59 +0800 Message-ID: <20220217134205.15400-12-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217134205.15400-1-jiaxin.yu@mediatek.com> References: <20220217134205.15400-1-jiaxin.yu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add gpio control for all audio interface separately. Signed-off-by: Jiaxin Yu --- sound/soc/mediatek/mt8186/mt8186-afe-gpio.c | 210 ++++++++++++++++++++ sound/soc/mediatek/mt8186/mt8186-afe-gpio.h | 19 ++ 2 files changed, 229 insertions(+) create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-gpio.c create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-gpio.h diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c b/sound/soc/mediat= ek/mt8186/mt8186-afe-gpio.c new file mode 100644 index 000000000000..6faec5c95bf3 --- /dev/null +++ b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// mt8186-afe-gpio.c -- Mediatek 8186 afe gpio ctrl +// +// Copyright (c) 2022 MediaTek Inc. +// Author: Jiaxin Yu + +#include +#include + +#include "mt8186-afe-common.h" +#include "mt8186-afe-gpio.h" + +struct pinctrl *aud_pinctrl; + +enum mt8186_afe_gpio { + MT8186_AFE_GPIO_CLK_MOSI_OFF, + MT8186_AFE_GPIO_CLK_MOSI_ON, + MT8186_AFE_GPIO_CLK_MISO_OFF, + MT8186_AFE_GPIO_CLK_MISO_ON, + MT8186_AFE_GPIO_DAT_MISO_OFF, + MT8186_AFE_GPIO_DAT_MISO_ON, + MT8186_AFE_GPIO_DAT_MOSI_OFF, + MT8186_AFE_GPIO_DAT_MOSI_ON, + MT8186_AFE_GPIO_I2S0_OFF, + MT8186_AFE_GPIO_I2S0_ON, + MT8186_AFE_GPIO_I2S1_OFF, + MT8186_AFE_GPIO_I2S1_ON, + MT8186_AFE_GPIO_I2S2_OFF, + MT8186_AFE_GPIO_I2S2_ON, + MT8186_AFE_GPIO_I2S3_OFF, + MT8186_AFE_GPIO_I2S3_ON, + MT8186_AFE_GPIO_TDM_OFF, + MT8186_AFE_GPIO_TDM_ON, + MT8186_AFE_GPIO_PCM_OFF, + MT8186_AFE_GPIO_PCM_ON, + MT8186_AFE_GPIO_GPIO_NUM +}; + +struct audio_gpio_attr { + const char *name; + bool gpio_prepare; + struct pinctrl_state *gpioctrl; +}; + +static struct audio_gpio_attr aud_gpios[MT8186_AFE_GPIO_GPIO_NUM] =3D { + [MT8186_AFE_GPIO_CLK_MOSI_OFF] =3D {"aud_clk_mosi_off", false, NULL}, + [MT8186_AFE_GPIO_CLK_MOSI_ON] =3D {"aud_clk_mosi_on", false, NULL}, + [MT8186_AFE_GPIO_CLK_MISO_OFF] =3D {"aud_clk_miso_off", false, NULL}, + [MT8186_AFE_GPIO_CLK_MISO_ON] =3D {"aud_clk_miso_on", false, NULL}, + [MT8186_AFE_GPIO_DAT_MISO_OFF] =3D {"aud_dat_miso_off", false, NULL}, + [MT8186_AFE_GPIO_DAT_MISO_ON] =3D {"aud_dat_miso_on", false, NULL}, + [MT8186_AFE_GPIO_DAT_MOSI_OFF] =3D {"aud_dat_mosi_off", false, NULL}, + [MT8186_AFE_GPIO_DAT_MOSI_ON] =3D {"aud_dat_mosi_on", false, NULL}, + [MT8186_AFE_GPIO_I2S0_OFF] =3D {"aud_gpio_i2s0_off", false, NULL}, + [MT8186_AFE_GPIO_I2S0_ON] =3D {"aud_gpio_i2s0_on", false, NULL}, + [MT8186_AFE_GPIO_I2S1_OFF] =3D {"aud_gpio_i2s1_off", false, NULL}, + [MT8186_AFE_GPIO_I2S1_ON] =3D {"aud_gpio_i2s1_on", false, NULL}, + [MT8186_AFE_GPIO_I2S2_OFF] =3D {"aud_gpio_i2s2_off", false, NULL}, + [MT8186_AFE_GPIO_I2S2_ON] =3D {"aud_gpio_i2s2_on", false, NULL}, + [MT8186_AFE_GPIO_I2S3_OFF] =3D {"aud_gpio_i2s3_off", false, NULL}, + [MT8186_AFE_GPIO_I2S3_ON] =3D {"aud_gpio_i2s3_on", false, NULL}, + [MT8186_AFE_GPIO_TDM_OFF] =3D {"aud_gpio_tdm_off", false, NULL}, + [MT8186_AFE_GPIO_TDM_ON] =3D {"aud_gpio_tdm_on", false, NULL}, + [MT8186_AFE_GPIO_PCM_OFF] =3D {"aud_gpio_pcm_off", false, NULL}, + [MT8186_AFE_GPIO_PCM_ON] =3D {"aud_gpio_pcm_on", false, NULL}, +}; + +static DEFINE_MUTEX(gpio_request_mutex); + +int mt8186_afe_gpio_init(struct device *dev) +{ + int ret; + int i =3D 0; + + aud_pinctrl =3D devm_pinctrl_get(dev); + if (IS_ERR(aud_pinctrl)) { + ret =3D PTR_ERR(aud_pinctrl); + dev_info(dev, "%s(), ret %d, cannot get aud_pinctrl!\n", + __func__, ret); + return -ENODEV; + } + + for (i =3D 0; i < ARRAY_SIZE(aud_gpios); i++) { + aud_gpios[i].gpioctrl =3D pinctrl_lookup_state(aud_pinctrl, + aud_gpios[i].name); + if (IS_ERR(aud_gpios[i].gpioctrl)) { + ret =3D PTR_ERR(aud_gpios[i].gpioctrl); + dev_info(dev, "%s(), pinctrl_lookup_state %s fail, ret %d\n", + __func__, aud_gpios[i].name, ret); + } else { + aud_gpios[i].gpio_prepare =3D true; + } + } + + /* gpio status init */ + mt8186_afe_gpio_request(dev, false, MT8186_DAI_ADDA, 0); + mt8186_afe_gpio_request(dev, false, MT8186_DAI_ADDA, 1); + + return 0; +} +EXPORT_SYMBOL_GPL(mt8186_afe_gpio_init); + +static int mt8186_afe_gpio_select(struct device *dev, + enum mt8186_afe_gpio type) +{ + int ret =3D 0; + + if (type < 0 || type >=3D MT8186_AFE_GPIO_GPIO_NUM) { + dev_info(dev, "%s(), error, invalid gpio type %d\n", + __func__, type); + return -EINVAL; + } + + if (!aud_gpios[type].gpio_prepare) { + dev_info(dev, "%s(), error, gpio type %d not prepared\n", + __func__, type); + return -EIO; + } + + ret =3D pinctrl_select_state(aud_pinctrl, + aud_gpios[type].gpioctrl); + if (ret) + dev_info(dev, "%s(), error, can not set gpio type %d\n", + __func__, type); + + return ret; +} + +static int mt8186_afe_gpio_adda_dl(struct device *dev, bool enable) +{ + if (enable) { + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_ON); + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_ON); + } else { + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_OFF); + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_OFF); + } + + return 0; +} + +static int mt8186_afe_gpio_adda_ul(struct device *dev, bool enable) +{ + if (enable) { + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_ON); + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_ON); + } else { + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_OFF); + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_OFF); + } + + return 0; +} + +int mt8186_afe_gpio_request(struct device *dev, bool enable, + int dai, int uplink) +{ + mutex_lock(&gpio_request_mutex); + switch (dai) { + case MT8186_DAI_ADDA: + if (uplink) + mt8186_afe_gpio_adda_ul(dev, enable); + else + mt8186_afe_gpio_adda_dl(dev, enable); + break; + case MT8186_DAI_I2S_0: + if (enable) + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S0_ON); + else + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S0_OFF); + break; + case MT8186_DAI_I2S_1: + if (enable) + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S1_ON); + else + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S1_OFF); + break; + case MT8186_DAI_I2S_2: + if (enable) + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S2_ON); + else + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S2_OFF); + break; + case MT8186_DAI_I2S_3: + if (enable) + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S3_ON); + else + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_I2S3_OFF); + break; + case MT8186_DAI_TDM_IN: + if (enable) + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_TDM_ON); + else + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_TDM_OFF); + break; + case MT8186_DAI_PCM: + if (enable) + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_PCM_ON); + else + mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_PCM_OFF); + break; + default: + mutex_unlock(&gpio_request_mutex); + dev_info(dev, "%s(), invalid dai %d\n", __func__, dai); + return -EINVAL; + } + mutex_unlock(&gpio_request_mutex); + return 0; +} diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-gpio.h b/sound/soc/mediat= ek/mt8186/mt8186-afe-gpio.h new file mode 100644 index 000000000000..1ddc27838eb1 --- /dev/null +++ b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * mt6833-afe-gpio.h -- Mediatek 6833 afe gpio ctrl definition + * + * Copyright (c) 2022 MediaTek Inc. + * Author: Jiaxin Yu + */ + +#ifndef _MT8186_AFE_GPIO_H_ +#define _MT8186_AFE_GPIO_H_ + +struct mtk_base_afe; + +int mt8186_afe_gpio_init(struct device *dev); + +int mt8186_afe_gpio_request(struct device *dev, bool enable, + int dai, int uplink); + +#endif --=20 2.18.0