From nobody Sun Sep 22 09:38:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D7A2C433EF for ; Thu, 17 Feb 2022 11:41:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240121AbiBQLlZ (ORCPT ); Thu, 17 Feb 2022 06:41:25 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:56796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240226AbiBQLku (ORCPT ); Thu, 17 Feb 2022 06:40:50 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB9B424BF6; Thu, 17 Feb 2022 03:40:35 -0800 (PST) X-UUID: 42dfc37c5d434c2a8223bbea2b676640-20220217 X-UUID: 42dfc37c5d434c2a8223bbea2b676640-20220217 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2055087631; Thu, 17 Feb 2022 19:40:30 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 17 Feb 2022 19:40:29 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 19:40:28 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , "Matthias Brugger" , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , , Hsin-Yi Wang , , , , , , "AngeloGioacchino Del Regno" , , , , Subject: [PATCH v5 33/34] iommu/mediatek: Backup/restore regsiters for multi banks Date: Thu, 17 Feb 2022 19:34:52 +0800 Message-ID: <20220217113453.13658-34-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220217113453.13658-1-yong.wu@mediatek.com> References: <20220217113453.13658-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each bank has some independent registers. thus backup/restore them for each a bank when suspend and resume. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 46 ++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 2e7ed4a2d6e1..d3b6c80bf51a 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -173,11 +173,12 @@ struct mtk_iommu_suspend_reg { u32 misc_ctrl; u32 dcm_dis; u32 ctrl_reg; - u32 int_control0; - u32 int_main_control; - u32 ivrp_paddr; u32 vld_pa_rng; u32 wr_len_ctrl; + + u32 int_control[MTK_IOMMU_BANK_MAX]; + u32 int_main_control[MTK_IOMMU_BANK_MAX]; + u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; }; =20 struct mtk_iommu_plat_data { @@ -1301,16 +1302,23 @@ static int __maybe_unused mtk_iommu_runtime_suspend= (struct device *dev) { struct mtk_iommu_data *data =3D dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg =3D &data->reg; - void __iomem *base =3D data->bank[0].base; + void __iomem *base; + int i =3D 0; =20 + base =3D data->bank[i].base; reg->wr_len_ctrl =3D readl_relaxed(base + REG_MMU_WR_LEN_CTRL); reg->misc_ctrl =3D readl_relaxed(base + REG_MMU_MISC_CTRL); reg->dcm_dis =3D readl_relaxed(base + REG_MMU_DCM_DIS); reg->ctrl_reg =3D readl_relaxed(base + REG_MMU_CTRL_REG); - reg->int_control0 =3D readl_relaxed(base + REG_MMU_INT_CONTROL0); - reg->int_main_control =3D readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); - reg->ivrp_paddr =3D readl_relaxed(base + REG_MMU_IVRP_PADDR); reg->vld_pa_rng =3D readl_relaxed(base + REG_MMU_VLD_PA_RNG); + do { + if (!data->plat_data->banks_enable[i]) + continue; + base =3D data->bank[i].base; + reg->int_control[i] =3D readl_relaxed(base + REG_MMU_INT_CONTROL0); + reg->int_main_control[i] =3D readl_relaxed(base + REG_MMU_INT_MAIN_CONTR= OL); + reg->ivrp_paddr[i] =3D readl_relaxed(base + REG_MMU_IVRP_PADDR); + } while (++i < data->plat_data->banks_num); clk_disable_unprepare(data->bclk); return 0; } @@ -1319,9 +1327,9 @@ static int __maybe_unused mtk_iommu_runtime_resume(st= ruct device *dev) { struct mtk_iommu_data *data =3D dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg =3D &data->reg; - struct mtk_iommu_domain *m4u_dom =3D data->bank[0].m4u_dom; - void __iomem *base =3D data->bank[0].base; - int ret; + struct mtk_iommu_domain *m4u_dom; + void __iomem *base; + int ret, i =3D 0; =20 ret =3D clk_prepare_enable(data->bclk); if (ret) { @@ -1333,18 +1341,26 @@ static int __maybe_unused mtk_iommu_runtime_resume(= struct device *dev) * Uppon first resume, only enable the clk and return, since the values o= f the * registers are not yet set. */ - if (!m4u_dom) + if (!reg->wr_len_ctrl) return 0; =20 + base =3D data->bank[i].base; writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); - writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); - writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); - writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_P= T_BASE_ADDR); + do { + m4u_dom =3D data->bank[i].m4u_dom; + if (!data->plat_data->banks_enable[i] || !m4u_dom) + continue; + base =3D data->bank[i].base; + writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); + writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL= ); + writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, + base + REG_MMU_PT_BASE_ADDR); + } while (++i < data->plat_data->banks_num); =20 /* * Users may allocate dma buffer before they call pm_runtime_get, --=20 2.18.0