From nobody Sun Sep 22 09:33:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34FC7C4332F for ; Thu, 17 Feb 2022 11:39:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240046AbiBQLkB (ORCPT ); Thu, 17 Feb 2022 06:40:01 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:56070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239168AbiBQLj6 (ORCPT ); Thu, 17 Feb 2022 06:39:58 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBD0B99EC7; Thu, 17 Feb 2022 03:39:41 -0800 (PST) X-UUID: 73317da8fe0a4dd88cf5626fc2c30607-20220217 X-UUID: 73317da8fe0a4dd88cf5626fc2c30607-20220217 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2052629432; Thu, 17 Feb 2022 19:39:37 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 17 Feb 2022 19:39:36 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 19:39:34 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , "Matthias Brugger" , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , , Hsin-Yi Wang , , , , , , "AngeloGioacchino Del Regno" , , , , Subject: [PATCH v5 28/34] iommu/mediatek: Add mtk_iommu_bank_data structure Date: Thu, 17 Feb 2022 19:34:47 +0800 Message-ID: <20220217113453.13658-29-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220217113453.13658-1-yong.wu@mediatek.com> References: <20220217113453.13658-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare for supporting multi-banks for the IOMMU HW, No functional change. Add a new structure(mtk_iommu_bank_data) for each a bank. Each a bank have the independent HW base/IRQ/tlb-range ops, and each a bank has its special iommu-domain(independent pgtable), thus, also move the domain information into it. In previous SoC, we have only one bank which could be treated as bank0( bankid always is 0 for the previous SoC). After adding this structure, the tlb operations and irq could use bank_data as parameter. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 179 +++++++++++++++++++++++++------------- 1 file changed, 117 insertions(+), 62 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 93c5802621d5..c803061c2c6e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -151,6 +151,7 @@ #define MTK_LARB_SUBCOM_MAX 8 =20 #define MTK_IOMMU_GROUP_MAX 8 +#define MTK_IOMMU_BANK_MAX 5 =20 enum mtk_iommu_plat { M4U_MT2712, @@ -187,25 +188,36 @@ struct mtk_iommu_plat_data { struct list_head *hw_list; unsigned int iova_region_nr; const struct mtk_iommu_iova_region *iova_region; + + u8 banks_num; + bool banks_enable[MTK_IOMMU_BANK_MAX]; unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; }; =20 -struct mtk_iommu_data { +struct mtk_iommu_bank_data { void __iomem *base; int irq; + u8 id; + struct device *parent_dev; + struct mtk_iommu_data *parent_data; + spinlock_t tlb_lock; /* lock for tlb range flush */ + struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ +}; + +struct mtk_iommu_data { struct device *dev; struct clk *bclk; phys_addr_t protect_base; /* protect memory base */ struct mtk_iommu_suspend_reg reg; - struct mtk_iommu_domain *m4u_dom; struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; bool enable_4GB; - spinlock_t tlb_lock; /* lock for tlb range flush */ =20 struct iommu_device iommu; const struct mtk_iommu_plat_data *plat_data; struct device *smicomm_dev; =20 + struct mtk_iommu_bank_data *bank; + struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */ struct regmap *pericfg; =20 @@ -225,7 +237,7 @@ struct mtk_iommu_domain { struct io_pgtable_cfg cfg; struct io_pgtable_ops *iop; =20 - struct mtk_iommu_data *data; + struct mtk_iommu_bank_data *bank; struct iommu_domain domain; =20 struct mutex mutex; /* Protect "data" in this structure */ @@ -322,20 +334,24 @@ static struct mtk_iommu_domain *to_mtk_domain(struct = iommu_domain *dom) =20 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) { - void __iomem *base =3D data->base; + /* Tlb flush all always is in bank0. */ + struct mtk_iommu_bank_data *bank =3D &data->bank[0]; + void __iomem *base =3D bank->base; unsigned long flags; =20 - spin_lock_irqsave(&data->tlb_lock, flags); + spin_lock_irqsave(&bank->tlb_lock, flags); writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel= _reg); writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); wmb(); /* Make sure the tlb flush all done */ - spin_unlock_irqrestore(&data->tlb_lock, flags); + spin_unlock_irqrestore(&bank->tlb_lock, flags); } =20 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, - struct mtk_iommu_data *data) + struct mtk_iommu_bank_data *bank) { - struct list_head *head =3D data->hw_list; + struct list_head *head =3D bank->parent_data->hw_list; + struct mtk_iommu_bank_data *curbank; + struct mtk_iommu_data *data; bool check_pm_status; unsigned long flags; void __iomem *base; @@ -365,9 +381,10 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned lo= ng iova, size_t size, continue; } =20 - base =3D data->base; + curbank =3D &data->bank[bank->id]; + base =3D curbank->base; =20 - spin_lock_irqsave(&data->tlb_lock, flags); + spin_lock_irqsave(&curbank->tlb_lock, flags); writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); =20 @@ -382,7 +399,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned lon= g iova, size_t size, =20 /* Clear the CPE status */ writel_relaxed(0, base + REG_MMU_CPE_DONE); - spin_unlock_irqrestore(&data->tlb_lock, flags); + spin_unlock_irqrestore(&curbank->tlb_lock, flags); =20 if (ret) { dev_warn(data->dev, @@ -397,12 +414,13 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned l= ong iova, size_t size, =20 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) { - struct mtk_iommu_data *data =3D dev_id; - struct mtk_iommu_domain *dom =3D data->m4u_dom; + struct mtk_iommu_bank_data *bank =3D dev_id; + struct mtk_iommu_data *data =3D bank->parent_data; + struct mtk_iommu_domain *dom =3D bank->m4u_dom; unsigned int fault_larb =3D MTK_INVALID_LARBID, fault_port =3D 0, sub_com= m =3D 0; u32 int_state, regval, va34_32, pa34_32; const struct mtk_iommu_plat_data *plat_data =3D data->plat_data; - void __iomem *base =3D data->base; + void __iomem *base =3D bank->base; u64 fault_iova, fault_pa; bool layer, write; =20 @@ -441,10 +459,10 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_i= d) fault_larb =3D data->plat_data->larbid_remap[fault_larb][sub_comm]; } =20 - if (report_iommu_fault(&dom->domain, data->dev, fault_iova, + if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { dev_err_ratelimited( - data->dev, + bank->parent_dev, "fault type=3D0x%x iova=3D0x%llx pa=3D0x%llx master=3D0x%x(larb=3D%d po= rt=3D%d) layer=3D%d %s\n", int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, layer, write ? "write" : "read"); @@ -541,12 +559,14 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu= _domain *dom, unsigned int domid) { const struct mtk_iommu_iova_region *region; - - /* Use the exist domain as there is only one pgtable here. */ - if (data->m4u_dom) { - dom->iop =3D data->m4u_dom->iop; - dom->cfg =3D data->m4u_dom->cfg; - dom->domain.pgsize_bitmap =3D data->m4u_dom->cfg.pgsize_bitmap; + struct mtk_iommu_domain *m4u_dom; + + /* Always use bank0 in sharing pgtable case */ + m4u_dom =3D data->bank[0].m4u_dom; + if (m4u_dom) { + dom->iop =3D m4u_dom->iop; + dom->cfg =3D m4u_dom->cfg; + dom->domain.pgsize_bitmap =3D m4u_dom->cfg.pgsize_bitmap; goto update_iova_region; } =20 @@ -609,6 +629,8 @@ static int mtk_iommu_attach_device(struct iommu_domain = *domain, struct mtk_iommu_domain *dom =3D to_mtk_domain(domain); struct list_head *hw_list =3D data->hw_list; struct device *m4udev =3D data->dev; + struct mtk_iommu_bank_data *bank; + unsigned int bankid =3D 0; int ret, domid; =20 domid =3D mtk_iommu_get_domain_id(dev, data->plat_data); @@ -616,7 +638,7 @@ static int mtk_iommu_attach_device(struct iommu_domain = *domain, return domid; =20 mutex_lock(&dom->mutex); - if (!dom->data) { + if (!dom->bank) { /* Data is in the frstdata in sharing pgtable case. */ frstdata =3D mtk_iommu_get_frst_data(hw_list); =20 @@ -625,12 +647,13 @@ static int mtk_iommu_attach_device(struct iommu_domai= n *domain, mutex_unlock(&dom->mutex); return -ENODEV; } - dom->data =3D data; + dom->bank =3D &data->bank[bankid]; } mutex_unlock(&dom->mutex); =20 mutex_lock(&data->mutex); - if (!data->m4u_dom) { /* Initialize the M4U HW */ + bank =3D &data->bank[bankid]; + if (!bank->m4u_dom) { /* Initialize the M4U HW */ ret =3D pm_runtime_resume_and_get(m4udev); if (ret < 0) goto err_unlock; @@ -640,9 +663,9 @@ static int mtk_iommu_attach_device(struct iommu_domain = *domain, pm_runtime_put(m4udev); goto err_unlock; } - data->m4u_dom =3D dom; + bank->m4u_dom =3D dom; writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, - data->base + REG_MMU_PT_BASE_ADDR); + bank->base + REG_MMU_PT_BASE_ADDR); =20 pm_runtime_put(m4udev); } @@ -669,7 +692,7 @@ static int mtk_iommu_map(struct iommu_domain *domain, u= nsigned long iova, struct mtk_iommu_domain *dom =3D to_mtk_domain(domain); =20 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ - if (dom->data->enable_4GB) + if (dom->bank->parent_data->enable_4GB) paddr |=3D BIT_ULL(32); =20 /* Synchronize with the tlb_lock */ @@ -690,7 +713,7 @@ static void mtk_iommu_flush_iotlb_all(struct iommu_doma= in *domain) { struct mtk_iommu_domain *dom =3D to_mtk_domain(domain); =20 - mtk_iommu_tlb_flush_all(dom->data); + mtk_iommu_tlb_flush_all(dom->bank->parent_data); } =20 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, @@ -699,7 +722,7 @@ static void mtk_iommu_iotlb_sync(struct iommu_domain *d= omain, struct mtk_iommu_domain *dom =3D to_mtk_domain(domain); size_t length =3D gather->end - gather->start + 1; =20 - mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->data); + mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); } =20 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long = iova, @@ -707,7 +730,7 @@ static void mtk_iommu_sync_map(struct iommu_domain *dom= ain, unsigned long iova, { struct mtk_iommu_domain *dom =3D to_mtk_domain(domain); =20 - mtk_iommu_tlb_flush_range_sync(iova, size, dom->data); + mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); } =20 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, @@ -718,7 +741,7 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_= domain *domain, =20 pa =3D dom->iop->iova_to_phys(dom->iop, iova); if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && - dom->data->enable_4GB && + dom->bank->parent_data->enable_4GB && pa >=3D MTK_IOMMU_4GB_MODE_REMAP_BASE) pa &=3D ~BIT_ULL(32); =20 @@ -885,16 +908,17 @@ static const struct iommu_ops mtk_iommu_ops =3D { =20 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) { + const struct mtk_iommu_bank_data *bank0 =3D &data->bank[0]; u32 regval; =20 if (data->plat_data->m4u_plat =3D=3D M4U_MT8173) { regval =3D F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; } else { - regval =3D readl_relaxed(data->base + REG_MMU_CTRL_REG); + regval =3D readl_relaxed(bank0->base + REG_MMU_CTRL_REG); regval |=3D F_MMU_TF_PROT_TO_PROGRAM_ADDR; } - writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); + writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); =20 if (data->enable_4GB && MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { @@ -903,31 +927,31 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_d= ata *data) * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. */ regval =3D F_MMU_VLD_PA_RNG(7, 4); - writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); + writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); } if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) - writel_relaxed(F_MMU_DCM, data->base + REG_MMU_DCM_DIS); + writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); else - writel_relaxed(0, data->base + REG_MMU_DCM_DIS); + writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); =20 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { /* write command throttling mode */ - regval =3D readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); + regval =3D readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); regval &=3D ~F_MMU_WR_THROT_DIS_MASK; - writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); + writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); } =20 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { /* The register is called STANDARD_AXI_MODE in this case */ regval =3D 0; } else { - regval =3D readl_relaxed(data->base + REG_MMU_MISC_CTRL); + regval =3D readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); if (MTK_IOMMU_HAS_FLAG(data->plat_data, NOT_STD_AXI_MODE)) regval &=3D ~F_MMU_STANDARD_AXI_MODE_MASK; if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) regval &=3D ~F_MMU_IN_ORDER_WR_EN_MASK; } - writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); + writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); =20 regval =3D F_L2_MULIT_HIT_EN | F_TABLE_WALK_FAULT_INT_EN | @@ -935,7 +959,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_dat= a *data) F_MISS_FIFO_OVERFLOW_INT_EN | F_PREFETCH_FIFO_ERR_INT_EN | F_MISS_FIFO_ERR_INT_EN; - writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); + writel_relaxed(regval, bank0->base + REG_MMU_INT_CONTROL0); =20 regval =3D F_INT_TRANSLATION_FAULT | F_INT_MAIN_MULTI_HIT_FAULT | @@ -944,19 +968,19 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_d= ata *data) F_INT_TLB_MISS_FAULT | F_INT_MISS_TRANSACTION_FIFO_FAULT | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; - writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); + writel_relaxed(regval, bank0->base + REG_MMU_INT_MAIN_CONTROL); =20 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) regval =3D (data->protect_base >> 1) | (data->enable_4GB << 31); else regval =3D lower_32_bits(data->protect_base) | upper_32_bits(data->protect_base); - writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); + writel_relaxed(regval, bank0->base + REG_MMU_IVRP_PADDR); =20 - if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, - dev_name(data->dev), (void *)data)) { - writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); - dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); + if (devm_request_irq(bank0->parent_dev, bank0->irq, mtk_iommu_isr, 0, + dev_name(bank0->parent_dev), (void *)bank0)) { + writel_relaxed(0, bank0->base + REG_MMU_PT_BASE_ADDR); + dev_err(bank0->parent_dev, "Failed @ IRQ-%d Request\n", bank0->irq); return -ENODEV; } =20 @@ -1048,9 +1072,11 @@ static int mtk_iommu_probe(struct platform_device *p= dev) struct component_match *match =3D NULL; struct regmap *infracfg; void *protect; - int ret; + int ret, banks_num; u32 val; char *p; + struct mtk_iommu_bank_data *bank; + void __iomem *base; =20 data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -1088,14 +1114,26 @@ static int mtk_iommu_probe(struct platform_device *= pdev) } =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(data->base)) - return PTR_ERR(data->base); + base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); ioaddr =3D res->start; =20 - data->irq =3D platform_get_irq(pdev, 0); - if (data->irq < 0) - return data->irq; + banks_num =3D data->plat_data->banks_num; + data->bank =3D devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KER= NEL); + if (!data->bank) + return -ENOMEM; + + bank =3D &data->bank[0]; + bank->id =3D 0; + bank->base =3D base; + bank->m4u_dom =3D NULL; + bank->irq =3D platform_get_irq(pdev, 0); + if (bank->irq < 0) + return bank->irq; + bank->parent_dev =3D dev; + bank->parent_data =3D data; + spin_lock_init(&bank->tlb_lock); =20 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { data->bclk =3D devm_clk_get(dev, "bclk"); @@ -1132,8 +1170,6 @@ static int mtk_iommu_probe(struct platform_device *pd= ev) if (ret) goto out_sysfs_remove; =20 - spin_lock_init(&data->tlb_lock); - if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { list_add_tail(&data->list, data->plat_data->hw_list); data->hw_list =3D data->plat_data->hw_list; @@ -1183,6 +1219,7 @@ static int mtk_iommu_probe(struct platform_device *pd= ev) static int mtk_iommu_remove(struct platform_device *pdev) { struct mtk_iommu_data *data =3D platform_get_drvdata(pdev); + struct mtk_iommu_bank_data *bank =3D &data->bank[0]; =20 iommu_device_sysfs_remove(&data->iommu); iommu_device_unregister(&data->iommu); @@ -1199,7 +1236,7 @@ static int mtk_iommu_remove(struct platform_device *p= dev) #endif } pm_runtime_disable(&pdev->dev); - devm_free_irq(&pdev->dev, data->irq, data); + devm_free_irq(&pdev->dev, bank->irq, bank); return 0; } =20 @@ -1207,7 +1244,7 @@ static int __maybe_unused mtk_iommu_runtime_suspend(s= truct device *dev) { struct mtk_iommu_data *data =3D dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg =3D &data->reg; - void __iomem *base =3D data->base; + void __iomem *base =3D data->bank[0].base; =20 reg->wr_len_ctrl =3D readl_relaxed(base + REG_MMU_WR_LEN_CTRL); reg->misc_ctrl =3D readl_relaxed(base + REG_MMU_MISC_CTRL); @@ -1225,8 +1262,8 @@ static int __maybe_unused mtk_iommu_runtime_resume(st= ruct device *dev) { struct mtk_iommu_data *data =3D dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg =3D &data->reg; - struct mtk_iommu_domain *m4u_dom =3D data->m4u_dom; - void __iomem *base =3D data->base; + struct mtk_iommu_domain *m4u_dom =3D data->bank[0].m4u_dom; + void __iomem *base =3D data->bank[0].base; int ret; =20 ret =3D clk_prepare_enable(data->bclk); @@ -1274,6 +1311,8 @@ static const struct mtk_iommu_plat_data mt2712_data = =3D { .hw_list =3D &m4ulist, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, .iova_region =3D single_domain, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region_nr =3D ARRAY_SIZE(single_domain), .larbid_remap =3D {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, }; @@ -1283,6 +1322,8 @@ static const struct mtk_iommu_plat_data mt6779_data = =3D { .flags =3D HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), .larbid_remap =3D {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, @@ -1293,6 +1334,8 @@ static const struct mtk_iommu_plat_data mt8167_data = =3D { .flags =3D RESET_AXI | HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), .larbid_remap =3D {{0}, {1}, {2}}, /* Linear mapping. */ @@ -1304,6 +1347,8 @@ static const struct mtk_iommu_plat_data mt8173_data = =3D { HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), .larbid_remap =3D {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ @@ -1313,6 +1358,8 @@ static const struct mtk_iommu_plat_data mt8183_data = =3D { .m4u_plat =3D M4U_MT8183, .flags =3D RESET_AXI | MTK_IOMMU_TYPE_MM, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), .larbid_remap =3D {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, @@ -1324,6 +1371,8 @@ static const struct mtk_iommu_plat_data mt8192_data = =3D { WR_THROT_EN | IOVA_34_EN | NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D mt8192_multi_dom, .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), .larbid_remap =3D {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, @@ -1336,6 +1385,8 @@ static const struct mtk_iommu_plat_data mt8195_data_i= nfra =3D { MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, .pericfg_comp_str =3D "mediatek,mt8195-pericfg_ao", .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), }; @@ -1347,6 +1398,8 @@ static const struct mtk_iommu_plat_data mt8195_data_v= do =3D { SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, .hw_list =3D &m4ulist, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D mt8192_multi_dom, .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), .larbid_remap =3D {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, @@ -1360,6 +1413,8 @@ static const struct mtk_iommu_plat_data mt8195_data_v= pp =3D { SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, .hw_list =3D &m4ulist, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, .iova_region =3D mt8192_multi_dom, .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), .larbid_remap =3D {{1}, {3}, --=20 2.18.0