From nobody Sun Sep 22 09:19:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B218C433F5 for ; Thu, 17 Feb 2022 11:39:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240006AbiBQLjZ (ORCPT ); Thu, 17 Feb 2022 06:39:25 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:47962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240084AbiBQLjO (ORCPT ); Thu, 17 Feb 2022 06:39:14 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 363142AE72F; Thu, 17 Feb 2022 03:38:44 -0800 (PST) X-UUID: 38a29895429d42169a49741cade37994-20220217 X-UUID: 38a29895429d42169a49741cade37994-20220217 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1653767341; Thu, 17 Feb 2022 19:38:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 17 Feb 2022 19:38:39 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 19:38:38 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , "Matthias Brugger" , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , , Hsin-Yi Wang , , , , , , "AngeloGioacchino Del Regno" , , , , Subject: [PATCH v5 23/34] iommu/mediatek: Only adjust code about register base Date: Thu, 17 Feb 2022 19:34:42 +0800 Message-ID: <20220217113453.13658-24-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220217113453.13658-1-yong.wu@mediatek.com> References: <20220217113453.13658-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No functional change. Use "base" instead of the data->base. This is avoid to touch too many lines in the next patches. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 51 +++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0370fd6f0eca..c068e0c0ebf4 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -227,12 +227,12 @@ static struct mtk_iommu_domain *to_mtk_domain(struct = iommu_domain *dom) =20 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) { + void __iomem *base =3D data->base; unsigned long flags; =20 spin_lock_irqsave(&data->tlb_lock, flags); - writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + data->plat_data->inv_sel_reg); - writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); + writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel= _reg); + writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); wmb(); /* Make sure the tlb flush all done */ spin_unlock_irqrestore(&data->tlb_lock, flags); } @@ -243,6 +243,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned lon= g iova, size_t size, struct list_head *head =3D data->hw_list; bool check_pm_status; unsigned long flags; + void __iomem *base; int ret; u32 tmp; =20 @@ -269,23 +270,23 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned l= ong iova, size_t size, continue; } =20 + base =3D data->base; + spin_lock_irqsave(&data->tlb_lock, flags); writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + data->plat_data->inv_sel_reg); + base + data->plat_data->inv_sel_reg); =20 - writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), - data->base + REG_MMU_INVLD_START_A); + writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), - data->base + REG_MMU_INVLD_END_A); - writel_relaxed(F_MMU_INV_RANGE, - data->base + REG_MMU_INVALIDATE); + base + REG_MMU_INVLD_END_A); + writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); =20 /* tlb sync */ - ret =3D readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, + ret =3D readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, tmp, tmp !=3D 0, 10, 1000); =20 /* Clear the CPE status */ - writel_relaxed(0, data->base + REG_MMU_CPE_DONE); + writel_relaxed(0, base + REG_MMU_CPE_DONE); spin_unlock_irqrestore(&data->tlb_lock, flags); =20 if (ret) { @@ -305,23 +306,25 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_i= d) struct mtk_iommu_domain *dom =3D data->m4u_dom; unsigned int fault_larb =3D MTK_INVALID_LARBID, fault_port =3D 0, sub_com= m =3D 0; u32 int_state, regval, va34_32, pa34_32; + const struct mtk_iommu_plat_data *plat_data =3D data->plat_data; + void __iomem *base =3D data->base; u64 fault_iova, fault_pa; bool layer, write; =20 /* Read error info from registers */ - int_state =3D readl_relaxed(data->base + REG_MMU_FAULT_ST1); + int_state =3D readl_relaxed(base + REG_MMU_FAULT_ST1); if (int_state & F_REG_MMU0_FAULT_MASK) { - regval =3D readl_relaxed(data->base + REG_MMU0_INT_ID); - fault_iova =3D readl_relaxed(data->base + REG_MMU0_FAULT_VA); - fault_pa =3D readl_relaxed(data->base + REG_MMU0_INVLD_PA); + regval =3D readl_relaxed(base + REG_MMU0_INT_ID); + fault_iova =3D readl_relaxed(base + REG_MMU0_FAULT_VA); + fault_pa =3D readl_relaxed(base + REG_MMU0_INVLD_PA); } else { - regval =3D readl_relaxed(data->base + REG_MMU1_INT_ID); - fault_iova =3D readl_relaxed(data->base + REG_MMU1_FAULT_VA); - fault_pa =3D readl_relaxed(data->base + REG_MMU1_INVLD_PA); + regval =3D readl_relaxed(base + REG_MMU1_INT_ID); + fault_iova =3D readl_relaxed(base + REG_MMU1_FAULT_VA); + fault_pa =3D readl_relaxed(base + REG_MMU1_INVLD_PA); } layer =3D fault_iova & F_MMU_FAULT_VA_LAYER_BIT; write =3D fault_iova & F_MMU_FAULT_VA_WRITE_BIT; - if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { + if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { va34_32 =3D FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); fault_iova =3D fault_iova & F_MMU_INVAL_VA_31_12_MASK; fault_iova |=3D (u64)va34_32 << 32; @@ -329,12 +332,12 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_i= d) pa34_32 =3D FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); fault_pa |=3D (u64)pa34_32 << 32; =20 - if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { + if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { fault_port =3D F_MMU_INT_ID_PORT_ID(regval); - if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_2BITS)) { + if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID(regval); - } else if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_3BITS)) { + } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { fault_larb =3D F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm =3D F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); } else { @@ -353,9 +356,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) } =20 /* Interrupt clear */ - regval =3D readl_relaxed(data->base + REG_MMU_INT_CONTROL0); + regval =3D readl_relaxed(base + REG_MMU_INT_CONTROL0); regval |=3D F_INT_CLR_BIT; - writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); + writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); =20 mtk_iommu_tlb_flush_all(data); =20 --=20 2.18.0