From nobody Sun Sep 22 09:31:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 968A4C433F5 for ; Thu, 17 Feb 2022 11:39:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240008AbiBQLjV (ORCPT ); Thu, 17 Feb 2022 06:39:21 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:47900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240091AbiBQLjF (ORCPT ); Thu, 17 Feb 2022 06:39:05 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5C4E99ECA; Thu, 17 Feb 2022 03:38:31 -0800 (PST) X-UUID: 2c338d9b6145499b9015c0b7c599b251-20220217 X-UUID: 2c338d9b6145499b9015c0b7c599b251-20220217 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1404140774; Thu, 17 Feb 2022 19:38:28 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 17 Feb 2022 19:38:26 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 19:38:25 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , "Matthias Brugger" , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , , Hsin-Yi Wang , , , , , , "AngeloGioacchino Del Regno" , , , , Subject: [PATCH v5 22/34] iommu/mediatek: Add mt8195 support Date: Thu, 17 Feb 2022 19:34:41 +0800 Message-ID: <20220217113453.13658-23-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220217113453.13658-1-yong.wu@mediatek.com> References: <20220217113453.13658-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mt8195 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other is for vpp. and 1 INFRA IOMMU. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 43 +++++++++++++++++++++++++++++++++++++++ drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 44 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 158185302d53..0370fd6f0eca 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1232,6 +1232,46 @@ static const struct mtk_iommu_plat_data mt8192_data = =3D { {0, 14, 16}, {0, 13, 18, 17}}, }; =20 +static const struct mtk_iommu_plat_data mt8195_data_infra =3D { + .m4u_plat =3D M4U_MT8195, + .flags =3D WR_THROT_EN | DCM_DISABLE | PM_CLK_AO | + MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, + .pericfg_comp_str =3D "mediatek,mt8195-pericfg_ao", + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .iova_region =3D single_domain, + .iova_region_nr =3D ARRAY_SIZE(single_domain), +}; + +static const struct mtk_iommu_plat_data mt8195_data_vdo =3D { + .m4u_plat =3D M4U_MT8195, + .flags =3D HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | + WR_THROT_EN | NOT_STD_AXI_MODE | IOVA_34_EN | + SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, + .hw_list =3D &m4ulist, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .iova_region =3D mt8192_multi_dom, + .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), + .larbid_remap =3D {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, + {13, 17, 15/* 17b */, 25}, {5}}, +}; + +static const struct mtk_iommu_plat_data mt8195_data_vpp =3D { + .m4u_plat =3D M4U_MT8195, + .flags =3D HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | + WR_THROT_EN | NOT_STD_AXI_MODE | IOVA_34_EN | + SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, + .hw_list =3D &m4ulist, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .iova_region =3D mt8192_multi_dom, + .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), + .larbid_remap =3D {{1}, {3}, + {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, + {8}, {20}, {12}, + /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ + {14, 16, 29, 26, 30, 31, 18}, + {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, +}; + static const struct of_device_id mtk_iommu_of_ids[] =3D { { .compatible =3D "mediatek,mt2712-m4u", .data =3D &mt2712_data}, { .compatible =3D "mediatek,mt6779-m4u", .data =3D &mt6779_data}, @@ -1239,6 +1279,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = =3D { { .compatible =3D "mediatek,mt8173-m4u", .data =3D &mt8173_data}, { .compatible =3D "mediatek,mt8183-m4u", .data =3D &mt8183_data}, { .compatible =3D "mediatek,mt8192-m4u", .data =3D &mt8192_data}, + { .compatible =3D "mediatek,mt8195-iommu-infra", .data =3D &mt8195_data_i= nfra}, + { .compatible =3D "mediatek,mt8195-iommu-vdo", .data =3D &mt8195_data_v= do}, + { .compatible =3D "mediatek,mt8195-iommu-vpp", .data =3D &mt8195_data_v= pp}, {} }; =20 diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 04e5e5e7fd62..9dba98bb12eb 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -46,6 +46,7 @@ enum mtk_iommu_plat { M4U_MT8173, M4U_MT8183, M4U_MT8192, + M4U_MT8195, }; =20 struct mtk_iommu_iova_region; --=20 2.18.0