From nobody Sun Sep 22 09:25:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF121C43217 for ; Thu, 17 Feb 2022 11:36:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239890AbiBQLhK (ORCPT ); Thu, 17 Feb 2022 06:37:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:42046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239909AbiBQLhH (ORCPT ); Thu, 17 Feb 2022 06:37:07 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B83FF106627; Thu, 17 Feb 2022 03:36:50 -0800 (PST) X-UUID: 581605e0d72a4b9a9311175d78bb031d-20220217 X-UUID: 581605e0d72a4b9a9311175d78bb031d-20220217 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 164362; Thu, 17 Feb 2022 19:36:47 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 17 Feb 2022 19:36:46 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 19:36:45 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , "Matthias Brugger" , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , , Hsin-Yi Wang , , , , , , "AngeloGioacchino Del Regno" , , , , Subject: [PATCH v5 11/34] iommu/mediatek: Add a flag NON_STD_AXI Date: Thu, 17 Feb 2022 19:34:30 +0800 Message-ID: <20220217113453.13658-12-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220217113453.13658-1-yong.wu@mediatek.com> References: <20220217113453.13658-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new flag NON_STD_AXI, All the previous SoC support this flag. Prepare for adding infra and apu iommu which don't support this. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 3418b5782830..ce593f77649f 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -122,6 +122,7 @@ #define IOVA_34_EN BIT(8) #define SHARE_PGTABLE BIT(9) /* 2 HW share pgtable */ #define DCM_DISABLE BIT(10) +#define NOT_STD_AXI_MODE BIT(11) =20 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ ((((pdata)->flags) & (_x)) =3D=3D (_x)) @@ -783,7 +784,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_dat= a *data) regval =3D 0; } else { regval =3D readl_relaxed(data->base + REG_MMU_MISC_CTRL); - regval &=3D ~F_MMU_STANDARD_AXI_MODE_MASK; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, NOT_STD_AXI_MODE)) + regval &=3D ~F_MMU_STANDARD_AXI_MODE_MASK; if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) regval &=3D ~F_MMU_IN_ORDER_WR_EN_MASK; } @@ -1056,7 +1058,8 @@ static const struct dev_pm_ops mtk_iommu_pm_ops =3D { =20 static const struct mtk_iommu_plat_data mt2712_data =3D { .m4u_plat =3D M4U_MT2712, - .flags =3D HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABL= E, + .flags =3D HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABL= E | + NOT_STD_AXI_MODE, .hw_list =3D &m4ulist, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, .iova_region =3D single_domain, @@ -1066,7 +1069,8 @@ static const struct mtk_iommu_plat_data mt2712_data = =3D { =20 static const struct mtk_iommu_plat_data mt6779_data =3D { .m4u_plat =3D M4U_MT6779, - .flags =3D HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, + .flags =3D HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN | + NOT_STD_AXI_MODE, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), @@ -1075,7 +1079,7 @@ static const struct mtk_iommu_plat_data mt6779_data = =3D { =20 static const struct mtk_iommu_plat_data mt8167_data =3D { .m4u_plat =3D M4U_MT8167, - .flags =3D RESET_AXI | HAS_LEGACY_IVRP_PADDR, + .flags =3D RESET_AXI | HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), @@ -1085,7 +1089,7 @@ static const struct mtk_iommu_plat_data mt8167_data = =3D { static const struct mtk_iommu_plat_data mt8173_data =3D { .m4u_plat =3D M4U_MT8173, .flags =3D HAS_4GB_MODE | HAS_BCLK | RESET_AXI | - HAS_LEGACY_IVRP_PADDR, + HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, .iova_region =3D single_domain, .iova_region_nr =3D ARRAY_SIZE(single_domain), @@ -1104,7 +1108,7 @@ static const struct mtk_iommu_plat_data mt8183_data = =3D { static const struct mtk_iommu_plat_data mt8192_data =3D { .m4u_plat =3D M4U_MT8192, .flags =3D HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN | - WR_THROT_EN | IOVA_34_EN, + WR_THROT_EN | IOVA_34_EN | NOT_STD_AXI_MODE, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, .iova_region =3D mt8192_multi_dom, .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), --=20 2.18.0