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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id g21sm20882584qtb.70.2022.02.15.16.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 16:29:20 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Anup Patel , Heiko Stuebner , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v4 1/6] RISC-V: Correctly print supported extensions Date: Tue, 15 Feb 2022 16:29:06 -0800 Message-Id: <20220216002911.1219593-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com> References: <20220216002911.1219593-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel Tested-by: Heiko Stuebner Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include =20 +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; =20 /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); --=20 2.30.2 From nobody Sun Jun 28 02:51:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFF26C4321E for ; Wed, 16 Feb 2022 00:29:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245065AbiBPA3n (ORCPT ); Tue, 15 Feb 2022 19:29:43 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244663AbiBPA3g (ORCPT ); Tue, 15 Feb 2022 19:29:36 -0500 Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E63FF70EA for ; Tue, 15 Feb 2022 16:29:24 -0800 (PST) Received: by mail-qk1-x732.google.com with SMTP id de39so343890qkb.13 for ; Tue, 15 Feb 2022 16:29:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oPhfrRu9lOMUwT/7SSpNUGyvJjdNpXCP/wW++bFxhRc=; b=YPlmDeBF2w6ovQYBYeEzPbox6WtothHnO7nsxF53hmX5zJ0jsbDAZKFrpdr0D1vh0z BbtZFa59zGUcnQ6/cbDnd6PQANTTzmOeB+gsU48SuAocmqBcD4N+sy7LAskYEaXBbwON faFomcz6BuIUnNy12LVRLPmhUmXV2EuhqKhLv5YuTTEKFMqRf/Emz0Vl33gr1+NI30yy WOWkisZcDD98K0wjYQAUeBQPkSOJ2RrMxr4zqfkXb6dusQu7XfRJqSUgx4b6fbppCbtY VEq5tpGWHkbhOf7QjDe3WcQ0aDkKljAApomEwZzmb4UtaF2z/YR0SswW3HCXgIO6LJm8 WaXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oPhfrRu9lOMUwT/7SSpNUGyvJjdNpXCP/wW++bFxhRc=; b=b8GBZ6QfJNJhgCcYQBkWAxCAlbqgU0jUqLqYPFDpkJWUYulEyzOBpxuyjUO0GrzuJh y69+cg1snd6xXp+9kom9M6tECv8D+sgY144h/FxDo9COp9Mc3T9NwXoOmSjbp6yfffUk vDQY67E83r6RunUoTlDaCteslX337Gt33pMAjM0SIoV+Q64YozyEiGJpj5fVpcDX6UPn D/pT3I8InLe/t8Ompq5uBHkeevYg2f1eK7JEeleQSW+v2xG+vfFx7cI0TSzu61dVG+HN Q7FMr74gHCEa2zCIigbijLgjO4qBv35ggoor95zsBYBt3Ktu7tcuIbPHq6lyfYOK4tAW xJdw== X-Gm-Message-State: AOAM533OIjW/9M8Nt3EJVR8gBbAtGIyzn8CXnWIqiZIO9nPEaNxw4mxy h7kPmPzAb2UlsC7HbULp6jJRbXHqVTmKUwOo X-Google-Smtp-Source: ABdhPJwjUXfhUdSHWN5jaqEIsJNOX3lvX7622QszkSBMLvEK3VhO3Psn4rluzieRO/ioHE2DD9qi0Q== X-Received: by 2002:a37:2797:0:b0:605:bbdb:310d with SMTP id n145-20020a372797000000b00605bbdb310dmr208086qkn.638.1644971363199; Tue, 15 Feb 2022 16:29:23 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id g21sm20882584qtb.70.2022.02.15.16.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 16:29:22 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v4 2/6] RISC-V: Minimal parser for "riscv, isa" strings Date: Tue, 15 Feb 2022 16:29:07 -0800 Message-Id: <20220216002911.1219593-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com> References: <20220216002911.1219593-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra [Fixed workaround for QEMU] Signed-off-by: Tsukasa OI Tested-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 67 ++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dd3d57eb4eea..65664422b04d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; + int i, j; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -92,23 +93,67 @@ void __init riscv_fill_hwcap(void) continue; } =20 - i =3D 0; - isa_len =3D strlen(isa); #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) - i +=3D 4; + isa +=3D 4; #elif IS_ENABLED(CONFIG_64BIT) if (!strncmp(isa, "rv64", 4)) - i +=3D 4; + isa +=3D 4; #endif - for (; i < isa_len; ++i) { - this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + for (; *isa; ++isa) { + const char *ext =3D isa++; + const char *ext_end =3D isa; + bool ext_long =3D false, ext_err =3D false; + + switch (*ext) { + case 's': + case 'x': + case 'z': + /** + * Workaround for invalid single-letter 's' (QEMU). + * It works until multi-letter extension starting + * with "Su" appears. + */ + if (*ext =3D=3D 's' && ext[-1] !=3D '_' && ext[1] =3D=3D 'u') + break; + ext_long =3D true; + /* Multi-letter extension must be delimited */ + for (; *isa && *isa !=3D '_'; ++isa) + if (!islower(*isa) && !isdigit(*isa)) + ext_err =3D true; + break; + default: + if (unlikely(!islower(*ext))) { + ext_err =3D true; + break; + } + /* Find next extension */ + if (!isdigit(*isa)) + break; + /* Skip the minor version */ + while (isdigit(*++isa)) + ; + if (*isa !=3D 'p') + break; + if (!isdigit(*++isa)) { + --isa; + break; + } + /* Skip the major version */ + while (isdigit(*++isa)) + ; + break; + } + if (*isa !=3D '_') + --isa; /* - * TODO: X, Y and Z extension parsing for Host ISA - * bitmap will be added in-future. + * TODO: Full version-aware handling including + * multi-letter extensions will be added in-future. */ - if ('a' <=3D isa[i] && isa[i] < 'x') - this_isa |=3D (1UL << (isa[i] - 'a')); + if (ext_err || ext_long) + continue; + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); } =20 /* --=20 2.30.2 From nobody Sun Jun 28 02:51:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7771C433FE for ; Wed, 16 Feb 2022 00:29:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245073AbiBPA3p (ORCPT ); Tue, 15 Feb 2022 19:29:45 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244731AbiBPA3i (ORCPT ); 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id g21sm20882584qtb.70.2022.02.15.16.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 16:29:24 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Heiko Stuebner , Anup Patel , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v4 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Date: Tue, 15 Feb 2022 16:29:08 -0800 Message-Id: <20220216002911.1219593-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com> References: <20220216002911.1219593-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by: Heiko Stuebner Reviewed-by: Anup Patel Signed-off-by: Tsukasa OI [Improved commit text and comments] Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 35 ++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 65664422b04d..cd9eb34f8d11 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -119,8 +119,28 @@ void __init riscv_fill_hwcap(void) ext_long =3D true; /* Multi-letter extension must be delimited */ for (; *isa && *isa !=3D '_'; ++isa) - if (!islower(*isa) && !isdigit(*isa)) + if (unlikely(!islower(*isa) + && !isdigit(*isa))) ext_err =3D true; + /* Parse backwards */ + ext_end =3D isa; + if (unlikely(ext_err)) + break; + if (!isdigit(ext_end[-1])) + break; + /* Skip the minor version */ + while (isdigit(*--ext_end)) + ; + if (ext_end[0] !=3D 'p' + || !isdigit(ext_end[-1])) { + /* Advance it to offset the pre-decrement */ + ++ext_end; + break; + } + /* Skip the major version */ + while (isdigit(*--ext_end)) + ; + ++ext_end; break; default: if (unlikely(!islower(*ext))) { @@ -146,14 +166,13 @@ void __init riscv_fill_hwcap(void) } if (*isa !=3D '_') --isa; - /* - * TODO: Full version-aware handling including - * multi-letter extensions will be added in-future. - */ - if (ext_err || ext_long) + + if (unlikely(ext_err)) continue; - this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + if (!ext_long) { + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); + } } =20 /* --=20 2.30.2 From nobody Sun Jun 28 02:51:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98391C4332F for ; Wed, 16 Feb 2022 00:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245080AbiBPA3r (ORCPT ); Tue, 15 Feb 2022 19:29:47 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245054AbiBPA3k (ORCPT ); Tue, 15 Feb 2022 19:29:40 -0500 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D343F70FC for ; Tue, 15 Feb 2022 16:29:28 -0800 (PST) Received: by mail-qt1-x82e.google.com with SMTP id o3so546388qtm.12 for ; Tue, 15 Feb 2022 16:29:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+mccZjH8NSKhWBiWsNwtOYrEp5jTHyxoNdNyuVqRQ88=; b=mDyg+hQZjMQDU9Uq7wsWXXtGXQt/Kj3wzuz1/ouJ/1Wf9LjhMW6HW/T5utJ7R+WoUO 8ZXqbkqpEOb7GH1YMqNDIXq+OW1lM5Ma7mLStdU64iy/UHbzDEKDPbQjJ3HcCvwwdlbI bsswUsWe0lxui3GYvtDlMTQKfDytGV898nYDWDOQANRtVJSQ1Kv35c7mkzYzj5MRe47v RRGq65bEr75KzZdsUYEPWi1htw2XehtkmyS9FwVO5wnnBz6H/lkp6qAEkHXXQI54eeQt Z/NDyijOhyhwoQBNpbyY6YKCoQU5JfwFIcTXE+jrErWVabp3/EAv827jBRw0BggzjQ41 FXMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+mccZjH8NSKhWBiWsNwtOYrEp5jTHyxoNdNyuVqRQ88=; b=OACcaZqDWEM5OSmrpnPFKbJGWfSajf5jWOa6K7XKLTrG9M6tBGnbfyYpXlpwwPQCdU 0Z5cBPIj7vBlzIezN5x+Ug2DCj9BQEHypUR/E3B3Ipdce+81MGrX+p4Ak5/qo51fr+Tz gyFUxcmyeHy0MUq63MK5K7An9siB+D3F5iqF2p/t8x0Vz6ZueqZzXeo/pEDBAZauVu06 j0hc+FG6v/z0mzvbmpe7RaYmB/0vS7PPhOh3D8L8r0lj4tkmC0J/AwfaqBrDX1dh9a9z 0Md3xa+WBELBhcXtHCFI5pxRw1Ut9UISxOuaDwlZF5M1zsR0sjqzPV7KvsYuGA13LAiz oHRA== X-Gm-Message-State: AOAM531WVIfl7KVgekCtM8Ae7yOKIWFGBAdvGwRJIWCLM+inEZKwXJvS Hl3U1Tk12HMOIdwjgfaLOcvTszNeC7Yd1rS0 X-Google-Smtp-Source: ABdhPJxX/1iKDISaumVfrJKyBSCp+qB9sw5uGTWszMRMIRfujWc3uyE9wjTNu2++q4autCmibTBZPQ== X-Received: by 2002:a05:622a:4d2:b0:2d7:1d2e:6dd0 with SMTP id q18-20020a05622a04d200b002d71d2e6dd0mr372899qtx.615.1644971367357; Tue, 15 Feb 2022 16:29:27 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id g21sm20882584qtb.70.2022.02.15.16.29.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 16:29:26 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , heiko@sntech.de, Rob Herring Subject: [PATCH v4 4/6] RISC-V: Implement multi-letter ISA extension probing framework Date: Tue, 15 Feb 2022 16:29:09 -0800 Message-Id: <20220216002911.1219593-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com> References: <20220216002911.1219593-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..170bd80da520 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') =20 +/* + * Increse this to higher value as kernel support more ISA extensions. + */ #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +/* The base ID for multi-letter ISA extensions */ +#define RISCV_ISA_EXT_BASE 26 + +/* + * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter + * extensions while all the multi-letter extensions should define the next + * available logical extension id. + */ +enum riscv_isa_ext_id { + RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, +}; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index cd9eb34f8d11..59c70c104256 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) =20 for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; - unsigned long this_isa =3D 0; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -100,6 +100,7 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; const char *ext_end =3D isa; @@ -167,12 +168,22 @@ void __init riscv_fill_hwcap(void) if (*isa !=3D '_') --isa; =20 +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + set_bit(bit, this_isa); \ + pr_info("Found ISA extension %s", name);\ + } \ + } while (false) \ + if (unlikely(ext_err)) continue; if (!ext_long) { this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + set_bit(*ext - 'a', this_isa); } +#undef SET_ISA_EXT_MAP } =20 /* @@ -185,10 +196,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap =3D this_hwcap; =20 - if (riscv_isa[0]) - riscv_isa[0] &=3D this_isa; + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else - riscv_isa[0] =3D this_isa; + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } =20 /* We don't support systems with F but without D, so mask those out @@ -202,7 +214,7 @@ void __init riscv_fill_hwcap(void) for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); - pr_info("riscv: ISA extensions %s\n", print_str); + pr_info("riscv: base ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) --=20 2.30.2 From nobody Sun Jun 28 02:51:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C424BC433EF for ; Wed, 16 Feb 2022 00:29:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245088AbiBPA3u (ORCPT ); Tue, 15 Feb 2022 19:29:50 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244115AbiBPA3l (ORCPT ); Tue, 15 Feb 2022 19:29:41 -0500 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA1EFF70E3 for ; Tue, 15 Feb 2022 16:29:30 -0800 (PST) Received: by mail-qk1-x735.google.com with SMTP id o25so372159qkj.7 for ; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id g21sm20882584qtb.70.2022.02.15.16.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 16:29:29 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , heiko@sntech.de, Rob Herring Subject: [PATCH v4 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Tue, 15 Feb 2022 16:29:10 -0800 Message-Id: <20220216002911.1219593-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com> References: <20220216002911.1219593-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59c70c104256..cb9c9e0aab31 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + const char *temp; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } =20 + temp =3D isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa +=3D 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp =3D=3D isa) + continue; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; --=20 2.30.2 From nobody Sun Jun 28 02:51:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7518C4332F for ; Wed, 16 Feb 2022 00:29:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245098AbiBPA3x (ORCPT ); Tue, 15 Feb 2022 19:29:53 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244663AbiBPA3n (ORCPT ); Tue, 15 Feb 2022 19:29:43 -0500 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 894EAF70E3 for ; Tue, 15 Feb 2022 16:29:32 -0800 (PST) Received: by mail-qk1-x72e.google.com with SMTP id d84so367297qke.8 for ; Tue, 15 Feb 2022 16:29:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=saY5DtvepsvwegCELkFkB7RgpB9RohGc6lIP30RliiM=; b=WeZDZR/wgQ3HJBPaI1lbXHd1ymtPQLDkS89Y+hauG1FO7BiVnsUlJENU/aTTHJpzEc froSAw9Ech0bJ+/c1Eraap/5RgylGvP7owPvkrrM6DFIeriyFvDtSEYJItciK+P4Q+a4 ZP5M4HEm1g7/v2Ef94+/nNSZaRNRm8L84VFyZ6sXbTE9YoJyfSqPFlpxEIik7YVM+TbG N8fGGs4RzKaRlfIuJqT0RWYV9frhIGhYUyECWmefGtcKfY7AIBCPxirqDhAOIxi/Bpbz kEwPGV+cemQeaXAUaJayW4Hiez9IXaR63DTPml67Vo00MLrsCxo9jgVcVldPNI7DRUsX 0VBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=saY5DtvepsvwegCELkFkB7RgpB9RohGc6lIP30RliiM=; b=lCl+5rlL6YgIHt7Dd9yAIhRrR0nFQQpG3zCltLiolA3LxXy/lJhS5gNauSkMizzqv+ AyZcOrHu7E7QJmJ3d8f4piaDVDEpiXjYhSYrpY8J8W+IKVBM4PmvGD06dIBWeXhvf9dd kORY/NFliP5V+Nb4aX5V1r+97WQCWlQYtlsvKJ/B7V+YvHDQTRmI540OpuACtWPuvUMd mLaRSfkNC+cDmAsOi8QybGxh9t2GV7XTO4My4pp08tyERMY09km6rFSUSi45XHBCrGen 72EmR/7FKYVGpQE5Qpv63eAizcrTTWSqmok5/h7k1h9dQUeXSqn3o2ErWokrdasJiE6l cgJA== X-Gm-Message-State: AOAM531sLD/Z+p99aTyvs62olBmZ/MlsMJGpDLKH1fw+hzLxT85C6fAF rQz2Qi06JgXGGVKQP75JIMyiN6xbuiz0FPwB X-Google-Smtp-Source: ABdhPJxgLsfYpRA+QvmhMNAXVF99c28x84OUD52yELKhbQvJUdEA4sPu3mofe6wteSIvVcp8Ebs2nQ== X-Received: by 2002:a37:d2c7:0:b0:47b:4cd8:5dbc with SMTP id f190-20020a37d2c7000000b0047b4cd85dbcmr187629qkj.567.1644971371452; Tue, 15 Feb 2022 16:29:31 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id g21sm20882584qtb.70.2022.02.15.16.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 16:29:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , heiko@sntech.de, Rob Herring Subject: [PATCH v4 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Tue, 15 Feb 2022 16:29:11 -0800 Message-Id: <20220216002911.1219593-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com> References: <20220216002911.1219593-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Parse only the enabled ISA extension and print them in a separate row. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 7 ++++++ arch/riscv/kernel/cpu.c | 44 ++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, }; =20 +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..ced7e5be8641 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -63,12 +64,50 @@ int riscv_of_parent_hartid(struct device_node *node) } =20 #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop =3D #UPROP, \ + .isa_ext_id =3D EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] =3D { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i =3D 0, arr_sz; + + arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <=3D 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i =3D 0; i <=3D arr_sz; i++) { + edata =3D &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} =20 static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + char *ext_start; + int isa_len =3D strlen(isa); + int base_isa_len =3D isa_len; + + ext_start =3D strnchr(isa, isa_len, '_'); + if (ext_start) + base_isa_len =3D isa_len - strlen(ext_start); + + /* Print only the base ISA as it is */ seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + seq_write(f, isa, base_isa_len); seq_puts(f, "\n"); } =20 @@ -115,6 +154,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) --=20 2.30.2