From nobody Fri Dec 19 19:16:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD0E3C433F5 for ; Wed, 16 Feb 2022 10:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233059AbiBPK2A (ORCPT ); Wed, 16 Feb 2022 05:28:00 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232902AbiBPK1M (ORCPT ); Wed, 16 Feb 2022 05:27:12 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C797212E22; Wed, 16 Feb 2022 02:26:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645007217; x=1676543217; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tOG0HGFswSqrhB0EjQg7576eejc092m+g6ZKmtluB4I=; b=nGhJIKJlfsEfmsZZFCk121fQdy8L4foDLaA+plhH5z2+i1p8fh7/mIlb HfD+4zE9uCUZFdDbicg2kifwUa4v0m7i1Xm4nu9FY68JJ5zwY7IoHouWL ECqcpGgd/ZBbpyt9NhjnuoyaM8LHFflJI6ttyiesqRet/zhS8zKBKwUNK lniBUAXT8OtkK15LM3geZf+8ULczGIYhXV+qzfmaaJVYmS68uZv118YTZ BF2hy+DvMiJ01qo7fZQKOC/ce2wBGFsmhGwAI38rUwZVzN4HSgL/lLimb zC+31910dNGxpDwL6cMTy4e9uBPJvXUAOMSuu8lWhiaLGPYfL483QgVWo A==; X-IronPort-AV: E=McAfee;i="6200,9189,10259"; a="250312483" X-IronPort-AV: E=Sophos;i="5.88,373,1635231600"; d="scan'208";a="250312483" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 02:26:51 -0800 X-IronPort-AV: E=Sophos;i="5.88,373,1635231600"; d="scan'208";a="498708646" Received: from embargo.jf.intel.com ([10.165.9.183]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 02:26:51 -0800 From: Yang Weijiang To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com, like.xu.linux@gmail.com, vkuznets@redhat.com, wei.w.wang@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Yang Weijiang , Like Xu Subject: [PATCH v9 17/17] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID Date: Tue, 15 Feb 2022 16:25:44 -0500 Message-Id: <20220215212544.51666-18-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220215212544.51666-1-weijiang.yang@intel.com> References: <20220215212544.51666-1-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Arch LBR feature bit in CPU cap-mask to expose the feature. Only max LBR depth is supported for guest, and it's consistent with host Arch LBR settings. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Yang Weijiang --- arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 8cd864411a1c..285628887734 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -102,6 +102,16 @@ static int kvm_check_cpuid(struct kvm_vcpu *vcpu, if (vaddr_bits !=3D 48 && vaddr_bits !=3D 57 && vaddr_bits !=3D 0) return -EINVAL; } + best =3D cpuid_entry2_find(entries, nent, 0x1c, 0); + if (best) { + unsigned int eax, ebx, ecx, edx; + + /* Reject user-space CPUID if depth is different from host's.*/ + cpuid_count(0x1c, 0, &eax, &ebx, &ecx, &edx); + + if ((best->eax & 0xff) !=3D BIT(fls(eax & 0xff) - 1)) + return -EINVAL; + } =20 /* * Exposing dynamic xfeatures to the guest requires additional @@ -600,7 +610,7 @@ void kvm_set_cpu_caps(void) F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | - F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) + F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(ARCH_LBR) ); =20 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ @@ -1023,6 +1033,27 @@ static inline int __do_cpuid_func(struct kvm_cpuid_a= rray *array, u32 function) goto out; } break; + /* Architectural LBR */ + case 0x1c: { + u32 lbr_depth_mask =3D entry->eax & 0xff; + + if (!lbr_depth_mask || + !kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) { + entry->eax =3D entry->ebx =3D entry->ecx =3D entry->edx =3D 0; + break; + } + /* + * KVM only exposes the maximum supported depth, which is the + * fixed value used on the host side. + * KVM doesn't allow VMM userspace to adjust LBR depth because + * guest LBR emulation depends on the configuration of host LBR + * driver. + */ + lbr_depth_mask =3D BIT((fls(lbr_depth_mask) - 1)); + entry->eax &=3D ~0xff; + entry->eax |=3D lbr_depth_mask; + break; + } /* Intel AMX TILE */ case 0x1d: if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { --=20 2.27.0