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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 1/6] RISC-V: Correctly print supported extensions Date: Tue, 15 Feb 2022 01:02:06 -0800 Message-Id: <20220215090211.911366-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra Tested-by: Heiko Stuebner Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include =20 +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; =20 /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); --=20 2.30.2 From nobody Mon Jun 29 06:31:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29863C433EF for ; Tue, 15 Feb 2022 09:02:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235556AbiBOJCv (ORCPT ); Tue, 15 Feb 2022 04:02:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235537AbiBOJCq (ORCPT ); Tue, 15 Feb 2022 04:02:46 -0500 Received: from mail-qt1-x836.google.com (mail-qt1-x836.google.com [IPv6:2607:f8b0:4864:20::836]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6554110610A for ; Tue, 15 Feb 2022 01:02:35 -0800 (PST) Received: by mail-qt1-x836.google.com with SMTP id e16so17958716qtq.6 for ; Tue, 15 Feb 2022 01:02:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jKIMNTCTSaMpDoiqtlH3Q9QXsNmu9SOq71EHGRiXKQg=; b=IKo/im9vNvmw3DDbv7pl3Jy9rQHe0pf4uWP6c70xfG0w+L4au40G42ELqNNlEIA5t5 lotcK9NYVkKEcMFnpug+isg/KHOOChYTsJtA16RR+TbVa03ziUCKC/Fo5mw1PqrqzhtA Blvot4EgBJLkRgNAM+hVnd9AC/c8iSPBO6+Wy5D7qQm5/01SKrw/DRSMKXYJu1vS78tD dbUlx/AVYIoYfRA+tjbRv2MapUG0BRXUVnK9MmPN46SmiBQg14AHV6WYM5FNl4gbaw/D NAdbSrlv+ILXXpa7B/0Fm8qCNJBeWr0VxgnfpvbXtOuvdc2gbPza0pR0RnP4ttCQXTrd K76A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jKIMNTCTSaMpDoiqtlH3Q9QXsNmu9SOq71EHGRiXKQg=; b=4wlA0h70FO8/eTsYY+cxZxsz2133MVbwBLchwDOETDDik82l95HahDuW82b5Pv5BxY Nqob9byf2nprOsKAlq/QOAe2Sev80n3lVy19cQDi31Sw6YFHZTRVpYAbk9Cgm96+6570 PpQfqHn+oH+NvbHcN5bjFP/k02yA8NVd4HNzQG/cuaYuv1laxx3I1Ln+JqUAWCawSUE3 B+5tFq+VlWXvQOBIOcqFUchebBFK4F+097EscHHY/5JwKbB2FzmJLWGkEFdLcy+Sl1AR ra2OKGtHzG9bub1+/Q8U93Fs64ol3PreY5DwZeE1JYHh0aSUQ/slip8ezM6tu1xKZ9yF BGYQ== X-Gm-Message-State: AOAM533jW1RtLqzAW8FBQSX6qffK7P7kciZ15VRQQMFQWdFBWwEYP6hw RFFV/yMVesT6k49R1T8VlQo0HROF6xz7ihQP X-Google-Smtp-Source: ABdhPJzx9QXJ2FNduXLIO3eucXJXSddratxrtG+GboFKt493dIEOaNkDPKFaL7o5yk74IsytWpegew== X-Received: by 2002:a05:622a:1351:: with SMTP id w17mr1961454qtk.447.1644915754311; Tue, 15 Feb 2022 01:02:34 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:33 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 2/6] RISC-V: Minimal parser for "riscv, isa" strings Date: Tue, 15 Feb 2022 01:02:07 -0800 Message-Id: <20220215090211.911366-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra [Fixed workaround for QEMU] Signed-off-by: Tsukasa OI Tested-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 66 ++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dd3d57eb4eea..9d5448542226 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; + int i, j; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -92,23 +93,66 @@ void __init riscv_fill_hwcap(void) continue; } =20 - i =3D 0; - isa_len =3D strlen(isa); #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) - i +=3D 4; + isa +=3D 4; #elif IS_ENABLED(CONFIG_64BIT) if (!strncmp(isa, "rv64", 4)) - i +=3D 4; + isa +=3D 4; #endif - for (; i < isa_len; ++i) { - this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + for (; *isa; ++isa) { + const char *ext =3D isa++; + const char *ext_end =3D isa; + bool ext_long =3D false, ext_err =3D false; + + switch (*ext) { + case 's': + case 'x': + case 'z': + /** + * Workaround for invalid single-letter 's' (QEMU). + * It works until multi-letter extension starting + * with "Su" appears. + */ + if (*ext =3D=3D 's' && ext[-1] !=3D '_' && ext[1] =3D=3D 'u') + break; + ext_long =3D true; + /* Multi-letter extension must be delimited */ + for (; *isa && *isa !=3D '_'; ++isa) + if (!islower(*isa) && !isdigit(*isa)) + ext_err =3D true; + /* ... but must be ignored. */ + break; + default: + if (unlikely(!islower(*ext))) { + ext_err =3D true; + break; + } + /* Find next extension */ + if (!isdigit(*isa)) + break; + while (isdigit(*++isa)) + ; + if (*isa !=3D 'p') + break; + if (!isdigit(*++isa)) { + --isa; + break; + } + while (isdigit(*++isa)) + ; + break; + } + if (*isa !=3D '_') + --isa; /* - * TODO: X, Y and Z extension parsing for Host ISA - * bitmap will be added in-future. + * TODO: Full version-aware handling including + * multi-letter extensions will be added in-future. */ - if ('a' <=3D isa[i] && isa[i] < 'x') - this_isa |=3D (1UL << (isa[i] - 'a')); + if (ext_err || ext_long) + continue; + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); } =20 /* --=20 2.30.2 From nobody Mon Jun 29 06:31:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1D21C433F5 for ; Tue, 15 Feb 2022 09:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235572AbiBOJC4 (ORCPT ); Tue, 15 Feb 2022 04:02:56 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235544AbiBOJCq (ORCPT ); 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:35 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Date: Tue, 15 Feb 2022 01:02:08 -0800 Message-Id: <20220215090211.911366-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Signed-off-by: Tsukasa OI [Improved commit text and comments] Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 38 ++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 9d5448542226..cd9eb34f8d11 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -119,9 +119,28 @@ void __init riscv_fill_hwcap(void) ext_long =3D true; /* Multi-letter extension must be delimited */ for (; *isa && *isa !=3D '_'; ++isa) - if (!islower(*isa) && !isdigit(*isa)) + if (unlikely(!islower(*isa) + && !isdigit(*isa))) ext_err =3D true; - /* ... but must be ignored. */ + /* Parse backwards */ + ext_end =3D isa; + if (unlikely(ext_err)) + break; + if (!isdigit(ext_end[-1])) + break; + /* Skip the minor version */ + while (isdigit(*--ext_end)) + ; + if (ext_end[0] !=3D 'p' + || !isdigit(ext_end[-1])) { + /* Advance it to offset the pre-decrement */ + ++ext_end; + break; + } + /* Skip the major version */ + while (isdigit(*--ext_end)) + ; + ++ext_end; break; default: if (unlikely(!islower(*ext))) { @@ -131,6 +150,7 @@ void __init riscv_fill_hwcap(void) /* Find next extension */ if (!isdigit(*isa)) break; + /* Skip the minor version */ while (isdigit(*++isa)) ; if (*isa !=3D 'p') @@ -139,20 +159,20 @@ void __init riscv_fill_hwcap(void) --isa; break; } + /* Skip the major version */ while (isdigit(*++isa)) ; break; } if (*isa !=3D '_') --isa; - /* - * TODO: Full version-aware handling including - * multi-letter extensions will be added in-future. - */ - if (ext_err || ext_long) + + if (unlikely(ext_err)) continue; - this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + if (!ext_long) { + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); + } } =20 /* --=20 2.30.2 From nobody Mon Jun 29 06:31:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40EF2C433F5 for ; Tue, 15 Feb 2022 09:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235606AbiBOJDJ (ORCPT ); Tue, 15 Feb 2022 04:03:09 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235573AbiBOJC5 (ORCPT ); Tue, 15 Feb 2022 04:02:57 -0500 Received: from mail-qt1-x831.google.com (mail-qt1-x831.google.com [IPv6:2607:f8b0:4864:20::831]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F5701160D3 for ; Tue, 15 Feb 2022 01:02:39 -0800 (PST) Received: by mail-qt1-x831.google.com with SMTP id z15so146452qtx.13 for ; Tue, 15 Feb 2022 01:02:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tvH+QlgZ/sWTfV6i2aUa3kw0ko5FhadKBSyH+clOvO0=; b=zDOmDakQzSP/7sYVbqUvgTuqj3R9yqw9Io/yxg0eMVPUCokXz05l725Roqs13h03JD BW5lBqOCdY/gs2ZQZgoXuo59dK7DiiAmXU3sTp2opcf8b8eyCEQvJyCyFOCMk+ZRPuKk J5MAL1FANaw0dRduBoLdPyQR34ITQkk7JBUBnanfPZ3HLkS9s7itxzo6ZI6SQTd3f4H1 yfEha9FrysXE0pWov5Qav7AJFN+0wNW0v66l3I74aIq+aFJ/rFL016DdnN1vN0dGtKWk urU5TJzGKLu7VRgb9zliqAEdmSTu2CUiT4Q+RkpF2YamgfgavQBU9E6NYyvCA25mN/D7 2HyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tvH+QlgZ/sWTfV6i2aUa3kw0ko5FhadKBSyH+clOvO0=; b=iEGtbJYONjHMvAuwpWiwAOArfFwcRBTpVfGvEyeDUZ0J1MhH46BEmEycDKKTe5fqVO JC1KcKEOFAO4NYQ2aEbMI32grvcDodqqXt2CjUPVXky8uevzSopLTdbgYFcKnrRyJtou bLSbqj9+UEIg8rPYeHErJPNppxtokxie67nJ3unRdEKkw44D01eg4b4PeCyvWCJIhH9h AUXF72vF/vX+ZNG7sKeYenVFXOdOVEDci5YTSmhtdq/NmOy4c+6fOhc8i5Qs+VsBdFVD JGQEpYqzDwSCJcqwiVYwgnARTOPyTlptSR2hljO49Mn0w2rpDtaZTyMp5F4EttRLRLMv 7swQ== X-Gm-Message-State: AOAM532b3su17Xu+chHcAQMy1qiJ8KSLDnOZ3RerkXCYf5z1GNchGCec 8X5Yz3nNIc2uZHYYvFrivbTjm9iBaV2ZSC5N X-Google-Smtp-Source: ABdhPJxlQfhS9S4weNHZVTY2A2fhMEBUPvoDEPwMIijVKZ9lCBMABQvdT0Ef3nN/KBssjp9v9AHT8w== X-Received: by 2002:ac8:41cf:: with SMTP id o15mr1951017qtm.254.1644915758374; Tue, 15 Feb 2022 01:02:38 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:37 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 4/6] RISC-V: Implement multi-letter ISA extension probing framework Date: Tue, 15 Feb 2022 01:02:09 -0800 Message-Id: <20220215090211.911366-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 27 ++++++++++++++++++++++++--- 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..170bd80da520 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') =20 +/* + * Increse this to higher value as kernel support more ISA extensions. + */ #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +/* The base ID for multi-letter ISA extensions */ +#define RISCV_ISA_EXT_BASE 26 + +/* + * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter + * extensions while all the multi-letter extensions should define the next + * available logical extension id. + */ +enum riscv_isa_ext_id { + RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, +}; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index cd9eb34f8d11..af9a57ad3d4e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) =20 for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; - unsigned long this_isa =3D 0; + uint64_t this_isa =3D 0; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -167,12 +167,22 @@ void __init riscv_fill_hwcap(void) if (*isa !=3D '_') --isa; =20 +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + this_isa |=3D (1UL << bit); \ + pr_info("Found ISA extension %s", name);\ + } \ + } while (false) \ + if (unlikely(ext_err)) continue; if (!ext_long) { this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; this_isa |=3D (1UL << (*ext - 'a')); } +#undef SET_ISA_EXT_MAP } =20 /* @@ -185,10 +195,21 @@ void __init riscv_fill_hwcap(void) else elf_hwcap =3D this_hwcap; =20 - if (riscv_isa[0]) + if (riscv_isa[0]) { +#if IS_ENABLED(CONFIG_32BIT) + riscv_isa[0] &=3D this_isa & 0xFFFFFFFF; + riscv_isa[1] &=3D this_isa >> 32; +#else riscv_isa[0] &=3D this_isa; - else +#endif + } else { +#if IS_ENABLED(CONFIG_32BIT) + riscv_isa[0] =3D this_isa & 0xFFFFFFFF; + riscv_isa[1] =3D this_isa >> 32; +#else riscv_isa[0] =3D this_isa; +#endif + } } =20 /* We don't support systems with F but without D, so mask those out --=20 2.30.2 From nobody Mon Jun 29 06:31:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BB91C433FE for ; Tue, 15 Feb 2022 09:03:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235582AbiBOJDN (ORCPT ); Tue, 15 Feb 2022 04:03:13 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235547AbiBOJDC (ORCPT ); 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:39 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Tue, 15 Feb 2022 01:02:10 -0800 Message-Id: <20220215090211.911366-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index af9a57ad3d4e..0c818035ec92 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; uint64_t this_isa =3D 0; + const char *temp; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } =20 + temp =3D isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa +=3D 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp =3D=3D isa) + continue; for (; *isa; ++isa) { const char *ext =3D isa++; const char *ext_end =3D isa; --=20 2.30.2 From nobody Mon Jun 29 06:31:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 531E6C433F5 for ; Tue, 15 Feb 2022 09:03:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235631AbiBOJDU (ORCPT ); Tue, 15 Feb 2022 04:03:20 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235583AbiBOJDD (ORCPT ); Tue, 15 Feb 2022 04:03:03 -0500 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BA1B11628F for ; Tue, 15 Feb 2022 01:02:43 -0800 (PST) Received: by mail-qk1-x72c.google.com with SMTP id b35so16720509qkp.6 for ; Tue, 15 Feb 2022 01:02:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=saY5DtvepsvwegCELkFkB7RgpB9RohGc6lIP30RliiM=; b=RpittIM+xed10v1kmPiEatjI4Ljy47ofyiUgCuxFOn8ZZziqPDhh/myQGQPAINUO3i 7GEeXm9xSQ4K+hh08Dn3UTPYEfduE5BOgAfVvPVvq+LbXefkk2PtGugKr3R7Bq5Shg3L l65RE8JRn7wKBMv4IP8lxJxchuM8mKVTB0BIsFhG7ycILi8fop0+wYCkNthc2VgYNRgw tQn1pLTVVvHwjetbNQj6m6DIUM9bOp7S0eWWgWptMrKDZfDusbJBTYSZmYdxChHCA7Mz o4HeBU/BOenOIGN3q92ispv9rjskiw1SJW2/aKKC901k9rXRUKbUeyIZacy31AZs+5s7 Uc9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=saY5DtvepsvwegCELkFkB7RgpB9RohGc6lIP30RliiM=; b=10q+Ih5514BnDg0di19ly7ZmummPbghv772Z/whKrdVYEgYV4n974Yn3w3RFZL8/7A yN6AgWIeTRXk48tYFd2d9Vs+9wT9rcTrpP15vvAo78uZI1uRbtQe73bpxZYf3Jg/wJHy ep/c0iefc9agg+NFeNUygj+jS0EfWHwQGxJbMVieHew5Come5pMqfFLIwKm8QnRF3wR+ 3T4RQbC96WSJmDO4Y6HwF/FYRD1ywnu3wCxm1TqbPcTlMA3QEtcV0EuLTRUvG6AMc8oE GatnQ9Y4p0ek52OozfOGsrsVokXDErkOwyExe8lw0ObdKZSIe8yr9w/s0gjGPHf1dCUH cmtQ== X-Gm-Message-State: AOAM530FTWA1OjphXhHPAddtfRtTa8OntPHPjGkZP21f5eAeeUo7z2ld 7bEFbrPhI44uuQfp8TNWxOMlU9zO6Aegh1SJ X-Google-Smtp-Source: ABdhPJzWrAWIlcNBqPobt6iH7sIMmiipfJtGTQVs0pJXyjgYHpXU1Q6z4v1B5V/bclnDc6aB03Qyrw== X-Received: by 2002:a05:620a:2687:: with SMTP id c7mr1434792qkp.497.1644915762087; Tue, 15 Feb 2022 01:02:42 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:41 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Tue, 15 Feb 2022 01:02:11 -0800 Message-Id: <20220215090211.911366-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Parse only the enabled ISA extension and print them in a separate row. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 7 ++++++ arch/riscv/kernel/cpu.c | 44 ++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, }; =20 +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..ced7e5be8641 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -63,12 +64,50 @@ int riscv_of_parent_hartid(struct device_node *node) } =20 #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop =3D #UPROP, \ + .isa_ext_id =3D EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] =3D { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i =3D 0, arr_sz; + + arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <=3D 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i =3D 0; i <=3D arr_sz; i++) { + edata =3D &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} =20 static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + char *ext_start; + int isa_len =3D strlen(isa); + int base_isa_len =3D isa_len; + + ext_start =3D strnchr(isa, isa_len, '_'); + if (ext_start) + base_isa_len =3D isa_len - strlen(ext_start); + + /* Print only the base ISA as it is */ seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + seq_write(f, isa, base_isa_len); seq_puts(f, "\n"); } =20 @@ -115,6 +154,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) --=20 2.30.2