From nobody Sun Sep 22 09:19:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F620C433FE for ; Tue, 15 Feb 2022 08:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235079AbiBOICU (ORCPT ); Tue, 15 Feb 2022 03:02:20 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:53902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235033AbiBOICJ (ORCPT ); Tue, 15 Feb 2022 03:02:09 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76BBA1EED3; Tue, 15 Feb 2022 00:01:59 -0800 (PST) X-UUID: f040adba2e9343cc8528165acfa3bb8f-20220215 X-UUID: f040adba2e9343cc8528165acfa3bb8f-20220215 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1090011818; Tue, 15 Feb 2022 16:01:53 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 15 Feb 2022 16:01:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Feb 2022 16:01:52 +0800 From: Rex-BC Chen To: , , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [v2,6/6] drm/mediatek: add display support for MT8186 Date: Tue, 15 Feb 2022 15:59:53 +0800 Message-ID: <20220215075953.3310-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220215075953.3310-1-rex-bc.chen@mediatek.com> References: <20220215075953.3310-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yongqiang Niu - Add driver data for MT8186 in mtk_drm_drv.c. - Add mtk-disp-ovl and mt-disp-ovl-2l support for MT8186. Signed-off-by: Yongqiang Niu Signed-off-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 +++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 2146299e5f52..5fa56c7b9f5f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -456,6 +456,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dr= iver_data =3D { .fmt_rgb565_is_0 =3D true, }; =20 +static const struct mtk_disp_ovl_data mt8186_ovl_driver_data =3D { + .addr =3D DISP_REG_OVL_ADDR_MT8173, + .gmc_bits =3D 10, + .layer_nr =3D 4, + .fmt_rgb565_is_0 =3D true, + .smi_id_en =3D true, +}; + +static const struct mtk_disp_ovl_data mt8186_ovl_2l_driver_data =3D { + .addr =3D DISP_REG_OVL_ADDR_MT8173, + .gmc_bits =3D 10, + .layer_nr =3D 2, + .fmt_rgb565_is_0 =3D true, + .smi_id_en =3D true, +}; + static const struct mtk_disp_ovl_data mt8192_ovl_driver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, @@ -479,8 +495,12 @@ static const struct of_device_id mtk_disp_ovl_driver_d= t_match[] =3D { .data =3D &mt8173_ovl_driver_data}, { .compatible =3D "mediatek,mt8183-disp-ovl", .data =3D &mt8183_ovl_driver_data}, + { .compatible =3D "mediatek,mt8186-disp-ovl", + .data =3D &mt8186_ovl_driver_data}, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D &mt8183_ovl_2l_driver_data}, + { .compatible =3D "mediatek,mt8186-disp-ovl-2l", + .data =3D &mt8186_ovl_2l_driver_data}, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D &mt8192_ovl_driver_data}, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 6efb423ccc92..754b1be25d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -158,6 +158,24 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[]= =3D { DDP_COMPONENT_DPI0, }; =20 +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] =3D { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] =3D { + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] =3D { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, @@ -221,6 +239,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys= _driver_data =3D { .ext_len =3D ARRAY_SIZE(mt8183_mtk_ddp_ext), }; =20 +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =3D { + .main_path =3D mt8186_mtk_ddp_main, + .main_len =3D ARRAY_SIZE(mt8186_mtk_ddp_main), + .ext_path =3D mt8186_mtk_ddp_ext, + .ext_len =3D ARRAY_SIZE(mt8186_mtk_ddp_ext), +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { .main_path =3D mt8192_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8192_mtk_ddp_main), @@ -463,6 +488,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8183-disp-mutex", .data =3D (void *)MTK_DISP_MUTEX }, + { .compatible =3D "mediatek,mt8186-disp-mutex", + .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8192-disp-mutex", .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8173-disp-od", @@ -475,14 +502,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[= ] =3D { .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, + { .compatible =3D "mediatek,mt8186-disp-ovl", + .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D (void *)MTK_DISP_OVL_2L }, + { .compatible =3D "mediatek,mt8186-disp-ovl-2l", + .data =3D (void *)MTK_DISP_OVL_2L }, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", .data =3D (void *)MTK_DISP_OVL_2L }, { .compatible =3D "mediatek,mt8192-disp-postmask", .data =3D (void *)MTK_DISP_POSTMASK }, + { .compatible =3D "mediatek,mt8186-disp-postmask", + .data =3D (void *)MTK_DISP_POSTMASK}, { .compatible =3D "mediatek,mt2701-disp-pwm", .data =3D (void *)MTK_DISP_BLS }, { .compatible =3D "mediatek,mt8167-disp-pwm", @@ -511,12 +544,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[= ] =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8186-dpi", + .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8183-dsi", .data =3D (void *)MTK_DSI }, + { .compatible =3D "mediatek,mt8186-dsi", + .data =3D (void *)MTK_DSI }, { } }; =20 @@ -533,6 +570,8 @@ static const struct of_device_id mtk_drm_of_ids[] =3D { .data =3D &mt8173_mmsys_driver_data}, { .compatible =3D "mediatek,mt8183-mmsys", .data =3D &mt8183_mmsys_driver_data}, + { .compatible =3D "mediatek,mt8186-mmsys", + .data =3D &mt8186_mmsys_driver_data}, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver_data}, { } --=20 2.18.0