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[193.12.47.89]) by smtp.gmail.com with ESMTPSA id s7sm8676472wrw.71.2022.02.12.16.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Feb 2022 16:38:21 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Russell King , =?UTF-8?q?Marek=20Beh=C3=BAn?= , "Russell King (Oracle)" , linux-kernel@vger.kernel.org Subject: [PATCH net-next] net: dsa: mv88e6xxx: Fix validation of built-in PHYs on 6095/6097 Date: Sun, 13 Feb 2022 01:37:01 +0100 Message-Id: <20220213003702.2440875-1-tobias@waldekranz.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Organization: Westermo Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These chips have 8 built-in FE PHYs and 3 SERDES interfaces that can run at 1G. With the blamed commit, the built-in PHYs could no longer be connected to, using an MII PHY interface mode. Create a separate .phylink_get_caps callback for these chips, which takes the FE/GE split into consideration. Fixes: 2ee84cfefb1e ("net: dsa: mv88e6xxx: convert to phylink_generic_valid= ate()") Signed-off-by: Tobias Waldekranz --- drivers/net/dsa/mv88e6xxx/chip.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 85527fe4fcc8..622b3b4ed513 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -580,6 +580,27 @@ static const u8 mv88e6185_phy_interface_modes[] =3D { [MV88E6185_PORT_STS_CMODE_PHY] =3D PHY_INTERFACE_MODE_SGMII, }; =20 +static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int po= rt, + struct phylink_config *config) +{ + u8 cmode =3D chip->ports[port].cmode; + + config->mac_capabilities =3D MAC_SYM_PAUSE | MAC_10 | MAC_100; + + if (mv88e6xxx_phy_is_internal(chip->ds, port)) { + if (cmode =3D=3D MV88E6185_PORT_STS_CMODE_PHY) + __set_bit(PHY_INTERFACE_MODE_MII, + config->supported_interfaces); + } else { + if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && + mv88e6185_phy_interface_modes[cmode]) + __set_bit(mv88e6185_phy_interface_modes[cmode], + config->supported_interfaces); + + config->mac_capabilities |=3D MAC_1000FD; + } +} + static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int po= rt, struct phylink_config *config) { @@ -3803,7 +3824,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops =3D { .reset =3D mv88e6185_g1_reset, .vtu_getnext =3D mv88e6185_g1_vtu_getnext, .vtu_loadpurge =3D mv88e6185_g1_vtu_loadpurge, - .phylink_get_caps =3D mv88e6185_phylink_get_caps, + .phylink_get_caps =3D mv88e6095_phylink_get_caps, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, }; =20 @@ -3850,7 +3871,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops =3D { .rmu_disable =3D mv88e6085_g1_rmu_disable, .vtu_getnext =3D mv88e6352_g1_vtu_getnext, .vtu_loadpurge =3D mv88e6352_g1_vtu_loadpurge, - .phylink_get_caps =3D mv88e6185_phylink_get_caps, + .phylink_get_caps =3D mv88e6095_phylink_get_caps, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, }; =20 --=20 2.25.1