From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3085C433F5 for ; Fri, 11 Feb 2022 20:35:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353241AbiBKUft (ORCPT ); Fri, 11 Feb 2022 15:35:49 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353232AbiBKUfs (ORCPT ); Fri, 11 Feb 2022 15:35:48 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1230CE9; Fri, 11 Feb 2022 12:35:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=ZY+4UzN2WsDPgL2gVR7iKaKFAM0xvtPr/UDebgU3Vi4=; b=qip3yploNB1CieXBmeXBbwwToa GpgyZmY6iR6WTGVJcQVqX+sHEciBgdlIEhELZYoF4U+0YKUVvoG6C1DJJiWamB+STn/7GTbvq37UE aW+l8O5INjyybsgvU02pl1GwYLbhIBb4UzsLRka+IgDIBLfvL/Ruw0HUMYDAVy7KrgrE=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcdr-0005vF-CT; Fri, 11 Feb 2022 15:35:44 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:07 -0500 Message-Id: <20220211203520.3902374-2-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 01/14] rtc: pcf2127: add variant-specific configuration structure X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Create variant-specific configuration structures to simplify the implementation of new variants into this driver. It will also avoid to have too many tests for a specific variant, or a list of variants for new devices, inside the code itself. Add configuration options for the support of the NVMEM, bit CD0 in register WD_CTL as well as the maximum number of registers for each variant, instead of hardcoding the variant (PCF2127) inside the i2c_device_id and spi_device_id structures. Also specify a different maximum number of registers (max_register) for the PCF2129. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 96 +++++++++++++++++++++++++++++++-------- 1 file changed, 78 insertions(+), 18 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index eae9ecbc7fb5..216a1ddfacda 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include =20 @@ -101,10 +102,17 @@ PCF2127_BIT_CTRL2_WDTF | \ PCF2127_BIT_CTRL2_TSF2) =20 +struct pcf21xx_config { + int max_register; + unsigned int has_nvmem:1; + unsigned int has_bit_wd_ctl_cd0:1; +}; + struct pcf2127 { struct rtc_device *rtc; struct watchdog_device wdd; struct regmap *regmap; + const struct pcf21xx_config *cfg; time64_t ts; bool ts_valid; bool irq_enabled; @@ -631,8 +639,27 @@ static const struct attribute_group pcf2127_attr_group= =3D { .attrs =3D pcf2127_attrs, }; =20 +enum pcf21xx_type { + PCF2127, + PCF2129, + PCF21XX_LAST_ID +}; + +static struct pcf21xx_config pcf21xx_cfg[] =3D { + [PCF2127] =3D { + .max_register =3D 0x1d, + .has_nvmem =3D 1, + .has_bit_wd_ctl_cd0 =3D 1, + }, + [PCF2129] =3D { + .max_register =3D 0x19, + .has_nvmem =3D 0, + .has_bit_wd_ctl_cd0 =3D 0, + }, +}; + static int pcf2127_probe(struct device *dev, struct regmap *regmap, - int alarm_irq, const char *name, bool is_pcf2127) + int alarm_irq, const char *name, const struct pcf21xx_config *config) { struct pcf2127 *pcf2127; int ret =3D 0; @@ -645,6 +672,7 @@ static int pcf2127_probe(struct device *dev, struct reg= map *regmap, return -ENOMEM; =20 pcf2127->regmap =3D regmap; + pcf2127->cfg =3D config; =20 dev_set_drvdata(dev, pcf2127); =20 @@ -687,7 +715,7 @@ static int pcf2127_probe(struct device *dev, struct reg= map *regmap, set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); } =20 - if (is_pcf2127) { + if (pcf2127->cfg->has_nvmem) { struct nvmem_config nvmem_cfg =3D { .priv =3D pcf2127, .reg_read =3D pcf2127_nvmem_read, @@ -733,7 +761,7 @@ static int pcf2127_probe(struct device *dev, struct reg= map *regmap, PCF2127_BIT_WD_CTL_TF1 | PCF2127_BIT_WD_CTL_TF0, PCF2127_BIT_WD_CTL_CD1 | - (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) | + (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | PCF2127_BIT_WD_CTL_TF1); if (ret) { dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); @@ -798,9 +826,9 @@ static int pcf2127_probe(struct device *dev, struct reg= map *regmap, =20 #ifdef CONFIG_OF static const struct of_device_id pcf2127_of_match[] =3D { - { .compatible =3D "nxp,pcf2127" }, - { .compatible =3D "nxp,pcf2129" }, - { .compatible =3D "nxp,pca2129" }, + { .compatible =3D "nxp,pcf2127", .data =3D &pcf21xx_cfg[PCF2127] }, + { .compatible =3D "nxp,pcf2129", .data =3D &pcf21xx_cfg[PCF2129] }, + { .compatible =3D "nxp,pca2129", .data =3D &pcf21xx_cfg[PCF2129] }, {} }; MODULE_DEVICE_TABLE(of, pcf2127_of_match); @@ -884,19 +912,36 @@ static const struct regmap_bus pcf2127_i2c_regmap =3D= { =20 static struct i2c_driver pcf2127_i2c_driver; =20 +static const struct i2c_device_id pcf2127_i2c_id[]; + static int pcf2127_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct regmap *regmap; - static const struct regmap_config config =3D { + static struct regmap_config config =3D { .reg_bits =3D 8, .val_bits =3D 8, - .max_register =3D 0x1d, }; + const struct pcf21xx_config *variant; =20 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) return -ENODEV; =20 + if (client->dev.of_node) { + variant =3D of_device_get_match_data(&client->dev); + if (!variant) + return -ENODEV; + } else { + enum pcf21xx_type type =3D + i2c_match_id(pcf2127_i2c_id, client)->driver_data; + + if (type >=3D PCF21XX_LAST_ID) + return -ENODEV; + variant =3D &pcf21xx_cfg[type]; + } + + config.max_register =3D variant->max_register, + regmap =3D devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, &client->dev, &config); if (IS_ERR(regmap)) { @@ -906,13 +951,13 @@ static int pcf2127_i2c_probe(struct i2c_client *clien= t, } =20 return pcf2127_probe(&client->dev, regmap, client->irq, - pcf2127_i2c_driver.driver.name, id->driver_data); + pcf2127_i2c_driver.driver.name, variant); } =20 static const struct i2c_device_id pcf2127_i2c_id[] =3D { - { "pcf2127", 1 }, - { "pcf2129", 0 }, - { "pca2129", 0 }, + { "pcf2127", PCF2127 }, + { "pcf2129", PCF2129 }, + { "pca2129", PCF2129 }, { } }; MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); @@ -952,17 +997,32 @@ static void pcf2127_i2c_unregister_driver(void) #if IS_ENABLED(CONFIG_SPI_MASTER) =20 static struct spi_driver pcf2127_spi_driver; +static const struct spi_device_id pcf2127_spi_id[]; =20 static int pcf2127_spi_probe(struct spi_device *spi) { - static const struct regmap_config config =3D { + static struct regmap_config config =3D { .reg_bits =3D 8, .val_bits =3D 8, .read_flag_mask =3D 0xa0, .write_flag_mask =3D 0x20, - .max_register =3D 0x1d, }; struct regmap *regmap; + const struct pcf21xx_config *variant; + + if (spi->dev.of_node) { + variant =3D of_device_get_match_data(&spi->dev); + if (!variant) + return -ENODEV; + } else { + enum pcf21xx_type type =3D spi_get_device_id(spi)->driver_data; + + if (type >=3D PCF21XX_LAST_ID) + return -ENODEV; + variant =3D &pcf21xx_cfg[type]; + } + + config.max_register =3D variant->max_register, =20 regmap =3D devm_regmap_init_spi(spi, &config); if (IS_ERR(regmap)) { @@ -973,13 +1033,13 @@ static int pcf2127_spi_probe(struct spi_device *spi) =20 return pcf2127_probe(&spi->dev, regmap, spi->irq, pcf2127_spi_driver.driver.name, - spi_get_device_id(spi)->driver_data); + variant); } =20 static const struct spi_device_id pcf2127_spi_id[] =3D { - { "pcf2127", 1 }, - { "pcf2129", 0 }, - { "pca2129", 0 }, + { "pcf2127", PCF2127 }, + { "pcf2129", PCF2129 }, + { "pca2129", PCF2129 }, { } }; MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E389C4332F for ; Fri, 11 Feb 2022 20:35:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353252AbiBKUfv (ORCPT ); Fri, 11 Feb 2022 15:35:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353240AbiBKUft (ORCPT ); Fri, 11 Feb 2022 15:35:49 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08B32CE7; Fri, 11 Feb 2022 12:35:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=kCATJ0uTBRIhYUXirxDytwSygCtVdynTmJpa02u30IE=; b=gGgzTOZa+auyuo6yUWGLs3zquE 7tja2aEaKMb2rdnzgj7Kd0azAw1mqDS7j+E0HkD1uGPve4nuvZDqJGgLgRkZJ2M2s64EVCWN+D9WF ayfmItCyquyPhFx73JYoWETtLeXVa0U8Knpt1Oej3bZw4JkL+IQXgCLrXNJqzdk+ayQM=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcds-0005vF-Qa; Fri, 11 Feb 2022 15:35:45 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:08 -0500 Message-Id: <20220211203520.3902374-3-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 02/14] rtc: pcf2127: adapt for time/date registers at any offset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve This will simplify the implementation of new variants into this driver. Some variants (PCF2131) have a 100th seconds register. This register is currently not supported in this driver. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 68 ++++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 216a1ddfacda..dcc0f22586fc 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -44,14 +44,17 @@ #define PCF2127_BIT_CTRL3_BF BIT(3) #define PCF2127_BIT_CTRL3_BTSE BIT(4) /* Time and date registers */ -#define PCF2127_REG_SC 0x03 +#define PCF2127_REG_TIME_DATE_BASE 0x03 +/* Time and date registers offsets (starting from base register) */ +#define PCF2127_OFFSET_TD_SC 0 +#define PCF2127_OFFSET_TD_MN 1 +#define PCF2127_OFFSET_TD_HR 2 +#define PCF2127_OFFSET_TD_DM 3 +#define PCF2127_OFFSET_TD_DW 4 +#define PCF2127_OFFSET_TD_MO 5 +#define PCF2127_OFFSET_TD_YR 6 +/* Time and date registers bits */ #define PCF2127_BIT_SC_OSF BIT(7) -#define PCF2127_REG_MN 0x04 -#define PCF2127_REG_HR 0x05 -#define PCF2127_REG_DM 0x06 -#define PCF2127_REG_DW 0x07 -#define PCF2127_REG_MO 0x08 -#define PCF2127_REG_YR 0x09 /* Alarm registers */ #define PCF2127_REG_ALARM_SC 0x0A #define PCF2127_REG_ALARM_MN 0x0B @@ -106,6 +109,7 @@ struct pcf21xx_config { int max_register; unsigned int has_nvmem:1; unsigned int has_bit_wd_ctl_cd0:1; + u8 regs_td_base; /* Time/data base registers. */ }; =20 struct pcf2127 { @@ -125,27 +129,31 @@ struct pcf2127 { static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) { struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev); - unsigned char buf[10]; + unsigned char buf[7]; + unsigned int ctrl3; int ret; =20 /* * Avoid reading CTRL2 register as it causes WD_VAL register * value to reset to 0 which means watchdog is stopped. */ - ret =3D regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3, - (buf + PCF2127_REG_CTRL3), - ARRAY_SIZE(buf) - PCF2127_REG_CTRL3); - if (ret) { - dev_err(dev, "%s: read error\n", __func__); + ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &ctrl3); + if (ret) return ret; - } =20 - if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF) + if (ctrl3 & PCF2127_BIT_CTRL3_BLF) dev_info(dev, "low voltage detected, check/replace RTC battery.\n"); =20 + ret =3D regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_td_base, + buf, sizeof(buf)); + if (ret) { + dev_err(dev, "%s: read error\n", __func__); + return ret; + } + /* Clock integrity is not guaranteed when OSF flag is set. */ - if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) { + if (buf[PCF2127_OFFSET_TD_SC] & PCF2127_BIT_SC_OSF) { /* * no need clear the flag here, * it will be cleared once the new date is saved @@ -158,18 +166,18 @@ static int pcf2127_rtc_read_time(struct device *dev, = struct rtc_time *tm) dev_dbg(dev, "%s: raw data is cr3=3D%02x, sec=3D%02x, min=3D%02x, hr=3D%02x, " "mday=3D%02x, wday=3D%02x, mon=3D%02x, year=3D%02x\n", - __func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC], - buf[PCF2127_REG_MN], buf[PCF2127_REG_HR], - buf[PCF2127_REG_DM], buf[PCF2127_REG_DW], - buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]); - - tm->tm_sec =3D bcd2bin(buf[PCF2127_REG_SC] & 0x7F); - tm->tm_min =3D bcd2bin(buf[PCF2127_REG_MN] & 0x7F); - tm->tm_hour =3D bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */ - tm->tm_mday =3D bcd2bin(buf[PCF2127_REG_DM] & 0x3F); - tm->tm_wday =3D buf[PCF2127_REG_DW] & 0x07; - tm->tm_mon =3D bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */ - tm->tm_year =3D bcd2bin(buf[PCF2127_REG_YR]); + __func__, ctrl3, buf[PCF2127_OFFSET_TD_SC], + buf[PCF2127_OFFSET_TD_MN], buf[PCF2127_OFFSET_TD_HR], + buf[PCF2127_OFFSET_TD_DM], buf[PCF2127_OFFSET_TD_DW], + buf[PCF2127_OFFSET_TD_MO], buf[PCF2127_OFFSET_TD_YR]); + + tm->tm_sec =3D bcd2bin(buf[PCF2127_OFFSET_TD_SC] & 0x7F); + tm->tm_min =3D bcd2bin(buf[PCF2127_OFFSET_TD_MN] & 0x7F); + tm->tm_hour =3D bcd2bin(buf[PCF2127_OFFSET_TD_HR] & 0x3F); /* rtc hr 0-23= */ + tm->tm_mday =3D bcd2bin(buf[PCF2127_OFFSET_TD_DM] & 0x3F); + tm->tm_wday =3D buf[PCF2127_OFFSET_TD_DW] & 0x07; + tm->tm_mon =3D bcd2bin(buf[PCF2127_OFFSET_TD_MO] & 0x1F) - 1; /* rtc mn 1= -12 */ + tm->tm_year =3D bcd2bin(buf[PCF2127_OFFSET_TD_YR]); tm->tm_year +=3D 100; =20 dev_dbg(dev, "%s: tm is secs=3D%d, mins=3D%d, hours=3D%d, " @@ -207,7 +215,7 @@ static int pcf2127_rtc_set_time(struct device *dev, str= uct rtc_time *tm) buf[i++] =3D bin2bcd(tm->tm_year - 100); =20 /* write register's data */ - err =3D regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); + err =3D regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_td_base, bu= f, i); if (err) { dev_err(dev, "%s: err=3D%d", __func__, err); @@ -650,11 +658,13 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x1d, .has_nvmem =3D 1, .has_bit_wd_ctl_cd0 =3D 1, + .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, }, [PCF2129] =3D { .max_register =3D 0x19, .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, + .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, }, }; =20 --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB0B1C4332F for ; Fri, 11 Feb 2022 20:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353266AbiBKUfz (ORCPT ); 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Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcdu-0005vF-3o; Fri, 11 Feb 2022 15:35:46 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:09 -0500 Message-Id: <20220211203520.3902374-4-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 03/14] rtc: pcf2127: adapt for alarm registers at any offset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve This will simplify the implementation of new variants into this driver. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 42 ++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index dcc0f22586fc..d89bcb17e12a 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -56,11 +56,14 @@ /* Time and date registers bits */ #define PCF2127_BIT_SC_OSF BIT(7) /* Alarm registers */ -#define PCF2127_REG_ALARM_SC 0x0A -#define PCF2127_REG_ALARM_MN 0x0B -#define PCF2127_REG_ALARM_HR 0x0C -#define PCF2127_REG_ALARM_DM 0x0D -#define PCF2127_REG_ALARM_DW 0x0E +#define PCF2127_REG_ALARM_BASE 0x0A +/* Alarm registers offsets (starting from base register) */ +#define PCF2127_OFFSET_ALARM_SC 0 +#define PCF2127_OFFSET_ALARM_MN 1 +#define PCF2127_OFFSET_ALARM_HR 2 +#define PCF2127_OFFSET_ALARM_DM 3 +#define PCF2127_OFFSET_ALARM_DW 4 +/* Alarm bits */ #define PCF2127_BIT_ALARM_AE BIT(7) /* CLKOUT control register */ #define PCF2127_REG_CLKOUT 0x0f @@ -110,6 +113,7 @@ struct pcf21xx_config { unsigned int has_nvmem:1; unsigned int has_bit_wd_ctl_cd0:1; u8 regs_td_base; /* Time/data base registers. */ + u8 regs_alarm_base; /* Alarm function base registers. */ }; =20 struct pcf2127 { @@ -402,18 +406,18 @@ static int pcf2127_rtc_read_alarm(struct device *dev,= struct rtc_wkalrm *alrm) if (ret) return ret; =20 - ret =3D regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, - sizeof(buf)); + ret =3D regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, + buf, sizeof(buf)); if (ret) return ret; =20 alrm->enabled =3D ctrl2 & PCF2127_BIT_CTRL2_AIE; alrm->pending =3D ctrl2 & PCF2127_BIT_CTRL2_AF; =20 - alrm->time.tm_sec =3D bcd2bin(buf[0] & 0x7F); - alrm->time.tm_min =3D bcd2bin(buf[1] & 0x7F); - alrm->time.tm_hour =3D bcd2bin(buf[2] & 0x3F); - alrm->time.tm_mday =3D bcd2bin(buf[3] & 0x3F); + alrm->time.tm_sec =3D bcd2bin(buf[PCF2127_OFFSET_ALARM_SC] & 0x7F); + alrm->time.tm_min =3D bcd2bin(buf[PCF2127_OFFSET_ALARM_MN] & 0x7F); + alrm->time.tm_hour =3D bcd2bin(buf[PCF2127_OFFSET_ALARM_HR] & 0x3F); + alrm->time.tm_mday =3D bcd2bin(buf[PCF2127_OFFSET_ALARM_DM] & 0x3F); =20 return 0; } @@ -447,14 +451,14 @@ static int pcf2127_rtc_set_alarm(struct device *dev, = struct rtc_wkalrm *alrm) if (ret) return ret; =20 - buf[0] =3D bin2bcd(alrm->time.tm_sec); - buf[1] =3D bin2bcd(alrm->time.tm_min); - buf[2] =3D bin2bcd(alrm->time.tm_hour); - buf[3] =3D bin2bcd(alrm->time.tm_mday); - buf[4] =3D PCF2127_BIT_ALARM_AE; /* Do not match on week day */ + buf[PCF2127_OFFSET_ALARM_SC] =3D bin2bcd(alrm->time.tm_sec); + buf[PCF2127_OFFSET_ALARM_MN] =3D bin2bcd(alrm->time.tm_min); + buf[PCF2127_OFFSET_ALARM_HR] =3D bin2bcd(alrm->time.tm_hour); + buf[PCF2127_OFFSET_ALARM_DM] =3D bin2bcd(alrm->time.tm_mday); + buf[PCF2127_OFFSET_ALARM_DW] =3D PCF2127_BIT_ALARM_AE; /* Do not match on= week day */ =20 - ret =3D regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, - sizeof(buf)); + ret =3D regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, + buf, sizeof(buf)); if (ret) return ret; =20 @@ -659,12 +663,14 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .has_nvmem =3D 1, .has_bit_wd_ctl_cd0 =3D 1, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, + .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, }, [PCF2129] =3D { .max_register =3D 0x19, .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, + .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, }, }; =20 --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF57DC433EF for ; Fri, 11 Feb 2022 20:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353285AbiBKUf6 (ORCPT ); Fri, 11 Feb 2022 15:35:58 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353240AbiBKUfw (ORCPT ); Fri, 11 Feb 2022 15:35:52 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B03F9CEC; Fri, 11 Feb 2022 12:35:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=HmmltoINHI01K88EtWHY5eRcs24eb/8vx1n0+e8dIH4=; b=yguxQhLC8zEVTs12uYqNkzvyxX AQ0TLnHv6aQJQQuapvqnGk1/utl7KkC0H/1P5+NSrckHkN+ePRV8Sw+AoYe4QMWvDITGYnN/+FiEu WWcPTH9g7OOtlSqEU+VHVxLA5uZ1BR9D8WCcrCAop0dFu5HLywJj1EkhWvtdos6J4gwU=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcdv-0005vF-AV; Fri, 11 Feb 2022 15:35:47 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:10 -0500 Message-Id: <20220211203520.3902374-5-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 04/14] rtc: pcf2127: adapt for WD registers at any offset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve This will simplify the implementation of new variants into this driver. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index d89bcb17e12a..2c5cda04e21b 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -114,6 +114,8 @@ struct pcf21xx_config { unsigned int has_bit_wd_ctl_cd0:1; u8 regs_td_base; /* Time/data base registers. */ u8 regs_alarm_base; /* Alarm function base registers. */ + u8 reg_wd_ctl; /* Watchdog control register. */ + u8 reg_wd_val; /* Watchdog value register. */ }; =20 struct pcf2127 { @@ -297,7 +299,7 @@ static int pcf2127_wdt_ping(struct watchdog_device *wdd) { struct pcf2127 *pcf2127 =3D watchdog_get_drvdata(wdd); =20 - return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); + return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeo= ut); } =20 /* @@ -331,7 +333,7 @@ static int pcf2127_wdt_stop(struct watchdog_device *wdd) { struct pcf2127 *pcf2127 =3D watchdog_get_drvdata(wdd); =20 - return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, + return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, PCF2127_WD_VAL_STOP); } =20 @@ -380,7 +382,7 @@ static int pcf2127_watchdog_init(struct device *dev, st= ruct pcf2127 *pcf2127) watchdog_set_drvdata(&pcf2127->wdd, pcf2127); =20 /* Test if watchdog timer is started by bootloader */ - ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); + ret =3D regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeo= ut); if (ret) return ret; =20 @@ -664,6 +666,8 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .has_bit_wd_ctl_cd0 =3D 1, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, + .reg_wd_ctl =3D PCF2127_REG_WD_CTL, + .reg_wd_val =3D PCF2127_REG_WD_VAL, }, [PCF2129] =3D { .max_register =3D 0x19, @@ -671,6 +675,8 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .has_bit_wd_ctl_cd0 =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, + .reg_wd_ctl =3D PCF2127_REG_WD_CTL, + .reg_wd_val =3D PCF2127_REG_WD_VAL, }, }; =20 @@ -771,7 +777,7 @@ static int pcf2127_probe(struct device *dev, struct reg= map *regmap, * as T. Bits labeled as T must always be written with * logic 0. */ - ret =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, + ret =3D regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, PCF2127_BIT_WD_CTL_CD1 | PCF2127_BIT_WD_CTL_CD0 | PCF2127_BIT_WD_CTL_TF1 | --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB999C433F5 for ; Fri, 11 Feb 2022 20:35:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353270AbiBKUf5 (ORCPT ); Fri, 11 Feb 2022 15:35:57 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244770AbiBKUfw (ORCPT ); Fri, 11 Feb 2022 15:35:52 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C33DCEF; Fri, 11 Feb 2022 12:35:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=8CdyIHSXKPv3TDN98TzS/C5SoJwYhyk3U3q/EcXPZ/Q=; b=t/T8IqZmu3OgriJx2oM4MrnQ9u pv6O69qn19RdcXn7Qw36dlgh55ib3fxehz5YcEhek+A/hnNnX61eNHA3HWc/r8gGRRnan3v6Ct56L M81T+j/EwHZgyBipn9Tuz90V03vB24wYRhfl5qqQEGKehRDloeCA6jVAlcFF7j8fF7fo=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcdw-0005vF-C0; Fri, 11 Feb 2022 15:35:48 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:11 -0500 Message-Id: <20220211203520.3902374-6-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 05/14] rtc: pcf2127: adapt for CLKOUT register at any offset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve This will simplify the implementation of new variants into this driver. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 2c5cda04e21b..c73574b59c9d 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -116,6 +116,7 @@ struct pcf21xx_config { u8 regs_alarm_base; /* Alarm function base registers. */ u8 reg_wd_ctl; /* Watchdog control register. */ u8 reg_wd_val; /* Watchdog value register. */ + u8 reg_clkout; /* Clkout register. */ }; =20 struct pcf2127 { @@ -668,6 +669,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2127_REG_WD_CTL, .reg_wd_val =3D PCF2127_REG_WD_VAL, + .reg_clkout =3D PCF2127_REG_CLKOUT, }, [PCF2129] =3D { .max_register =3D 0x19, @@ -677,6 +679,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2127_REG_WD_CTL, .reg_wd_val =3D PCF2127_REG_WD_VAL, + .reg_clkout =3D PCF2127_REG_CLKOUT, }, }; =20 @@ -755,12 +758,12 @@ static int pcf2127_probe(struct device *dev, struct r= egmap *regmap, regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, PCF2127_BIT_CTRL1_POR_OVRD); =20 - ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); + ret =3D regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); if (ret < 0) return ret; =20 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { - ret =3D regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, + ret =3D regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, PCF2127_BIT_CLKOUT_OTPR); if (ret < 0) return ret; --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 385EFC433F5 for ; Fri, 11 Feb 2022 20:36:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353302AbiBKUgG (ORCPT ); Fri, 11 Feb 2022 15:36:06 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353273AbiBKUf4 (ORCPT ); Fri, 11 Feb 2022 15:35:56 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79EC5CE9; Fri, 11 Feb 2022 12:35:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=kugmdnaWhoSDUqD+tKHhpU+TKIhb0MzNOBAr7JhGVDw=; b=ZNNrlrbzjO0t3hX3v5UnMg4I9W gU9P6w4yGtLJ2dGEPr/Oyl4I2EevmYfCzwTxMX1vGoSxZyAegHblcmInLTyXRdOCOKAbZk6BQa6Af eiwvv5IxZj1HZq26fwCOS0qQNeNquSr5UfnIpd3E5v8OpfUh65Fpr7MlpedXSkJR+coU=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcdx-0005vF-Fs; Fri, 11 Feb 2022 15:35:51 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:12 -0500 Message-Id: <20220211203520.3902374-7-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 06/14] rtc: pcf2127: add support for multiple TS functions X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve This will simplify the implementation of new variants into this driver. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 303 +++++++++++++++++++++++++++----------- 1 file changed, 215 insertions(+), 88 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index c73574b59c9d..841b928e1415 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -75,16 +75,19 @@ #define PCF2127_BIT_WD_CTL_CD0 BIT(6) #define PCF2127_BIT_WD_CTL_CD1 BIT(7) #define PCF2127_REG_WD_VAL 0x11 -/* Tamper timestamp registers */ -#define PCF2127_REG_TS_CTRL 0x12 +/* Tamper timestamp1 registers */ +#define PCF2127_REG_TS1_BASE 0x12 +/* Tamper timestamp registers common offsets (starting from base register)= */ +#define PCF2127_OFFSET_TS_CTL 0 +#define PCF2127_OFFSET_TS_SC 1 +#define PCF2127_OFFSET_TS_MN 2 +#define PCF2127_OFFSET_TS_HR 3 +#define PCF2127_OFFSET_TS_DM 4 +#define PCF2127_OFFSET_TS_MO 5 +#define PCF2127_OFFSET_TS_YR 6 +/* Tamper timestamp registers common bits */ #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) #define PCF2127_BIT_TS_CTRL_TSM BIT(7) -#define PCF2127_REG_TS_SC 0x13 -#define PCF2127_REG_TS_MN 0x14 -#define PCF2127_REG_TS_HR 0x15 -#define PCF2127_REG_TS_DM 0x16 -#define PCF2127_REG_TS_MO 0x17 -#define PCF2127_REG_TS_YR 0x18 /* * RAM registers * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is @@ -108,6 +111,20 @@ PCF2127_BIT_CTRL2_WDTF | \ PCF2127_BIT_CTRL2_TSF2) =20 +struct pcf21xx_ts_config { + u8 regs_base; /* Base register to read timestamp values. */ + /* TS input pin driven to GND detection (supported by all variants): */ + u8 low_reg; /* Interrupt control register. */ + u8 low_bit; /* Interrupt flag in low_reg control register. */ + /* TS input pin driven to intermediate level between GND and supply + * detection (optional feature depending on variant): + */ + u8 inter_reg; /* Interrupt control register. */ + u8 inter_bit; /* Interrupt flag in inter_reg control register. */ + u8 ie_reg; /* Interrupt enable control register. */ + u8 ie_bit; /* Interrupt enable bit. */ +}; + struct pcf21xx_config { int max_register; unsigned int has_nvmem:1; @@ -117,6 +134,9 @@ struct pcf21xx_config { u8 reg_wd_ctl; /* Watchdog control register. */ u8 reg_wd_val; /* Watchdog value register. */ u8 reg_clkout; /* Clkout register. */ + unsigned int ts_count; + struct pcf21xx_ts_config ts[4]; + struct attribute_group attribute_group; }; =20 struct pcf2127 { @@ -124,9 +144,9 @@ struct pcf2127 { struct watchdog_device wdd; struct regmap *regmap; const struct pcf21xx_config *cfg; - time64_t ts; - bool ts_valid; bool irq_enabled; + time64_t ts[4]; /* Timestamp values. */ + bool ts_valid[4]; /* Timestamp valid indication. */ }; =20 /* @@ -469,38 +489,39 @@ static int pcf2127_rtc_set_alarm(struct device *dev, = struct rtc_wkalrm *alrm) } =20 /* - * This function reads ctrl2 register, caller is responsible for calling - * pcf2127_wdt_active_ping() + * This function reads one timestamp function data, caller is responsible = for + * calling pcf2127_wdt_active_ping() */ -static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) +static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, + int ts_id) { struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev); struct rtc_time tm; int ret; - unsigned char data[25]; + unsigned char data[7]; /* To store result of reading 7 consecutive + * timestamp registers. + */ =20 - ret =3D regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data, - sizeof(data)); + ret =3D regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].regs_ba= se, + data, sizeof(data)); if (ret) { - dev_err(dev, "%s: read error ret=3D%d\n", __func__, ret); + dev_err(dev, "%s: bulk read error ret=3D%d\n", __func__, ret); return ret; } =20 dev_dbg(dev, - "%s: raw data is cr1=3D%02x, cr2=3D%02x, cr3=3D%02x, ts_sc=3D%02x, ts_mn= =3D%02x, ts_hr=3D%02x, ts_dm=3D%02x, ts_mo=3D%02x, ts_yr=3D%02x\n", - __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2], - data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC], - data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR], - data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO], - data[PCF2127_REG_TS_YR]); - - tm.tm_sec =3D bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F); - tm.tm_min =3D bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F); - tm.tm_hour =3D bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F); - tm.tm_mday =3D bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F); + "%s: raw data is ts_sc=3D%02x, ts_mn=3D%02x, ts_hr=3D%02x, ts_dm=3D%02x,= ts_mo=3D%02x, ts_yr=3D%02x\n", + __func__, data[PCF2127_OFFSET_TS_SC], data[PCF2127_OFFSET_TS_MN], + data[PCF2127_OFFSET_TS_HR], data[PCF2127_OFFSET_TS_DM], + data[PCF2127_OFFSET_TS_MO], data[PCF2127_OFFSET_TS_YR]); + + tm.tm_sec =3D bcd2bin(data[PCF2127_OFFSET_TS_SC] & 0x7F); + tm.tm_min =3D bcd2bin(data[PCF2127_OFFSET_TS_MN] & 0x7F); + tm.tm_hour =3D bcd2bin(data[PCF2127_OFFSET_TS_HR] & 0x3F); + tm.tm_mday =3D bcd2bin(data[PCF2127_OFFSET_TS_DM] & 0x3F); /* TS_MO register (month) value range: 1-12 */ - tm.tm_mon =3D bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1; - tm.tm_year =3D bcd2bin(data[PCF2127_REG_TS_YR]); + tm.tm_mon =3D bcd2bin(data[PCF2127_OFFSET_TS_MO] & 0x1F) - 1; + tm.tm_year =3D bcd2bin(data[PCF2127_OFFSET_TS_YR]); if (tm.tm_year < 70) tm.tm_year +=3D 100; /* assume we are in 1970...2069 */ =20 @@ -514,18 +535,21 @@ static int pcf2127_rtc_ts_read(struct device *dev, ti= me64_t *ts) return 0; }; =20 -static void pcf2127_rtc_ts_snapshot(struct device *dev) +static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) { struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev); int ret; =20 + if (ts_id >=3D pcf2127->cfg->ts_count) + return; + /* Let userspace read the first timestamp */ - if (pcf2127->ts_valid) + if (pcf2127->ts_valid[ts_id]) return; =20 - ret =3D pcf2127_rtc_ts_read(dev, &pcf2127->ts); + ret =3D pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); if (!ret) - pcf2127->ts_valid =3D true; + pcf2127->ts_valid[ts_id] =3D true; } =20 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) @@ -546,7 +570,7 @@ static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) return IRQ_NONE; =20 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) - pcf2127_rtc_ts_snapshot(dev); + pcf2127_rtc_ts_snapshot(dev, 0); =20 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, @@ -575,28 +599,40 @@ static const struct rtc_class_ops pcf2127_rtc_ops =3D= { =20 /* sysfs interface */ =20 -static ssize_t timestamp0_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) +static ssize_t timestamp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count, int ts_id) { struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev->parent); int ret; =20 + if (ts_id >=3D pcf2127->cfg->ts_count) + return 0; + if (pcf2127->irq_enabled) { - pcf2127->ts_valid =3D false; + pcf2127->ts_valid[ts_id] =3D false; } else { - ret =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, - PCF2127_BIT_CTRL1_TSF1, 0); + /* Always clear LOW interrupt bit. */ + ret =3D regmap_update_bits(pcf2127->regmap, + pcf2127->cfg->ts[ts_id].low_reg, + pcf2127->cfg->ts[ts_id].low_bit, + 0); + if (ret) { - dev_err(dev, "%s: update ctrl1 ret=3D%d\n", __func__, ret); + dev_err(dev, "%s: update TS low ret=3D%d\n", __func__, ret); return ret; } =20 - ret =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, - PCF2127_BIT_CTRL2_TSF2, 0); - if (ret) { - dev_err(dev, "%s: update ctrl2 ret=3D%d\n", __func__, ret); - return ret; + if (pcf2127->cfg->ts[ts_id].inter_bit) { + /* Clear INTERMEDIATE interrupt bit if supported. */ + ret =3D regmap_update_bits(pcf2127->regmap, + pcf2127->cfg->ts[ts_id].inter_reg, + pcf2127->cfg->ts[ts_id].inter_bit, + 0); + if (ret) { + dev_err(dev, "%s: update TS intermediate ret=3D%d\n", __func__, ret); + return ret; + } } =20 ret =3D pcf2127_wdt_active_ping(&pcf2127->wdd); @@ -605,34 +641,63 @@ static ssize_t timestamp0_store(struct device *dev, } =20 return count; +} + +static ssize_t timestamp0_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return timestamp_store(dev, attr, buf, count, 0); }; =20 -static ssize_t timestamp0_show(struct device *dev, - struct device_attribute *attr, char *buf) +static ssize_t timestamp_show(struct device *dev, + struct device_attribute *attr, char *buf, + int ts_id) { struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev->parent); - unsigned int ctrl1, ctrl2; int ret; time64_t ts; =20 + if (ts_id >=3D pcf2127->cfg->ts_count) + return 0; + if (pcf2127->irq_enabled) { - if (!pcf2127->ts_valid) + if (!pcf2127->ts_valid[ts_id]) return 0; - ts =3D pcf2127->ts; + ts =3D pcf2127->ts[ts_id]; } else { - ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); - if (ret) - return 0; + u8 valid_low =3D 0; + u8 valid_inter =3D 0; + unsigned int ctrl; =20 - ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); + /* Check if TS input pin is driven to GND, supported by all + * variants. + */ + ret =3D regmap_read(pcf2127->regmap, + pcf2127->cfg->ts[ts_id].low_reg, + &ctrl); if (ret) return 0; =20 - if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && - !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) + valid_low =3D ctrl & pcf2127->cfg->ts[ts_id].low_bit; + + if (pcf2127->cfg->ts[ts_id].inter_bit) { + /* Check if TS input pin is driven to intermediate level + * between GND and supply, if supported by variant. + */ + ret =3D regmap_read(pcf2127->regmap, + pcf2127->cfg->ts[ts_id].inter_reg, + &ctrl); + if (ret) + return 0; + + valid_inter =3D ctrl & pcf2127->cfg->ts[ts_id].inter_bit; + } + + if (!valid_low && !valid_inter) return 0; =20 - ret =3D pcf2127_rtc_ts_read(dev->parent, &ts); + ret =3D pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); if (ret) return 0; =20 @@ -641,6 +706,12 @@ static ssize_t timestamp0_show(struct device *dev, return ret; } return sprintf(buf, "%llu\n", (unsigned long long)ts); +} + +static ssize_t timestamp0_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return timestamp_show(dev, attr, buf, 0); }; =20 static DEVICE_ATTR_RW(timestamp0); @@ -650,10 +721,6 @@ static struct attribute *pcf2127_attrs[] =3D { NULL }; =20 -static const struct attribute_group pcf2127_attr_group =3D { - .attrs =3D pcf2127_attrs, -}; - enum pcf21xx_type { PCF2127, PCF2129, @@ -670,6 +737,19 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .reg_wd_ctl =3D PCF2127_REG_WD_CTL, .reg_wd_val =3D PCF2127_REG_WD_VAL, .reg_clkout =3D PCF2127_REG_CLKOUT, + .ts_count =3D 1, + .ts[0] =3D { + .regs_base =3D PCF2127_REG_TS1_BASE, + .low_reg =3D PCF2127_REG_CTRL1, + .low_bit =3D PCF2127_BIT_CTRL1_TSF1, + .inter_reg =3D PCF2127_REG_CTRL2, + .inter_bit =3D PCF2127_BIT_CTRL2_TSF2, + .ie_reg =3D PCF2127_REG_CTRL2, + .ie_bit =3D PCF2127_BIT_CTRL2_TSIE, + }, + .attribute_group =3D { + .attrs =3D pcf2127_attrs, + }, }, [PCF2129] =3D { .max_register =3D 0x19, @@ -680,15 +760,81 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .reg_wd_ctl =3D PCF2127_REG_WD_CTL, .reg_wd_val =3D PCF2127_REG_WD_VAL, .reg_clkout =3D PCF2127_REG_CLKOUT, + .ts_count =3D 1, + .ts[0] =3D { + .regs_base =3D PCF2127_REG_TS1_BASE, + .low_reg =3D PCF2127_REG_CTRL1, + .low_bit =3D PCF2127_BIT_CTRL1_TSF1, + .inter_reg =3D PCF2127_REG_CTRL2, + .inter_bit =3D PCF2127_BIT_CTRL2_TSF2, + .ie_reg =3D PCF2127_REG_CTRL2, + .ie_bit =3D PCF2127_BIT_CTRL2_TSIE, + }, + .attribute_group =3D { + .attrs =3D pcf2127_attrs, + }, }, }; =20 +/* + * Enable timestamp function and corresponding interrupt(s). + */ +static int pcf2127_enable_ts(struct device *dev, int ts_id) +{ + struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev); + int ret; + + if (ts_id >=3D pcf2127->cfg->ts_count) { + dev_err(dev, "%s: invalid tamper detection ID (%d)\n", + __func__, ts_id); + return -EINVAL; + } + + /* Enable timestamp function. */ + ret =3D regmap_update_bits(pcf2127->regmap, + pcf2127->cfg->ts[ts_id].regs_base, + PCF2127_BIT_TS_CTRL_TSOFF | + PCF2127_BIT_TS_CTRL_TSM, + PCF2127_BIT_TS_CTRL_TSM); + if (ret) { + dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", + __func__, ts_id); + return ret; + } + + /* TS input pin driven to GND detection is supported by all variants. + * Make sure that low_bit is defined. + */ + if (pcf2127->cfg->ts[ts_id].low_bit =3D=3D 0) { + dev_err(dev, "%s: tamper detection LOW configuration invalid\n", + __func__); + return ret; + } + + /* + * Enable interrupt generation when TSF timestamp flag is set. + * Interrupt signals are open-drain outputs and can be left floating if + * unused. + */ + ret =3D regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_re= g, + pcf2127->cfg->ts[ts_id].ie_bit, + pcf2127->cfg->ts[ts_id].ie_bit); + if (ret) { + dev_err(dev, "%s: tamper detection TSIE%d config failed\n", + __func__, ts_id); + return ret; + } + + return ret; +} + static int pcf2127_probe(struct device *dev, struct regmap *regmap, int alarm_irq, const char *name, const struct pcf21xx_config *config) { struct pcf2127 *pcf2127; int ret =3D 0; unsigned int val; + int i; =20 dev_dbg(dev, "%s\n", __func__); =20 @@ -812,34 +958,15 @@ static int pcf2127_probe(struct device *dev, struct r= egmap *regmap, } =20 /* - * Enable timestamp function and store timestamp of first trigger - * event until TSF1 and TSF2 interrupt flags are cleared. + * Enable timestamp functions 1 to 4. */ - ret =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, - PCF2127_BIT_TS_CTRL_TSOFF | - PCF2127_BIT_TS_CTRL_TSM, - PCF2127_BIT_TS_CTRL_TSM); - if (ret) { - dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", - __func__); - return ret; - } - - /* - * Enable interrupt generation when TSF1 or TSF2 timestamp flags - * are set. Interrupt signal is an open-drain output and can be - * left floating if unused. - */ - ret =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, - PCF2127_BIT_CTRL2_TSIE, - PCF2127_BIT_CTRL2_TSIE); - if (ret) { - dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", - __func__); - return ret; + for (i =3D 0; i < pcf2127->cfg->ts_count; i++) { + ret =3D pcf2127_enable_ts(dev, i); + if (ret) + return ret; } =20 - ret =3D rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); + ret =3D rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); if (ret) { dev_err(dev, "%s: tamper sysfs registering failed\n", __func__); --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7588EC4332F for ; Fri, 11 Feb 2022 20:36:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353307AbiBKUgI (ORCPT ); Fri, 11 Feb 2022 15:36:08 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353283AbiBKUf6 (ORCPT ); Fri, 11 Feb 2022 15:35:58 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EEF7CE7; Fri, 11 Feb 2022 12:35:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=LDgI3NKyR0PW8j6XTLsS22/qvHpHAXh0SRJ/GdUUxNk=; b=W9I+fBF1GWZ2ZuLLE/sOveYcfp 5Tj9FPm1HT14h8X7dhgaH6jPbmGIDxqgOtxPkKZ03SYhiTFaippz169sfzYg0TzPlVlKxFYWXTtZK Ixcvr2lbu9ko6Vhsril0qm+yWZOXoZXPy/7Vgv1ZG30aEs+aLdCL/HRa+HO5JaDKxInQ=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIcdz-0005vF-VM; Fri, 11 Feb 2022 15:35:53 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:13 -0500 Message-Id: <20220211203520.3902374-8-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 07/14] rtc: pcf2127: add support for PCF2131 RTC X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve This RTC is very similar in functionality to the PCF2127/29. Basically it: -supports two new control registers at offsets 4 and 5 -supports a new reset register (not implemented in this driver) -supports 4 tamper detection functions instead of 1 -has no nvmem (like the PCF2129) -has two output interrupt pins Because of that, most of the register addresses are very different, although they still follow the same layout. For example, the tamper registers have a different base address, but the offsets are all the same. Signed-off-by: Hugo Villeneuve --- drivers/rtc/Kconfig | 4 +- drivers/rtc/rtc-pcf2127.c | 234 ++++++++++++++++++++++++++++++++++---- 2 files changed, 215 insertions(+), 23 deletions(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index d85a3c31347c..9b083ca6b4c4 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -899,9 +899,9 @@ config RTC_DRV_PCF2127 select REGMAP_SPI if SPI_MASTER select WATCHDOG_CORE if WATCHDOG help - If you say yes here you get support for the NXP PCF2127/29 RTC + If you say yes here you get support for the NXP PCF2127/29/31 RTC chips with integrated quartz crystal for industrial applications. - Both chips also have watchdog timer and tamper switch detection + These chips also have watchdog timer and tamper switch detection features. =20 PCF2127 has an additional feature of 512 bytes battery backed diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 841b928e1415..a52af7465d69 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -1,16 +1,26 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * An I2C and SPI driver for the NXP PCF2127/29 RTC + * An I2C and SPI driver for the NXP PCF2127/29/31 RTC * Copyright 2013 Til-Technologies + * Copyright 2021 DimOnOff * * Author: Renaud Cerrato * * Watchdog and tamper functions * Author: Bruno Thomsen * + * PCF2131 support + * Author: Hugo Villeneuve + * * based on the other drivers in this same directory. * - * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf + * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf + * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf + */ + +/* + * The following features are not yet implemented for the PCF2131: + * - support for 1/100th seconds */ =20 #include @@ -43,8 +53,30 @@ #define PCF2127_BIT_CTRL3_BLF BIT(2) #define PCF2127_BIT_CTRL3_BF BIT(3) #define PCF2127_BIT_CTRL3_BTSE BIT(4) +/* Control register 4 */ +#define PCF2131_REG_CTRL4 0x03 +#define PCF2131_BIT_CTRL4_TSF4 BIT(4) +#define PCF2131_BIT_CTRL4_TSF3 BIT(5) +#define PCF2131_BIT_CTRL4_TSF2 BIT(6) +#define PCF2131_BIT_CTRL4_TSF1 BIT(7) +/* Control register 5 */ +#define PCF2131_REG_CTRL5 0x04 +#define PCF2131_BIT_CTRL5_TSIE4 BIT(4) +#define PCF2131_BIT_CTRL5_TSIE3 BIT(5) +#define PCF2131_BIT_CTRL5_TSIE2 BIT(6) +#define PCF2131_BIT_CTRL5_TSIE1 BIT(7) +/* Software reset register */ +#define PCF2131_REG_SR_RESET 0x05 +#define PCF2131_SR_RESET_READ_PATTERN 0b00100100 /* Fixed pattern. */ +#define PCF2131_SR_RESET_RESET_CMD 0x2C /* SR is bit 3. */ /* Time and date registers */ #define PCF2127_REG_TIME_DATE_BASE 0x03 +#define PCF2131_REG_TIME_DATE_BASE 0x07 /* Register 0x06 is 100th seconds, + * but we do not support it. By + * using offset 0x07, we can be + * compatible with existing + * time/date functions. + */ /* Time and date registers offsets (starting from base register) */ #define PCF2127_OFFSET_TD_SC 0 #define PCF2127_OFFSET_TD_MN 1 @@ -57,6 +89,7 @@ #define PCF2127_BIT_SC_OSF BIT(7) /* Alarm registers */ #define PCF2127_REG_ALARM_BASE 0x0A +#define PCF2131_REG_ALARM_BASE 0x0E /* Alarm registers offsets (starting from base register) */ #define PCF2127_OFFSET_ALARM_SC 0 #define PCF2127_OFFSET_ALARM_MN 1 @@ -67,16 +100,26 @@ #define PCF2127_BIT_ALARM_AE BIT(7) /* CLKOUT control register */ #define PCF2127_REG_CLKOUT 0x0f +#define PCF2131_REG_CLKOUT 0x13 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) /* Watchdog registers */ #define PCF2127_REG_WD_CTL 0x10 +#define PCF2131_REG_WD_CTL 0x35 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) #define PCF2127_BIT_WD_CTL_TF1 BIT(1) #define PCF2127_BIT_WD_CTL_CD0 BIT(6) #define PCF2127_BIT_WD_CTL_CD1 BIT(7) #define PCF2127_REG_WD_VAL 0x11 +#define PCF2131_REG_WD_VAL 0x36 /* Tamper timestamp1 registers */ #define PCF2127_REG_TS1_BASE 0x12 +#define PCF2131_REG_TS1_BASE 0x14 +/* Tamper timestamp2 registers */ +#define PCF2131_REG_TS2_BASE 0x1B +/* Tamper timestamp3 registers */ +#define PCF2131_REG_TS3_BASE 0x22 +/* Tamper timestamp4 registers */ +#define PCF2131_REG_TS4_BASE 0x29 /* Tamper timestamp registers common offsets (starting from base register)= */ #define PCF2127_OFFSET_TS_CTL 0 #define PCF2127_OFFSET_TS_SC 1 @@ -92,11 +135,22 @@ * RAM registers * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is * battery backed and can survive a power outage. - * PCF2129 doesn't have this feature. + * PCF2129/31 doesn't have this feature. */ #define PCF2127_REG_RAM_ADDR_MSB 0x1A #define PCF2127_REG_RAM_WRT_CMD 0x1C #define PCF2127_REG_RAM_RD_CMD 0x1D +/* Interrupt mask registers */ +#define PCF2131_REG_INT_A_MASK1 0x31 +#define PCF2131_REG_INT_A_MASK2 0x32 +#define PCF2131_REG_INT_B_MASK1 0x33 +#define PCF2131_REG_INT_B_MASK2 0x34 +#define PCF2131_BIT_INT_BLIE BIT(0) +#define PCF2131_BIT_INT_BIE BIT(1) +#define PCF2131_BIT_INT_AIE BIT(2) +#define PCF2131_BIT_INT_WD_CD BIT(3) +#define PCF2131_BIT_INT_SI BIT(4) +#define PCF2131_BIT_INT_MI BIT(5) =20 /* Watchdog timer value constants */ #define PCF2127_WD_VAL_STOP 0 @@ -110,6 +164,14 @@ PCF2127_BIT_CTRL2_AF | \ PCF2127_BIT_CTRL2_WDTF | \ PCF2127_BIT_CTRL2_TSF2) +#define PCF2131_CTRL2_IRQ_MASK ( \ + PCF2127_BIT_CTRL2_AF | \ + PCF2127_BIT_CTRL2_WDTF) +#define PCF2131_CTRL4_IRQ_MASK ( \ + PCF2131_BIT_CTRL4_TSF4 | \ + PCF2131_BIT_CTRL4_TSF3 | \ + PCF2131_BIT_CTRL4_TSF2 | \ + PCF2131_BIT_CTRL4_TSF1) =20 struct pcf21xx_ts_config { u8 regs_base; /* Base register to read timestamp values. */ @@ -370,7 +432,7 @@ static int pcf2127_wdt_set_timeout(struct watchdog_devi= ce *wdd, } =20 static const struct watchdog_info pcf2127_wdt_info =3D { - .identity =3D "NXP PCF2127/PCF2129 Watchdog", + .identity =3D "NXP PCF2127/29/31 Watchdog", .options =3D WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, }; =20 @@ -555,30 +617,64 @@ static void pcf2127_rtc_ts_snapshot(struct device *de= v, int ts_id) static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) { struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev); - unsigned int ctrl1, ctrl2; + unsigned int ctrl2; int ret =3D 0; =20 - ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); - if (ret) - return IRQ_NONE; - ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); if (ret) return IRQ_NONE; =20 - if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) - return IRQ_NONE; + if (pcf2127->cfg->ts_count =3D=3D 1) { + /* PCF2127/29 */ + unsigned int ctrl1; + + ret =3D regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); + if (ret) + return IRQ_NONE; + + if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) + return IRQ_NONE; =20 - if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) - pcf2127_rtc_ts_snapshot(dev, 0); + if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) + pcf2127_rtc_ts_snapshot(dev, 0); =20 - if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) - regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, - ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); + if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) + regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, + ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); + + if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) + regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, + ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); + } else { + /* PCF2131. */ + unsigned int ctrl4; + + ret =3D regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4); + if (ret) + return IRQ_NONE; =20 - if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) - regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, - ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); + if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK)) + return IRQ_NONE; + + if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) { + int i; + int tsf_bit =3D PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */ + + for (i =3D 0; i < pcf2127->cfg->ts_count; i++) { + if (ctrl4 & tsf_bit) + pcf2127_rtc_ts_snapshot(dev, i); + + tsf_bit =3D tsf_bit >> 1; + } + + regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4, + ctrl4 & ~PCF2131_CTRL4_IRQ_MASK); + } + + if (ctrl2 & PCF2131_CTRL2_IRQ_MASK) + regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, + ctrl2 & ~PCF2131_CTRL2_IRQ_MASK); + } =20 if (ctrl2 & PCF2127_BIT_CTRL2_AF) rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); @@ -650,6 +746,27 @@ static ssize_t timestamp0_store(struct device *dev, return timestamp_store(dev, attr, buf, count, 0); }; =20 +static ssize_t timestamp1_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return timestamp_store(dev, attr, buf, count, 1); +}; + +static ssize_t timestamp2_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return timestamp_store(dev, attr, buf, count, 2); +}; + +static ssize_t timestamp3_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return timestamp_store(dev, attr, buf, count, 3); +}; + static ssize_t timestamp_show(struct device *dev, struct device_attribute *attr, char *buf, int ts_id) @@ -714,16 +831,46 @@ static ssize_t timestamp0_show(struct device *dev, return timestamp_show(dev, attr, buf, 0); }; =20 +static ssize_t timestamp1_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return timestamp_show(dev, attr, buf, 1); +}; + +static ssize_t timestamp2_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return timestamp_show(dev, attr, buf, 2); +}; + +static ssize_t timestamp3_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return timestamp_show(dev, attr, buf, 3); +}; + static DEVICE_ATTR_RW(timestamp0); +static DEVICE_ATTR_RW(timestamp1); +static DEVICE_ATTR_RW(timestamp2); +static DEVICE_ATTR_RW(timestamp3); =20 static struct attribute *pcf2127_attrs[] =3D { &dev_attr_timestamp0.attr, NULL }; =20 +static struct attribute *pcf2131_attrs[] =3D { + &dev_attr_timestamp0.attr, + &dev_attr_timestamp1.attr, + &dev_attr_timestamp2.attr, + &dev_attr_timestamp3.attr, + NULL +}; + enum pcf21xx_type { PCF2127, PCF2129, + PCF2131, PCF21XX_LAST_ID }; =20 @@ -774,6 +921,48 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .attrs =3D pcf2127_attrs, }, }, + [PCF2131] =3D { + .max_register =3D 0x36, + .has_nvmem =3D 0, + .has_bit_wd_ctl_cd0 =3D 0, + .regs_td_base =3D PCF2131_REG_TIME_DATE_BASE, + .regs_alarm_base =3D PCF2131_REG_ALARM_BASE, + .reg_wd_ctl =3D PCF2131_REG_WD_CTL, + .reg_wd_val =3D PCF2131_REG_WD_VAL, + .reg_clkout =3D PCF2131_REG_CLKOUT, + .ts_count =3D 4, + .ts[0] =3D { + .regs_base =3D PCF2131_REG_TS1_BASE, + .low_reg =3D PCF2131_REG_CTRL4, + .low_bit =3D PCF2131_BIT_CTRL4_TSF1, + .ie_reg =3D PCF2131_REG_CTRL5, + .ie_bit =3D PCF2131_BIT_CTRL5_TSIE1, + }, + .ts[1] =3D { + .regs_base =3D PCF2131_REG_TS2_BASE, + .low_reg =3D PCF2131_REG_CTRL4, + .low_bit =3D PCF2131_BIT_CTRL4_TSF2, + .ie_reg =3D PCF2131_REG_CTRL5, + .ie_bit =3D PCF2131_BIT_CTRL5_TSIE2, + }, + .ts[2] =3D { + .regs_base =3D PCF2131_REG_TS3_BASE, + .low_reg =3D PCF2131_REG_CTRL4, + .low_bit =3D PCF2131_BIT_CTRL4_TSF3, + .ie_reg =3D PCF2131_REG_CTRL5, + .ie_bit =3D PCF2131_BIT_CTRL5_TSIE3, + }, + .ts[3] =3D { + .regs_base =3D PCF2131_REG_TS4_BASE, + .low_reg =3D PCF2131_REG_CTRL4, + .low_bit =3D PCF2131_BIT_CTRL4_TSF4, + .ie_reg =3D PCF2131_REG_CTRL5, + .ie_bit =3D PCF2131_BIT_CTRL5_TSIE4, + }, + .attribute_group =3D { + .attrs =3D pcf2131_attrs, + }, + }, }; =20 /* @@ -921,7 +1110,7 @@ static int pcf2127_probe(struct device *dev, struct re= gmap *regmap, * Watchdog timer enabled and reset pin /RST activated when timed out. * Select 1Hz clock source for watchdog timer. * Note: Countdown timer disabled and not available. - * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD + * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD * of register watchdg_tim_ctl. The bit[6] is labeled * as T. Bits labeled as T must always be written with * logic 0. @@ -981,6 +1170,7 @@ static const struct of_device_id pcf2127_of_match[] = =3D { { .compatible =3D "nxp,pcf2127", .data =3D &pcf21xx_cfg[PCF2127] }, { .compatible =3D "nxp,pcf2129", .data =3D &pcf21xx_cfg[PCF2129] }, { .compatible =3D "nxp,pca2129", .data =3D &pcf21xx_cfg[PCF2129] }, + { .compatible =3D "nxp,pcf2131", .data =3D &pcf21xx_cfg[PCF2131] }, {} }; MODULE_DEVICE_TABLE(of, pcf2127_of_match); @@ -1110,6 +1300,7 @@ static const struct i2c_device_id pcf2127_i2c_id[] = =3D { { "pcf2127", PCF2127 }, { "pcf2129", PCF2129 }, { "pca2129", PCF2129 }, + { "pcf2131", PCF2131 }, { } }; MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); @@ -1192,6 +1383,7 @@ static const struct spi_device_id pcf2127_spi_id[] = =3D { { "pcf2127", PCF2127 }, { "pcf2129", PCF2129 }, { "pca2129", PCF2129 }, + { "pcf2131", PCF2131 }, { } }; MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); @@ -1256,5 +1448,5 @@ static void __exit pcf2127_exit(void) module_exit(pcf2127_exit) =20 MODULE_AUTHOR("Renaud Cerrato "); -MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); +MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver"); MODULE_LICENSE("GPL v2"); --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03964C433EF for ; Fri, 11 Feb 2022 20:36:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353319AbiBKUgP (ORCPT ); Fri, 11 Feb 2022 15:36:15 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235821AbiBKUf7 (ORCPT ); Fri, 11 Feb 2022 15:35:59 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 795C5CF1; Fri, 11 Feb 2022 12:35:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=Wv4FHJN/eexiTb373COf63qSzuJufwmU8rnNAU+bfGY=; b=DYsvLqIW9WnTWiLsN4RYb+3lrG 0ic3hMxOF8TbBt2GP5HkK1eDVcITCd11wOxWBW8udJiXQn6KS6EXziZg7L6usUaUbtigH8MZRRFev jLcs4Ah7NCwo5hffzWLUI3L+qBBTFBnMScHzetKOqYrLJnnRMlK2BvhrJbC4niebA+cQ=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIce2-0005vF-8H; Fri, 11 Feb 2022 15:35:54 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:14 -0500 Message-Id: <20220211203520.3902374-9-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 08/14] rtc: pcf2127: add support for PCF2131 interrupts on output INT_A X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve The PCF2127 and PCF2129 have one output interrupt pin. The PCF2131 has two, named INT_A and INT_B. The hardware support that any interrupt source can be routed to either one or both of them. Force all interrupt sources to go to the INT A pin. Support to route any interrupt source to INT A/B pins is not supported by this driver at the moment. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index a52af7465d69..ee1e9d8285bb 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -191,6 +191,7 @@ struct pcf21xx_config { int max_register; unsigned int has_nvmem:1; unsigned int has_bit_wd_ctl_cd0:1; + unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */ u8 regs_td_base; /* Time/data base registers. */ u8 regs_alarm_base; /* Alarm function base registers. */ u8 reg_wd_ctl; /* Watchdog control register. */ @@ -879,6 +880,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x1d, .has_nvmem =3D 1, .has_bit_wd_ctl_cd0 =3D 1, + .has_int_a_b =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2127_REG_WD_CTL, @@ -902,6 +904,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x19, .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, + .has_int_a_b =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2127_REG_WD_CTL, @@ -925,6 +928,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x36, .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, + .has_int_a_b =3D 1, .regs_td_base =3D PCF2131_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2131_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2131_REG_WD_CTL, @@ -1017,6 +1021,28 @@ static int pcf2127_enable_ts(struct device *dev, int= ts_id) return ret; } =20 +/* Route all interrupt sources to INT A pin. */ +static int pcf2127_configure_interrupt_pins(struct device *dev) +{ + struct pcf2127 *pcf2127 =3D dev_get_drvdata(dev); + int ret; + + /* Mask bits need to be cleared to enable corresponding + * interrupt source. + */ + ret =3D regmap_write(pcf2127->regmap, + PCF2131_REG_INT_A_MASK1, 0); + if (ret) + return ret; + + ret =3D regmap_write(pcf2127->regmap, + PCF2131_REG_INT_A_MASK2, 0); + if (ret) + return ret; + + return ret; +} + static int pcf2127_probe(struct device *dev, struct regmap *regmap, int alarm_irq, const char *name, const struct pcf21xx_config *config) { @@ -1075,6 +1101,15 @@ static int pcf2127_probe(struct device *dev, struct = regmap *regmap, set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); } =20 + if (pcf2127->cfg->has_int_a_b) { + /* Configure int A/B pins, independently of alarm_irq. */ + ret =3D pcf2127_configure_interrupt_pins(dev); + if (ret) { + dev_err(dev, "failed to configure interrupt pins\n"); + return ret; + } + } + if (pcf2127->cfg->has_nvmem) { struct nvmem_config nvmem_cfg =3D { .priv =3D pcf2127, --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81A0DC433EF for ; Fri, 11 Feb 2022 20:36:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353313AbiBKUgL (ORCPT ); Fri, 11 Feb 2022 15:36:11 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352004AbiBKUgC (ORCPT ); Fri, 11 Feb 2022 15:36:02 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 105FDCF2; Fri, 11 Feb 2022 12:35:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=VtlQGULht92YsYdE9lX3WxpCltrMBfZKtbq5yoFFj7A=; b=csAz+aIYYS33qL4959nBEUfukt NbgyFWApRZHQ+AWznxY6onui2+jAqU3NSIHp9R1inEj/Eu9wrfozFkTOnDmSFO2R+/lWSu/ATHK7W /AJrgW9OTxqIlAFTFOQ+tswh1s1fBwwtFoZzsIVMyHVviRkV6ICVQ/708X9e/2zYxLOc=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIce3-0005vF-BK; Fri, 11 Feb 2022 15:35:55 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:15 -0500 Message-Id: <20220211203520.3902374-10-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 09/14] rtc: pcf2127: set PWRMNG value for PCF2131 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Default PWRMNG[2:0] bits are set to 000b for PCF2127/29, but to 111b for PCF2131. Set these bits to 000b to select same mode as PCF2127/29. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index ee1e9d8285bb..09b3d0ef4eff 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -53,6 +53,7 @@ #define PCF2127_BIT_CTRL3_BLF BIT(2) #define PCF2127_BIT_CTRL3_BF BIT(3) #define PCF2127_BIT_CTRL3_BTSE BIT(4) +#define PCF2127_CTRL3_PWRMNG_MASK GENMASK(7, 5) /* Control register 4 */ #define PCF2131_REG_CTRL4 0x03 #define PCF2131_BIT_CTRL4_TSF4 BIT(4) @@ -1128,6 +1129,20 @@ static int pcf2127_probe(struct device *dev, struct = regmap *regmap, regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, PCF2127_BIT_CTRL1_POR_OVRD); =20 + /* Make sure PWRMNG[2:0] is set to 000b. This is the default for + * PCF2127/29, but not for PCF2131 (default of 111b). + * + * PWRMNG[2:0] =3D 000b: + * battery switch-over function is enabled in standard mode; + * battery low detection function is enabled + */ + ret =3D regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL3, + PCF2127_CTRL3_PWRMNG_MASK); + if (ret < 0) { + dev_err(dev, "PWRMNG config failed\n"); + return ret; + } + ret =3D regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); if (ret < 0) return ret; --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88B66C433EF for ; Fri, 11 Feb 2022 20:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353331AbiBKUgV (ORCPT ); Fri, 11 Feb 2022 15:36:21 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353287AbiBKUgC (ORCPT ); Fri, 11 Feb 2022 15:36:02 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E7A9CF9; Fri, 11 Feb 2022 12:35:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=szliCvhlN5Z9BaTB8NpXRzmfXL5JLtC0U/5WIBQHRGk=; b=BRh/uUiG+rFL3jtQbFPIQZUU10 yz+IIB9g6/hXPIKNCwTpENbTnXs+wpPYfXOtMG2wd4YxGvZfbwBPxqvU0vpXLiyRGIU1EnDWrYZEV MepC/oalOwvQ1qOlR8/AKbF5DR1Oi/Ucd09un7NXJai8hY1dF7CTswvPKkl+E9WSulM4=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIce4-0005vF-A3; Fri, 11 Feb 2022 15:35:56 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:16 -0500 Message-Id: <20220211203520.3902374-11-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 10/14] rtc: pcf2127: read and validate PCF2131 device signature X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Make sure the device we are probing is really the device we are interested in. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 09b3d0ef4eff..8f3b34efff7f 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -193,11 +193,13 @@ struct pcf21xx_config { unsigned int has_nvmem:1; unsigned int has_bit_wd_ctl_cd0:1; unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */ + unsigned int has_reset_reg:1; /* If variant has a reset register. */ u8 regs_td_base; /* Time/data base registers. */ u8 regs_alarm_base; /* Alarm function base registers. */ u8 reg_wd_ctl; /* Watchdog control register. */ u8 reg_wd_val; /* Watchdog value register. */ u8 reg_clkout; /* Clkout register. */ + u8 reg_reset; /* Reset register if available. */ unsigned int ts_count; struct pcf21xx_ts_config ts[4]; struct attribute_group attribute_group; @@ -882,6 +884,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .has_nvmem =3D 1, .has_bit_wd_ctl_cd0 =3D 1, .has_int_a_b =3D 0, + .has_reset_reg =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2127_REG_WD_CTL, @@ -906,6 +909,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, .has_int_a_b =3D 0, + .has_reset_reg =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2127_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2127_REG_WD_CTL, @@ -930,11 +934,13 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, .has_int_a_b =3D 1, + .has_reset_reg =3D 1, .regs_td_base =3D PCF2131_REG_TIME_DATE_BASE, .regs_alarm_base =3D PCF2131_REG_ALARM_BASE, .reg_wd_ctl =3D PCF2131_REG_WD_CTL, .reg_wd_val =3D PCF2131_REG_WD_VAL, .reg_clkout =3D PCF2131_REG_CLKOUT, + .reg_reset =3D PCF2131_REG_SR_RESET, .ts_count =3D 4, .ts[0] =3D { .regs_base =3D PCF2131_REG_TS1_BASE, @@ -1074,6 +1080,20 @@ static int pcf2127_probe(struct device *dev, struct = regmap *regmap, pcf2127->rtc->uie_unsupported =3D 1; clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); =20 + /* Read device signature if available. */ + if (pcf2127->cfg->has_reset_reg) { + ret =3D regmap_read(pcf2127->regmap, pcf2127->cfg->reg_reset, &val); + if (ret < 0) { + dev_err(dev, "reading RESET register failed\n"); + return ret; + } + + if (val !=3D PCF2131_SR_RESET_READ_PATTERN) { + dev_err(dev, "invalid device signature: $%02X\n", (u8)val); + return -ENODEV; + } + } + if (alarm_irq > 0) { unsigned long flags; =20 --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10CECC433EF for ; Fri, 11 Feb 2022 20:36:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353325AbiBKUgT (ORCPT ); Fri, 11 Feb 2022 15:36:19 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353284AbiBKUgC (ORCPT ); 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Fri, 11 Feb 2022 15:35:58 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:17 -0500 Message-Id: <20220211203520.3902374-12-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 11/14] rtc: pcf2127: adapt time/date registers write sequence for PCF2131 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve The sequence for updating the time/date registers is slightly different between PCF2127/29 and PCF2131. For PCF2127/29, during write operations, the time counting circuits (memory locations 03h through 09h) are automatically blocked. For PCF2131, time/date registers write access requires setting the STOP bit and sending the clear prescaler instruction (CPR). STOP then needs to be released once write operation is completed. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 8f3b34efff7f..84ec7d5fda59 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -39,6 +39,7 @@ #define PCF2127_REG_CTRL1 0x00 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) #define PCF2127_BIT_CTRL1_TSF1 BIT(4) +#define PCF2127_BIT_CTRL1_STOP BIT(5) /* Control register 2 */ #define PCF2127_REG_CTRL2 0x01 #define PCF2127_BIT_CTRL2_AIE BIT(1) @@ -70,6 +71,7 @@ #define PCF2131_REG_SR_RESET 0x05 #define PCF2131_SR_RESET_READ_PATTERN 0b00100100 /* Fixed pattern. */ #define PCF2131_SR_RESET_RESET_CMD 0x2C /* SR is bit 3. */ +#define PCF2131_SR_RESET_CPR_CMD 0xA4 /* CPR is bit 7. */ /* Time and date registers */ #define PCF2127_REG_TIME_DATE_BASE 0x03 #define PCF2131_REG_TIME_DATE_BASE 0x07 /* Register 0x06 is 100th seconds, @@ -307,7 +309,31 @@ static int pcf2127_rtc_set_time(struct device *dev, st= ruct rtc_time *tm) /* year */ buf[i++] =3D bin2bcd(tm->tm_year - 100); =20 - /* write register's data */ + /* Write access to time registers: + * PCF2127/29: no special action required. + * PCF2131: requires setting the STOP bit. STOP bit needs to + * be cleared after time registers are updated. + * It is also recommended to set CPR bit, although + * write access will work without it. + */ + if (pcf2127->cfg->has_reset_reg) { + err =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, + PCF2127_BIT_CTRL1_STOP, + PCF2127_BIT_CTRL1_STOP); + if (err) { + dev_err(dev, "setting STOP bit failed\n"); + return err; + } + + err =3D regmap_write(pcf2127->regmap, pcf2127->cfg->reg_reset, + PCF2131_SR_RESET_CPR_CMD); + if (err) { + dev_err(dev, "sending CPR cmd failed\n"); + return err; + } + } + + /* write time register's data */ err =3D regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_td_base, bu= f, i); if (err) { dev_err(dev, @@ -315,6 +341,16 @@ static int pcf2127_rtc_set_time(struct device *dev, st= ruct rtc_time *tm) return err; } =20 + if (pcf2127->cfg->has_reset_reg) { + /* Clear STOP bit (PCF2131 only) after write is completed. */ + err =3D regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, + PCF2127_BIT_CTRL1_STOP, 0); + if (err) { + dev_err(dev, "clearing STOP bit failed\n"); + return err; + } + } + return 0; } =20 --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D1D2C433EF for ; Fri, 11 Feb 2022 20:36:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353336AbiBKUgX (ORCPT ); Fri, 11 Feb 2022 15:36:23 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353293AbiBKUgE (ORCPT ); Fri, 11 Feb 2022 15:36:04 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51639CE9; Fri, 11 Feb 2022 12:36:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=K2AaiHeuAPOhUIx+banJClIWKx7DCqmxRbmOpC7PYoY=; b=TttlfvumnwWnAE597s4Fm//C6s J60XnWZvWKUQjnbhZijREdOqjvUxnpDTsmhYF1qIJfv3GBHLtU7QIVWRNReXt2LupNtQCWdYotdA3 Lr63dh53E6MkylZ1Kgw7ytOKwBoKedKI1vCqvaXDjMtO/pB633nPclVLf1LSgYCB/6Ik=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIce6-0005vF-GP; Fri, 11 Feb 2022 15:35:59 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:18 -0500 Message-Id: <20220211203520.3902374-13-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 12/14] rtc: pcf2127: support generic watchdog timing configuration X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Introduce in the configuration structure two new values to hold the watchdog clock source and the min_hw_heartbeat_ms value. The minimum and maximum timeout values are automatically computed from the watchdog clock source value for each variant. The PCF2131 has no 1Hz watchdog clock source, as is the case for PCF2127/29. The next best choice is using a 1/4Hz clock, giving a watchdog timeout range between 4 and 1016s. By using the same register configuration as for the PCF2127/29, the 1/4Hz clock source is selected. Note: the PCF2127 datasheet gives a min/max range between 1 and 255s, but it should be between 2 and 254s, because the watchdog is triggered when the timer value reaches 1, not 0. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 56 +++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 84ec7d5fda59..7733122ac971 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -157,9 +157,29 @@ =20 /* Watchdog timer value constants */ #define PCF2127_WD_VAL_STOP 0 -#define PCF2127_WD_VAL_MIN 2 -#define PCF2127_WD_VAL_MAX 255 -#define PCF2127_WD_VAL_DEFAULT 60 +#define PCF2127_WD_VAL_DEFAULT 60 /* In seconds. */ +/* PCF2127/29 watchdog timer value constants */ +#define PCF2127_WD_CLOCK_HZ_X1000 1000 /* 1Hz */ +#define PCF2127_WD_MIN_HW_HEARTBEAT_MS 500 +/* PCF2131 watchdog timer value constants */ +#define PCF2131_WD_CLOCK_HZ_X1000 250 /* 1/4Hz */ +#define PCF2131_WD_MIN_HW_HEARTBEAT_MS 4000 +/* + * Compute watchdog period, t, in seconds, from the WATCHDG_TIM_VAL regist= er + * value, n, and the clock frequency, f, in Hz. + * + * The PCF2127/29 datasheet gives t as: + * t =3D n / f + * The PCF2131 datasheet gives t as: + * t =3D (n - 1) / f + * For both variants, the watchdog is triggered when the WATCHDG_TIM_VAL r= eaches + * the value 1, and not zero. Consequently, the equation from the PCF2131 + * datasheet seems to be the correct one for both variants. + */ +#define WD_PERIOD_S(_n_, _f1000_) ((1000 * ((_n_) - 1)) / (_f1000_)) + +/* Compute value of WATCHDG_TIM_VAL to obtain period t, in seconds. */ +#define WD_COUNTER(_t_, _f1000_) ((((_t_) * (_f1000_)) / 1000) + 1) =20 /* Mask for currently enabled interrupts */ #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) @@ -202,6 +222,11 @@ struct pcf21xx_config { u8 reg_wd_val; /* Watchdog value register. */ u8 reg_clkout; /* Clkout register. */ u8 reg_reset; /* Reset register if available. */ + + /* Watchdog configuration. */ + int wdd_clock_hz_x1000; /* Value in Hz multiplicated by 1000 */ + int wdd_min_hw_heartbeat_ms; + unsigned int ts_count; struct pcf21xx_ts_config ts[4]; struct attribute_group attribute_group; @@ -496,10 +521,19 @@ static int pcf2127_watchdog_init(struct device *dev, = struct pcf2127 *pcf2127) pcf2127->wdd.parent =3D dev; pcf2127->wdd.info =3D &pcf2127_wdt_info; pcf2127->wdd.ops =3D &pcf2127_watchdog_ops; - pcf2127->wdd.min_timeout =3D PCF2127_WD_VAL_MIN; - pcf2127->wdd.max_timeout =3D PCF2127_WD_VAL_MAX; - pcf2127->wdd.timeout =3D PCF2127_WD_VAL_DEFAULT; - pcf2127->wdd.min_hw_heartbeat_ms =3D 500; + + pcf2127->wdd.min_timeout =3D + WD_PERIOD_S(2, pcf2127->cfg->wdd_clock_hz_x1000); + pcf2127->wdd.max_timeout =3D + WD_PERIOD_S(255, pcf2127->cfg->wdd_clock_hz_x1000); + pcf2127->wdd.timeout =3D WD_COUNTER(PCF2127_WD_VAL_DEFAULT, + pcf2127->cfg->wdd_clock_hz_x1000); + + dev_dbg(dev, "%s min =3D %ds\n", __func__, pcf2127->wdd.min_timeout); + dev_dbg(dev, "%s max =3D %ds\n", __func__, pcf2127->wdd.max_timeout); + dev_dbg(dev, "%s def =3D %d\n", __func__, pcf2127->wdd.timeout); + + pcf2127->wdd.min_hw_heartbeat_ms =3D pcf2127->cfg->wdd_min_hw_heartbeat_m= s; pcf2127->wdd.status =3D WATCHDOG_NOWAYOUT_INIT_STATUS; =20 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); @@ -926,6 +960,8 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .reg_wd_ctl =3D PCF2127_REG_WD_CTL, .reg_wd_val =3D PCF2127_REG_WD_VAL, .reg_clkout =3D PCF2127_REG_CLKOUT, + .wdd_clock_hz_x1000 =3D PCF2127_WD_CLOCK_HZ_X1000, + .wdd_min_hw_heartbeat_ms =3D PCF2127_WD_MIN_HW_HEARTBEAT_MS, .ts_count =3D 1, .ts[0] =3D { .regs_base =3D PCF2127_REG_TS1_BASE, @@ -951,6 +987,8 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .reg_wd_ctl =3D PCF2127_REG_WD_CTL, .reg_wd_val =3D PCF2127_REG_WD_VAL, .reg_clkout =3D PCF2127_REG_CLKOUT, + .wdd_clock_hz_x1000 =3D PCF2127_WD_CLOCK_HZ_X1000, + .wdd_min_hw_heartbeat_ms =3D PCF2127_WD_MIN_HW_HEARTBEAT_MS, .ts_count =3D 1, .ts[0] =3D { .regs_base =3D PCF2127_REG_TS1_BASE, @@ -977,6 +1015,8 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .reg_wd_val =3D PCF2131_REG_WD_VAL, .reg_clkout =3D PCF2131_REG_CLKOUT, .reg_reset =3D PCF2131_REG_SR_RESET, + .wdd_clock_hz_x1000 =3D PCF2131_WD_CLOCK_HZ_X1000, + .wdd_min_hw_heartbeat_ms =3D PCF2131_WD_MIN_HW_HEARTBEAT_MS, .ts_count =3D 4, .ts[0] =3D { .regs_base =3D PCF2131_REG_TS1_BASE, @@ -1214,7 +1254,7 @@ static int pcf2127_probe(struct device *dev, struct r= egmap *regmap, =20 /* * Watchdog timer enabled and reset pin /RST activated when timed out. - * Select 1Hz clock source for watchdog timer. + * Select 1Hz clock source for watchdog timer (1/4Hz for PCF2131). * Note: Countdown timer disabled and not available. * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD * of register watchdg_tim_ctl. The bit[6] is labeled --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01551C433FE for ; Fri, 11 Feb 2022 20:36:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353343AbiBKUg0 (ORCPT ); Fri, 11 Feb 2022 15:36:26 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353288AbiBKUgE (ORCPT ); Fri, 11 Feb 2022 15:36:04 -0500 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFB2ACE7; Fri, 11 Feb 2022 12:36:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=bXIdQJ/4ESH6YhgujxY4yyNTtX8QtVpyBZQqoqBhJLo=; b=Vl7Vyy66HibNGaw63EovC3JtF8 AdNK8sVs6I9IS9GxAGlYO1/XIQUl1XjLc4BjhZgmFDO2otPV98FXrJ5pXrCF6HXRYi0Xkl3R/flFT 9pcnAB9XEIip4RiAgmFZMyGHcj9uH2A3Ss4Z4GIc8xNpcMT9VyKH1lafHi1IVIophREY=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIce7-0005vF-Ud; Fri, 11 Feb 2022 15:36:00 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:19 -0500 Message-Id: <20220211203520.3902374-14-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 13/14] rtc: pcf2127: add flag for watchdog register value read support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve The watchdog value register cannot be read on the PCF2131 after being set. Add a new flag to identify which variant has read access to this register, and use this flag to selectively test if watchdog timer was started by bootloader. Signed-off-by: Hugo Villeneuve --- drivers/rtc/rtc-pcf2127.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 7733122ac971..8accdece7d51 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -214,6 +214,7 @@ struct pcf21xx_config { int max_register; unsigned int has_nvmem:1; unsigned int has_bit_wd_ctl_cd0:1; + unsigned int wd_val_reg_readable:1; /* If watchdog value register can be = read. */ unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */ unsigned int has_reset_reg:1; /* If variant has a reset register. */ u8 regs_td_base; /* Time/data base registers. */ @@ -511,7 +512,6 @@ static const struct watchdog_ops pcf2127_watchdog_ops = =3D { =20 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf21= 27) { - u32 wdd_timeout; int ret; =20 if (!IS_ENABLED(CONFIG_WATCHDOG) || @@ -539,12 +539,17 @@ static int pcf2127_watchdog_init(struct device *dev, = struct pcf2127 *pcf2127) watchdog_set_drvdata(&pcf2127->wdd, pcf2127); =20 /* Test if watchdog timer is started by bootloader */ - ret =3D regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeo= ut); - if (ret) - return ret; + if (pcf2127->cfg->wd_val_reg_readable) { + u32 wdd_timeout; + + ret =3D regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, + &wdd_timeout); + if (ret) + return ret; =20 - if (wdd_timeout) - set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); + if (wdd_timeout) + set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); + } =20 return devm_watchdog_register_device(dev, &pcf2127->wdd); } @@ -953,6 +958,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x1d, .has_nvmem =3D 1, .has_bit_wd_ctl_cd0 =3D 1, + .wd_val_reg_readable =3D 1, .has_int_a_b =3D 0, .has_reset_reg =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, @@ -980,6 +986,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x19, .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, + .wd_val_reg_readable =3D 1, .has_int_a_b =3D 0, .has_reset_reg =3D 0, .regs_td_base =3D PCF2127_REG_TIME_DATE_BASE, @@ -1007,6 +1014,7 @@ static struct pcf21xx_config pcf21xx_cfg[] =3D { .max_register =3D 0x36, .has_nvmem =3D 0, .has_bit_wd_ctl_cd0 =3D 0, + .wd_val_reg_readable =3D 0, .has_int_a_b =3D 1, .has_reset_reg =3D 1, .regs_td_base =3D PCF2131_REG_TIME_DATE_BASE, --=20 2.30.2 From nobody Sun Jun 28 05:36:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2578DC433F5 for ; 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b=EE2n7i9uSaLVtix5ZXvnWQB8zW 7PDswhSh857ISrqO6QpH6os6PjpB7Ho+4Ix2Qs0EUXkqsizkWK3uHc5CpvbA5Y9Is/tBxViEfuTht elsFZMLx7f1c9RmYmhrNtsk/jgCNKmWusBXkwglUs6OH3uT3h+dwkC+Bok0Uf2JseYdM=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:55274 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1nIce9-0005vF-2E; Fri, 11 Feb 2022 15:36:01 -0500 From: Hugo Villeneuve To: hvilleneuve@dimonoff.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com, Rob Herring Cc: hugo@hugovil.com, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Date: Fri, 11 Feb 2022 15:35:20 -0500 Message-Id: <20220211203520.3902374-15-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220211203520.3902374-1-hugo@hugovil.com> References: <20220211203520.3902374-1-hugo@hugovil.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH 14/14] dt-bindings: rtc: pcf2127: add PCF2131 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Add support for new NXP RTC PCF2131. Signed-off-by: Hugo Villeneuve --- .../devicetree/bindings/rtc/nxp,pcf2127.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Docum= entation/devicetree/bindings/rtc/nxp,pcf2127.yaml index cde7b1675ead..57eb0a58afa3 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml @@ -14,7 +14,9 @@ maintainers: =20 properties: compatible: - const: nxp,pcf2127 + enum: + - nxp,pcf2127 + - nxp,pcf2131 =20 reg: maxItems: 1 @@ -48,4 +50,19 @@ examples: }; }; =20 + - | + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + rtc@53 { + compatible =3D "nxp,pcf2131"; + reg =3D <0x53>; + pinctrl-0 =3D <&rtc_nint_pins>; + interrupts-extended =3D <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>; + reset-source; + }; + }; + ... --=20 2.30.2