From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B767C433EF for ; Fri, 11 Feb 2022 18:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349453AbiBKSQo (ORCPT ); Fri, 11 Feb 2022 13:16:44 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:57388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245125AbiBKSQk (ORCPT ); Fri, 11 Feb 2022 13:16:40 -0500 Received: from st43p00im-ztbu10063701.me.com (st43p00im-ztbu10063701.me.com [17.58.63.178]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E8E3CEC for ; Fri, 11 Feb 2022 10:16:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1644603397; bh=mgjRMc/t3hJSZuo+CfZ8yOM9oXgwhCun+n3Gpc9EK2w=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=IFiRMxDjhsRIObQc1EMdp/R3qCT9vRgO9DG+fDHnqu47Vxtq3Wmg0mTKGd9lQtBlg IHYXiRZ2FgPhkhIKlUZT+4XA7G9yvxDQ1LcEw7RN0DBN7zFkci1l5GJRJUnlMtvrdl zveBP9nmfbRFTkvuka3p+20cQwmY1+UZbnLpD7bh833mcIOdsM78MTWmPnOonjnST8 aLOEvIwpn6zqg/rcsS1LiMGpEJMJGVOVd+KuaDsZz7xyT65knWgECbe5nXDNJsnfgt OgydQBlk1Tg0JbIPZqKrWyDNZtDbumkvSaBQvhJcKZJZauQTAZdJ5SCAnH8PJ1+bV+ laq0D9F+DSQAA== Received: from localhost (lfbn-lyo-1-306-208.w2-7.abo.wanadoo.fr [2.7.142.208]) by st43p00im-ztbu10063701.me.com (Postfix) with ESMTPSA id 45C97D006D2; Fri, 11 Feb 2022 18:16:37 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 1/7] ARM: dts: sti: ensure unique unit-address in stih407-clock Date: Fri, 11 Feb 2022 19:16:08 +0100 Message-Id: <20220211181614.683497-2-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.425,18.0.572,17.0.605.474.0000000_definitions?= =?UTF-8?Q?=3D2022-01-14=5F01:2022-01-14=5F01,2020-02-14=5F11,2020-01-23?= =?UTF-8?Q?=5F02_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 mlxlogscore=726 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move quadfs and a9-mux clocks nodes into clockgen nodes so that they can get the reg property from the parent node and ensure only one node has the address. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih407-clock.dtsi | 101 ++++++++++++--------------- 1 file changed, 46 insertions(+), 55 deletions(-) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih4= 07-clock.dtsi index 9cce9541e26b..350bcfcf498b 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -29,7 +29,7 @@ clocks { */ clockgen-a9@92b0000 { compatible =3D "st,clkgen-c32"; - reg =3D <0x92b0000 0xffff>; + reg =3D <0x92b0000 0x10000>; =20 clockgen_a9_pll: clockgen-a9-pll { #clock-cells =3D <1>; @@ -37,32 +37,27 @@ clockgen_a9_pll: clockgen-a9-pll { =20 clocks =3D <&clk_sysin>; }; - }; =20 - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells =3D <0>; - compatible =3D "st,stih407-clkgen-a9-mux"; - reg =3D <0x92b0000 0x10000>; - - clocks =3D <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; + clk_m_a9: clk-m-a9 { + #clock-cells =3D <0>; + compatible =3D "st,stih407-clkgen-a9-mux"; =20 + clocks =3D <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; =20 - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells =3D <0>; - compatible =3D "fixed-factor-clock"; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; =20 - clocks =3D <&clk_m_a9>; - clock-div =3D <2>; - clock-mult =3D <1>; + clocks =3D <&clk_m_a9>; + clock-div =3D <2>; + clock-mult =3D <1>; + }; }; }; =20 @@ -87,14 +82,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { }; }; =20 - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-pll"; - reg =3D <0x9103000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9103000 0x1000>; @@ -113,6 +100,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 { clocks =3D <&clk_sysin>; }; =20 + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-pll"; + + clocks =3D <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-c0"; @@ -142,18 +136,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { }; }; =20 - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d0"; - reg =3D <0x9104000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9104000 0x1000>; =20 + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d0"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-d0"; @@ -166,18 +159,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { }; }; =20 - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d2"; - reg =3D <0x9106000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9106000 0x1000>; =20 + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d2"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-d2"; @@ -192,18 +184,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { }; }; =20 - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d3"; - reg =3D <0x9107000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9107000 0x1000>; =20 + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d3"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-d3"; --=20 2.25.1 From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 473BAC433F5 for ; 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Fri, 11 Feb 2022 18:16:39 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 2/7] ARM: dts: sti: ensure unique unit-address in stih410-clock Date: Fri, 11 Feb 2022 19:16:09 +0100 Message-Id: <20220211181614.683497-3-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425,18.0.816 definitions=2022-02-11_05:2022-02-11,2022-02-11 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=710 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move quadfs and a9-mux clocks nodes into clockgen nodes so that they can get the reg property from the parent node and ensure only one node has the address. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih410-clock.dtsi | 100 +++++++++++++-------------- 1 file changed, 48 insertions(+), 52 deletions(-) diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih4= 10-clock.dtsi index 6b0e6d4477a3..abac98a1810b 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -32,7 +32,7 @@ clocks { */ clockgen-a9@92b0000 { compatible =3D "st,clkgen-c32"; - reg =3D <0x92b0000 0xffff>; + reg =3D <0x92b0000 0x10000>; =20 clockgen_a9_pll: clockgen-a9-pll { #clock-cells =3D <1>; @@ -40,29 +40,29 @@ clockgen_a9_pll: clockgen-a9-pll { =20 clocks =3D <&clk_sysin>; }; - }; =20 - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells =3D <0>; - compatible =3D "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg =3D <0x92b0000 0x10000>; - - clocks =3D <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; /* - * ARM Peripheral clock for timers + * ARM CPU related clocks. */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells =3D <0>; - compatible =3D "fixed-factor-clock"; - clocks =3D <&clk_m_a9>; - clock-div =3D <2>; - clock-mult =3D <1>; + compatible =3D "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks =3D <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&clk_m_a9>; + clock-div =3D <2>; + clock-mult =3D <1>; + }; }; }; =20 @@ -87,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { }; }; =20 - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-pll"; - reg =3D <0x9103000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9103000 0x1000>; @@ -113,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 { clocks =3D <&clk_sysin>; }; =20 + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-pll"; + + clocks =3D <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih410-c0"; @@ -142,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { }; }; =20 - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d0"; - reg =3D <0x9104000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9104000 0x1000>; =20 + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d0"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih410-d0"; @@ -166,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { }; }; =20 - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d2"; - reg =3D <0x9106000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9106000 0x1000>; =20 + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d2"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-d2"; @@ -192,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { }; }; =20 - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d3"; - reg =3D <0x9107000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9107000 0x1000>; =20 + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d3"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-d3"; --=20 2.25.1 From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A6AC433FE for ; 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Fri, 11 Feb 2022 18:16:43 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 3/7] ARM: dts: sti: ensure unique unit-address in stih418-clock Date: Fri, 11 Feb 2022 19:16:10 +0100 Message-Id: <20220211181614.683497-4-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425,18.0.816 definitions=2022-02-11_05:2022-02-11,2022-02-11 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=710 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move quadfs and a9-mux clocks nodes into clockgen nodes so that they can get the reg property from the parent node and ensure only one node has the address. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih418-clock.dtsi | 101 +++++++++++++-------------- 1 file changed, 48 insertions(+), 53 deletions(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih4= 18-clock.dtsi index e84c476b83ed..e1749e92a2e7 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -32,7 +32,7 @@ clocks { */ clockgen-a9@92b0000 { compatible =3D "st,clkgen-c32"; - reg =3D <0x92b0000 0xffff>; + reg =3D <0x92b0000 0x10000>; =20 clockgen_a9_pll: clockgen-a9-pll { #clock-cells =3D <1>; @@ -40,30 +40,29 @@ clockgen_a9_pll: clockgen-a9-pll { =20 clocks =3D <&clk_sysin>; }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells =3D <0>; - compatible =3D "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg =3D <0x92b0000 0x10000>; - - clocks =3D <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; =20 /* - * ARM Peripheral clock for timers + * ARM CPU related clocks. */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells =3D <0>; - compatible =3D "fixed-factor-clock"; - clocks =3D <&clk_m_a9>; - clock-div =3D <2>; - clock-mult =3D <1>; + compatible =3D "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks =3D <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&clk_m_a9>; + clock-div =3D <2>; + clock-mult =3D <1>; + }; }; }; =20 @@ -88,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { }; }; =20 - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-pll"; - reg =3D <0x9103000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9103000 0x1000>; @@ -114,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 { clocks =3D <&clk_sysin>; }; =20 + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-pll"; + + clocks =3D <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih418-c0"; @@ -143,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { }; }; =20 - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d0"; - reg =3D <0x9104000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9104000 0x1000>; =20 + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d0"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih410-d0"; @@ -167,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { }; }; =20 - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d2"; - reg =3D <0x9106000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9106000 0x1000>; =20 + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d2"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih418-d2"; @@ -193,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { }; }; =20 - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells =3D <1>; - compatible =3D "st,quadfs-d3"; - reg =3D <0x9107000 0x1000>; - - clocks =3D <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible =3D "st,clkgen-c32"; reg =3D <0x9107000 0x1000>; =20 + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells =3D <1>; + compatible =3D "st,quadfs-d3"; + + clocks =3D <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells =3D <1>; compatible =3D "st,flexgen", "st,flexgen-stih407-d3"; --=20 2.25.1 From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E33FC433FE for ; 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Fri, 11 Feb 2022 18:16:49 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 4/7] ARM: dts: sti: move some nodes out of the soc section in stih407-family.dtsi Date: Fri, 11 Feb 2022 19:16:11 +0100 Message-Id: <20220211181614.683497-5-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.138,18.0.816,17.11.62.513.0000000_definitions?= =?UTF-8?Q?=3D2022-01-17=5F04:2020-02-14=5F02,2022-01-17=5F04,2021-12-02?= =?UTF-8?Q?=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 bulkscore=0 mlxlogscore=806 malwarescore=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move all nodes without reg property out of the soc section of stih407-family.dtsi and DT including stih407-family.dtsi. This avoid to set a <0> reg property. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- v2: squash together 4 commits from v1 containing related modifications to avoid compilation issues arch/arm/boot/dts/stih407-family.dtsi | 262 +++++++++++++------------- arch/arm/boot/dts/stih410-b2260.dts | 14 +- arch/arm/boot/dts/stih418-b2199.dts | 22 +-- arch/arm/boot/dts/stihxxx-b2120.dtsi | 22 +-- 4 files changed, 155 insertions(+), 165 deletions(-) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih= 407-family.dtsi index 21f3347a91d6..1713f7878117 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -115,37 +115,140 @@ pwm_regulator: pwm-regulator { status =3D "okay"; }; =20 - soc { - #address-cells =3D <1>; - #size-cells =3D <1>; - interrupt-parent =3D <&intc>; + restart: restart-controller { + compatible =3D "st,stih407-restart"; + st,syscfg =3D <&syscfg_sbc_reg>; + status =3D "okay"; + }; + + powerdown: powerdown-controller { + compatible =3D "st,stih407-powerdown"; + #reset-cells =3D <1>; + }; + + softreset: softreset-controller { + compatible =3D "st,stih407-softreset"; + #reset-cells =3D <1>; + }; + + picophyreset: picophyreset-controller { + compatible =3D "st,stih407-picophyreset"; + #reset-cells =3D <1>; + }; + + irq-syscfg { + compatible =3D "st,stih407-irq-syscfg"; + st,syscfg =3D <&syscfg_core>; + st,irq-device =3D , + ; + st,fiq-device =3D , + ; + }; + + usb2_picophy0: phy1 { + compatible =3D "st,stih407-usb2-phy"; + #phy-cells =3D <0>; + st,syscfg =3D <&syscfg_core 0x100 0xf4>; + resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY2_RESET>; + reset-names =3D "global", "port"; + }; + + miphy28lp_phy: miphy28lp { + compatible =3D "st,miphy28lp-phy"; + st,syscfg =3D <&syscfg_core>; + #address-cells =3D <1>; + #size-cells =3D <1>; ranges; - compatible =3D "simple-bus"; =20 - restart: restart-controller@0 { - compatible =3D "st,stih407-restart"; - reg =3D <0 0>; - st,syscfg =3D <&syscfg_sbc_reg>; - status =3D "okay"; - }; + phy_port0: port@9b22000 { + reg =3D <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>; + reg-names =3D "sata-up", + "pcie-up", + "pipew"; + + st,syscfg =3D <0x114 0x818 0xe0 0xec>; + #phy-cells =3D <1>; =20 - powerdown: powerdown-controller@0 { - compatible =3D "st,stih407-powerdown"; - reg =3D <0 0>; - #reset-cells =3D <1>; + reset-names =3D "miphy-sw-rst"; + resets =3D <&softreset STIH407_MIPHY0_SOFTRESET>; }; =20 - softreset: softreset-controller@0 { - compatible =3D "st,stih407-softreset"; - reg =3D <0 0>; - #reset-cells =3D <1>; + phy_port1: port@9b2a000 { + reg =3D <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>; + reg-names =3D "sata-up", + "pcie-up", + "pipew"; + + st,syscfg =3D <0x118 0x81c 0xe4 0xf0>; + + #phy-cells =3D <1>; + + reset-names =3D "miphy-sw-rst"; + resets =3D <&softreset STIH407_MIPHY1_SOFTRESET>; }; =20 - picophyreset: picophyreset-controller@0 { - compatible =3D "st,stih407-picophyreset"; - reg =3D <0 0>; - #reset-cells =3D <1>; + phy_port2: port@8f95000 { + reg =3D <0x8f95000 0xff>, + <0x8f90000 0xff>; + reg-names =3D "pipew", + "usb3-up"; + + st,syscfg =3D <0x11c 0x820>; + + #phy-cells =3D <1>; + + reset-names =3D "miphy-sw-rst"; + resets =3D <&softreset STIH407_MIPHY2_SOFTRESET>; }; + }; + + st231_gp0: st231-gp0 { + compatible =3D "st,st231-rproc"; + memory-region =3D <&gp0_reserved>; + resets =3D <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names =3D "sw_reset"; + clocks =3D <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency =3D <600000000>; + st,syscfg =3D <&syscfg_core 0x22c>; + #mbox-cells =3D <1>; + mbox-names =3D "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes =3D <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2= 0 0>; + }; + + st231_delta: st231-delta { + compatible =3D "st,st231-rproc"; + memory-region =3D <&delta_reserved>; + resets =3D <&softreset STIH407_ST231_DMU_SOFTRESET>; + reset-names =3D "sw_reset"; + clocks =3D <&clk_s_c0_flexgen CLK_ST231_DMU>; + clock-frequency =3D <600000000>; + st,syscfg =3D <&syscfg_core 0x224>; + #mbox-cells =3D <1>; + mbox-names =3D "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes =3D <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3= 0 0>; + }; + + delta0 { + compatible =3D "st,st-delta"; + clock-names =3D "delta", + "delta-st231", + "delta-flash-promip"; + clocks =3D <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&intc>; + ranges; + compatible =3D "simple-bus"; =20 syscfg_sbc: sbc-syscfg@9620000 { compatible =3D "st,stih407-sbc-syscfg", "syscon"; @@ -189,16 +292,6 @@ syscfg_lpm: lpm-syscfg@94b5100 { reg =3D <0x94b5100 0x1000>; }; =20 - irq-syscfg@0 { - compatible =3D "st,stih407-irq-syscfg"; - reg =3D <0 0>; - st,syscfg =3D <&syscfg_core>; - st,irq-device =3D , - ; - st,fiq-device =3D , - ; - }; - /* Display */ vtg_main: sti-vtg-main@8d02800 { compatible =3D "st,vtg"; @@ -389,70 +482,6 @@ i2c@9541000 { status =3D "disabled"; }; =20 - usb2_picophy0: phy1@0 { - compatible =3D "st,stih407-usb2-phy"; - reg =3D <0 0>; - #phy-cells =3D <0>; - st,syscfg =3D <&syscfg_core 0x100 0xf4>; - resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names =3D "global", "port"; - }; - - miphy28lp_phy: miphy28lp@0 { - compatible =3D "st,miphy28lp-phy"; - st,syscfg =3D <&syscfg_core>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - reg =3D <0 0>; - - phy_port0: port@9b22000 { - reg =3D <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names =3D "sata-up", - "pcie-up", - "pipew"; - - st,syscfg =3D <0x114 0x818 0xe0 0xec>; - #phy-cells =3D <1>; - - reset-names =3D "miphy-sw-rst"; - resets =3D <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg =3D <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names =3D "sata-up", - "pcie-up", - "pipew"; - - st,syscfg =3D <0x118 0x81c 0xe4 0xf0>; - - #phy-cells =3D <1>; - - reset-names =3D "miphy-sw-rst"; - resets =3D <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg =3D <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names =3D "pipew", - "usb3-up"; - - st,syscfg =3D <0x11c 0x820>; - - #phy-cells =3D <1>; - - reset-names =3D "miphy-sw-rst"; - resets =3D <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - spi@9840000 { compatible =3D "st,comms-ssc4-spi"; reg =3D <0x9840000 0x110>; @@ -815,34 +844,6 @@ mailbox3: mailbox@8f03000 { status =3D "okay"; }; =20 - st231_gp0: st231-gp0@0 { - compatible =3D "st,st231-rproc"; - reg =3D <0 0>; - memory-region =3D <&gp0_reserved>; - resets =3D <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names =3D "sw_reset"; - clocks =3D <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency =3D <600000000>; - st,syscfg =3D <&syscfg_core 0x22c>; - #mbox-cells =3D <1>; - mbox-names =3D "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes =3D <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox= 2 0 0>; - }; - - st231_delta: st231-delta@0 { - compatible =3D "st,st231-rproc"; - reg =3D <0 0>; - memory-region =3D <&delta_reserved>; - resets =3D <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names =3D "sw_reset"; - clocks =3D <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency =3D <600000000>; - st,syscfg =3D <&syscfg_core 0x224>; - #mbox-cells =3D <1>; - mbox-names =3D "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes =3D <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox= 3 0 0>; - }; - /* fdma audio */ fdma0: dma-controller@8e20000 { compatible =3D "st,stih407-fdma-mpe31-11", "st,slim-rproc"; @@ -986,16 +987,5 @@ sti_uni_reader1: sti-uni-reader@8d84000 { =20 status =3D "disabled"; }; - - delta0@0 { - compatible =3D "st,st-delta"; - reg =3D <0 0>; - clock-names =3D "delta", - "delta-st231", - "delta-flash-promip"; - clocks =3D <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; }; }; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih41= 0-b2260.dts index 9d579c16c295..c2d3b6de55d0 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -75,6 +75,13 @@ codec { }; }; =20 + miphy28lp_phy: miphy28lp { + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { @@ -196,13 +203,6 @@ hdmiddc: i2c@9541000 { status =3D "okay"; }; =20 - miphy28lp_phy: miphy28lp@0 { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - sata1: sata@9b28000 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih41= 8-b2199.dts index b66e2b29edea..d21bcc7c1271 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -37,6 +37,17 @@ green { }; }; =20 + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { sbc_serial0: serial@9530000 { status =3D "okay"; @@ -84,17 +95,6 @@ mmc0: sdhci@9060000 { non-removable; }; =20 - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - st_dwc3: dwc3@8f94000 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihx= xx-b2120.dtsi index d051f080e52e..4c72dedcd1be 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -71,6 +71,17 @@ codec { }; }; =20 + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { sbc_serial0: serial@9530000 { status =3D "okay"; @@ -128,17 +139,6 @@ hdmiddc: i2c@9541000 { st,i2c-min-sda-pulse-width-us =3D <5>; }; =20 - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - st_dwc3: dwc3@8f94000 { status =3D "okay"; }; --=20 2.25.1 From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C908C433F5 for ; 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Fri, 11 Feb 2022 18:16:53 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 5/7] ARM: dts: sti: remove delta node from stih410.dtsi Date: Fri, 11 Feb 2022 19:16:12 +0100 Message-Id: <20220211181614.683497-6-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425,18.0.816 definitions=2022-02-11_05:2022-02-11,2022-02-11 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=747 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The delta0 node within stih410.dtsi is identical to the one already written within stih407-family.dtsi and included within stih410.dtsi. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih410.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 6d847019c554..fe83d9a522bf 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -274,16 +274,6 @@ thermal@91a0000 { interrupts =3D ; }; =20 - delta0@0 { - compatible =3D "st,st-delta"; - clock-names =3D "delta", - "delta-st231", - "delta-flash-promip"; - clocks =3D <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - sti-cec@94a087c { compatible =3D "st,stih-cec"; reg =3D <0x94a087c 0x64>; --=20 2.25.1 From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC94EC433F5 for ; Fri, 11 Feb 2022 18:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352614AbiBKSRG (ORCPT ); Fri, 11 Feb 2022 13:17:06 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:57828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352598AbiBKSRA (ORCPT ); Fri, 11 Feb 2022 13:17:00 -0500 Received: from st43p00im-ztdg10073201.me.com (st43p00im-ztdg10073201.me.com [17.58.63.177]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8D11D43 for ; Fri, 11 Feb 2022 10:16:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1644603417; bh=Rg0EIUG5YQ/nG3yQzZ80SkA2uhlV3mGvQHIXfsmLoRk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=p/MFjwttwRQM0R5xLX7LXKQwp05C2DIKB9JPfYqk6B85svRVzfrsFxA92m4jZzmEj P+7bFOjXPT0P+uv4BoH7T0fIGdqGT2UFCGgl3pbM/ZyzJCF98WA9t8QNnvRCYQdxp5 XoexvO3NZ3iBg0CO+101e0oHXssAv/zEbAeQ4I/v1Ffb+rdUSqGPFRhH8UFnqDp4o0 I0YFLerSoBp1+2zUI6LwgFQrVJEBrN3JbDdVi4Ra0cJPxBD9kZjlckmRuX6ZKEoZY0 jxiGoRbZhBJbwRDp5DPATf8uF9GP0UadVyJl0CfwT0xxjV2cdbroysO6Nihyz2ONrg XGhT/25X+Z3HQ== Received: from localhost (lfbn-lyo-1-306-208.w2-7.abo.wanadoo.fr [2.7.142.208]) by st43p00im-ztdg10073201.me.com (Postfix) with ESMTPSA id 3B2719A0FD3; Fri, 11 Feb 2022 18:16:57 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 6/7] ARM: dts: sti: move usb picophy nodes out of soc in stih410.dtsi Date: Fri, 11 Feb 2022 19:16:13 +0100 Message-Id: <20220211181614.683497-7-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.138,18.0.816,17.11.62.513.0000000_definitions?= =?UTF-8?Q?=3D2022-01-17=5F04:2020-02-14=5F02,2022-01-17=5F04,2021-12-02?= =?UTF-8?Q?=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=915 adultscore=0 suspectscore=0 clxscore=1015 spamscore=0 malwarescore=0 phishscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section. Since they are controlled via syscfg, there is no reg property needed, which is required when having the node within the soc section. Modification is done within stih410.dtsi and within related board dts files (stih410-b2120.dts, stih410-b2260.dts). Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- v2: squash together 3 commits from v1 to avoid compilation issues arch/arm/boot/dts/stih410-b2120.dts | 16 +++++------ arch/arm/boot/dts/stih410-b2260.dts | 16 +++++------ arch/arm/boot/dts/stih410.dtsi | 42 ++++++++++++++--------------- 3 files changed, 36 insertions(+), 38 deletions(-) diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih41= 0-b2120.dts index 9d3b118f5f0f..538ff98ca1b1 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -24,6 +24,14 @@ aliases { ethernet0 =3D ðernet0; }; =20 + usb2_picophy1: phy2 { + status =3D "okay"; + }; + + usb2_picophy2: phy3 { + status =3D "okay"; + }; + soc { =20 mmc0: sdhci@9060000 { @@ -33,14 +41,6 @@ mmc0: sdhci@9060000 { sd-uhs-ddr50; }; =20 - usb2_picophy1: phy2@0 { - status =3D "okay"; - }; - - usb2_picophy2: phy3@0 { - status =3D "okay"; - }; - ohci0: usb@9a03c00 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih41= 0-b2260.dts index c2d3b6de55d0..26d93f26f6d0 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -82,6 +82,14 @@ phy_port1: port@9b2a000 { }; }; =20 + usb2_picophy1: phy2 { + status =3D "okay"; + }; + + usb2_picophy2: phy3 { + status =3D "okay"; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { @@ -152,14 +160,6 @@ pwm1: pwm@9510000 { status =3D "okay"; }; =20 - usb2_picophy1: phy2@0 { - status =3D "okay"; - }; - - usb2_picophy2: phy3@0 { - status =3D "okay"; - }; - ohci0: usb@9a03c00 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index fe83d9a522bf..ce2f62cf129b 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -12,31 +12,29 @@ aliases { bdisp0 =3D &bdisp0; }; =20 - soc { - usb2_picophy1: phy2@0 { - compatible =3D "st,stih407-usb2-phy"; - reg =3D <0 0>; - #phy-cells =3D <0>; - st,syscfg =3D <&syscfg_core 0xf8 0xf4>; - resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names =3D "global", "port"; + usb2_picophy1: phy2 { + compatible =3D "st,stih407-usb2-phy"; + #phy-cells =3D <0>; + st,syscfg =3D <&syscfg_core 0xf8 0xf4>; + resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names =3D "global", "port"; + + status =3D "disabled"; + }; =20 - status =3D "disabled"; - }; + usb2_picophy2: phy3 { + compatible =3D "st,stih407-usb2-phy"; + #phy-cells =3D <0>; + st,syscfg =3D <&syscfg_core 0xfc 0xf4>; + resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names =3D "global", "port"; =20 - usb2_picophy2: phy3@0 { - compatible =3D "st,stih407-usb2-phy"; - reg =3D <0 0>; - #phy-cells =3D <0>; - st,syscfg =3D <&syscfg_core 0xfc 0xf4>; - resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names =3D "global", "port"; - - status =3D "disabled"; - }; + status =3D "disabled"; + }; =20 + soc { ohci0: usb@9a03c00 { compatible =3D "st,st-ohci-300x"; reg =3D <0x9a03c00 0x100>; --=20 2.25.1 From nobody Sun Jun 28 05:33:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 824F4C433F5 for ; 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Fri, 11 Feb 2022 18:16:59 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v2 7/7] ARM: dts: sti: move usb picophy nodes out of soc in stih418.dtsi Date: Fri, 11 Feb 2022 19:16:14 +0100 Message-Id: <20220211181614.683497-8-avolmat@me.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211181614.683497-1-avolmat@me.com> References: <20220211181614.683497-1-avolmat@me.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.425,18.0.572,17.0.605.474.0000000_definitions?= =?UTF-8?Q?=3D2022-01-14=5F01:2022-01-14=5F01,2020-02-14=5F11,2020-01-23?= =?UTF-8?Q?=5F02_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 mlxlogscore=766 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2202110099 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section. Since they are controlled via syscfg, there is no reg property needed, which is required when having the node within the soc section. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih418.dtsi | 38 ++++++++++++++++------------------ 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 97eda4392fbe..b35b9b7a7ccc 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -26,31 +26,29 @@ cpu@3 { }; }; =20 + usb2_picophy1: phy2 { + compatible =3D "st,stih407-usb2-phy"; + #phy-cells =3D <0>; + st,syscfg =3D <&syscfg_core 0xf8 0xf4>; + resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names =3D "global", "port"; + }; + + usb2_picophy2: phy3 { + compatible =3D "st,stih407-usb2-phy"; + #phy-cells =3D <0>; + st,syscfg =3D <&syscfg_core 0xfc 0xf4>; + resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names =3D "global", "port"; + }; + soc { rng11: rng@8a8a000 { status =3D "disabled"; }; =20 - usb2_picophy1: phy2@0 { - compatible =3D "st,stih407-usb2-phy"; - reg =3D <0 0>; - #phy-cells =3D <0>; - st,syscfg =3D <&syscfg_core 0xf8 0xf4>; - resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names =3D "global", "port"; - }; - - usb2_picophy2: phy3@0 { - compatible =3D "st,stih407-usb2-phy"; - reg =3D <0 0>; - #phy-cells =3D <0>; - st,syscfg =3D <&syscfg_core 0xfc 0xf4>; - resets =3D <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names =3D "global", "port"; - }; - ohci0: usb@9a03c00 { compatible =3D "st,st-ohci-300x"; reg =3D <0x9a03c00 0x100>; --=20 2.25.1