From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC1FAC433EF for ; Fri, 11 Feb 2022 12:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239240AbiBKM05 (ORCPT ); Fri, 11 Feb 2022 07:26:57 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349977AbiBKM0w (ORCPT ); Fri, 11 Feb 2022 07:26:52 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BCE3FE77; Fri, 11 Feb 2022 04:26:51 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8292111D4; Fri, 11 Feb 2022 04:26:51 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF0273F70D; Fri, 11 Feb 2022 04:26:49 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH v10 01/18] clk: sunxi-ng: h616-r: Add RTC gate clock Date: Fri, 11 Feb 2022 12:26:26 +0000 Message-Id: <20220211122643.1343315-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The H616 features an (undocumented) bus clock gate for accessing the RTC registers. This seems to be enabled at reset (or by the BootROM), but is there anyway. Since the new RTC clock binding for the H616 requires this "bus" clock to be specified in the DT, add this to R_CCU clock driver and expose it on the DT side with a new number. Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 4 ++++ drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 2 +- include/dt-bindings/clock/sun50i-h6-r-ccu.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/= ccu-sun50i-h6-r.c index 712e103382d8..26fb092f6df6 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -98,6 +98,8 @@ static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1= ", 0x1cc, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", 0x1ec, BIT(0), 0); +static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1", + 0x20c, BIT(0), 0); =20 /* Information of IR(RX) mod clock is gathered from BSP source code */ static const char * const r_mod0_default_parents[] =3D { "osc32k", "osc24M= " }; @@ -147,6 +149,7 @@ static struct ccu_common *sun50i_h616_r_ccu_clks[] =3D { &r_apb2_i2c_clk.common, &r_apb2_rsb_clk.common, &r_apb1_ir_clk.common, + &r_apb1_rtc_clk.common, &ir_clk.common, }; =20 @@ -179,6 +182,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks= =3D { [CLK_R_APB2_I2C] =3D &r_apb2_i2c_clk.common.hw, [CLK_R_APB2_RSB] =3D &r_apb2_rsb_clk.common.hw, [CLK_R_APB1_IR] =3D &r_apb1_ir_clk.common.hw, + [CLK_R_APB1_RTC] =3D &r_apb1_rtc_clk.common.hw, [CLK_IR] =3D &ir_clk.common.hw, }, .num =3D CLK_NUMBER, diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/= ccu-sun50i-h6-r.h index 7e290b840803..10e9b66afc6a 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h @@ -14,6 +14,6 @@ =20 #define CLK_R_APB2 3 =20 -#define CLK_NUMBER (CLK_R_APB2_RSB + 1) +#define CLK_NUMBER (CLK_R_APB1_RTC + 1) =20 #endif /* _CCU_SUN50I_H6_R_H */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindi= ngs/clock/sun50i-h6-r-ccu.h index 890368d252c4..a96087abc86f 100644 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -22,5 +22,6 @@ #define CLK_W1 12 =20 #define CLK_R_APB2_RSB 13 +#define CLK_R_APB1_RTC 14 =20 #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AAF7C4332F for ; Fri, 11 Feb 2022 12:27:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350004AbiBKM1B (ORCPT ); Fri, 11 Feb 2022 07:27:01 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349988AbiBKM0y (ORCPT ); Fri, 11 Feb 2022 07:26:54 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A0374E77; Fri, 11 Feb 2022 04:26:53 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E03C139F; Fri, 11 Feb 2022 04:26:53 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B32D93F70D; Fri, 11 Feb 2022 04:26:51 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH v10 02/18] clk: sunxi-ng: h616: Add PLL derived 32KHz clock Date: Fri, 11 Feb 2022 12:26:27 +0000 Message-Id: <20220211122643.1343315-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RTC section of the H616 manual mentions in a half-sentence the existence of a clock "32K divided by PLL_PERI(2X)". This is used as one of the possible inputs for the mux that selects the clock for the 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some boards use that clock output to compensate for a missing 32KHz crystal. On the OrangePi Zero2 this is for instance connected to the LPO pin of the WiFi/BT chip. The new RTC clock binding requires this clock to be named as one input clock, so we need to expose this to the DT. In contrast to the D1 SoC there does not seem to be a gate for this clock, so just use a fixed divider clock, using a newly assigned clock number. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 7 +++++++ drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 2 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/= ccu-sun50i-h616.c index 49a2474cf314..f4e896b19a16 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c @@ -704,6 +704,12 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-p= eriph0-2x", pll_periph0_parents, 1, 2, 0); =20 +static const struct clk_hw *pll_periph0_2x_hws[] =3D { + &pll_periph0_2x_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", + pll_periph0_2x_hws, 36621, 1, 0); + static const struct clk_hw *pll_periph1_parents[] =3D { &pll_periph1_clk.common.hw }; @@ -852,6 +858,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = =3D { [CLK_PLL_DDR1] =3D &pll_ddr1_clk.common.hw, [CLK_PLL_PERIPH0] =3D &pll_periph0_clk.common.hw, [CLK_PLL_PERIPH0_2X] =3D &pll_periph0_2x_clk.hw, + [CLK_PLL_SYSTEM_32K] =3D &pll_system_32k_clk.hw, [CLK_PLL_PERIPH1] =3D &pll_periph1_clk.common.hw, [CLK_PLL_PERIPH1_2X] =3D &pll_periph1_2x_clk.hw, [CLK_PLL_GPU] =3D &pll_gpu_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/= ccu-sun50i-h616.h index dd671b413f22..fdd2f4d5103f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h @@ -51,6 +51,6 @@ =20 #define CLK_BUS_DRAM 56 =20 -#define CLK_NUMBER (CLK_BUS_HDCP + 1) +#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1) =20 #endif /* _CCU_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindi= ngs/clock/sun50i-h616-ccu.h index 4fc08b0df2f3..1191aca53ac6 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -111,5 +111,6 @@ #define CLK_BUS_TVE0 125 #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 +#define CLK_PLL_SYSTEM_32K 128 =20 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C22FC433FE for ; Fri, 11 Feb 2022 12:27:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350020AbiBKM1F (ORCPT ); Fri, 11 Feb 2022 07:27:05 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349992AbiBKM04 (ORCPT ); Fri, 11 Feb 2022 07:26:56 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9BAE9F28; Fri, 11 Feb 2022 04:26:55 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F5E01042; Fri, 11 Feb 2022 04:26:55 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A02483F70D; Fri, 11 Feb 2022 04:26:53 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Alessandro Zummo , Alexandre Belloni , linux-rtc@vger.kernel.org Subject: [PATCH v10 03/18] rtc: sun6i: Fix time overflow handling Date: Fri, 11 Feb 2022 12:26:28 +0000 Message-Id: <20220211122643.1343315-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using "unsigned long" for UNIX timestamps is never a good idea, and comparing the value of such a variable against U32_MAX does not do anything useful on 32-bit systems. Use the proper time64_t type when dealing with timestamps, and avoid cutting down the time range unnecessarily. This also fixes the flawed check for the alarm time being too far into the future. The check for this condition is actually somewhat theoretical, as the RTC counts till 2033 only anyways, and 2^32 seconds from now is not before the year 2157 - at which point I hope nobody will be using this hardware anymore. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/rtc/rtc-sun6i.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 35b34d14a1db..dc3ae851841c 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -139,7 +139,7 @@ struct sun6i_rtc_dev { const struct sun6i_rtc_clk_data *data; void __iomem *base; int irq; - unsigned long alarm; + time64_t alarm; =20 struct clk_hw hw; struct clk_hw *int_osc; @@ -511,10 +511,8 @@ static int sun6i_rtc_setalarm(struct device *dev, stru= ct rtc_wkalrm *wkalrm) struct sun6i_rtc_dev *chip =3D dev_get_drvdata(dev); struct rtc_time *alrm_tm =3D &wkalrm->time; struct rtc_time tm_now; - unsigned long time_now =3D 0; - unsigned long time_set =3D 0; - unsigned long time_gap =3D 0; - int ret =3D 0; + time64_t time_now, time_set; + int ret; =20 ret =3D sun6i_rtc_gettime(dev, &tm_now); if (ret < 0) { @@ -529,9 +527,7 @@ static int sun6i_rtc_setalarm(struct device *dev, struc= t rtc_wkalrm *wkalrm) return -EINVAL; } =20 - time_gap =3D time_set - time_now; - - if (time_gap > U32_MAX) { + if ((time_set - time_now) > U32_MAX) { dev_err(dev, "Date too far in the future\n"); return -EINVAL; } @@ -540,7 +536,7 @@ static int sun6i_rtc_setalarm(struct device *dev, struc= t rtc_wkalrm *wkalrm) writel(0, chip->base + SUN6I_ALRM_COUNTER); usleep_range(100, 300); =20 - writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); + writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER); chip->alarm =3D time_set; =20 sun6i_rtc_setaie(wkalrm->enabled, chip); --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F9D3C433F5 for ; Fri, 11 Feb 2022 12:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350033AbiBKM1I (ORCPT ); Fri, 11 Feb 2022 07:27:08 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349994AbiBKM06 (ORCPT ); Fri, 11 Feb 2022 07:26:58 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7C22DF60; Fri, 11 Feb 2022 04:26:57 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B0A112FC; Fri, 11 Feb 2022 04:26:57 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8DF163F70D; Fri, 11 Feb 2022 04:26:55 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Alessandro Zummo , Alexandre Belloni , linux-rtc@vger.kernel.org Subject: [PATCH v10 04/18] rtc: sun6i: Add support for linear day storage Date: Fri, 11 Feb 2022 12:26:29 +0000 Message-Id: <20220211122643.1343315-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer versions of the Allwinner RTC, as for instance found in the H616 SoC, no longer store a broken-down day/month/year representation in the RTC_DAY_REG, but just a linear day number. The user manual does not give any indication about the expected epoch time of this day count, but the BSP kernel uses the UNIX epoch, which allows easy support due to existing conversion functions in the kernel. Allow tagging a compatible string with a flag, and use that to mark those new RTCs. Then convert between a UNIX day number (converted into seconds) and the broken-down day representation using mktime64() and time64_to_tm() in the set_time/get_time functions. That enables support for the RTC in those new chips. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/rtc/rtc-sun6i.c | 69 +++++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index dc3ae851841c..996d05938839 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -111,6 +111,8 @@ #define SUN6I_YEAR_MIN 1970 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) =20 +#define SECS_PER_DAY (24 * 3600ULL) + /* * There are other differences between models, including: * @@ -134,12 +136,15 @@ struct sun6i_rtc_clk_data { unsigned int has_auto_swt : 1; }; =20 +#define RTC_LINEAR_DAY BIT(0) + struct sun6i_rtc_dev { struct rtc_device *rtc; const struct sun6i_rtc_clk_data *data; void __iomem *base; int irq; time64_t alarm; + unsigned long flags; =20 struct clk_hw hw; struct clk_hw *int_osc; @@ -468,22 +473,30 @@ static int sun6i_rtc_gettime(struct device *dev, stru= ct rtc_time *rtc_tm) } while ((date !=3D readl(chip->base + SUN6I_RTC_YMD)) || (time !=3D readl(chip->base + SUN6I_RTC_HMS))); =20 + if (chip->flags & RTC_LINEAR_DAY) { + /* + * Newer chips store a linear day number, the manual + * does not mandate any epoch base. The BSP driver uses + * the UNIX epoch, let's just copy that, as it's the + * easiest anyway. + */ + rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); + } else { + rtc_tm->tm_mday =3D SUN6I_DATE_GET_DAY_VALUE(date); + rtc_tm->tm_mon =3D SUN6I_DATE_GET_MON_VALUE(date) - 1; + rtc_tm->tm_year =3D SUN6I_DATE_GET_YEAR_VALUE(date); + + /* + * switch from (data_year->min)-relative offset to + * a (1900)-relative one + */ + rtc_tm->tm_year +=3D SUN6I_YEAR_OFF; + } + rtc_tm->tm_sec =3D SUN6I_TIME_GET_SEC_VALUE(time); rtc_tm->tm_min =3D SUN6I_TIME_GET_MIN_VALUE(time); rtc_tm->tm_hour =3D SUN6I_TIME_GET_HOUR_VALUE(time); =20 - rtc_tm->tm_mday =3D SUN6I_DATE_GET_DAY_VALUE(date); - rtc_tm->tm_mon =3D SUN6I_DATE_GET_MON_VALUE(date); - rtc_tm->tm_year =3D SUN6I_DATE_GET_YEAR_VALUE(date); - - rtc_tm->tm_mon -=3D 1; - - /* - * switch from (data_year->min)-relative offset to - * a (1900)-relative one - */ - rtc_tm->tm_year +=3D SUN6I_YEAR_OFF; - return 0; } =20 @@ -568,20 +581,25 @@ static int sun6i_rtc_settime(struct device *dev, stru= ct rtc_time *rtc_tm) u32 date =3D 0; u32 time =3D 0; =20 - rtc_tm->tm_year -=3D SUN6I_YEAR_OFF; - rtc_tm->tm_mon +=3D 1; - - date =3D SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | - SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | - SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); - - if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) - date |=3D SUN6I_LEAP_SET_VALUE(1); - time =3D SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); =20 + if (chip->flags & RTC_LINEAR_DAY) { + /* The division will cut off the H:M:S part of rtc_tm. */ + date =3D div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); + } else { + rtc_tm->tm_year -=3D SUN6I_YEAR_OFF; + rtc_tm->tm_mon +=3D 1; + + date =3D SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | + SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | + SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); + + if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) + date |=3D SUN6I_LEAP_SET_VALUE(1); + } + /* Check whether registers are writable */ if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, SUN6I_LOSC_CTRL_ACC_MASK, 50)) { @@ -714,6 +732,8 @@ static int sun6i_rtc_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, chip); =20 + chip->flags =3D (unsigned long)of_device_get_match_data(&pdev->dev); + chip->irq =3D platform_get_irq(pdev, 0); if (chip->irq < 0) return chip->irq; @@ -760,7 +780,10 @@ static int sun6i_rtc_probe(struct platform_device *pde= v) return PTR_ERR(chip->rtc); =20 chip->rtc->ops =3D &sun6i_rtc_ops; - chip->rtc->range_max =3D 2019686399LL; /* 2033-12-31 23:59:59 */ + if (chip->flags & RTC_LINEAR_DAY) + chip->rtc->range_max =3D (65536 * SECS_PER_DAY) - 1; + else + chip->rtc->range_max =3D 2019686399LL; /* 2033-12-31 23:59:59 */ =20 ret =3D devm_rtc_register_device(chip->rtc); if (ret) --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CBDFC433FE for ; Fri, 11 Feb 2022 12:27:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344109AbiBKM1K (ORCPT ); Fri, 11 Feb 2022 07:27:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349995AbiBKM1B (ORCPT ); Fri, 11 Feb 2022 07:27:01 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 64AAFF65; Fri, 11 Feb 2022 04:26:59 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 33B1711D4; Fri, 11 Feb 2022 04:26:59 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C5C93F70D; Fri, 11 Feb 2022 04:26:57 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Alessandro Zummo , Alexandre Belloni , linux-rtc@vger.kernel.org Subject: [PATCH v10 05/18] rtc: sun6i: Add support for broken-down alarm registers Date: Fri, 11 Feb 2022 12:26:30 +0000 Message-Id: <20220211122643.1343315-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer versions of the Allwinner RTC, for instance as found in the H616 SoC, not only store the current day as a linear number, but also change the way the alarm is handled: There are now two registers, that explicitly store the wakeup time, in the same format as the current time. Add support for that variant by writing the requested wakeup time directly into the registers, instead of programming the seconds left, as the old SoCs required. Signed-off-by: Andre Przywara Reviewed by: Jernej Skrabec --- drivers/rtc/rtc-sun6i.c | 57 +++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 996d05938839..799d98ee6df6 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -49,7 +49,8 @@ =20 /* Alarm 0 (counter) */ #define SUN6I_ALRM_COUNTER 0x0020 -#define SUN6I_ALRM_CUR_VAL 0x0024 +/* This holds the remaining alarm seconds on older SoCs (current value) */ +#define SUN6I_ALRM_COUNTER_HMS 0x0024 #define SUN6I_ALRM_EN 0x0028 #define SUN6I_ALRM_EN_CNT_EN BIT(0) #define SUN6I_ALRM_IRQ_EN 0x002c @@ -524,32 +525,54 @@ static int sun6i_rtc_setalarm(struct device *dev, str= uct rtc_wkalrm *wkalrm) struct sun6i_rtc_dev *chip =3D dev_get_drvdata(dev); struct rtc_time *alrm_tm =3D &wkalrm->time; struct rtc_time tm_now; - time64_t time_now, time_set; + time64_t time_set; + u32 counter_val, counter_val_hms; int ret; =20 - ret =3D sun6i_rtc_gettime(dev, &tm_now); - if (ret < 0) { - dev_err(dev, "Error in getting time\n"); - return -EINVAL; - } - time_set =3D rtc_tm_to_time64(alrm_tm); - time_now =3D rtc_tm_to_time64(&tm_now); - if (time_set <=3D time_now) { - dev_err(dev, "Date to set in the past\n"); - return -EINVAL; - } =20 - if ((time_set - time_now) > U32_MAX) { - dev_err(dev, "Date too far in the future\n"); - return -EINVAL; + if (chip->flags & RTC_LINEAR_DAY) { + /* + * The alarm registers hold the actual alarm time, encoded + * in the same way (linear day + HMS) as the current time. + */ + counter_val_hms =3D SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | + SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | + SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); + /* The division will cut off the H:M:S part of alrm_tm. */ + counter_val =3D div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); + } else { + /* The alarm register holds the number of seconds left. */ + time64_t time_now; + + ret =3D sun6i_rtc_gettime(dev, &tm_now); + if (ret < 0) { + dev_err(dev, "Error in getting time\n"); + return -EINVAL; + } + + time_now =3D rtc_tm_to_time64(&tm_now); + if (time_set <=3D time_now) { + dev_err(dev, "Date to set in the past\n"); + return -EINVAL; + } + if ((time_set - time_now) > U32_MAX) { + dev_err(dev, "Date too far in the future\n"); + return -EINVAL; + } + + counter_val =3D time_set - time_now; } =20 sun6i_rtc_setaie(0, chip); writel(0, chip->base + SUN6I_ALRM_COUNTER); + if (chip->flags & RTC_LINEAR_DAY) + writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); usleep_range(100, 300); =20 - writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER); + writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); + if (chip->flags & RTC_LINEAR_DAY) + writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); chip->alarm =3D time_set; =20 sun6i_rtc_setaie(wkalrm->enabled, chip); --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CF95C433FE for ; Fri, 11 Feb 2022 12:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350051AbiBKM1N (ORCPT ); Fri, 11 Feb 2022 07:27:13 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350006AbiBKM1B (ORCPT ); Fri, 11 Feb 2022 07:27:01 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4C799F28; Fri, 11 Feb 2022 04:27:01 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1A9AD1477; Fri, 11 Feb 2022 04:27:01 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 655FD3F70D; Fri, 11 Feb 2022 04:26:59 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Alessandro Zummo , Alexandre Belloni , linux-rtc@vger.kernel.org Subject: [PATCH v10 06/18] rtc: sun6i: Add Allwinner H616 support Date: Fri, 11 Feb 2022 12:26:31 +0000 Message-Id: <20220211122643.1343315-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The H616 RTC changes its day storage to the newly introduced linear day scheme, so pair the new compatible string with this feature flag. The RTC clock parts are handled in a separate driver now, so we skip the clock parts in this driver completely. Signed-off-by: Andre Przywara --- drivers/rtc/rtc-sun6i.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 799d98ee6df6..5252ce4cbda4 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -831,6 +831,8 @@ static const struct of_device_id sun6i_rtc_dt_ids[] =3D= { { .compatible =3D "allwinner,sun8i-v3-rtc" }, { .compatible =3D "allwinner,sun50i-h5-rtc" }, { .compatible =3D "allwinner,sun50i-h6-rtc" }, + { .compatible =3D "allwinner,sun50i-h616-rtc", + .data =3D (void *)RTC_LINEAR_DAY }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11D1BC433F5 for ; Fri, 11 Feb 2022 12:27:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350057AbiBKM1S (ORCPT ); Fri, 11 Feb 2022 07:27:18 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242921AbiBKM1E (ORCPT ); Fri, 11 Feb 2022 07:27:04 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1DBE7F50; Fri, 11 Feb 2022 04:27:03 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E11ED139F; Fri, 11 Feb 2022 04:27:02 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4C0D93F70D; Fri, 11 Feb 2022 04:27:01 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 07/18] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Date: Fri, 11 Feb 2022 12:26:32 +0000 Message-Id: <20220211122643.1343315-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This (relatively) new SoC is similar to the H6, but drops the (broken) PCIe support and the USB 3.0 controller. It also gets the management controller removed, which in turn removes *some*, but not all of the devices formerly dedicated to the ARISC (CPUS). And while there is still the extra sunxi interrupt controller, the package lacks the corresponding NMI pin, so no interrupts for the PMIC. The reserved memory node is actually handled by Trusted Firmware now, but U-Boot fails to propagate this to a separately loaded DTB, so we keep it in here for now, until U-Boot learns to do this properly. Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 574 ++++++++++++++++++ 1 file changed, 574 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi new file mode 100644 index 000000000000..cc06cdd15ba5 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Arm Ltd. +// based on the H6 dtsi, which is: +// Copyright (C) 2017 Icenowy Zheng + +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <0>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <1>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <2>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <3>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 512KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@40000000 { + reg =3D <0x0 0x40000000 0x0 0x80000>; + no-map; + }; + }; + + osc24M: osc24M-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc24M"; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts =3D , + , + , + ; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x40000000>; + + syscon: syscon@3000000 { + compatible =3D "allwinner,sun50i-h616-system-control"; + reg =3D <0x03000000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + sram_c: sram@28000 { + compatible =3D "mmio-sram"; + reg =3D <0x00028000 0x30000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x00028000 0x30000>; + }; + }; + + ccu: clock@3001000 { + compatible =3D "allwinner,sun50i-h616-ccu"; + reg =3D <0x03001000 0x1000>; + clocks =3D <&osc24M>, <&rtc 0>, <&rtc 2>; + clock-names =3D "hosc", "losc", "iosc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + watchdog: watchdog@30090a0 { + compatible =3D "allwinner,sun50i-h616-wdt", + "allwinner,sun6i-a31-wdt"; + reg =3D <0x030090a0 0x20>; + interrupts =3D ; + clocks =3D <&osc24M>; + }; + + pio: pinctrl@300b000 { + compatible =3D "allwinner,sun50i-h616-pinctrl"; + reg =3D <0x0300b000 0x400>; + interrupts =3D , + , + , + , + , + , + , + ; + clocks =3D <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + ext_rgmii_pins: rgmii-pins { + pins =3D "PI0", "PI1", "PI2", "PI3", "PI4", + "PI5", "PI7", "PI8", "PI9", "PI10", + "PI11", "PI12", "PI13", "PI14", "PI15", + "PI16"; + function =3D "emac0"; + drive-strength =3D <40>; + }; + + i2c0_pins: i2c0-pins { + pins =3D "PI6", "PI7"; + function =3D "i2c0"; + }; + + i2c3_ph_pins: i2c3-ph-pins { + pins =3D "PH4", "PH5"; + function =3D "i2c3"; + }; + + ir_rx_pin: ir-rx-pin { + pins =3D "PH10"; + function =3D "ir_rx"; + }; + + mmc0_pins: mmc0-pins { + pins =3D "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function =3D "mmc0"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins =3D "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function =3D "mmc1"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins =3D "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function =3D "mmc2"; + drive-strength =3D <30>; + bias-pull-up; + }; + + spi0_pins: spi0-pins { + pins =3D "PC0", "PC2", "PC3", "PC4"; + function =3D "spi0"; + }; + + spi1_pins: spi1-pins { + pins =3D "PH6", "PH7", "PH8"; + function =3D "spi1"; + }; + + spi1_cs_pin: spi1-cs-pin { + pins =3D "PH5"; + function =3D "spi1"; + }; + + uart0_ph_pins: uart0-ph-pins { + pins =3D "PH0", "PH1"; + function =3D "uart0"; + }; + + uart1_pins: uart1-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + }; + + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + }; + }; + + gic: interrupt-controller@3021000 { + compatible =3D "arm,gic-400"; + reg =3D <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins>; + status =3D "disabled"; + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun50i-h616-emmc", + "allwinner,sun50i-a100-emmc"; + reg =3D <0x04022000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc2_pins>; + status =3D "disabled"; + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + uart0: serial@5000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + status =3D "disabled"; + }; + + uart1: serial@5000400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + status =3D "disabled"; + }; + + uart2: serial@5000800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000800 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + status =3D "disabled"; + }; + + uart3: serial@5000c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000c00 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + status =3D "disabled"; + }; + + uart4: serial@5001000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05001000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART4>; + resets =3D <&ccu RST_BUS_UART4>; + status =3D "disabled"; + }; + + uart5: serial@5001400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05001400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART5>; + resets =3D <&ccu RST_BUS_UART5>; + status =3D "disabled"; + }; + + i2c0: i2c@5002000 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c@5002400 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c@5002800 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3: i2c@5002c00 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002c00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C3>; + resets =3D <&ccu RST_BUS_I2C3>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4: i2c@5003000 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05003000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C4>; + resets =3D <&ccu RST_BUS_I2C4>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi0: spi@5010000 { + compatible =3D "allwinner,sun50i-h616-spi", + "allwinner,sun8i-h3-spi"; + reg =3D <0x05010000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names =3D "ahb", "mod"; + resets =3D <&ccu RST_BUS_SPI0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi1: spi@5011000 { + compatible =3D "allwinner,sun50i-h616-spi", + "allwinner,sun8i-h3-spi"; + reg =3D <0x05011000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names =3D "ahb", "mod"; + resets =3D <&ccu RST_BUS_SPI1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + emac0: ethernet@5020000 { + compatible =3D "allwinner,sun50i-h616-emac", + "allwinner,sun50i-a64-emac"; + syscon =3D <&syscon>; + reg =3D <0x05020000 0x10000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + resets =3D <&ccu RST_BUS_EMAC0>; + reset-names =3D "stmmaceth"; + clocks =3D <&ccu CLK_BUS_EMAC0>; + clock-names =3D "stmmaceth"; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + rtc: rtc@7000000 { + compatible =3D "allwinner,sun50i-h616-rtc"; + reg =3D <0x07000000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, + <&ccu CLK_PLL_SYSTEM_32K>; + clock-names =3D "bus", "hosc", + "pll-32k"; + clock-output-names =3D "osc32k", "osc32k-out", "iosc"; + #clock-cells =3D <1>; + }; + + r_ccu: clock@7010000 { + compatible =3D "allwinner,sun50i-h616-r-ccu"; + reg =3D <0x07010000 0x210>; + clocks =3D <&osc24M>, <&rtc 0>, <&rtc 2>, + <&ccu CLK_PLL_PERIPH0>; + clock-names =3D "hosc", "losc", "iosc", "pll-periph"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + r_pio: pinctrl@7022000 { + compatible =3D "allwinner,sun50i-h616-r-pinctrl"; + reg =3D <0x07022000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + r_i2c_pins: r-i2c-pins { + pins =3D "PL0", "PL1"; + function =3D "s_i2c"; + }; + + r_rsb_pins: r-rsb-pins { + pins =3D "PL0", "PL1"; + function =3D "s_rsb"; + }; + }; + + ir: ir@7040000 { + compatible =3D "allwinner,sun50i-h616-ir", + "allwinner,sun6i-a31-ir"; + reg =3D <0x07040000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names =3D "apb", "ir"; + resets =3D <&r_ccu RST_R_APB1_IR>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ir_rx_pin>; + status =3D "disabled"; + }; + + r_i2c: i2c@7081400 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x07081400 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB2_I2C>; + resets =3D <&r_ccu RST_R_APB2_I2C>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + r_rsb: rsb@7083000 { + compatible =3D "allwinner,sun50i-h616-rsb", + "allwinner,sun8i-a23-rsb"; + reg =3D <0x07083000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB2_RSB>; + clock-frequency =3D <3000000>; + resets =3D <&r_ccu RST_R_APB2_RSB>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r_rsb_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25E3AC433F5 for ; Fri, 11 Feb 2022 12:27:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350059AbiBKM1V (ORCPT ); Fri, 11 Feb 2022 07:27:21 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350019AbiBKM1F (ORCPT ); Fri, 11 Feb 2022 07:27:05 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CB11DF57; Fri, 11 Feb 2022 04:27:04 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A2711509; Fri, 11 Feb 2022 04:27:04 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1E7A03F70D; Fri, 11 Feb 2022 04:27:03 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 08/18] dt-bindings: arm: sunxi: Add two H616 board compatible strings Date: Fri, 11 Feb 2022 12:26:33 +0000 Message-Id: <20220211122643.1343315-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Andre Przywara Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index c8a3102c0fde..185ced5da6b8 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -853,6 +853,11 @@ properties: - const: yones-toptech,bs1078-v2 - const: allwinner,sun6i-a31s =20 + - description: X96 Mate TV box + items: + - const: hechuang,x96-mate + - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -953,4 +958,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 =20 + - description: Xunlong OrangePi Zero 2 + items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 061C9C433FE for ; Fri, 11 Feb 2022 12:27:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350006AbiBKM10 (ORCPT ); Fri, 11 Feb 2022 07:27:26 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350032AbiBKM1I (ORCPT ); Fri, 11 Feb 2022 07:27:08 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 975DDF50; Fri, 11 Feb 2022 04:27:06 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59D70139F; Fri, 11 Feb 2022 04:27:06 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CD3C23F70D; Fri, 11 Feb 2022 04:27:04 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 09/18] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Date: Fri, 11 Feb 2022 12:26:34 +0000 Message-Id: <20220211122643.1343315-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The OrangePi Zero 2 is a development board with the new H616 SoC. It comes with the following features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 512MiB/1GiB DDR3 DRAM - AXP305 PMIC - Raspberry-Pi-1 compatible GPIO header - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports - 1 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - on-board 2MiB bootable SPI NOR flash - 1Gbps Ethernet port (via RTL8211F PHY) - micro-HDMI port - unsupported Allwinner WiFi/BT chip For more details see: https://linux-sunxi.org/Orange_Pi_Zero_2 Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-h616-orangepi-zero2.dts | 203 ++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero= 2.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 8fa5c060a4fe..df2214e6d946 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6-mini.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b= /arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts new file mode 100644 index 000000000000..ca07cae698ce --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + model =3D "OrangePi Zero2"; + compatible =3D "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; + + aliases { + ethernet0 =3D &emac0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + function =3D LED_FUNCTION_POWER; + color =3D ; + gpios =3D <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state =3D "on"; + }; + + led-1 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&emac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ext_rgmii_pins>; + phy-mode =3D "rgmii"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_dcdce>; + allwinner,rx-delay-ps =3D <3100>; + allwinner,tx-delay-ps =3D <700>; + status =3D "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + vmmc-supply =3D <®_dcdce>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&r_rsb { + status =3D "okay"; + + axp305: pmic@745 { + compatible =3D "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells =3D <1>; + reg =3D <0x745>; + + x-powers,self-working-mode; + vina-supply =3D <®_vcc5v>; + vinb-supply =3D <®_vcc5v>; + vinc-supply =3D <®_vcc5v>; + vind-supply =3D <®_vcc5v>; + vine-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-sys"; + }; + + reg_aldo2: aldo2 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext"; + }; + + reg_aldo3: aldo3 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext2"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8"; + }; + + bldo2 { + /* unused */ + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + /* reserved */ + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1080000>; + regulator-name =3D "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1080000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&spi0 { + status =3D "okay"; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_ph_pins>; + status =3D "okay"; +}; --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EAC2C433FE for ; Fri, 11 Feb 2022 12:27:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347239AbiBKM1b (ORCPT ); Fri, 11 Feb 2022 07:27:31 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350036AbiBKM1J (ORCPT ); Fri, 11 Feb 2022 07:27:09 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 42553E77; Fri, 11 Feb 2022 04:27:08 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 112BA13D5; Fri, 11 Feb 2022 04:27:08 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 874E13F70D; Fri, 11 Feb 2022 04:27:06 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 10/18] arm64: dts: allwinner: h616: Add X96 Mate TV box support Date: Fri, 11 Feb 2022 12:26:35 +0000 Message-Id: <20220211122643.1343315-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The X96 Mate is an Allwinner H616 based TV box, featuring: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 2GiB/4GiB RAM (fully usable!) - 16/32/64GiB eMMC - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported) - Unsupported Allwinner WiFi chip - 2 x USB 2.0 host ports - HDMI port - IR receiver - 5V/2A DC power supply via barrel plug For more information see: https://linux-sunxi.org/X96_Mate Add a basic devicetree for it, with SD card and eMMC working, as well as serial and the essential peripherals, like the AXP PMIC. This DT is somewhat minimal, and should work on many other similar TV boxes with the Allwinner H616 chip. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++ 2 files changed, 178 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index df2214e6d946..6a96494a2e0a 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-pine-h64-model-b.= dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-orangepi-zero2.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-x96-mate.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/= arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts new file mode 100644 index 000000000000..aedb3a3dff38 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2021 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include + +/ { + model =3D "X96 Mate"; + compatible =3D "hechuang,x96-mate", "allwinner,sun50i-h616"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&ir { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_dcdce>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&mmc2 { + vmmc-supply =3D <®_dcdce>; + vqmmc-supply =3D <®_bldo1>; + bus-width =3D <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; + +&r_rsb { + status =3D "okay"; + + axp305: pmic@745 { + compatible =3D "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells =3D <1>; + reg =3D <0x745>; + + x-powers,self-working-mode; + vina-supply =3D <®_vcc5v>; + vinb-supply =3D <®_vcc5v>; + vinc-supply =3D <®_vcc5v>; + vind-supply =3D <®_vcc5v>; + vine-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-sys"; + }; + + /* Enabled by the Android BSP */ + reg_aldo2: aldo2 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext"; + status =3D "disabled"; + }; + + /* Enabled by the Android BSP */ + reg_aldo3: aldo3 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext2"; + status =3D "disabled"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8"; + }; + + /* Enabled by the Android BSP */ + reg_bldo2: bldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8-2"; + status =3D "disabled"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-name =3D "vcc2v5"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1080000>; + regulator-name =3D "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1080000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt =3D <1360000>; + regulator-max-microvolt =3D <1360000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_ph_pins>; + status =3D "okay"; +}; --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDDA6C43219 for ; Fri, 11 Feb 2022 12:27:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350073AbiBKM13 (ORCPT ); Fri, 11 Feb 2022 07:27:29 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350046AbiBKM1K (ORCPT ); Fri, 11 Feb 2022 07:27:10 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EA0C4F63; Fri, 11 Feb 2022 04:27:09 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9FC2139F; Fri, 11 Feb 2022 04:27:09 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 428DF3F70D; Fri, 11 Feb 2022 04:27:08 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 11/18] dt-bindings: usb: Add H616 compatible string Date: Fri, 11 Feb 2022 12:26:36 +0000 Message-Id: <20220211122643.1343315-12-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Allwinner H616 contains four fully OHCI/EHCI compatible USB host controllers, so just add their compatible strings to the list of generic OHCI/EHCI controllers. Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ehci.yaml index 8913497624de..f4fab05f60dd 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -30,6 +30,7 @@ properties: - allwinner,sun4i-a10-ehci - allwinner,sun50i-a64-ehci - allwinner,sun50i-h6-ehci + - allwinner,sun50i-h616-ehci - allwinner,sun5i-a13-ehci - allwinner,sun6i-a31-ehci - allwinner,sun7i-a20-ehci diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ohci.yaml index acbf94fa5f74..d27e113b2e00 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -20,6 +20,7 @@ properties: - allwinner,sun4i-a10-ohci - allwinner,sun50i-a64-ohci - allwinner,sun50i-h6-ohci + - allwinner,sun50i-h616-ohci - allwinner,sun5i-a13-ohci - allwinner,sun6i-a31-ohci - allwinner,sun7i-a20-ohci --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96598C433F5 for ; Fri, 11 Feb 2022 12:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350089AbiBKM1d (ORCPT ); Fri, 11 Feb 2022 07:27:33 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350045AbiBKM1N (ORCPT ); Fri, 11 Feb 2022 07:27:13 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D084CF50 for ; Fri, 11 Feb 2022 04:27:11 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E46813D5; Fri, 11 Feb 2022 04:27:11 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EA7F23F70D; Fri, 11 Feb 2022 04:27:09 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Vinod Koul , linux-phy@lists.infradead.org Subject: [PATCH v10 12/18] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Date: Fri, 11 Feb 2022 12:26:37 +0000 Message-Id: <20220211122643.1343315-13-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Tested-by: Samuel Holland --- drivers/phy/allwinner/phy-sun4i-usb.c | 30 ++++++++++++--------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/= phy-sun4i-usb.c index 788dd5cdbb7d..142f4cafdc78 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -43,7 +43,7 @@ #define REG_PHYCTL_A33 0x10 #define REG_PHY_OTGCTL 0x20 =20 -#define REG_PMU_UNK1 0x10 +#define REG_HCI_PHY_CTL 0x10 =20 #define PHYCTL_DATA BIT(7) =20 @@ -82,6 +82,7 @@ /* A83T specific control bits for PHY0 */ #define PHY_CTL_VBUSVLDEXT BIT(5) #define PHY_CTL_SIDDQ BIT(3) +#define PHY_CTL_H3_SIDDQ BIT(1) =20 /* A83T specific control bits for PHY2 HSIC */ #define SUNXI_EHCI_HS_FORCE BIT(20) @@ -115,9 +116,9 @@ struct sun4i_usb_phy_cfg { int hsic_index; enum sun4i_usb_phy_type type; u32 disc_thresh; + u32 hci_phy_ctl_clear; u8 phyctl_offset; bool dedicated_clocks; - bool enable_pmu_unk1; bool phy0_dual_route; int missing_phys; }; @@ -288,6 +289,12 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } =20 + if (phy->pmu && data->cfg->hci_phy_ctl_clear) { + val =3D readl(phy->pmu + REG_HCI_PHY_CTL); + val &=3D ~data->cfg->hci_phy_ctl_clear; + writel(val, phy->pmu + REG_HCI_PHY_CTL); + } + if (data->cfg->type =3D=3D sun8i_a83t_phy || data->cfg->type =3D=3D sun50i_h6_phy) { if (phy->index =3D=3D 0) { @@ -297,11 +304,6 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, data->base + data->cfg->phyctl_offset); } } else { - if (phy->pmu && data->cfg->enable_pmu_unk1) { - val =3D readl(phy->pmu + REG_PMU_UNK1); - writel(val & ~2, phy->pmu + REG_PMU_UNK1); - } - /* Enable USB 45 Ohm resistor calibration */ if (phy->index =3D=3D 0) sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); @@ -863,7 +865,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg =3D= { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A10, .dedicated_clocks =3D false, - .enable_pmu_unk1 =3D false, }; =20 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg =3D { @@ -872,7 +873,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg =3D= { .disc_thresh =3D 2, .phyctl_offset =3D REG_PHYCTL_A10, .dedicated_clocks =3D false, - .enable_pmu_unk1 =3D false, }; =20 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg =3D { @@ -881,7 +881,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg =3D= { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A10, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D false, }; =20 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg =3D { @@ -890,7 +889,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg =3D= { .disc_thresh =3D 2, .phyctl_offset =3D REG_PHYCTL_A10, .dedicated_clocks =3D false, - .enable_pmu_unk1 =3D false, }; =20 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg =3D { @@ -899,7 +897,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg =3D= { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A10, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D false, }; =20 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg =3D { @@ -908,7 +905,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg =3D= { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A33, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D false, }; =20 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg =3D { @@ -925,7 +921,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg =3D { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A33, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D true, + .hci_phy_ctl_clear =3D PHY_CTL_H3_SIDDQ, .phy0_dual_route =3D true, }; =20 @@ -935,7 +931,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg =3D= { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A33, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D true, + .hci_phy_ctl_clear =3D PHY_CTL_H3_SIDDQ, .phy0_dual_route =3D true, }; =20 @@ -945,7 +941,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg =3D= { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A33, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D true, + .hci_phy_ctl_clear =3D PHY_CTL_H3_SIDDQ, .phy0_dual_route =3D true, }; =20 @@ -955,7 +951,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = =3D { .disc_thresh =3D 3, .phyctl_offset =3D REG_PHYCTL_A33, .dedicated_clocks =3D true, - .enable_pmu_unk1 =3D true, + .hci_phy_ctl_clear =3D PHY_CTL_H3_SIDDQ, .phy0_dual_route =3D true, }; =20 --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2C61C433F5 for ; Fri, 11 Feb 2022 12:27:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350095AbiBKM1g (ORCPT ); Fri, 11 Feb 2022 07:27:36 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242867AbiBKM1O (ORCPT ); Fri, 11 Feb 2022 07:27:14 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CC2EFF28 for ; Fri, 11 Feb 2022 04:27:13 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9BCFA1476; Fri, 11 Feb 2022 04:27:13 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF1703F70D; Fri, 11 Feb 2022 04:27:11 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Vinod Koul , linux-phy@lists.infradead.org, Philipp Zabel Subject: [PATCH v10 13/18] phy: sun4i-usb: Allow reset line to be shared Date: Fri, 11 Feb 2022 12:26:38 +0000 Message-Id: <20220211122643.1343315-14-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The USB HCIs (and PHYs?) in Allwinner's newer generation SoCs (H616) rely on the reset line of USB PHY 2 to be de-asserted, even when only one of the other PHYs is actually in use. To make those ports work, we include this reset line in the HCIs' resets property, which requires this line to be shareable. Change the call to allocate the reset line to mark it as shared, to enable the other ports on those SoCs. Signed-off-by: Andre Przywara Reviewed-by: Philipp Zabel Acked-by: Samuel Holland --- drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/= phy-sun4i-usb.c index 142f4cafdc78..126ef74d013c 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -788,7 +788,7 @@ static int sun4i_usb_phy_probe(struct platform_device *= pdev) } =20 snprintf(name, sizeof(name), "usb%d_reset", i); - phy->reset =3D devm_reset_control_get(dev, name); + phy->reset =3D devm_reset_control_get_shared(dev, name); if (IS_ERR(phy->reset)) { dev_err(dev, "failed to get reset %s\n", name); return PTR_ERR(phy->reset); --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4E91C433EF for ; Fri, 11 Feb 2022 12:27:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350101AbiBKM1i (ORCPT ); Fri, 11 Feb 2022 07:27:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345518AbiBKM1Q (ORCPT ); Fri, 11 Feb 2022 07:27:16 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B36F5F50 for ; Fri, 11 Feb 2022 04:27:15 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 836B814BF; Fri, 11 Feb 2022 04:27:15 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CDB823F70D; Fri, 11 Feb 2022 04:27:13 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Vinod Koul , linux-phy@lists.infradead.org Subject: [PATCH v10 14/18] phy: sun4i-usb: Introduce port2 SIDDQ quirk Date: Fri, 11 Feb 2022 12:26:39 +0000 Message-Id: <20220211122643.1343315-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" At least the Allwinner H616 SoC requires a weird quirk to make most USB PHYs work: Only port2 works out of the box, but all other ports need some help from this port2 to work correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in the PMU PHY control register needs to be cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... Instead of disguising this as some generic feature, do exactly that in our PHY init: If the quirk bit is set, and we initialise a PHY other than PHY2, ungate this one special clock, and clear the SIDDQ bit. We can pull in the other required clocks via the DT. Signed-off-by: Andre Przywara --- drivers/phy/allwinner/phy-sun4i-usb.c | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/= phy-sun4i-usb.c index 126ef74d013c..316ef5fca831 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -120,6 +120,7 @@ struct sun4i_usb_phy_cfg { u8 phyctl_offset; bool dedicated_clocks; bool phy0_dual_route; + bool needs_phy2_siddq; int missing_phys; }; =20 @@ -289,6 +290,50 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } =20 + /* Some PHYs on some SoCs need the help of PHY2 to work. */ + if (data->cfg->needs_phy2_siddq && phy->index !=3D 2) { + struct sun4i_usb_phy *phy2 =3D &data->phys[2]; + + ret =3D clk_prepare_enable(phy2->clk); + if (ret) { + reset_control_assert(phy->reset); + clk_disable_unprepare(phy->clk2); + clk_disable_unprepare(phy->clk); + return ret; + } + + ret =3D reset_control_deassert(phy2->reset); + if (ret) { + clk_disable_unprepare(phy2->clk); + reset_control_assert(phy->reset); + clk_disable_unprepare(phy->clk2); + clk_disable_unprepare(phy->clk); + return ret; + } + + /* + * This extra clock is just needed to access the + * REG_HCI_PHY_CTL PMU register for PHY2. + */ + ret =3D clk_prepare_enable(phy2->clk2); + if (ret) { + reset_control_assert(phy2->reset); + clk_disable_unprepare(phy2->clk); + reset_control_assert(phy->reset); + clk_disable_unprepare(phy->clk2); + clk_disable_unprepare(phy->clk); + return ret; + } + + if (phy2->pmu && data->cfg->hci_phy_ctl_clear) { + val =3D readl(phy2->pmu + REG_HCI_PHY_CTL); + val &=3D ~data->cfg->hci_phy_ctl_clear; + writel(val, phy2->pmu + REG_HCI_PHY_CTL); + } + + clk_disable_unprepare(phy->clk2); + } + if (phy->pmu && data->cfg->hci_phy_ctl_clear) { val =3D readl(phy->pmu + REG_HCI_PHY_CTL); val &=3D ~data->cfg->hci_phy_ctl_clear; @@ -354,6 +399,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy) data->phy0_init =3D false; } =20 + if (data->cfg->needs_phy2_siddq && phy->index !=3D 2) { + struct sun4i_usb_phy *phy2 =3D &data->phys[2]; + + clk_disable_unprepare(phy2->clk); + reset_control_assert(phy2->reset); + } + sun4i_usb_phy_passby(phy, 0); reset_control_assert(phy->reset); clk_disable_unprepare(phy->clk2); @@ -785,6 +837,13 @@ static int sun4i_usb_phy_probe(struct platform_device = *pdev) dev_err(dev, "failed to get clock %s\n", name); return PTR_ERR(phy->clk2); } + } else { + snprintf(name, sizeof(name), "pmu%d_clk", i); + phy->clk2 =3D devm_clk_get_optional(dev, name); + if (IS_ERR(phy->clk2)) { + dev_err(dev, "failed to get clock %s\n", name); + return PTR_ERR(phy->clk2); + } } =20 snprintf(name, sizeof(name), "usb%d_reset", i); --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52D50C433EF for ; Fri, 11 Feb 2022 12:27:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350104AbiBKM16 (ORCPT ); Fri, 11 Feb 2022 07:27:58 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350072AbiBKM1Y (ORCPT ); Fri, 11 Feb 2022 07:27:24 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A632CF6E for ; Fri, 11 Feb 2022 04:27:17 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 743DB150C; Fri, 11 Feb 2022 04:27:17 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B60303F70D; Fri, 11 Feb 2022 04:27:15 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Vinod Koul , linux-phy@lists.infradead.org Subject: [PATCH v10 15/18] phy: sun4i-usb: Add support for the H616 USB PHY Date: Fri, 11 Feb 2022 12:26:40 +0000 Message-Id: <20220211122643.1343315-16-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The USB PHY used in the Allwinner H616 SoC inherits some traits from its various predecessors: it has four full PHYs like the H3, needs some extra bits to be set like the H6, and puts SIDDQ on a different bit like the A100. Plus it needs this weird PHY2 quirk. Name all those properties in a new config struct and assign a new compatible name to it. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland --- drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/= phy-sun4i-usb.c index 316ef5fca831..85a9771280b7 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -1024,6 +1024,17 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = =3D { .missing_phys =3D BIT(1) | BIT(2), }; =20 +static const struct sun4i_usb_phy_cfg sun50i_h616_cfg =3D { + .num_phys =3D 4, + .type =3D sun50i_h6_phy, + .disc_thresh =3D 3, + .phyctl_offset =3D REG_PHYCTL_A33, + .dedicated_clocks =3D true, + .phy0_dual_route =3D true, + .hci_phy_ctl_clear =3D PHY_CTL_SIDDQ, + .needs_phy2_siddq =3D true, +}; + static const struct of_device_id sun4i_usb_phy_of_match[] =3D { { .compatible =3D "allwinner,sun4i-a10-usb-phy", .data =3D &sun4i_a10_cfg= }, { .compatible =3D "allwinner,sun5i-a13-usb-phy", .data =3D &sun5i_a13_cfg= }, @@ -1038,6 +1049,7 @@ static const struct of_device_id sun4i_usb_phy_of_mat= ch[] =3D { { .compatible =3D "allwinner,sun50i-a64-usb-phy", .data =3D &sun50i_a64_cfg}, { .compatible =3D "allwinner,sun50i-h6-usb-phy", .data =3D &sun50i_h6_cfg= }, + { .compatible =3D "allwinner,sun50i-h616-usb-phy", .data =3D &sun50i_h616= _cfg }, { }, }; MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE906C433F5 for ; Fri, 11 Feb 2022 12:27:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350142AbiBKM1u (ORCPT ); Fri, 11 Feb 2022 07:27:50 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350054AbiBKM1Z (ORCPT ); Fri, 11 Feb 2022 07:27:25 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 63419F7B; Fri, 11 Feb 2022 04:27:19 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32FA4139F; Fri, 11 Feb 2022 04:27:19 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A79B53F70D; Fri, 11 Feb 2022 04:27:17 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 16/18] arm64: dts: allwinner: h616: Add USB nodes Date: Fri, 11 Feb 2022 12:26:41 +0000 Message-Id: <20220211122643.1343315-17-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the nodes for the MUSB and the four USB host controllers to the SoC .dtsi, along with the PHY node needed to bind all of them together. EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires some quirks (handled in the driver). Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi index cc06cdd15ba5..bf27ad1890cb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -486,6 +486,166 @@ mdio0: mdio { }; }; =20 + usbotg: usb@5100000 { + compatible =3D "allwinner,sun50i-h616-musb", + "allwinner,sun8i-h3-musb"; + reg =3D <0x05100000 0x0400>; + clocks =3D <&ccu CLK_BUS_OTG>; + resets =3D <&ccu RST_BUS_OTG>; + interrupts =3D ; + interrupt-names =3D "mc"; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + extcon =3D <&usbphy 0>; + status =3D "disabled"; + }; + + usbphy: phy@5100400 { + compatible =3D "allwinner,sun50i-h616-usb-phy"; + reg =3D <0x05100400 0x24>, + <0x05101800 0x14>, + <0x05200800 0x14>, + <0x05310800 0x14>, + <0x05311800 0x14>; + reg-names =3D "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks =3D <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>, + <&ccu CLK_BUS_EHCI2>; + clock-names =3D "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy", + "pmu2_clk"; + resets =3D <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names =3D "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status =3D "disabled"; + #phy-cells =3D <1>; + }; + + ehci0: usb@5101000 { + compatible =3D "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg =3D <0x05101000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci0: usb@5101400 { + compatible =3D "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg =3D <0x05101400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci1: usb@5200000 { + compatible =3D "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg =3D <0x05200000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci1: usb@5200400 { + compatible =3D "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg =3D <0x05200400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci2: usb@5310000 { + compatible =3D "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg =3D <0x05310000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_BUS_EHCI2>, + <&ccu CLK_USB_OHCI2>; + resets =3D <&ccu RST_BUS_OHCI2>, + <&ccu RST_BUS_EHCI2>; + phys =3D <&usbphy 2>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci2: usb@5310400 { + compatible =3D "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg =3D <0x05310400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets =3D <&ccu RST_BUS_OHCI2>; + phys =3D <&usbphy 2>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci3: usb@5311000 { + compatible =3D "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg =3D <0x05311000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_BUS_EHCI3>, + <&ccu CLK_USB_OHCI3>; + resets =3D <&ccu RST_BUS_OHCI3>, + <&ccu RST_BUS_EHCI3>; + phys =3D <&usbphy 3>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci3: usb@5311400 { + compatible =3D "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg =3D <0x05311400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets =3D <&ccu RST_BUS_OHCI3>; + phys =3D <&usbphy 3>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + rtc: rtc@7000000 { compatible =3D "allwinner,sun50i-h616-rtc"; reg =3D <0x07000000 0x400>; --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5B22C433EF for ; Fri, 11 Feb 2022 12:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344888AbiBKM1z (ORCPT ); Fri, 11 Feb 2022 07:27:55 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244887AbiBKM1Z (ORCPT ); Fri, 11 Feb 2022 07:27:25 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 21839FC1; Fri, 11 Feb 2022 04:27:21 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E50CC1509; Fri, 11 Feb 2022 04:27:20 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 69A6F3F70D; Fri, 11 Feb 2022 04:27:19 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 17/18] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes Date: Fri, 11 Feb 2022 12:26:42 +0000 Message-Id: <20220211122643.1343315-18-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The OrangePi Zero 2 has one USB-A host port, VBUS is provided by a GPIO controlled regulator. The USB-C port is meant to power the board, but is also connected to the USB 0 port, which we configure as an MUSB peripheral. Signed-off-by: Andre Przywara --- .../allwinner/sun50i-h616-orangepi-zero2.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b= /arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index ca07cae698ce..a26201288872 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -49,8 +49,25 @@ reg_vcc5v: vcc5v { regulator-max-microvolt =3D <5000000>; regulator-always-on; }; + + reg_usb1_vbus: usb1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + enable-active-high; + gpio =3D <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + status =3D "okay"; + }; }; =20 +&ehci1 { + status =3D "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + &emac0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ext_rgmii_pins>; @@ -76,6 +93,10 @@ &mmc0 { status =3D "okay"; }; =20 +&ohci1 { + status =3D "okay"; +}; + &r_rsb { status =3D "okay"; =20 @@ -201,3 +222,24 @@ &uart0 { pinctrl-0 =3D <&uart0_ph_pins>; status =3D "okay"; }; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb1_vbus-supply =3D <®_usb1_vbus>; + status =3D "okay"; +}; --=20 2.25.1 From nobody Sun Jun 28 06:41:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF687C433F5 for ; Fri, 11 Feb 2022 12:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235611AbiBKM1s (ORCPT ); Fri, 11 Feb 2022 07:27:48 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350084AbiBKM1Z (ORCPT ); Fri, 11 Feb 2022 07:27:25 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CE118FC2; Fri, 11 Feb 2022 04:27:22 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9C8551515; Fri, 11 Feb 2022 04:27:22 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 20C303F70D; Fri, 11 Feb 2022 04:27:21 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Rob Herring , Ondrej Jirman , Icenowy Zheng , Samuel Holland , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v10 18/18] arm64: dts: allwinner: h616: X96 Mate: Add USB nodes Date: Fri, 11 Feb 2022 12:26:43 +0000 Message-Id: <20220211122643.1343315-19-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com> References: <20220211122643.1343315-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The X96 Mate TV box has two USB-A ports, VBUS is always on and connected to the DC input. Since USB port 0 is connected to an USB-A receptable, we configure it as a host port. Using it as a peripheral is dangerous, because VBUS is always on. Signed-off-by: Andre Przywara --- .../dts/allwinner/sun50i-h616-x96-mate.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/= arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts index aedb3a3dff38..5c3586717c00 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -32,6 +32,14 @@ reg_vcc5v: vcc5v { }; }; =20 +&ehci0 { + status =3D "okay"; +}; + +&ehci2 { + status =3D "okay"; +}; + &ir { status =3D "okay"; }; @@ -54,6 +62,14 @@ &mmc2 { status =3D "okay"; }; =20 +&ohci0 { + status =3D "okay"; +}; + +&ohci2 { + status =3D "okay"; +}; + &r_rsb { status =3D "okay"; =20 @@ -175,3 +191,12 @@ &uart0 { pinctrl-0 =3D <&uart0_ph_pins>; status =3D "okay"; }; + +&usbotg { + dr_mode =3D "host"; /* USB A type receptable */ + status =3D "okay"; +}; + +&usbphy { + status =3D "okay"; +}; --=20 2.25.1