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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:29 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 1/6] RISC-V: Correctly print supported extensions Date: Thu, 10 Feb 2022 13:40:13 -0800 Message-Id: <20220210214018.55739-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include =20 +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; =20 /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); --=20 2.30.2 From nobody Mon Jun 29 11:20:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FB53C433F5 for ; Thu, 10 Feb 2022 21:40:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344738AbiBJVkg (ORCPT ); Thu, 10 Feb 2022 16:40:36 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344714AbiBJVkc (ORCPT ); Thu, 10 Feb 2022 16:40:32 -0500 Received: from mail-oo1-xc2f.google.com (mail-oo1-xc2f.google.com [IPv6:2607:f8b0:4864:20::c2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD58C26C2 for ; Thu, 10 Feb 2022 13:40:32 -0800 (PST) Received: by mail-oo1-xc2f.google.com with SMTP id 189-20020a4a03c6000000b003179d7b30d8so8045939ooi.2 for ; Thu, 10 Feb 2022 13:40:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XxLurPe5gtmMACmwYrmQ7RV4VZQpgtW/wJpQ92EZaMA=; b=ZGAexjLB1fsWd1qu3I8dybz0nQgpssACPs0RnY+Wbrn6/mWSSoTmwXtMt9tNeO8Fkc 0I+n/5SG7WgyBJUEanBaXBjICX1pVeCelvfL/q4Xt/QFRo37bcM9/PxgLviQdD4zbMFl 5h58IG8lVAZ1J6bPIwLAp9BJ1/w8D8iX9uPpIWgrmAisAvF8kDTVY/Xx6EKmp+kqXapJ fs2it4qhJDundsIeMW62C6Djp0MgjOappTSv95/++s+Vlh1846suJzz2o+PBfhgkUTN7 iO9VjOWP46FjzScJjuh2v27wQaujMWU43ViE7bryqlB+xX/DBpouqO0D986eCoGCFBrP 0MWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XxLurPe5gtmMACmwYrmQ7RV4VZQpgtW/wJpQ92EZaMA=; b=Ippm+8rGwXd/wyhwTkylfL6yli3qcMoGN1eEASaZXNw9zsoQkDDYmFj15RO/W0pIXs 3WyMcf6pB6eVnqfr65jrITrubft9gHKl9WQN7Ck+3dTFdGbLxIHWZcwhB5YH9HuN68xP LY+EW/P5YPoOqIx+3KQHi5hSbb4PgsF3aFpbQH0Ci0khi074Ayai0GUs6ZKtx6TbIHsx bWndvlRkVAn0BVffouIm6u7aSMr1ugg0AIVxd0oOouRsBiKfle2rFU1EQvHj3XiSjdBZ HqdhRy9cd5vm7gzUOqMq+MdLbTX0+vTuqHLDxSZIyu/QHLD7rrVMkRppfjhujPe42HOG ZjdQ== X-Gm-Message-State: AOAM532gXSDnyhvRKFNM/1sc2RB8MwPFJNze1BWFI0U+GWX+yBY6KW7s XpjmFuBtyhPD/0wYHxqO05GC8ZG8W1fRlikA X-Google-Smtp-Source: ABdhPJwAVQp1nDJtdS+/A4GMweHMJUn2o2jysgwreocFk+ixOF7CGDbCRGXOrigMVd948zf4+Dd27g== X-Received: by 2002:a05:6870:5a8c:: with SMTP id dt12mr1460469oab.327.1644529232021; Thu, 10 Feb 2022 13:40:32 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 2/6] RISC-V: Minimal parser for "riscv, isa" strings Date: Thu, 10 Feb 2022 13:40:14 -0800 Message-Id: <20220210214018.55739-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. Signed-off-by: Tsukasa OI [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 67 ++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dd3d57eb4eea..e19ae4391a9b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; + int i, j; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -92,23 +93,67 @@ void __init riscv_fill_hwcap(void) continue; } =20 - i =3D 0; - isa_len =3D strlen(isa); #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) - i +=3D 4; + isa +=3D 4; #elif IS_ENABLED(CONFIG_64BIT) if (!strncmp(isa, "rv64", 4)) - i +=3D 4; + isa +=3D 4; #endif - for (; i < isa_len; ++i) { - this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + for (; *isa; ++isa) { + const char *ext =3D isa++; + bool ext_long, ext_err =3D false; + + switch (*ext) { + case 's': + case 'x': + case 'z': + /** + * 's' is a special case because: + * It can be present in base extension for supervisor + * Multi-letter extensions can start with 's' as well for + * Supervisor extensions (i.e. sstc, sscofpmf, svinval) + */ + if (*ext =3D=3D 's' && ext[-1] !=3D '_') + break; + ext_long =3D true; + /* Multi-letter extension must be delimited */ + for (; *isa && *isa !=3D '_'; ++isa) + if (!islower(*isa) && !isdigit(*isa)) + ext_err =3D true; + /* ... but must be ignored. */ + break; + default: + ext_long =3D false; + if (!islower(*ext)) { + ext_err =3D true; + break; + } + /* Find next extension */ + if (!isdigit(*isa)) + break; + while (isdigit(*++isa)) + ; + if (*isa !=3D 'p') + break; + if (!isdigit(*++isa)) { + --isa; + break; + } + while (isdigit(*++isa)) + ; + break; + } + if (*isa !=3D '_') + --isa; /* - * TODO: X, Y and Z extension parsing for Host ISA - * bitmap will be added in-future. + * TODO: Full version-aware handling including + * multi-letter extensions will be added in-future. */ - if ('a' <=3D isa[i] && isa[i] < 'x') - this_isa |=3D (1UL << (isa[i] - 'a')); + if (ext_err || ext_long) + continue; + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); } =20 /* --=20 2.30.2 From nobody Mon Jun 29 11:20:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD14FC433FE for ; Thu, 10 Feb 2022 21:40:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344736AbiBJVki (ORCPT ); Thu, 10 Feb 2022 16:40:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344720AbiBJVke (ORCPT ); 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:33 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 3/6] RISC-V: Extract multi-letter extension names from "riscv,isa" Date: Thu, 10 Feb 2022 13:40:15 -0800 Message-Id: <20220210214018.55739-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Signed-off-by: Tsukasa OI [Improved commit text and comments] Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e19ae4391a9b..e9e3b0693d16 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -102,6 +102,7 @@ void __init riscv_fill_hwcap(void) #endif for (; *isa; ++isa) { const char *ext =3D isa++; + const char *ext_end =3D isa; bool ext_long, ext_err =3D false; =20 switch (*ext) { @@ -119,19 +120,39 @@ void __init riscv_fill_hwcap(void) ext_long =3D true; /* Multi-letter extension must be delimited */ for (; *isa && *isa !=3D '_'; ++isa) - if (!islower(*isa) && !isdigit(*isa)) + if (unlikely(!islower(*isa) + && !isdigit(*isa))) ext_err =3D true; - /* ... but must be ignored. */ + /* Parse backwards */ + ext_end =3D isa; + if (unlikely(ext_err)) + break; + if (!isdigit(ext_end[-1])) + break; + /* Skip the minor version */ + while (isdigit(*--ext_end)) + ; + if (ext_end[0] !=3D 'p' + || !isdigit(ext_end[-1])) { + /* Advance it to offset the pre-decrement */ + ++ext_end; + break; + } + /* Skip the major version */ + while (isdigit(*--ext_end)) + ; + ++ext_end; break; default: ext_long =3D false; - if (!islower(*ext)) { + if (unlikely(!islower(*ext))) { ext_err =3D true; break; } /* Find next extension */ if (!isdigit(*isa)) break; + /* Skip the minor version */ while (isdigit(*++isa)) ; if (*isa !=3D 'p') @@ -140,20 +161,20 @@ void __init riscv_fill_hwcap(void) --isa; break; } + /* Skip the major version */ while (isdigit(*++isa)) ; break; } if (*isa !=3D '_') --isa; - /* - * TODO: Full version-aware handling including - * multi-letter extensions will be added in-future. - */ - if (ext_err || ext_long) + + if (unlikely(ext_err)) continue; - this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + if (!ext_long) { + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); + } } =20 /* --=20 2.30.2 From nobody Mon Jun 29 11:20:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 316DCC433F5 for ; Thu, 10 Feb 2022 21:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344753AbiBJVkm (ORCPT ); Thu, 10 Feb 2022 16:40:42 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344741AbiBJVkg (ORCPT ); Thu, 10 Feb 2022 16:40:36 -0500 Received: from mail-oo1-xc35.google.com (mail-oo1-xc35.google.com [IPv6:2607:f8b0:4864:20::c35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19CEC2734 for ; Thu, 10 Feb 2022 13:40:36 -0800 (PST) Received: by mail-oo1-xc35.google.com with SMTP id u47-20020a4a9732000000b00316d0257de0so8036097ooi.7 for ; Thu, 10 Feb 2022 13:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9HqpIlANdkOQKOXjwBjs8cYmBoShBh+rol5NQg2UHcQ=; b=sEIOgtn1hTncoRYD7rw8soECdhc+qTSuHFirYdgpmhgl11ZRxUmCTJqQVLp3uySO+W cWU9hHTcbrqdsckB4wBTllc/wKv00ME8JP7Kd53Mo4WiUozmQaHHnQ9cj3vRPUTSn/fF IlIOXfazff84lCs44cUF7H1kpTHRjy38zyayW8YKBIJYqZx9DwY2WvZTAi4uumZfvpcH z97M8iueKtbeA9mK57qbseZ9uMRuK3PMSfFtn/ytwtDFyxTVldrjOEscwCdZGImYqZGH s8YuADiDbhjizT4sb6v8MYxBmaDok5yNbwKiPCssHErMqICrXYMohrA7/oWN7P3RDraK g0Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9HqpIlANdkOQKOXjwBjs8cYmBoShBh+rol5NQg2UHcQ=; b=Jh6CE30cgis8GuVJ4fkRROOOZra+e8RJtU+yqEWL5PEjyso+ugVkW4DXFXeGHfaw7d tsHwqTfVrsL1BtO7u+gfhMXSnt1656iTOZWSint/oftOSDFU7wvvFMt/yLai5o50d0+c TnVGB/v91dVQUsKfe2pldPI1GC42UWc8TmmBnL3bN5P/OawjcIV+pUT5Day4+HK3Fgbb GCcC9jNrw4PVsmP5ksm4PhTeV9PsXMMGf11R71HET3B1vbjLcBEP2KPJ7kpm0VzxXxfp zMIXcGmh4evckNa+pAdUn5Mv5Q+HDkguMfmF2WTf5c5d7bFhFIpOtep4aYanLox/NmbW TqVA== X-Gm-Message-State: AOAM532jNYfUNEbyiE18vxf4v76qK5VTVQgPUEq4oEQd3iyrHb4FmFas 8RJBgdprbYoUP1L06eW0wZ7DoVls4XDgwiRx X-Google-Smtp-Source: ABdhPJwswvuwH8xTFr0UU7nRSK+wVt/HmmuoJ/He9mWLY9YbklssjC7cpvnAPAdYQwCb8VUFbiowSg== X-Received: by 2002:a05:6870:e495:: with SMTP id v21mr1423427oag.39.1644529235166; Thu, 10 Feb 2022 13:40:35 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:34 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 4/6] RISC-V: Implement multi-letter ISA extension probing framework Date: Thu, 10 Feb 2022 13:40:16 -0800 Message-Id: <20220210214018.55739-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 27 ++++++++++++++++++++++++--- 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..170bd80da520 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') =20 +/* + * Increse this to higher value as kernel support more ISA extensions. + */ #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +/* The base ID for multi-letter ISA extensions */ +#define RISCV_ISA_EXT_BASE 26 + +/* + * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter + * extensions while all the multi-letter extensions should define the next + * available logical extension id. + */ +enum riscv_isa_ext_id { + RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, +}; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e9e3b0693d16..469b9739faf7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) =20 for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; - unsigned long this_isa =3D 0; + uint64_t this_isa =3D 0; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -169,12 +169,22 @@ void __init riscv_fill_hwcap(void) if (*isa !=3D '_') --isa; =20 +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + this_isa |=3D (1UL << bit); \ + pr_info("Found ISA extension %s", name);\ + } \ + } while (false) \ + if (unlikely(ext_err)) continue; if (!ext_long) { this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; this_isa |=3D (1UL << (*ext - 'a')); } +#undef SET_ISA_EXT_MAP } =20 /* @@ -187,10 +197,21 @@ void __init riscv_fill_hwcap(void) else elf_hwcap =3D this_hwcap; =20 - if (riscv_isa[0]) + if (riscv_isa[0]) { +#if IS_ENABLED(CONFIG_32BIT) + riscv_isa[0] &=3D this_isa & 0xFFFFFFFF; + riscv_isa[1] &=3D this_isa >> 32; +#else riscv_isa[0] &=3D this_isa; - else +#endif + } else { +#if IS_ENABLED(CONFIG_32BIT) + riscv_isa[0] =3D this_isa & 0xFFFFFFFF; + riscv_isa[1] =3D this_isa >> 32; +#else riscv_isa[0] =3D this_isa; +#endif + } } =20 /* We don't support systems with F but without D, so mask those out --=20 2.30.2 From nobody Mon Jun 29 11:20:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBA4AC4332F for ; Thu, 10 Feb 2022 21:40:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344739AbiBJVkr (ORCPT ); Thu, 10 Feb 2022 16:40:47 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243868AbiBJVkh (ORCPT ); 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:36 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Thu, 10 Feb 2022 13:40:17 -0800 Message-Id: <20220210214018.55739-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 469b9739faf7..cca579bae8a0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; uint64_t this_isa =3D 0; + char *temp; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } =20 + temp =3D (char *)isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa +=3D 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp =3D=3D isa) + continue; for (; *isa; ++isa) { const char *ext =3D isa++; const char *ext_end =3D isa; --=20 2.30.2 From nobody Mon Jun 29 11:20:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A548C433FE for ; Thu, 10 Feb 2022 21:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344762AbiBJVkt (ORCPT ); Thu, 10 Feb 2022 16:40:49 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344740AbiBJVki (ORCPT ); Thu, 10 Feb 2022 16:40:38 -0500 Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49D612710 for ; Thu, 10 Feb 2022 13:40:39 -0800 (PST) Received: by mail-oo1-xc34.google.com with SMTP id t75-20020a4a3e4e000000b002e9c0821d78so8084192oot.4 for ; Thu, 10 Feb 2022 13:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=saY5DtvepsvwegCELkFkB7RgpB9RohGc6lIP30RliiM=; b=46zfGr3Kc5ND2ogjveHMMDJajmm20RjiQ5jLchAHKSOeQKPxbVdIY+oOIVYm/iux6G ZW7C8F9MHh0yrmBybRjiWtF0Xu0TFxrjlGVldYLEb13JSmAp10UwNlCF/RQs3NzeLRRw 2fy36iHMRabUOaLns1XyogS6wb2Zks+GqSdmRph/bI6MJPxl0saHoEkNH7YyzZQ4fId2 +pOuGvF2Q4fzB5TYRyebqrzn4PKDTXp8IVhCjORaAesIgT4iGxFQTo0yXwp2hn40ig2y 16NA6FAr6bH+/4dUQKItEPAZiRomvHhNA/crV+uSdzIGkPshdjxQ0yAaA8xLgSiwIjNe ZXOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=saY5DtvepsvwegCELkFkB7RgpB9RohGc6lIP30RliiM=; b=tGnJrwyXRieBjVK7IyuHrUKJ9pgPdxKgn+6AL0VB8TI/5svTp3JZjhCHmUhrET5+1e 926P2hqqPAJNGcTLCNFDAfNH9UpNvzOycNzFj2JEKwfwWPkz0jhd8JvA+AmOjKKrx63o Gy0fQzjmXmV+//KN9QAuQKsDdrE2AQsk98VOoUr65g9EEAJbhnbarpG/X7LXoPoBIk4K fZqlq8nXj54Lqoo0+OvKefMJLe8xrA8MAka+mm6jGwRJoVVQ6FhRyZhA8Pm6CNg6aVMZ aJ3j8Ljvx6EAB7GgJC9DIQXOUYeceH3MKAMcbCBZ9APfFxPgoX2o72sWn9Qi3gkVcvCe WChw== X-Gm-Message-State: AOAM533ecttCTSJHWLM6LMegE849Yry154+M4E8PvMnLiED+6QKncVi/ dQOVgfyhMjosa4GrlMVGcbx+L2RJRcOAMHbf X-Google-Smtp-Source: ABdhPJwjL2U7/u0jBP7WaACxI4KC0/AXyKMGE0aYyO5DPcLm++C2In2k7oqNhs9hXD+RC9AH2QAtbA== X-Received: by 2002:a05:6870:e3c6:: with SMTP id y6mr1357918oad.200.1644529238281; Thu, 10 Feb 2022 13:40:38 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id u5sm8700000ooo.46.2022.02.10.13.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Feb 2022 13:40:37 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Thu, 10 Feb 2022 13:40:18 -0800 Message-Id: <20220210214018.55739-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> References: <20220210214018.55739-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Parse only the enabled ISA extension and print them in a separate row. Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 7 ++++++ arch/riscv/kernel/cpu.c | 44 ++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, }; =20 +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..ced7e5be8641 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -63,12 +64,50 @@ int riscv_of_parent_hartid(struct device_node *node) } =20 #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop =3D #UPROP, \ + .isa_ext_id =3D EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] =3D { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i =3D 0, arr_sz; + + arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <=3D 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i =3D 0; i <=3D arr_sz; i++) { + edata =3D &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} =20 static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + char *ext_start; + int isa_len =3D strlen(isa); + int base_isa_len =3D isa_len; + + ext_start =3D strnchr(isa, isa_len, '_'); + if (ext_start) + base_isa_len =3D isa_len - strlen(ext_start); + + /* Print only the base ISA as it is */ seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + seq_write(f, isa, base_isa_len); seq_puts(f, "\n"); } =20 @@ -115,6 +154,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) --=20 2.30.2