From nobody Sun Jun 28 08:39:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D50CAC433EF for ; Thu, 10 Feb 2022 02:33:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbiBJCdx (ORCPT ); Wed, 9 Feb 2022 21:33:53 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:46432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230095AbiBJCds (ORCPT ); Wed, 9 Feb 2022 21:33:48 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCDAC237D2 for ; Wed, 9 Feb 2022 18:33:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644460429; x=1675996429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OWnYMkE7rv7BP25MrUGzKPIKcqXSEAtS5doI11hP+Y0=; b=cEu7lWnjVc+6zt9E15Zqd+401qUuQpP+v383M1prJDZR7tZXjEvfrHIU V86yYCzSJFR7f54oroe5RgbeWUHDAiRfnNAZKr/4L65IWW393bahmsd4o yXjynhBwrBBzWv19DJmVAg6e7gjCGEkGEnclngYc3G/ikaYNZ/u/qR6yb jUwqE+g/5FFqoEzUfnX+Hs/BfkJNb0AKnhXF1bJnviFvdmjJoH5cAUQoK 9UY4P/cGqIzURS4OFYDESkc134AMddnU8xiYD0ffsw676TXQqf+cQmLJc YLXPuhSlPQLWn0UnrwR/EZJ4RnmuQpybRyjJYX/UgWXLkzl7a9uoH7FLe w==; IronPort-SDR: eYLmNNkfGEeTrLV0GHhqboKWtUmQqQltTsdFidEkzGqh62JoZiYJgr/qR+/l8AimU4PgsTB+j9 CRI+EY6n7r5sZdLJyBYxoHzxHHjMedd0v0WMvxmqB4ZTwK2oSUgzWw1zmNQbC0rBDnz8oUVKX0 /SSdoapEL5u24R+Ri1Y+5tYYRMY+tV4BMTZMZ2ldX4eBVqBh7kLxDhGTWGQ2Zo6NKCuIvQfTWv UuqzTRr5sLzQEmPcAqSTPTiFzxkcOf7EDGqjNtT+f8ubNGUBArfHWUFuODlpmU6lpDwJgLeiDk i0rJYlHvVG8g+D3Zo3SEU32u X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="148216716" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Feb 2022 19:33:47 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 9 Feb 2022 19:33:45 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 9 Feb 2022 19:33:41 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 1/3] mtd: spi-nor: core: Add helpers to read/write any register Date: Thu, 10 Feb 2022 04:33:32 +0200 Message-ID: <20220210023334.408926-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210023334.408926-1-tudor.ambarus@microchip.com> References: <20220210023334.408926-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Tested-By: Takahiro Kuwano --- drivers/mtd/spi-nor/core.c | 41 ++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 4 ++++ 2 files changed, 45 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 7d5e3acb0ae7..d394179689e6 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -307,6 +307,47 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t= to, size_t len, return nor->controller_ops->write(nor, to, len, buf); } =20 +/** + * spi_nor_read_reg() - read register to flash memory + * @nor: pointer to 'struct spi_nor'. + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + if (!nor->spimem) + return -EOPNOTSUPP; + + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + +/** + * spi_nor_write_reg() - write register to flash memory + * @nor: pointer to 'struct spi_nor' + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + int ret; + + if (!nor->spimem) + return -EOPNOTSUPP; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + /** * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. * @nor: pointer to 'struct spi_nor'. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index cbfb4fa7647f..c728454b5424 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -578,6 +578,10 @@ ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t = from, size_t len, u8 *buf); ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf); +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); int spi_nor_erase_sector(struct spi_nor *nor, u32 addr); =20 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8= *buf); --=20 2.25.1 From nobody Sun Jun 28 08:39:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25790C433EF for ; Thu, 10 Feb 2022 02:34:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230394AbiBJCd5 (ORCPT ); Wed, 9 Feb 2022 21:33:57 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:46444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230115AbiBJCds (ORCPT ); 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d="scan'208";a="161726856" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Feb 2022 19:33:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 9 Feb 2022 19:33:49 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 9 Feb 2022 19:33:45 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 2/3] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Date: Thu, 10 Feb 2022 04:33:33 +0200 Message-ID: <20220210023334.408926-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210023334.408926-1-tudor.ambarus@microchip.com> References: <20220210023334.408926-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 105 +++++++++++++++++--------------- 1 file changed, 55 insertions(+), 50 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 7f66b5943ceb..013aa6a52737 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -17,73 +17,72 @@ #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */ #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */ =20 -static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enabl= e) +/* Micron ST SPI NOR flash operations. */ +#define SPI_NOR_MICRON_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int spi_nor_micron_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 20 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - *buf =3D 20; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; + /* Use 20 dummy cycles for memory array reads. */ + *buf =3D 20; + op =3D (struct spi_mem_op) + SPI_NOR_MICRON_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - } + buf[0] =3D SPINOR_MT_OCT_DTR; + op =3D (struct spi_mem_op) + SPI_NOR_MICRON_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; =20 - ret =3D spi_nor_write_enable(nor); + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_MT_OCT_DTR; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. The next register is the dummy - * cycle configuration register. Since the transaction needs to - * be at least 2 bytes wide, set the next register to its - * default value. This also makes sense because the value was - * changed when enabling 8D-8D-8D mode, it should be reset when - * disabling. - */ - buf[0] =3D SPINOR_MT_EXSPI; - buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; - } + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_MT_CFR0V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + return 0; +} =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); +static int spi_nor_micron_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. The next register is the dummy cycle configuration + * register. Since the transaction needs to be at least 2 bytes wide, + * set the next register to its default value. This also makes sense + * because the value was changed when enabling 8D-8D-8D mode, it should + * be reset when disabling. + */ + buf[0] =3D SPINOR_MT_EXSPI; + buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; + op =3D (struct spi_mem_op) + SPI_NOR_MICRON_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf); + ret =3D spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, nor->reg_proto); + ret =3D spi_nor_read_id(nor, 0, 0, buf, nor->reg_proto); if (ret) return ret; =20 @@ -93,6 +92,12 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_no= r *nor, bool enable) return 0; } =20 +static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enabl= e) +{ + return enable ? spi_nor_micron_octal_dtr_en(nor) : + spi_nor_micron_octal_dtr_dis(nor); +} + static void mt35xu512aba_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D spi_nor_micron_octal_dtr_enable; --=20 2.25.1 From nobody Sun Jun 28 08:39:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F93FC433F5 for ; Thu, 10 Feb 2022 02:34:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230475AbiBJCeA (ORCPT ); Wed, 9 Feb 2022 21:34:00 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:46476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230316AbiBJCdw (ORCPT ); Wed, 9 Feb 2022 21:33:52 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4312237D4 for ; Wed, 9 Feb 2022 18:33:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644460434; x=1675996434; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yykgA2NLZMLLQxzpDi7wv3MT1+A8SrBWEcGrIX62WjE=; b=WdQfWryltyfEtQZvopxMPaZ6xyS8h8tMopfYYF+rpF9M6wQcDYFAr6OL RXyDnWmRQidJxEkOqDKT9k394wLClfxjCykpnGpy9XcEGI+3klUHNK1hU PV+6vY6Syj3yGC+PH+ckX7CWjFQ9PHOeaaI9O+z+A9ooKH9VZAaJOJuS1 O08ARg+9bhd1MIfVWn6/NmKRgDxHTs3n/oU338AA39UY9NhkCqhHDz2HE tXl5NuLXrK0YzYuPixVnMjGW/5CGzgJGSu2H96M2FGxYGZR6c7aPglZdu nq+d2HnGsipboBZOO9RugHK11CNxxzIgjKZZS6z1hJvW96gs7lb8s+2Ig A==; IronPort-SDR: TvyNYGn4gqiblmgJVpHdKMY2JuE1dQyGi5TBoa7QPaT42tIulPKshTHwzmZR/wuJEXe+wXwrXJ ppnkM8Xx9MqqD6/tNDPv9zTpvA2Zu88Nbtd62yE5txSa7pV2+PdGA8pxY6eojzFyMnIkZ8wkq2 vachgoRQoi9ueyWslOPCfeIjn57WCEFq2G8vsXp/F6Pls9N6SKZnJWhvVGTxHa9y0BatDXBr5A twR1bzYvDGHmVNpJLn7AdRNt2qp8XHMUyJ8U3sFwtpRBjG9y03X5uW5+QJUyB3y8/ulFxImU37 jogw3UxcXczxCtztm3FaIMaz X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="153075495" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Feb 2022 19:33:54 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 9 Feb 2022 19:33:53 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 9 Feb 2022 19:33:50 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 3/3] mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable() Date: Thu, 10 Feb 2022 04:33:34 +0200 Message-ID: <20220210023334.408926-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210023334.408926-1-tudor.ambarus@microchip.com> References: <20220210023334.408926-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 135 ++++++++++++++++++--------------- 1 file changed, 72 insertions(+), 63 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index d69a569f31e4..9bb239f1e142 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -19,85 +19,78 @@ #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 #define SPINOR_OP_CYPRESS_RD_FAST 0xee =20 -/** - * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashe= s. - * @nor: pointer to a 'struct spi_nor' - * @enable: whether to enable or disable Octal DTR - * - * This also sets the memory access latency cycles to 24 to allow the flas= h to - * run at up to 200MHz. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enab= le) +/* Spansion/Cypress SPI NOR flash operations. */ +#define SPI_NOR_SPANSION_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int spi_nor_cypress_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 24 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; - - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - - nor->read_dummy =3D 24; - } - - /* Set/unset the octal and DTR enable bits. */ - ret =3D spi_nor_write_enable(nor); + /* Use 24 dummy cycles for memory array reads. */ + *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + op =3D (struct spi_mem_op) + SPI_NOR_SPANSION_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, + 1, buf); + + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. Since there is no register at the - * next location, just initialize the value to 0 and let the - * transaction go on. - */ - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; - buf[1] =3D 0; - } + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; + + nor->read_dummy =3D 24; =20 + /* Set the octal and DTR enable bits. */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_CYPRESS_CFR5V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + SPI_NOR_SPANSION_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, + 1, buf); =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) + return ret; + + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; + + return 0; +} + +static int spi_nor_cypress_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; + + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. Since there is no register at the next location, + * just initialize the value to 0 and let the transaction go on. + */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + buf[1] =3D 0; + op =3D (struct spi_mem_op) + SPI_NOR_SPANSION_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, + 2, buf); + ret =3D spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, nor->reg_proto); + ret =3D spi_nor_read_id(nor, 0, 0, buf, nor->reg_proto); if (ret) return ret; =20 @@ -107,6 +100,22 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi= _nor *nor, bool enable) return 0; } =20 +/** + * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashe= s. + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal DTR + * + * This also sets the memory access latency cycles to 24 to allow the flas= h to + * run at up to 200MHz. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enab= le) +{ + return enable ? spi_nor_cypress_octal_dtr_en(nor) : + spi_nor_cypress_octal_dtr_dis(nor); +} + static void s28hs512t_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D spi_nor_cypress_octal_dtr_enable; --=20 2.25.1