From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99F7FC433F5 for ; Tue, 8 Feb 2022 18:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385646AbiBHS5m (ORCPT ); Tue, 8 Feb 2022 13:57:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385564AbiBHS5K (ORCPT ); Tue, 8 Feb 2022 13:57:10 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C273C0612BF; Tue, 8 Feb 2022 10:57:09 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id ED5D1CE1BEA; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5E275C340F2; Tue, 8 Feb 2022 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346624; bh=46GvYvu2qBY0XJLufv8o7VnMQWHTSSvKJFHbggT3hWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FxMpTLxNCgUtsT5hpcdQONA+9HkPQqHm/8V4KtnaE0HPW3vvIfU0xnAM6On57r9UQ YRIoMzbkmjIJ69Gbq9bINvaRQwr2mFtE8ROABbq/pw9Ksfftc/ddBiRKFPLV7YY1mQ +4TOmML+D+ZD81oe2S8Z9hy0yj2cKVLGCVzqponh3CFme6l0oQRjAsmFhAFt7yzP+A 8J+0HpU3rvMzSot8DQmMzfscJfS9gmW7eXm9O0eD4zH/A6c5/+kxRFBydRObld5M4V 0iZO1A0FUtStbYwIpyl5t2Sua3uNHi3riAUseSsi/pXr5944bnsH94qJPo0gKnyI1A lHXiHGJGqC5ZA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfi-006MEi-Cd; Tue, 08 Feb 2022 18:57:02 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v5 01/10] dt-bindings: arm-pmu: Document Apple PMU compatible strings Date: Tue, 8 Feb 2022 18:55:55 +0000 Message-Id: <20220208185604.1097957-2-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As we are about to add support fur the Apple PMUs, document the compatible strings associated with the two micro-architectures present in the Apple M1. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 981bac451698..7a04b8aaaec3 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,firestorm-pmu + - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC845C433EF for ; Tue, 8 Feb 2022 18:57:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385587AbiBHS5Q (ORCPT ); Tue, 8 Feb 2022 13:57:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385021AbiBHS5G (ORCPT ); Tue, 8 Feb 2022 13:57:06 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9608FC0612C0; Tue, 8 Feb 2022 10:57:05 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 30BE4613FB; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C6C5C340F6; Tue, 8 Feb 2022 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346624; bh=KnKaDKP2ZmunzG4S4wREZKGTAqqogy6WlIrJ0BuxmmM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lRJwpA4Jjy3FEGAiwT2a9iYnIda+++hysFncfCM+4m+vlBHvxlHfPz6p1b9Vkfe0M K4zGZCUG8RQaXb7HSbjhXlvPt4x/R3+VNJVK7/+xNu0kR0Ld/Zye87HGuoMNThaetS yGf/l6MH8Znmi8WlpJ/MeYB9db+nFYDNDWUNL5juoqRSvaS4z6ed41Mor6yS//U21R bjixGj+tKqGX10TSB+MGExDHVHPN1E5UHIss1SYwiEQin6o48VXKkR7zg7D9jxXAwl 97ZyBFP6YyEkeIlxm8l4ogTo3bf/nxiQ2y+0OtBK3oUJWInpKP2v7EyXUtCbGLNh9y qHxUHFN1J4DwQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfi-006MEi-KJ; Tue, 08 Feb 2022 18:57:02 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v5 02/10] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Date: Tue, 8 Feb 2022 18:55:56 +0000 Message-Id: <20220208185604.1097957-3-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC. We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/apple,aic.yaml | 2 ++ include/dt-bindings/interrupt-controller/apple-aic.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.= yaml index 97359024709a..c7577d401786 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU =20 The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include= /dt-bindings/interrupt-controller/apple-aic.h index 604f2bb30ac0..bf3aac0e5491 100644 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -11,5 +11,7 @@ #define AIC_TMR_HV_VIRT 1 #define AIC_TMR_GUEST_PHYS 2 #define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 =20 #endif --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BBE5C433F5 for ; Tue, 8 Feb 2022 18:57:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385605AbiBHS5W (ORCPT ); Tue, 8 Feb 2022 13:57:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385440AbiBHS5G (ORCPT ); Tue, 8 Feb 2022 13:57:06 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10297C0612C1; Tue, 8 Feb 2022 10:57:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 86E0C61411; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E53CAC340F9; Tue, 8 Feb 2022 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346624; bh=Zeps+GeA7ULcv2qdwDmPHpGj1ews/29DjRK2xfNXanY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=siBE5wAkKpbkSaStlvAa4XnSEEjqiefGF8kQMgfR3EJxzxhzPe01D2CDx+zxSM5i6 Dm9vvXPSbmlQvGKRh/FHlhZvLZo2YJzo9Tq6LvqmmIoHOQg9eQRjOR1i6N50I40XgU lcGgpbtpswOkKfSKHxw+k+1Jc5mGIjUaD92J70mQ/S2HF1hw8uix9+QkJWXuboLIhA fPEvdOWOgtXtsc6a8/4CGF8xZt6++bvRak2dOkrXQa8eJrGl6RZGBGi1fc+fJ+LBox 7jCsSs+xpBBwoQC2YRA8cz5MN4p3P/HCQpFTHGlA0NqQPK956Y2Jjt9I4SV3K/e3sT p6kH3FWVkj5Cw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfi-006MEi-Sd; Tue, 08 Feb 2022 18:57:02 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v5 03/10] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts Date: Tue, 8 Feb 2022 18:55:57 +0000 Message-Id: <20220208185604.1097957-4-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier --- .../interrupt-controller/apple,aic.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.= yaml index c7577d401786..85c85b694217 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -70,6 +70,35 @@ properties: power-domains: maxItems: 1 =20 + affinities: + type: object + additionalProperties: false + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + additionalProperties: false + properties: + apple,fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - cpus + required: - compatible - '#interrupt-cells' --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A77BC433F5 for ; Tue, 8 Feb 2022 18:57:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385608AbiBHS50 (ORCPT ); Tue, 8 Feb 2022 13:57:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385406AbiBHS5G (ORCPT ); Tue, 8 Feb 2022 13:57:06 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1189FC0612C3; Tue, 8 Feb 2022 10:57:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A2D5061419; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 160F4C340FD; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346625; bh=G9atuG1gvxA8sTH+XdAwaAyR2vEMcWxrL85sv2f+EY0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E3WB8Fp5/j6P1MX4QGFjrBPj86py5t00elz2sKjwWe+nOevEvqCEH2exn784G1pwd frRPfO6Zy2Oi+lexpI8OpyTIhVtPZqXZT8BvQvc15cym+Ao+xVBPREBmZ/UA8Wrf1V A3PGU7DpVje8rvpVvjAFzWy7YmXLgmwkJ4nf1TL+Ul1e+fez7NlZtVG2TKCadChPiP ETOJdibrPHgy1jH3X9xTtjl7ck/hRh4LrGLZiUpJdLQ755L03UwAYvfteE5K3aQAyq oLeTe8p2iZwjd05Dd+bcqzJrtODTjvBJIXvQOrwvIz09jGSfS5rimTAx5mvbmhoDJQ QXb6ec1JuPEXw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfj-006MEi-3b; Tue, 08 Feb 2022 18:57:03 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 04/10] irqchip/apple-aic: Parse FIQ affinities from device-tree Date: Tue, 8 Feb 2022 18:55:58 +0000 Message-Id: <20220208185604.1097957-5-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, parse the affinities kindly provided in the device-tree. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-apple-aic.c | 49 +++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 38091ebb9403..22d9b2058612 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -177,6 +177,9 @@ struct aic_irq_chip { void __iomem *base; struct irq_domain *hw_domain; struct irq_domain *ipi_domain; + struct { + cpumask_t aff; + } *fiq_aff[AIC_NR_FIQ]; int nr_hw; }; =20 @@ -793,12 +796,50 @@ static struct gic_kvm_info vgic_info __initdata =3D { .no_hw_deactivation =3D true, }; =20 +static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node= *aff) +{ + int i, n; + u32 fiq; + + if (of_property_read_u32(aff, "apple,fiq-index", &fiq) || + WARN_ON(fiq >=3D AIC_NR_FIQ) || ic->fiq_aff[fiq]) + return; + + n =3D of_property_count_elems_of_size(aff, "cpus", sizeof(u32)); + if (WARN_ON(n < 0)) + return; + + ic->fiq_aff[fiq] =3D kzalloc(sizeof(ic->fiq_aff[fiq]), GFP_KERNEL); + if (!ic->fiq_aff[fiq]) + return; + + for (i =3D 0; i < n; i++) { + struct device_node *cpu_node; + u32 cpu_phandle; + int cpu; + + if (of_property_read_u32_index(aff, "cpus", i, &cpu_phandle)) + continue; + + cpu_node =3D of_find_node_by_phandle(cpu_phandle); + if (WARN_ON(!cpu_node)) + continue; + + cpu =3D of_cpu_node_to_id(cpu_node); + if (WARN_ON(cpu < 0)) + continue; + + cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff); + } +} + static int __init aic_of_ic_init(struct device_node *node, struct device_n= ode *parent) { int i; void __iomem *regs; u32 info; struct aic_irq_chip *irqc; + struct device_node *affs; =20 regs =3D of_iomap(node, 0); if (WARN_ON(!regs)) @@ -832,6 +873,14 @@ static int __init aic_of_ic_init(struct device_node *n= ode, struct device_node *p return -ENODEV; } =20 + affs =3D of_get_child_by_name(node, "affinities"); + if (affs) { + struct device_node *chld; + + for_each_child_of_node(affs, chld) + build_fiq_affinity(irqc, chld); + } + set_handle_irq(aic_handle_irq); set_handle_fiq(aic_handle_fiq); =20 --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4716FC433F5 for ; Tue, 8 Feb 2022 18:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385593AbiBHS5T (ORCPT ); Tue, 8 Feb 2022 13:57:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385480AbiBHS5H (ORCPT ); Tue, 8 Feb 2022 13:57:07 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 711E9C0612AA; Tue, 8 Feb 2022 10:57:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CFCCE61426; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E794C340EE; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346625; bh=RNm6TqjW9fK94EZ39KVCSoOKWtsPJZNQI1TaJpf0GbU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BHq/pS4rf7UhA3iExt0lWC7tzrk/SrfgN7NNlZGVtHITCDjgTcoLFhfrW0l8wmr7K AGXRDcdkhrPkTB3ThCjeXadMPg9LfxkAd/0D7bMga3IW8461iQixm/1mnBTA6b0J0N /nPGcb9qNK6JJYZ0bvO95OTQD7kWh+7Cwtzs/o9NsBpfxZJPT03ljwuC4u7ARul1w7 N34h7lWVewo5Os0qb2WRLmQVlUYQe6IavJhoz7L7xGhNg5tVDfjnvauIvp0jaGvEA+ +jYu+ZUWoooW7aVl/VXa+egwCAwyMroiw2gUDe2TWMwj1HvdVIrX/xXNrec8nRQ27y ToXxVRqmsHkDg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfj-006MEi-C1; Tue, 08 Feb 2022 18:57:03 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 05/10] irqchip/apple-aic: Wire PMU interrupts Date: Tue, 8 Feb 2022 18:55:59 +0000 Message-Id: <20220208185604.1097957-6-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-apple-aic.c | 34 +++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 22d9b2058612..873544e58676 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -155,7 +155,7 @@ #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4) #define UPMSR_IACT BIT(0) =20 -#define AIC_NR_FIQ 4 +#define AIC_NR_FIQ 6 #define AIC_NR_SWIPI 32 =20 /* @@ -415,16 +415,15 @@ static void __exception_irq_entry aic_handle_fiq(stru= ct pt_regs *regs) aic_irqc->nr_hw + AIC_TMR_EL02_VIRT); } =20 - if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) = =3D=3D - (FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) { - /* - * Not supported yet, let's figure out how to handle this when - * we implement these proprietary performance counters. For now, - * just mask it and move on. - */ - pr_err_ratelimited("PMC FIQ fired. Masking.\n"); - sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT, - FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF)); + if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) { + int irq; + if (cpumask_test_cpu(smp_processor_id(), + &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff)) + irq =3D AIC_CPU_PMU_P; + else + irq =3D AIC_CPU_PMU_E; + generic_handle_domain_irq(aic_irqc->hw_domain, + aic_irqc->nr_hw + irq); } =20 if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) =3D=3D= UPMCR0_IMODE_FIQ && @@ -464,7 +463,18 @@ static int aic_irq_domain_map(struct irq_domain *id, u= nsigned int irq, handle_fasteoi_irq, NULL, NULL); irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); } else { - irq_set_percpu_devid(irq); + int fiq =3D hw - ic->nr_hw; + + switch (fiq) { + case AIC_CPU_PMU_P: + case AIC_CPU_PMU_E: + irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff); + break; + default: + irq_set_percpu_devid(irq); + break; + } + irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data, handle_percpu_devid_irq, NULL, NULL); } --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F1F4C433F5 for ; Tue, 8 Feb 2022 18:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385647AbiBHS5r (ORCPT ); Tue, 8 Feb 2022 13:57:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385562AbiBHS5K (ORCPT ); Tue, 8 Feb 2022 13:57:10 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FAEBC0612BD; Tue, 8 Feb 2022 10:57:08 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 20703CE1BF0; Tue, 8 Feb 2022 18:57:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84655C34102; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346625; bh=ffXhP80bXiWm6QZsRgVzkuhQFwsVc53UEqMBTezk5bA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QF3gwDPyWo5uLsZKvReJhYDDmS23LwS9BmP1BgkrGVfPcMqj6qaE8uEDETAyJyU3j Owkf6EVUXzWHNsdIhsB4msAz4BnJRKqnMXmHR4UJL5oHn4VPrfsETDSdhGiFfhR45/ Iiny68Le5ygiThMaMsMDnJzrA94GJIoVdVUkTHXYDNCQ5GAdln24QU4Uz/5YFbiIow 7t54QrKr5hsrYfWol7xUizMxRdsH3pHdgwkwodsGJGvhs0ZHEwPnvAYlzCc5NfMqdr 67FG9ca8WiHP/9PR3P71NI4SLPMg+4wM2de/RIZ43uKPpvl9y/+efQCPWuXI6OJPrW yIdx+a2SFCK3A== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfj-006MEi-JJ; Tue, 08 Feb 2022 18:57:03 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 06/10] arm64: dts: apple: Add t8103 PMU interrupt affinities Date: Tue, 8 Feb 2022 18:56:00 +0000 Message-Id: <20220208185604.1097957-7-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The two PMU pseudo interrupts have specific affinities. One set is affine to the small cores, and the other set affine to the big ones. Signed-off-by: Marc Zyngier --- arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 19afbc91020a..a2e006538c56 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -213,6 +213,18 @@ aic: interrupt-controller@23b100000 { interrupt-controller; reg =3D <0x2 0x3b100000 0x0 0x8000>; power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; }; =20 pmgr: power-management@23b700000 { --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3911C433FE for ; Tue, 8 Feb 2022 18:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385618AbiBHS52 (ORCPT ); Tue, 8 Feb 2022 13:57:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385490AbiBHS5I (ORCPT ); Tue, 8 Feb 2022 13:57:08 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94057C0612B9; Tue, 8 Feb 2022 10:57:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E7E306142F; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6904C340ED; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346625; bh=NvFa8/KGiLZPSE4OBVLx55ridSoU0xEWvMgTYnpxjME=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oNqZ1IOca5k5KaZZlFCaZzU6QvjFDU/hcA/UbZNsWaAoZk8ZtrZjY0oDr/dIeCImE QQYYnGcaZCEqG7H/h+1sW6RkOwY8nc6T9inC+N1DEIfhbSu1ev3azOqWpS1jdvaVCL HTqj8LBKzIXUrTEIhLHnLVsPjqjsg+PKnSkMPmdGLPc9WN7D9h5w3lNpV2j2BVGjbz AB5vgrWtgApoFPrBv5h6OAZ37HqBjGuf9rGRqLbyzE6lNPmFOU+mm93QoPkAVs4v// N0oOQbmUyakdN1HsCW8HPDSr6upEnN/b0oTC0m5lb2jZBizdItJd2Qdv7jH0f8qsAr P8BtldkkIAWBA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfj-006MEi-SH; Tue, 08 Feb 2022 18:57:03 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 07/10] arm64: dts: apple: Add t8303 PMU nodes Date: Tue, 8 Feb 2022 18:56:01 +0000 Message-Id: <20220208185604.1097957-8-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Advertise the two PMU nodes for the t8103 SoC. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index a2e006538c56..9f8f4145db88 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -97,6 +97,18 @@ timer { ; }; =20 + pmu-e { + compatible =3D "apple,icestorm-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,firestorm-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + clkref: clock-ref { compatible =3D "fixed-clock"; #clock-cells =3D <0>; --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02161C433FE for ; Tue, 8 Feb 2022 18:57:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385633AbiBHS5c (ORCPT ); Tue, 8 Feb 2022 13:57:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385530AbiBHS5I (ORCPT ); Tue, 8 Feb 2022 13:57:08 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93F77C0612B8; Tue, 8 Feb 2022 10:57:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 22D166142A; Tue, 8 Feb 2022 18:57:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA8E2C340F3; Tue, 8 Feb 2022 18:57:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346626; bh=KWdwaYmfieQ577sfQve0otGenOOT5DJLuSqbiyJn4NQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mkDKPHjPz30MLWZwdY3KX/fQ9Z5Am0IUOIcztL4UVtd5AYF7yNCA2EIsed3o8Tu6G /xG7Fvw0b0dHEM3OCDXU9IAYlQZ9Gsixzp5cVn+9bmc8lCv0uz9ED38i8VDLAzvAoU T0whhTPTfAYqFg9cgCRyvaybyyJKsoWYcZwpEPiQUy0L2XKK3PgOHsMqg1ExcxAQcI 9NlV8k89tUsmPE7knIgFBfn3bCXkf+4jpdj6WpYTknSDaMJOYVCaMMHVdW9RyG6BfP RFNfkJaXr3PikfjwKhpU+wh13zoFsNFdnDcDsg2sCvEjG8iHLxD5W7VNbEXA8DIIBv Zd/+K5UnIdt/A== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfk-006MEi-38; Tue, 08 Feb 2022 18:57:04 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 08/10] irqchip/apple-aic: Move PMU-specific registers to their own include file Date: Tue, 8 Feb 2022 18:56:02 +0000 Message-Id: <20220208185604.1097957-9-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/apple_m1_pmu.h | 19 +++++++++++++++++++ drivers/irqchip/irq-apple-aic.c | 11 +---------- 2 files changed, 20 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/include/asm/apple_m1_pmu.h diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h new file mode 100644 index 000000000000..b848af7faadc --- /dev/null +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __ASM_APPLE_M1_PMU_h +#define __ASM_APPLE_M1_PMU_h + +#include +#include + +/* Core PMC control register */ +#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) +#define PMCR0_IMODE GENMASK(10, 8) +#define PMCR0_IMODE_OFF 0 +#define PMCR0_IMODE_PMI 1 +#define PMCR0_IMODE_AIC 2 +#define PMCR0_IMODE_HALT 3 +#define PMCR0_IMODE_FIQ 4 +#define PMCR0_IACT BIT(11) + +#endif /* __ASM_APPLE_M1_PMU_h */ diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 873544e58676..b40199c6625e 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -109,16 +110,6 @@ * Note: sysreg-based IPIs are not supported yet. */ =20 -/* Core PMC control register */ -#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) -#define PMCR0_IMODE GENMASK(10, 8) -#define PMCR0_IMODE_OFF 0 -#define PMCR0_IMODE_PMI 1 -#define PMCR0_IMODE_AIC 2 -#define PMCR0_IMODE_HALT 3 -#define PMCR0_IMODE_FIQ 4 -#define PMCR0_IACT BIT(11) - /* IPI request registers */ #define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0) #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1) --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AC15C433F5 for ; Tue, 8 Feb 2022 18:57:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385639AbiBHS5h (ORCPT ); Tue, 8 Feb 2022 13:57:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385553AbiBHS5J (ORCPT ); Tue, 8 Feb 2022 13:57:09 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA557C0612BA; Tue, 8 Feb 2022 10:57:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 40233613F8; Tue, 8 Feb 2022 18:57:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 136B7C340F8; Tue, 8 Feb 2022 18:57:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346626; bh=byMO3nYSC2TvSH32oHHrAxbZ7HoV85bYK3g6rU+Vckk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PCD2UCJfQrsemk/xjjy64hyoqVb/mB4I/rPiPffQ5dGy8RnL/bCaW1dAwEL7jyduu azNmGpDY8iPWwe7baD/HFf3C9udWOGFv6OC5FxyBb/PU36gL3kHdO9CYj4hXfnWXuD yqhRwae27Bg0++C6bMNRCfNmgktFF9hnBsx4XWBVQo4TSBHVeGfQuqUuIbEUH2wK1h LqagRQnhC0KbgeFIkOIJ33eqY194m0uikUzG6crMIGFktwTy8pNX6U+ddqIep3nkHr AMcpHbhq+nHvTAu3WAW8e+v1doAja6ZoS8R+l9UNRmauSdt0sUxWz0glxkjh4dsNqo cKETcqwxV1yxg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfk-006MEi-BH; Tue, 08 Feb 2022 18:57:04 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 09/10] drivers/perf: arm_pmu: Handle 47 bit counters Date: Tue, 8 Feb 2022 18:56:03 +0000 Message-Id: <20220208185604.1097957-10-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current ARM PMU framework can only deal with 32 or 64bit counters. Teach it about a 47bit flavour. Yes, this is odd. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- drivers/perf/arm_pmu.c | 2 ++ include/linux/perf/arm_pmu.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 295cc7952d0e..0a9ed1a061ac 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_= event *event) { if (event->hw.flags & ARMPMU_EVT_64BIT) return GENMASK_ULL(63, 0); + else if (event->hw.flags & ARMPMU_EVT_47BIT) + return GENMASK_ULL(46, 0); else return GENMASK_ULL(31, 0); } diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 2512e2f9cd4e..0407a38b470a 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -26,6 +26,8 @@ */ /* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 1 +/* Event uses a 47bit counter */ +#define ARMPMU_EVT_47BIT 2 =20 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x --=20 2.30.2 From nobody Sun Jun 28 10:34:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39ADDC433FE for ; Tue, 8 Feb 2022 19:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385766AbiBHTDC (ORCPT ); Tue, 8 Feb 2022 14:03:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385672AbiBHTDB (ORCPT ); Tue, 8 Feb 2022 14:03:01 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A511AC0612C3; Tue, 8 Feb 2022 11:02:58 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4753EB81D1D; Tue, 8 Feb 2022 19:02:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ABB0EC004E1; Tue, 8 Feb 2022 19:02:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644346976; bh=IOrzP7AZQZvXLCOiOi008mSBOlUIwceqknphO08hNss=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OK/bqI3al4IVA1eZwL8e9sSQvDAo7x6FfoibOhO9t/PQAK2gDu/kXPzoiKrok82sF qwkDLXPIzFy90DxjU6RslM+Yv11iI74h7KgLr3MRq1s6dTRYrzHwmBEIt1iFUkmCOG dTY0zNxOOGOzoy1YaotL4749CGsgfiUC9+kGIQOla7K93WrGwSUxUcBfOzsHjaPuae /Cz0RD01RzTZb7HXaSwNk3kfboN+cjNPUDaE8gFccKVJAVJYGVUycn7nJIEa9wUhxv vbg+djHHDCdbvYmWsgLoOIaPVYdc59Zq8F6FZF8ISgw2M7zpXBr1plKRuw4IyZcQeu XA28eS6GWl/CA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHVfk-006MEi-IA; Tue, 08 Feb 2022 18:57:04 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v5 10/10] drivers/perf: Add Apple icestorm/firestorm CPU PMU driver Date: Tue, 8 Feb 2022 18:56:04 +0000 Message-Id: <20220208185604.1097957-11-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220208185604.1097957-1-maz@kernel.org> References: <20220208185604.1097957-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a new, weird and wonderful driver for the equally weird Apple PMU HW. Although the PMU itself is functional, we don't know much about the events yet, so this can be considered as yet another random number generator... Nonetheless, it can reliably count at least cycles and instructions in the usually wonky big-little way. For anything else, it of course supports raw event numbers. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/apple_m1_pmu.h | 45 ++ drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/apple_m1_cpu_pmu.c | 584 ++++++++++++++++++++++++++ 4 files changed, 637 insertions(+) create mode 100644 drivers/perf/apple_m1_cpu_pmu.c diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index b848af7faadc..99483b19b99f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -6,8 +6,21 @@ #include #include =20 +/* Counters */ +#define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0) +#define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0) +#define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0) +#define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0) +#define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0) +#define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0) +#define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0) +#define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0) +#define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0) +#define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0) + /* Core PMC control register */ #define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) +#define PMCR0_CNT_ENABLE_0_7 GENMASK(7, 0) #define PMCR0_IMODE GENMASK(10, 8) #define PMCR0_IMODE_OFF 0 #define PMCR0_IMODE_PMI 1 @@ -15,5 +28,37 @@ #define PMCR0_IMODE_HALT 3 #define PMCR0_IMODE_FIQ 4 #define PMCR0_IACT BIT(11) +#define PMCR0_PMI_ENABLE_0_7 GENMASK(19, 12) +#define PMCR0_STOP_CNT_ON_PMI BIT(20) +#define PMCR0_CNT_GLOB_L2C_EVT BIT(21) +#define PMCR0_DEFER_PMI_TO_ERET BIT(22) +#define PMCR0_ALLOW_CNT_EN_EL0 BIT(30) +#define PMCR0_CNT_ENABLE_8_9 GENMASK(33, 32) +#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44) + +#define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) +#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) +#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) +#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) + +#define SYS_IMP_APL_PMCR2_EL1 sys_reg(3, 1, 15, 2, 0) +#define SYS_IMP_APL_PMCR3_EL1 sys_reg(3, 1, 15, 3, 0) +#define SYS_IMP_APL_PMCR4_EL1 sys_reg(3, 1, 15, 4, 0) + +#define SYS_IMP_APL_PMESR0_EL1 sys_reg(3, 1, 15, 5, 0) +#define PMESR0_EVT_CNT_2 GENMASK(7, 0) +#define PMESR0_EVT_CNT_3 GENMASK(15, 8) +#define PMESR0_EVT_CNT_4 GENMASK(23, 16) +#define PMESR0_EVT_CNT_5 GENMASK(31, 24) + +#define SYS_IMP_APL_PMESR1_EL1 sys_reg(3, 1, 15, 6, 0) +#define PMESR1_EVT_CNT_6 GENMASK(7, 0) +#define PMESR1_EVT_CNT_7 GENMASK(15, 8) +#define PMESR1_EVT_CNT_8 GENMASK(23, 16) +#define PMESR1_EVT_CNT_9 GENMASK(31, 24) + +#define SYS_IMP_APL_PMSR_EL1 sys_reg(3, 1, 15, 13, 0) +#define PMSR_OVERFLOW GENMASK(9, 0) =20 #endif /* __ASM_APPLE_M1_PMU_h */ diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index e1a0c44bc686..d4fa0dabb05f 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -146,6 +146,13 @@ config MARVELL_CN10K_TAD_PMU Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) performance monitors on CN10K family silicons. =20 +config APPLE_M1_CPU_PMU + bool "Apple M1 CPU PMU support" + depends on ARM_PMU && ARCH_APPLE + help + Provides support for the non-architectural CPU PMUs present on + the Apple M1 SoCs and derivatives. + source "drivers/perf/hisilicon/Kconfig" =20 endmenu diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 2db5418d5b0a..21ad0832e3d4 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_XGENE_PMU) +=3D xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) +=3D arm_spe_pmu.o obj-$(CONFIG_ARM_DMC620_PMU) +=3D arm_dmc620_pmu.o obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_tad_pmu.o +obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c new file mode 100644 index 000000000000..979a7c2b4f56 --- /dev/null +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CPU PMU driver for the Apple M1 and derivatives + * + * Copyright (C) 2021 Google LLC + * + * Author: Marc Zyngier + * + * Most of the information used in this driver was provided by the + * Asahi Linux project. The rest was experimentally discovered. + */ + +#include +#include +#include + +#include +#include +#include + +#define M1_PMU_NR_COUNTERS 10 + +#define M1_PMU_CFG_EVENT GENMASK(7, 0) + +#define ANY_BUT_0_1 GENMASK(9, 2) +#define ONLY_2_TO_7 GENMASK(7, 2) +#define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) + +/* + * Description of the events we actually know about, as well as those with + * a specific counter affinity. Yes, this is a grand total of two known + * counters, and the rest is anybody's guess. + * + * Not all counters can count all events. Counters #0 and #1 are wired to + * count cycles and instructions respectively, and some events have + * bizarre mappings (every other counter, or even *one* counter). These + * restrictions equally apply to both P and E cores. + * + * It is worth noting that the PMUs attached to P and E cores are likely + * to be different because the underlying uarches are different. At the + * moment, we don't really need to distinguish between the two because we + * know next to nothing about the events themselves, and we already have + * per cpu-type PMU abstractions. + * + * If we eventually find out that the events are different across + * implementations, we'll have to introduce per cpu-type tables. + */ +enum m1_pmu_events { + M1_PMU_PERFCTR_UNKNOWN_01 =3D 0x01, + M1_PMU_PERFCTR_CPU_CYCLES =3D 0x02, + M1_PMU_PERFCTR_INSTRUCTIONS =3D 0x8c, + M1_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + M1_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + M1_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + M1_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + M1_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + M1_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + M1_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + M1_PMU_PERFCTR_UNKNOWN_96 =3D 0x96, + M1_PMU_PERFCTR_UNKNOWN_97 =3D 0x97, + M1_PMU_PERFCTR_UNKNOWN_98 =3D 0x98, + M1_PMU_PERFCTR_UNKNOWN_99 =3D 0x99, + M1_PMU_PERFCTR_UNKNOWN_9a =3D 0x9a, + M1_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + M1_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, + M1_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + M1_PMU_PERFCTR_UNKNOWN_bf =3D 0xbf, + M1_PMU_PERFCTR_UNKNOWN_c0 =3D 0xc0, + M1_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + M1_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + M1_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + M1_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + M1_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + M1_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + M1_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + M1_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + M1_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + M1_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + M1_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + M1_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + M1_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + M1_PMU_CFG_COUNT_USER =3D BIT(8), + M1_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +/* + * Per-event affinity table. Most events can be installed on counter + * 2-9, but there are a number of exceptions. Note that this table + * has been created experimentally, and I wouldn't be surprised if more + * counters had strange affinities. + */ +static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] =3D { + [0 ... M1_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [M1_PMU_PERFCTR_UNKNOWN_01] =3D BIT(7), + [M1_PMU_PERFCTR_CPU_CYCLES] =3D ANY_BUT_0_1 | BIT(0), + [M1_PMU_PERFCTR_INSTRUCTIONS] =3D BIT(7) | BIT(1), + [M1_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_96] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_97] =3D BIT(7), + [M1_PMU_PERFCTR_UNKNOWN_98] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_99] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9a] =3D BIT(7), + [M1_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [M1_PMU_PERFCTR_UNKNOWN_bf] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c0] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + +static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CPU_CYCLES, + [PERF_COUNT_HW_INSTRUCTIONS] =3D M1_PMU_PERFCTR_INSTRUCTIONS, + /* No idea about the rest yet */ +}; + +/* sysfs definitions */ +static ssize_t m1_pmu_events_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *page) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr =3D container_of(attr, struct perf_pmu_events_attr, attr); + + return sprintf(page, "event=3D0x%04llx\n", pmu_attr->id); +} + +#define M1_PMU_EVENT_ATTR(name, config) \ + PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) + +static struct attribute *m1_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CPU_CYCLES), + M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INSTRUCTIONS), + NULL, +}; + +static const struct attribute_group m1_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D m1_pmu_event_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-7"); + +static struct attribute *m1_pmu_format_attrs[] =3D { + &format_attr_event.attr, + NULL, +}; + +static const struct attribute_group m1_pmu_format_attr_group =3D { + .name =3D "format", + .attrs =3D m1_pmu_format_attrs, +}; + +/* Low level accessors. No synchronisation. */ +#define PMU_READ_COUNTER(_idx) \ + case _idx: return read_sysreg_s(SYS_IMP_APL_PMC## _idx ##_EL1) + +#define PMU_WRITE_COUNTER(_val, _idx) \ + case _idx: \ + write_sysreg_s(_val, SYS_IMP_APL_PMC## _idx ##_EL1); \ + return + +static u64 m1_pmu_read_hw_counter(unsigned int index) +{ + switch (index) { + PMU_READ_COUNTER(0); + PMU_READ_COUNTER(1); + PMU_READ_COUNTER(2); + PMU_READ_COUNTER(3); + PMU_READ_COUNTER(4); + PMU_READ_COUNTER(5); + PMU_READ_COUNTER(6); + PMU_READ_COUNTER(7); + PMU_READ_COUNTER(8); + PMU_READ_COUNTER(9); + } + + BUG(); +} + +static void m1_pmu_write_hw_counter(u64 val, unsigned int index) +{ + switch (index) { + PMU_WRITE_COUNTER(val, 0); + PMU_WRITE_COUNTER(val, 1); + PMU_WRITE_COUNTER(val, 2); + PMU_WRITE_COUNTER(val, 3); + PMU_WRITE_COUNTER(val, 4); + PMU_WRITE_COUNTER(val, 5); + PMU_WRITE_COUNTER(val, 6); + PMU_WRITE_COUNTER(val, 7); + PMU_WRITE_COUNTER(val, 8); + PMU_WRITE_COUNTER(val, 9); + } + + BUG(); +} + +#define get_bit_offset(index, mask) (__ffs(mask) + (index)) + +static void __m1_pmu_enable_counter(unsigned int index, bool en) +{ + u64 val, bit; + + switch (index) { + case 0 ... 7: + bit =3D BIT(get_bit_offset(index, PMCR0_CNT_ENABLE_0_7)); + break; + case 8 ... 9: + bit =3D BIT(get_bit_offset(index - 8, PMCR0_CNT_ENABLE_8_9)); + break; + default: + BUG(); + } + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + + if (en) + val |=3D bit; + else + val &=3D ~bit; + + write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); +} + +static void m1_pmu_enable_counter(unsigned int index) +{ + __m1_pmu_enable_counter(index, true); +} + +static void m1_pmu_disable_counter(unsigned int index) +{ + __m1_pmu_enable_counter(index, false); +} + +static void __m1_pmu_enable_counter_interrupt(unsigned int index, bool en) +{ + u64 val, bit; + + switch (index) { + case 0 ... 7: + bit =3D BIT(get_bit_offset(index, PMCR0_PMI_ENABLE_0_7)); + break; + case 8 ... 9: + bit =3D BIT(get_bit_offset(index - 8, PMCR0_PMI_ENABLE_8_9)); + break; + default: + BUG(); + } + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + + if (en) + val |=3D bit; + else + val &=3D ~bit; + + write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); +} + +static void m1_pmu_enable_counter_interrupt(unsigned int index) +{ + __m1_pmu_enable_counter_interrupt(index, true); +} + +static void m1_pmu_disable_counter_interrupt(unsigned int index) +{ + __m1_pmu_enable_counter_interrupt(index, false); +} + +static void m1_pmu_configure_counter(unsigned int index, u8 event, + bool user, bool kernel) +{ + u64 val, user_bit, kernel_bit; + int shift; + + switch (index) { + case 0 ... 7: + user_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); + kernel_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7)); + break; + case 8 ... 9: + user_bit =3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9)); + kernel_bit =3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9)); + break; + default: + BUG(); + } + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR1_EL1); + + if (user) + val |=3D user_bit; + else + val &=3D ~user_bit; + + if (kernel) + val |=3D kernel_bit; + else + val &=3D ~kernel_bit; + + write_sysreg_s(val, SYS_IMP_APL_PMCR1_EL1); + + /* + * Counters 0 and 1 have fixed events. For anything else, + * place the event at the expected location in the relevant + * register (PMESR0 holds the event configuration for counters + * 2-5, resp. PMESR1 for counters 6-9). + */ + switch (index) { + case 0 ... 1: + break; + case 2 ... 5: + shift =3D (index - 2) * 8; + val =3D read_sysreg_s(SYS_IMP_APL_PMESR0_EL1); + val &=3D ~((u64)0xff << shift); + val |=3D (u64)event << shift; + write_sysreg_s(val, SYS_IMP_APL_PMESR0_EL1); + break; + case 6 ... 9: + shift =3D (index - 6) * 8; + val =3D read_sysreg_s(SYS_IMP_APL_PMESR1_EL1); + val &=3D ~((u64)0xff << shift); + val |=3D (u64)event << shift; + write_sysreg_s(val, SYS_IMP_APL_PMESR1_EL1); + break; + } +} + +/* arm_pmu backend */ +static void m1_pmu_enable_event(struct perf_event *event) +{ + bool user, kernel; + u8 evt; + + evt =3D event->hw.config_base & M1_PMU_CFG_EVENT; + user =3D event->hw.config_base & M1_PMU_CFG_COUNT_USER; + kernel =3D event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL; + + m1_pmu_disable_counter_interrupt(event->hw.idx); + m1_pmu_disable_counter(event->hw.idx); + isb(); + + m1_pmu_configure_counter(event->hw.idx, evt, user, kernel); + m1_pmu_enable_counter(event->hw.idx); + m1_pmu_enable_counter_interrupt(event->hw.idx); + isb(); +} + +static void m1_pmu_disable_event(struct perf_event *event) +{ + m1_pmu_disable_counter_interrupt(event->hw.idx); + m1_pmu_disable_counter(event->hw.idx); + isb(); +} + +static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu) +{ + struct pmu_hw_events *cpuc =3D this_cpu_ptr(cpu_pmu->hw_events); + struct pt_regs *regs; + u64 overflow, state; + int idx; + + overflow =3D read_sysreg_s(SYS_IMP_APL_PMSR_EL1); + if (!overflow) { + /* Spurious interrupt? */ + state =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + state &=3D ~PMCR0_IACT; + write_sysreg_s(state, SYS_IMP_APL_PMCR0_EL1); + isb(); + return IRQ_NONE; + } + + cpu_pmu->stop(cpu_pmu); + + regs =3D get_irq_regs(); + + for (idx =3D 0; idx < cpu_pmu->num_events; idx++) { + struct perf_event *event =3D cpuc->events[idx]; + struct perf_sample_data data; + + if (!event) + continue; + + armpmu_event_update(event); + perf_sample_data_init(&data, 0, event->hw.last_period); + if (!armpmu_event_set_period(event)) + continue; + + if (perf_event_overflow(event, &data, regs)) + m1_pmu_disable_event(event); + } + + cpu_pmu->start(cpu_pmu); + + return IRQ_HANDLED; +} + +static u64 m1_pmu_read_counter(struct perf_event *event) +{ + return m1_pmu_read_hw_counter(event->hw.idx); +} + +static void m1_pmu_write_counter(struct perf_event *event, u64 value) +{ + m1_pmu_write_hw_counter(value, event->hw.idx); + isb(); +} + +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + unsigned long evtype =3D event->hw.config_base & M1_PMU_CFG_EVENT; + unsigned long affinity =3D m1_pmu_event_affinity[evtype]; + int idx; + + /* + * Place the event on the first free counter that can count + * this event. + * + * We could do a better job if we had a view of all the events + * counting on the PMU at any given time, and by placing the + * most constraining events first. + */ + for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + if (!test_and_set_bit(idx, cpuc->used_mask)) + return idx; + } + + return -EAGAIN; +} + +static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + clear_bit(event->hw.idx, cpuc->used_mask); +} + +static void __m1_pmu_set_mode(u8 mode) +{ + u64 val; + + val =3D read_sysreg_s(SYS_IMP_APL_PMCR0_EL1); + val &=3D ~(PMCR0_IMODE | PMCR0_IACT); + val |=3D FIELD_PREP(PMCR0_IMODE, mode); + write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); + isb(); +} + +static void m1_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_FIQ); +} + +static void m1_pmu_stop(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_OFF); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + /* + * Although the counters are 48bit wide, bit 47 is what + * triggers the overflow interrupt. Advertise the counters + * being 47bit wide to mimick the behaviour of the ARM PMU. + */ + event->hw.flags |=3D ARMPMU_EVT_47BIT; + return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static void m1_pmu_reset(void *info) +{ + int i; + + __m1_pmu_set_mode(PMCR0_IMODE_OFF); + + for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + m1_pmu_disable_counter(i); + m1_pmu_disable_counter_interrupt(i); + m1_pmu_write_hw_counter(0, i); + } + + isb(); +} + +static int m1_pmu_set_event_filter(struct hw_perf_event *event, + struct perf_event_attr *attr) +{ + unsigned long config_base =3D 0; + + if (!attr->exclude_guest) + return -EINVAL; + if (!attr->exclude_kernel) + config_base |=3D M1_PMU_CFG_COUNT_KERNEL; + if (!attr->exclude_user) + config_base |=3D M1_PMU_CFG_COUNT_USER; + + event->config_base =3D config_base; + + return 0; +} + +static int m1_pmu_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->handle_irq =3D m1_pmu_handle_irq; + cpu_pmu->enable =3D m1_pmu_enable_event; + cpu_pmu->disable =3D m1_pmu_disable_event; + cpu_pmu->read_counter =3D m1_pmu_read_counter; + cpu_pmu->write_counter =3D m1_pmu_write_counter; + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->stop =3D m1_pmu_stop; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; + + cpu_pmu->num_events =3D M1_PMU_NR_COUNTERS; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; + return 0; +} + +/* Device driver gunk */ +static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_icestorm_pmu"; + return m1_pmu_init(cpu_pmu); +} + +static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_firestorm_pmu"; + return m1_pmu_init(cpu_pmu); +} + +static const struct of_device_id m1_pmu_of_device_ids[] =3D { + { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, + { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { }, +}; +MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); + +static int m1_pmu_device_probe(struct platform_device *pdev) +{ + return arm_pmu_device_probe(pdev, m1_pmu_of_device_ids, NULL); +} + +static struct platform_driver m1_pmu_driver =3D { + .driver =3D { + .name =3D "apple-m1-cpu-pmu", + .of_match_table =3D m1_pmu_of_device_ids, + .suppress_bind_attrs =3D true, + }, + .probe =3D m1_pmu_device_probe, +}; + +module_platform_driver(m1_pmu_driver); +MODULE_LICENSE("GPL v2"); --=20 2.30.2