From nobody Mon Jun 29 14:48:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7142C433F5 for ; Tue, 8 Feb 2022 13:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359867AbiBHNnG (ORCPT ); Tue, 8 Feb 2022 08:43:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359740AbiBHNnC (ORCPT ); Tue, 8 Feb 2022 08:43:02 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23672C03FEDA; Tue, 8 Feb 2022 05:43:00 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 218DIbJ9030151; Tue, 8 Feb 2022 07:18:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1644326317; bh=/MGvuszmvjvuoww9S0UFwwLOh22VmZKc/qKlwQzw13c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cmrR+mAm1UxlDW+C1pBgXYZsPCZBIpuSyLaIkd3H4w+4PXAfbZ79/MxlN7E/vy2Nb vuExyuYIHckanprgu+q/WKJKgTsVCyYssC97nKsgHYzGWgpsHaSiASc4rNNCQvViX1 YFmHSLgXH5QC331jPpV150QbkrzPuXAvmZ18G5s8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 218DIbob108633 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Feb 2022 07:18:37 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 8 Feb 2022 07:18:37 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 8 Feb 2022 07:18:37 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 218DIUCg117228; Tue, 8 Feb 2022 07:18:34 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar CC: , , Subject: [PATCH 1/5] soc: ti: k3-socinfo: Add AM62x JTAG ID Date: Tue, 8 Feb 2022 18:48:23 +0530 Message-ID: <20220208131827.1430086-2-vigneshr@ti.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220208131827.1430086-1-vigneshr@ti.com> References: <20220208131827.1430086-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add JTAG ID entry to help identify AM62x SoC in kernel. Signed-off-by: Vignesh Raghavendra --- drivers/soc/ti/k3-socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index b6b2150aca4e..91f441ee6175 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -42,6 +42,7 @@ static const struct k3_soc_id { { 0xBB6D, "J7200" }, { 0xBB38, "AM64X" }, { 0xBB75, "J721S2"}, + { 0xBB7E, "AM62X" }, }; =20 static int --=20 2.35.1 From nobody Mon Jun 29 14:48:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10991C433EF for ; Tue, 8 Feb 2022 14:05:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377563AbiBHOFC (ORCPT ); Tue, 8 Feb 2022 09:05:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359354AbiBHOE6 (ORCPT ); Tue, 8 Feb 2022 09:04:58 -0500 X-Greylist: delayed 1806 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 08 Feb 2022 06:04:58 PST Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19329C03FECE; Tue, 8 Feb 2022 06:04:57 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 218DIeSd060742; Tue, 8 Feb 2022 07:18:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1644326320; bh=ZiOjVY7LaUfOv8g+mkFWBADUqQCcc3Bnf8I/9D6ObNc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vl/cmvm0SW2BnbrNiXiTnd5fQniR+Wd34c8y0fmNcx4yoN3OZa4pr5u7bCCA7j0rE 9+N0QkrlXZpsCeVXZDpdt7xzcErDOIEDiyS1J8c5cgDrrWA28v8/+TFnD7B1YrUkLv 4tzLDTTD0dcwygGmqR70MlEq2ZlQEwM72QSSqJ1Q= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 218DIeB0101774 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Feb 2022 07:18:40 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 8 Feb 2022 07:18:40 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 8 Feb 2022 07:18:40 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 218DIUCh117228; Tue, 8 Feb 2022 07:18:37 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar CC: , , Subject: [PATCH 2/5] dt-bindings: arm: ti: Add bindings for AM625 SoC Date: Tue, 8 Feb 2022 18:48:24 +0530 Message-ID: <20220208131827.1430086-3-vigneshr@ti.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220208131827.1430086-1-vigneshr@ti.com> References: <20220208131827.1430086-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Nishanth Menon The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index b03c10fa2e7a..64f3db3ea9dd 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -53,6 +53,12 @@ properties: - ti,am642-sk - const: ti,am642 =20 + - description: K3 AM625 SoC + items: + - enum: + - ti,am625-sk + - const: ti,am625 + - description: K3 J721s2 SoC items: - enum: --=20 2.35.1 From nobody Mon Jun 29 14:48:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E290CC433FE for ; Tue, 8 Feb 2022 13:38:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357998AbiBHNiP (ORCPT ); Tue, 8 Feb 2022 08:38:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234428AbiBHNiO (ORCPT ); Tue, 8 Feb 2022 08:38:14 -0500 X-Greylist: delayed 666 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 08 Feb 2022 05:38:12 PST Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA702C03FED3; Tue, 8 Feb 2022 05:38:12 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 218DIhQO046504; Tue, 8 Feb 2022 07:18:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1644326324; bh=iStzcmCeH6NHwwtYWkOdsTwcq37ww3bknEMWCmn2Jrc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vcx15+9AT4rhPas6/wWk1ODpYYXV+uZMoqYJ8UU7TIRIDLRH6RNE/CxFGR4MtnrHP WHER/Svea9IW00Wnf+O/MRARAy1PEQQBqQloe4YKKU65uO5RAMQIKqod3BxcwFUKWa BDoR5j2byOThq/CnBk4sxK5acksp58I2Rrt9PoCg= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 218DIhLW044502 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Feb 2022 07:18:43 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 8 Feb 2022 07:18:43 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 8 Feb 2022 07:18:43 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 218DIUCi117228; Tue, 8 Feb 2022 07:18:40 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar CC: , , Subject: [PATCH 3/5] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62 Date: Tue, 8 Feb 2022 18:48:25 +0530 Message-ID: <20220208131827.1430086-4-vigneshr@ti.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220208131827.1430086-1-vigneshr@ti.com> References: <20220208131827.1430086-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Suman Anna Add pinctrl macros for AM62x SoCs. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the SoC dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Suman Anna Signed-off-by: Vignesh Raghavendra --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl= /k3.h index 63e038e36ca3..a5204ab91d3e 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -41,4 +41,7 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mu= xmode)) =20 +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode= )) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxm= ode)) + #endif --=20 2.35.1 From nobody Mon Jun 29 14:48:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E74F6C433FE for ; Tue, 8 Feb 2022 14:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377833AbiBHOH1 (ORCPT ); Tue, 8 Feb 2022 09:07:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238012AbiBHOH0 (ORCPT ); Tue, 8 Feb 2022 09:07:26 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81EDBC03FECE; Tue, 8 Feb 2022 06:07:23 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 218DImMC073828; Tue, 8 Feb 2022 07:18:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1644326328; bh=WjzeYYq507Zk5HWwVy2OJS6eoRL8He44WskqXrkpki4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bPaSUW4sLapOeKJWvpwHK0QBq9O0vKPfJlYYD01+bNAMF96Lb2vTlneO7ZP3Pkl1m d11LfYLkiQmNkk1bHE0PGZJfrho6HkU7Q3Hib7w4DePk4Gek9FyBeuUVKRed8gSr/S temeh6RyzNaJp39++g3n6KWuxqNLMc2DNrNXckDo= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 218DImUj101846 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Feb 2022 07:18:48 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 8 Feb 2022 07:18:47 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 8 Feb 2022 07:18:47 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 218DIUCj117228; Tue, 8 Feb 2022 07:18:44 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar CC: , , Subject: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC Date: Tue, 8 Feb 2022 18:48:26 +0530 Message-ID: <20220208131827.1430086-5-vigneshr@ti.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220208131827.1430086-1-vigneshr@ti.com> References: <20220208131827.1430086-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. This add bare minimum DT describing ARM compute clusters, Main, MCU and Wakeup domain and interconnects, UARTs and I2Cs to enable booting using ramdisk. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Co-developed-by: Suman Anna Signed-off-by: Suman Anna Co-developed-by: Nishanth Menon Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 263 +++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 36 +++ arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 41 ++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 104 ++++++++ arch/arm64/boot/dts/ti/k3-am625.dtsi | 103 ++++++++ 5 files changed, 547 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi new file mode 100644 index 000000000000..81d6d99ca180 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Main Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible =3D "arm,gic-v3"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xC0000>; /* GICR */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts =3D ; + + gic_its: msi-controller@1820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its =3D <0x1000000 0x400000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + main_conf: syscon@100000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x00 0x00100000 0x00 0x20000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x00 0x00100000 0x20000>; + }; + + dmss: bus@48000000 { + compatible =3D "simple-mfd"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges; + ranges =3D <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id =3D <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible =3D "ti,am654-secure-proxy"; + #mbox-cells =3D <1>; + reg-names =3D "target_data", "rt", "scfg"; + reg =3D <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names =3D "rx_012"; + interrupts =3D ; + }; + }; + + dmsc: system-controller@44043000 { + compatible =3D "ti,k2g-sci"; + ti,host-id =3D <12>; + mbox-names =3D "rx", "tx"; + mboxes=3D <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names =3D "debug_messages"; + reg =3D <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + compatible =3D "ti,sci-pm-domain"; + #power-domain-cells =3D <2>; + }; + + k3_clks: clock-controller { + compatible =3D "ti,k2g-sci-clk"; + #clock-cells =3D <2>; + }; + + k3_reset: reset-controller { + compatible =3D "ti,sci-reset"; + #reset-cells =3D <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible =3D "pinctrl-single"; + reg =3D <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02800000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 146 0>; + clock-names =3D "fclk"; + }; + + main_uart1: serial@2810000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02810000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 152 0>; + clock-names =3D "fclk"; + }; + + main_uart2: serial@2820000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02820000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 153 0>; + clock-names =3D "fclk"; + }; + + main_uart3: serial@2830000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02830000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 154 0>; + clock-names =3D "fclk"; + }; + + main_uart4: serial@2840000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02840000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 155 0>; + clock-names =3D "fclk"; + }; + + main_uart5: serial@2850000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02850000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 156 0>; + clock-names =3D "fclk"; + }; + + main_uart6: serial@2860000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02860000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 158 0>; + clock-names =3D "fclk"; + }; + + main_i2c0: i2c@20000000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20000000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 102 2>; + clock-names =3D "fck"; + }; + + main_i2c1: i2c@20010000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20010000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 103 2>; + clock-names =3D "fck"; + }; + + main_i2c2: i2c@20020000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20020000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 104 2>; + clock-names =3D "fck"; + }; + + main_i2c3: i2c@20030000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20030000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 105 2>; + clock-names =3D "fck"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible =3D "ti,sci-intr"; + reg =3D <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type =3D <1>; + interrupt-controller; + interrupt-parent =3D <&gic500>; + #interrupt-cells =3D <1>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <3>; + ti,interrupt-ranges =3D <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells =3D <2>; + ti,ngpio =3D <87>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 77 0>; + clock-names =3D "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x0 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells =3D <2>; + ti,ngpio =3D <88>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 78 0>; + clock-names =3D "gpio"; + }; + + hwspinlock: spinlock@2a000000 { + compatible =3D "ti,am64-hwspinlock"; + reg =3D <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells =3D <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible =3D "ti,am64-mailbox"; + reg =3D <0x00 0x29000000 0x00 0x200>; + interrupts =3D , + ; + #mbox-cells =3D <1>; + ti,mbox-num-users =3D <4>; + ti,mbox-num-fifos =3D <16>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am62-mcu.dtsi new file mode 100644 index 000000000000..9d210d55fc71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible =3D "pinctrl-single"; + reg =3D <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + }; + + mcu_uart0: serial@4a00000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x04a00000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 149 0>; + clock-names =3D "fclk"; + }; + + mcu_i2c0: i2c@4900000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x04900000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 106 2>; + clock-names =3D "fck"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi new file mode 100644 index 000000000000..4090134676cf --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x00 0x43000000 0x00 0x20000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible =3D "ti,am654-chipid"; + reg =3D <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x2b300000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 114 0>; + clock-names =3D "fclk"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x02b200000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 107 4>; + clock-names =3D "fck"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k= 3-am62.dtsi new file mode 100644 index 000000000000..f1a46be27c37 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62 SoC Family + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +#include +#include +#include +#include +#include + +/ { + model =3D "Texas Instruments K3 AM625 SoC"; + compatible =3D "ti,am625"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + cbass_main: bus@f0000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges =3D <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MM= Rs */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace= */ + <0x00 0x0070C000 0x00 0x0070C000 0x00 0x00000200>, /* USB1 debug trace= */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router = */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral= window */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second periphera= l window */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral= window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* sa3 sproxy data = */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* sa3 sproxy confi= g */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core w= indow */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core w= indow */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + + /* Wakeup Domain Range */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + + cbass_mcu: bus@4000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Periph= eral window */ + }; + + cbass_wakeup: bus@2b000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Periph= eral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62-main.dtsi" +#include "k3-am62-mcu.dtsi" +#include "k3-am62-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/= k3-am625.dtsi new file mode 100644 index 000000000000..887f31c23fef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/pdf/spruiv7 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; + +#include "k3-am62.dtsi" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; +}; --=20 2.35.1 From nobody Mon Jun 29 14:48:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1284C433F5 for ; Tue, 8 Feb 2022 13:38:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358330AbiBHNiU (ORCPT ); Tue, 8 Feb 2022 08:38:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350534AbiBHNiO (ORCPT ); Tue, 8 Feb 2022 08:38:14 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00412C03FECE; Tue, 8 Feb 2022 05:38:13 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 218DIpN4046522; Tue, 8 Feb 2022 07:18:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1644326331; bh=2Lrs2N/K+QHBIr8RlKTBV2F6IiXsG6T8xZqSAtgp5gs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GEAENK9IcN6NprWk200mpWbV45p6xoizIpjapBwbqpDfTU5eFCW5cIl29CvjZR8xe HCubRdr2FlwEGgW6Ka+DRLtQ2tevJ5tVcNGj1Fx52wO4KAB1yLXu74h72o7XC+hk15 v5r+30JlYpYa+BXmoisN21dk4+rdZA7Vp3t2mH1k= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 218DIpbQ108801 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Feb 2022 07:18:51 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 8 Feb 2022 07:18:50 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 8 Feb 2022 07:18:51 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 218DIUCk117228; Tue, 8 Feb 2022 07:18:48 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar CC: , , Subject: [PATCH 5/5] arm64: dts: ti: Add support for AM62-SK Date: Tue, 8 Feb 2022 18:48:27 +0530 Message-ID: <20220208131827.1430086-6-vigneshr@ti.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220208131827.1430086-1-vigneshr@ti.com> References: <20220208131827.1430086-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nishanth Menon AM62 StarterKit (SK) board is a low cost, small form factor board designed for TI=E2=80=99s AM625 SoC. It supports the following interfaces: * 2 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable =C2=B5SD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 15-pin CSI header Add basic support for AM62-SK. Schematics: https://www.ti.com/lit/zip/sprr448 Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am625-sk.dts | 206 +++++++++++++++++++++++++ 2 files changed, 208 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 90be511bc4d0..02e5d80344d0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb =20 dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-sk.dtb + +dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts new file mode 100644 index 000000000000..9a6ff601f44d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 SK: https://www.ti.com/lit/zip/sprr448 + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; + +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible =3D "ti,am625-sk", "ti,am625"; + model =3D "Texas Instruments AM625 SK"; + + aliases { + serial2 =3D &main_uart0; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + bootargs =3D "console=3DttyS2,115200n8 earlycon=3Dns16550a,mmio32,0x0280= 0000"; + }; + + memory@80000000 { + device_type =3D "memory"; + /* 2G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + alignment =3D <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment =3D <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x200000>; + no-map; + }; + }; + + vmain_pd: fixed-regulator-vmain-pd { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vmain_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: fixedregulator-vcc5v0 { + /* Output of LM34936 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: fixedregulator-vcc-3v3-sys { + /* output of LM61460-Q1 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usr_led_pins_default>; + + led-0 { + label =3D "am62-sk:green:heartbeat"; + gpios =3D <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + default-state =3D "off"; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status =3D "reserved"; +}; + +&mcu_uart0 { + status =3D "disabled"; +}; + +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status =3D "reserved"; +}; + +&main_uart2 { + status =3D "disabled"; +}; + +&main_uart3 { + status =3D "disabled"; +}; + +&main_uart4 { + status =3D "disabled"; +}; + +&main_uart5 { + status =3D "disabled"; +}; + +&main_uart6 { + status =3D "disabled"; +}; + +&mcu_i2c0 { + status =3D "disabled"; +}; + +&wkup_i2c0 { + status =3D "disabled"; +}; + +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; +}; + +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <400000>; +}; + +&main_i2c2 { + status =3D "disabled"; +}; + +&main_i2c3 { + status =3D "disabled"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; --=20 2.35.1