From nobody Thu Nov 14 19:32:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E99BDC3527D for ; Tue, 8 Feb 2022 13:16:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349741AbiBHNQG (ORCPT ); Tue, 8 Feb 2022 08:16:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358096AbiBHMky (ORCPT ); Tue, 8 Feb 2022 07:40:54 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10B76C03FECA for ; Tue, 8 Feb 2022 04:40:54 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id om7so2925708pjb.5 for ; Tue, 08 Feb 2022 04:40:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sJY5Um+e3Zhwa51B9/uiFlDKmQ6du7mYuS31VfH399Q=; b=SDUVezZ2U7t3EKc/zBv6B+CFLef3IyaUyi9jwAdEPdFHZ4OhbAldQvTrcFyF4SpMpw XbL84xhIgwY3GULLblL6VThNKqcL6YfvDQmb6FFmCF/+07WiwmAJYzh3n0JhpmU5gUF4 b6b0N6R1MGh0WZrzWv0zOuyg3Nen/apn0TFfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sJY5Um+e3Zhwa51B9/uiFlDKmQ6du7mYuS31VfH399Q=; b=0bNaNg5Av2AMpTyY1PFG4A3RgTF3xg6qhzOrabTaL3RHR4IYoKw5x9Q/A/xJSrDa24 SQbLKI5Jtb6dsV3hIFpLdDjAeqfG8mX2FopPmtQ2DO4I530BQnUEjKfF9O+OGhRR9ffu rwaSpfSLamQzDw9LBBV24EHvyAPo0uhIRcW8jZa1UOaG+le91yTWqMBkIv3vOeKCGlxK 43VhgLzc1vn+SfzHHx1JYr9JTUzh/7M3jwr+olJ98l5dZA3dePlJeb4Rmf+krCEvDvPc mYVfr45QC34xNvyADp95xOeqP1PaoAepdP3YxgPvxqKZSmDYHYzf2H7uLM9wyCynhvQI iMDg== X-Gm-Message-State: AOAM533aK9CIf6lImJBViRQe97M4NocX3o+fyTxTKqLp1G6Fmp/ZZPYk NLPmV+sP1GR0l+zDHbLtuSUmIQ== X-Google-Smtp-Source: ABdhPJzIptVfF9/Nr+7xAEGmtgdzohLMSJf77H6U3m66Hps5mBQCBofvJaIC8Rc4OcVkb/jxNFfcfA== X-Received: by 2002:a17:902:7e06:: with SMTP id b6mr4461526plm.58.1644324053538; Tue, 08 Feb 2022 04:40:53 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:41b6:813e:c823:609c]) by smtp.gmail.com with ESMTPSA id h11sm15056939pfe.214.2022.02.08.04.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Feb 2022 04:40:53 -0800 (PST) From: Chen-Yu Tsai To: Stephen Boyd , Michael Turquette , Matthias Brugger Cc: Chen-Yu Tsai , Chun-Jie Chen , AngeloGioacchino Del Regno , Miles Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/31] clk: mediatek: gate: Consolidate gate type clk related code Date: Tue, 8 Feb 2022 20:40:05 +0800 Message-Id: <20220208124034.414635-3-wenst@chromium.org> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog In-Reply-To: <20220208124034.414635-1-wenst@chromium.org> References: <20220208124034.414635-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Right now some bits of the gate type clk code are in clk-gate.[ch], but other bits are in clk-mtk.[ch]. This is different from the cpumux and mux type clks, for which all of the code are found in the same files. Move the functions that register multiple clks from a given list, mtk_clk_register_gates_with_dev() and mtk_clk_register_gates(), to clk-gate.[ch] to consolidate all the code for the gate type clks. This commit only moves code with minor whitespace fixups to correct the code style. Further improvements, such as internalizing various functions and structures will be done in later commits. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chun-Jie Chen --- drivers/clk/mediatek/clk-gate.c | 53 ++++++++++++++++++++++++++++++++- drivers/clk/mediatek/clk-gate.h | 25 ++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 51 ------------------------------- drivers/clk/mediatek/clk-mtk.h | 25 ---------------- 4 files changed, 77 insertions(+), 77 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index 5d88b428565b..54921768bfba 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -11,9 +11,9 @@ #include #include #include +#include #include =20 -#include "clk-mtk.h" #include "clk-gate.h" =20 static u32 mtk_get_clockgating(struct clk_hw *hw) @@ -182,4 +182,55 @@ struct clk *mtk_clk_register_gate( } EXPORT_SYMBOL_GPL(mtk_clk_register_gate); =20 +int mtk_clk_register_gates_with_dev(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data, + struct device *dev) +{ + int i; + struct clk *clk; + struct regmap *regmap; + + if (!clk_data) + return -ENOMEM; + + regmap =3D device_node_to_regmap(node); + if (IS_ERR(regmap)) { + pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); + return PTR_ERR(regmap); + } + + for (i =3D 0; i < num; i++) { + const struct mtk_gate *gate =3D &clks[i]; + + if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) + continue; + + clk =3D mtk_clk_register_gate(gate->name, gate->parent_name, + regmap, + gate->regs->set_ofs, + gate->regs->clr_ofs, + gate->regs->sta_ofs, + gate->shift, gate->ops, + gate->flags, dev); + + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %pe\n", gate->name, clk); + continue; + } + + clk_data->clks[gate->id] =3D clk; + } + + return 0; +} + +int mtk_clk_register_gates(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data) +{ + return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); +} +EXPORT_SYMBOL_GPL(mtk_clk_register_gates); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gat= e.h index 3c3329ec54b7..432b571d23b3 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -43,6 +43,22 @@ struct clk *mtk_clk_register_gate( unsigned long flags, struct device *dev); =20 +struct mtk_gate_regs { + u32 sta_ofs; + u32 clr_ofs; + u32 set_ofs; +}; + +struct mtk_gate { + int id; + const char *name; + const char *parent_name; + const struct mtk_gate_regs *regs; + int shift; + const struct clk_ops *ops; + unsigned long flags; +}; + #define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ _ops, _flags) { \ .id =3D _id, \ @@ -57,4 +73,13 @@ struct clk *mtk_clk_register_gate( #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0) =20 +int mtk_clk_register_gates(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data); + +int mtk_clk_register_gates_with_dev(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data, + struct device *dev); + #endif /* __DRV_CLK_GATE_H */ diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 519a461cbb6f..0c5db3c71fdd 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -106,57 +106,6 @@ void mtk_clk_register_factors(const struct mtk_fixed_f= actor *clks, } EXPORT_SYMBOL_GPL(mtk_clk_register_factors); =20 -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, - int num, struct clk_onecell_data *clk_data, - struct device *dev) -{ - int i; - struct clk *clk; - struct regmap *regmap; - - if (!clk_data) - return -ENOMEM; - - regmap =3D device_node_to_regmap(node); - if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); - return PTR_ERR(regmap); - } - - for (i =3D 0; i < num; i++) { - const struct mtk_gate *gate =3D &clks[i]; - - if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) - continue; - - clk =3D mtk_clk_register_gate(gate->name, gate->parent_name, - regmap, - gate->regs->set_ofs, - gate->regs->clr_ofs, - gate->regs->sta_ofs, - gate->shift, gate->ops, gate->flags, dev); - - if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %pe\n", gate->name, clk); - continue; - } - - clk_data->clks[gate->id] =3D clk; - } - - return 0; -} - -int mtk_clk_register_gates(struct device_node *node, - const struct mtk_gate *clks, - int num, struct clk_onecell_data *clk_data) -{ - return mtk_clk_register_gates_with_dev(node, - clks, num, clk_data, NULL); -} -EXPORT_SYMBOL_GPL(mtk_clk_register_gates); - struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 0ff289d93452..bdec7dc5e07a 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -150,31 +150,6 @@ void mtk_clk_register_composites(const struct mtk_comp= osite *mcs, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); =20 -struct mtk_gate_regs { - u32 sta_ofs; - u32 clr_ofs; - u32 set_ofs; -}; - -struct mtk_gate { - int id; - const char *name; - const char *parent_name; - const struct mtk_gate_regs *regs; - int shift; - const struct clk_ops *ops; - unsigned long flags; -}; - -int mtk_clk_register_gates(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_onecell_data *clk_data); - -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, - int num, struct clk_onecell_data *clk_data, - struct device *dev); - struct mtk_clk_divider { int id; const char *name; --=20 2.35.0.263.gb82422642f-goog