From nobody Thu Nov 14 19:20:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1102C3527C for ; Tue, 8 Feb 2022 13:16:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350228AbiBHNQM (ORCPT ); Tue, 8 Feb 2022 08:16:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358330AbiBHMlS (ORCPT ); Tue, 8 Feb 2022 07:41:18 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF17BC03FEC0 for ; Tue, 8 Feb 2022 04:41:17 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id on2so7739315pjb.4 for ; Tue, 08 Feb 2022 04:41:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ucbCQXspAieTR5IRJ88apHKs0Oo+TcGwEm7YM7yoBFE=; b=oHY673UW7vPbSg3PGRcTlPVTR8Y6tSg1ME93cddkHRfN3evzBumjNKPjS9MMXetvGz cyaPopBpjfAlMvtxCgg+GHb5cpygQczzim0Yug0Mh8xdzazLH7miTaVhCIIXd9h9QdUn 7TbUW0Nsppw/Izk8VE5AGFZaPWyj9T5IpYftw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ucbCQXspAieTR5IRJ88apHKs0Oo+TcGwEm7YM7yoBFE=; b=o8tN4vftmkweCrp95tqcHqnrZhYStWnVhGk4dj9ZqJXkw2gqufOr/X/7zderbVgOFK ZnVji4xn40CpJyX/PeyTr2287VtKDJB0DZFcViyqTti407BBCaqGnTyQQn6tdlChR9Rc PnzwBHSX1MmU/8IpGGeqsQAYuU95TV4YlUWSEpPBd+dHDweToJDN7/Fkp5uTRZEOgQZ/ Kq+6ibtcl0+TnghWLO9lReYWRPOteuiYrJktwW6ezTmLTQySTg4HuuzbEkvqjf620hcq 2ehkG3SEdeCE7OadnLTJB3xfpGw96wL4u7SBtnYt8Kw46KKxD5aOwWGCuxrUAvg15eLr bZxA== X-Gm-Message-State: AOAM532N8Iu9MEyyYxVgnR3Dkf8E41s98tmI28g6tboYM522JTir2Pdc MBLSRVClMb++7Ye9Z7TZc3fMMA== X-Google-Smtp-Source: ABdhPJxdkJmcSGDXCQW6yjqpsQN+RjwrIexHzblWHmuV0z4WVMDQoML2GrmGp6e07CaXZlQ30GG28g== X-Received: by 2002:a17:902:7048:: with SMTP id h8mr4338247plt.40.1644324077323; Tue, 08 Feb 2022 04:41:17 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:41b6:813e:c823:609c]) by smtp.gmail.com with ESMTPSA id h11sm15056939pfe.214.2022.02.08.04.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Feb 2022 04:41:17 -0800 (PST) From: Chen-Yu Tsai To: Stephen Boyd , Michael Turquette , Matthias Brugger Cc: Chen-Yu Tsai , Chun-Jie Chen , AngeloGioacchino Del Regno , Miles Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 13/31] clk: mediatek: pll: Implement unregister API Date: Tue, 8 Feb 2022 20:40:16 +0800 Message-Id: <20220208124034.414635-14-wenst@chromium.org> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog In-Reply-To: <20220208124034.414635-1-wenst@chromium.org> References: <20220208124034.414635-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PLL clk type within the MediaTek clk driver library only has a register function, and no corresponding unregister function. This means there is no way for its users to properly implement cleanup and removal. Add a matching unregister function for the PLL type clk. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chun-Jie Chen --- drivers/clk/mediatek/clk-pll.c | 55 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-pll.h | 2 ++ 2 files changed, 57 insertions(+) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 64f59554bc9b..b54e33b75d4e 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -360,6 +360,21 @@ static struct clk *mtk_clk_register_pll(const struct m= tk_pll_data *data, return clk; } =20 +static void mtk_clk_unregister_pll(struct clk *clk) +{ + struct clk_hw *hw; + struct mtk_clk_pll *pll; + + hw =3D __clk_get_hw(clk); + if (!hw) + return; + + pll =3D to_mtk_clk_pll(hw); + + clk_unregister(clk); + kfree(pll); +} + void mtk_clk_register_plls(struct device_node *node, const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *= clk_data) { @@ -388,4 +403,44 @@ void mtk_clk_register_plls(struct device_node *node, } EXPORT_SYMBOL_GPL(mtk_clk_register_plls); =20 +static __iomem void *mtk_clk_pll_get_base(struct clk *clk, + const struct mtk_pll_data *data) +{ + struct clk_hw *hw =3D __clk_get_hw(clk); + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); + + return pll->base_addr - data->reg; +} + +void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data) +{ + __iomem void *base =3D NULL; + int i; + + if (!clk_data) + return; + + for (i =3D num_plls; i > 0; i--) { + const struct mtk_pll_data *pll =3D &plls[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[pll->id])) + continue; + + /* + * This is quite ugly but unfortunately the clks don't have + * any device tied to them, so there's no place to store the + * pointer to the I/O region base address. We have to fetch + * it from one of the registered clks. + */ + base =3D mtk_clk_pll_get_base(clk_data->clks[pll->id], pll); + + mtk_clk_unregister_pll(clk_data->clks[pll->id]); + clk_data->clks[pll->id] =3D ERR_PTR(-ENOENT); + } + + iounmap(base); +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index d01b0c38311d..a889b1e472e7 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -51,5 +51,7 @@ struct mtk_pll_data { void mtk_clk_register_plls(struct device_node *node, const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data); +void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data); =20 #endif /* __DRV_CLK_MTK_PLL_H */ --=20 2.35.0.263.gb82422642f-goog