From nobody Mon Jun 29 16:02:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBDB5C4167B for ; Mon, 7 Feb 2022 19:02:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235814AbiBGTAp (ORCPT ); Mon, 7 Feb 2022 14:00:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237961AbiBGS6b (ORCPT ); Mon, 7 Feb 2022 13:58:31 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 889A2C0401E2 for ; Mon, 7 Feb 2022 10:58:30 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id m18so347045lfq.4 for ; Mon, 07 Feb 2022 10:58:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=snejp.pl; s=gmail; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zN5qVhMXDmfd9ze7N6KYypaBmSnSMGRHWVYJBUbt0Fs=; b=IWr4AlZQx5VFs6t4FDnOW2eeW8c7pFK8KHaR1xtBOk1//ZldLCNNtm3t5rdP6B0LqP CnViBpQnI4gpipP6s0j94bA7oTGyVUg6Fsogxig7Su8pMRRlyyzvsDaa+c3MN3GC9JS4 4AiRWNq0hXcykYFDbkaZUfuxM//eVmgnId+yfNIzrt6Sjh6bDAU8avuGrT5QvRqoaJvY x2iYV0W225o+N7LP3JJYo5+hYc0Rf032z0BStxNWLoI6PpUj69RLoLlcstv7yh9jE4ZE 8Crr5eIkIRju8GbmSlzTmg4KFAlxZfg2SiFCLAqdvsTd0IZahEnw+PF7tr6QZ2pc2ey0 7tqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zN5qVhMXDmfd9ze7N6KYypaBmSnSMGRHWVYJBUbt0Fs=; b=VZbKLTg4aEopruzp4LaFgJgGnHgyvSGV46UD2mVvYQRwaYGSgsYH8NGsYeozl//bkK mbFkopkNchIYZkoKKmsTE+oaXLtD0gPxIPdvfyqhTNYkuDsfp3jxItBYtZrdpUJIwd3F OXUwn9eJOhVGYd6n8gA4scRHBwikSJUgedEaIeywEgUpURYF5/fgoFg0ty9idFZG5960 sklUY92HPX3/j9DuixGWccVcD3DX9FYnw+niJlJd6um9vsJiiu0ICBCtIrBshDOs7cwy Hy+G0AWEwzX9Oxv/b4sxuIdxzmR1bAE7la62CHydPqJ5HyNporUcfyhkmq0xHLiJRObP oqPQ== X-Gm-Message-State: AOAM533xohwUBteiaGZX9alAMEsAOoBPVIqxojh0GqDtpyC/HBXpD5Bj 2oTyyKhbWzyFy3jSXGADt4VLPQ== X-Google-Smtp-Source: ABdhPJzmEegeXsttXRDan5LZ+7Vo55qdSB1sSrtL6aE83GumiObdYLqb+O98qCnGrWw079yFbRlkGg== X-Received: by 2002:ac2:530c:: with SMTP id c12mr594430lfh.122.1644260308964; Mon, 07 Feb 2022 10:58:28 -0800 (PST) Received: from Lenovo330 ([82.160.139.10]) by smtp.gmail.com with ESMTPSA id k10sm1599061lfo.187.2022.02.07.10.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Feb 2022 10:58:28 -0800 (PST) Received: from localhost (Lenovo330 [local]) by Lenovo330 (OpenSMTPD) with ESMTPA id 2e966975; Mon, 7 Feb 2022 18:58:26 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Jeffrey Hugo , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Luca Weiss Cc: Bartosz Dudziak Subject: [PATCH v2 1/2] dt-bindings: clock: Add support for the MSM8226 mmcc Date: Mon, 7 Feb 2022 19:54:10 +0100 Message-Id: <20220207185411.19118-2-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220207185411.19118-1-bartosz.dudziak@snejp.pl> References: <20220207185411.19118-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the multimedia clock controller found on MSM8226. Signed-off-by: Bartosz Dudziak Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/qcom,mmcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Docum= entation/devicetree/bindings/clock/qcom,mmcc.yaml index 68fdc3d498..4b79e89fd1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,mmcc-apq8064 - qcom,mmcc-apq8084 + - qcom,mmcc-msm8226 - qcom,mmcc-msm8660 - qcom,mmcc-msm8960 - qcom,mmcc-msm8974 --=20 2.25.1 From nobody Mon Jun 29 16:02:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22FF3C433EF for ; Mon, 7 Feb 2022 19:02:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235055AbiBGTAW (ORCPT ); Mon, 7 Feb 2022 14:00:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234258AbiBGS6e (ORCPT ); Mon, 7 Feb 2022 13:58:34 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 495B1C0401DA for ; Mon, 7 Feb 2022 10:58:33 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id o12so28691301lfg.12 for ; Mon, 07 Feb 2022 10:58:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=snejp.pl; s=gmail; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/mWZr+uDc9QxBiJVSzk1tr/WIMti2XTI+KWpafLMe3I=; b=icY/8gaGucD72W9gS3YLloXyXjUOUJFJBOu46a2nKHMXnRa2sS8eQ56yVRDV9xIbhl UUaqbcu8nwokIA+vq4ze3g40/jf/CP+9H3nRH3O/XGWMNP5THX5lzEephD9mjWPxx8d0 yvik0a1cbvfGaOWPDs7TQDS9TcJk+0LdNmzWP6lbd0AN5i4vsNWRvlXuky3a8wZUwmvO 5Ub8Ce6O3kex/YMroaBbB953+2TZ+77aXy2WjmkodLQM7B0/53Oufs+kgDXjnG0gyMBz 1ecdwfrdxknujSosRi1mkNIouToW0KMaq7KiK83kcZ/SgQGIkGaYG4ggOTVJnyrnm8UG ZmhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/mWZr+uDc9QxBiJVSzk1tr/WIMti2XTI+KWpafLMe3I=; b=Zakueli4ZrEFMohGKei4Xnov4exLfVp0/yM3l6O/YlgKqgX7qCmyNoZljxuJNBjsDx zTnOUhiFEtqzN9zerl6A/+m8P30mqxS8Tmi5WdvkONnZgqdIDdPr3OnkQbcibX1UbACU /CAcuP03J4Xt1fS3e5oUO/oSEdzbbrN6CmFpHJhrD8V7cNYO/wX7eUcLGXdf4SDqpyra P5llW0LmHNRAUlgCiD7Nmsw7KcI0XVPpqz4PnbnX0La8E7TFnTxMPATk2qQcEPEPa4iF lWO88v6WOWExO1TFH1hNwAz/7lpctoUqvEd8ogJ+PwpP44amhve1MMraIxLsRZSYghkg XehA== X-Gm-Message-State: AOAM533yK+u5EDVNmAVVfMzhCFox7zR3brVjdKsPA1bvJgnfsiZLXDz7 qqquNJVbPkeDNKd8YdQL9/D30Q== X-Google-Smtp-Source: ABdhPJzg3IfbSNSJsDg9Rs7wbThdg0FsX4J/lu4sVmhVjukW6lxQdrVLEf2zKygUUT9TxfYrbGw1sA== X-Received: by 2002:a05:6512:2606:: with SMTP id bt6mr604545lfb.187.1644260311631; Mon, 07 Feb 2022 10:58:31 -0800 (PST) Received: from Lenovo330 ([82.160.139.10]) by smtp.gmail.com with ESMTPSA id k10sm1599061lfo.187.2022.02.07.10.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Feb 2022 10:58:29 -0800 (PST) Received: from localhost (Lenovo330 [local]) by Lenovo330 (OpenSMTPD) with ESMTPA id 74b98d09; Mon, 7 Feb 2022 18:58:26 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Jeffrey Hugo , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Luca Weiss Cc: Bartosz Dudziak Subject: [PATCH v2 2/2] clk: qcom: Add MSM8226 Multimedia Clock Controller support Date: Mon, 7 Feb 2022 19:54:11 +0100 Message-Id: <20220207185411.19118-3-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220207185411.19118-1-bartosz.dudziak@snejp.pl> References: <20220207185411.19118-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Modify the existing MSM8974 multimedia clock controller driver to support the MMCC found on MSM8226 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Bartosz Dudziak --- drivers/clk/qcom/mmcc-msm8974.c | 206 +++++++++++++++++++++++++++++++- 1 file changed, 201 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm897= 4.c index a1552b6771..f74662925a 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -257,6 +257,18 @@ static struct clk_rcg2 mmss_ahb_clk_src =3D { }, }; =20 +static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0, 16, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(75000000, P_GPLL0, 8, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(150000000, P_GPLL0, 4, 0, 0), + F(200000000, P_MMPLL0, 4, 0, 0), + F(266666666, P_MMPLL0, 3, 0, 0), + { } +}; + static struct freq_tbl ftbl_mmss_axi_clk[] =3D { F( 19200000, P_XO, 1, 0, 0), F( 37500000, P_GPLL0, 16, 0, 0), @@ -364,6 +376,23 @@ static struct clk_rcg2 csi3_clk_src =3D { }, }; =20 +static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] =3D { + F(37500000, P_GPLL0, 16, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(60000000, P_GPLL0, 10, 0, 0), + F(80000000, P_GPLL0, 7.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(109090000, P_GPLL0, 5.5, 0, 0), + F(133330000, P_GPLL0, 4.5, 0, 0), + F(150000000, P_GPLL0, 4, 0, 0), + F(200000000, P_GPLL0, 3, 0, 0), + F(228570000, P_MMPLL0, 3.5, 0, 0), + F(266670000, P_MMPLL0, 3, 0, 0), + F(320000000, P_MMPLL0, 2.5, 0, 0), + F(400000000, P_MMPLL0, 2, 0, 0), + { } +}; + static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] =3D { F(37500000, P_GPLL0, 16, 0, 0), F(50000000, P_GPLL0, 12, 0, 0), @@ -407,6 +436,18 @@ static struct clk_rcg2 vfe1_clk_src =3D { }, }; =20 +static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] =3D { + F(37500000, P_GPLL0, 16, 0, 0), + F(60000000, P_GPLL0, 10, 0, 0), + F(75000000, P_GPLL0, 8, 0, 0), + F(92310000, P_GPLL0, 6.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(133330000, P_MMPLL0, 6, 0, 0), + F(177780000, P_MMPLL0, 4.5, 0, 0), + F(200000000, P_MMPLL0, 4, 0, 0), + { } +}; + static struct freq_tbl ftbl_mdss_mdp_clk[] =3D { F(37500000, P_GPLL0, 16, 0, 0), F(60000000, P_GPLL0, 10, 0, 0), @@ -513,6 +554,14 @@ static struct clk_rcg2 pclk1_clk_src =3D { }, }; =20 +static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] =3D { + F(66700000, P_GPLL0, 9, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(133330000, P_MMPLL0, 6, 0, 0), + F(160000000, P_MMPLL0, 5, 0, 0), + { } +}; + static struct freq_tbl ftbl_venus0_vcodec0_clk[] =3D { F(50000000, P_GPLL0, 12, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), @@ -593,6 +642,13 @@ static struct clk_rcg2 camss_gp1_clk_src =3D { }, }; =20 +static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 5, 1, 5), + F(66670000, P_GPLL0, 9, 0, 0), + { } +}; + static struct freq_tbl ftbl_camss_mclk0_3_clk[] =3D { F(4800000, P_XO, 4, 0, 0), F(6000000, P_GPLL0, 10, 1, 10), @@ -705,6 +761,15 @@ static struct clk_rcg2 csi2phytimer_clk_src =3D { }, }; =20 +static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] =3D { + F(133330000, P_GPLL0, 4.5, 0, 0), + F(150000000, P_GPLL0, 4, 0, 0), + F(266670000, P_MMPLL0, 3, 0, 0), + F(320000000, P_MMPLL0, 2.5, 0, 0), + F(400000000, P_MMPLL0, 2, 0, 0), + { } +}; + static struct freq_tbl ftbl_camss_vfe_cpp_clk[] =3D { F(133330000, P_GPLL0, 4.5, 0, 0), F(266670000, P_MMPLL0, 3, 0, 0), @@ -2366,6 +2431,116 @@ static struct gdsc oxilicx_gdsc =3D { .pwrsts =3D PWRSTS_OFF_ON, }; =20 +static struct clk_regmap *mmcc_msm8226_clocks[] =3D { + [MMSS_AHB_CLK_SRC] =3D &mmss_ahb_clk_src.clkr, + [MMSS_AXI_CLK_SRC] =3D &mmss_axi_clk_src.clkr, + [MMPLL0] =3D &mmpll0.clkr, + [MMPLL0_VOTE] =3D &mmpll0_vote, + [MMPLL1] =3D &mmpll1.clkr, + [MMPLL1_VOTE] =3D &mmpll1_vote, + [CSI0_CLK_SRC] =3D &csi0_clk_src.clkr, + [CSI1_CLK_SRC] =3D &csi1_clk_src.clkr, + [VFE0_CLK_SRC] =3D &vfe0_clk_src.clkr, + [MDP_CLK_SRC] =3D &mdp_clk_src.clkr, + [JPEG0_CLK_SRC] =3D &jpeg0_clk_src.clkr, + [PCLK0_CLK_SRC] =3D &pclk0_clk_src.clkr, + [VCODEC0_CLK_SRC] =3D &vcodec0_clk_src.clkr, + [CCI_CLK_SRC] =3D &cci_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] =3D &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] =3D &camss_gp1_clk_src.clkr, + [MCLK0_CLK_SRC] =3D &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] =3D &mclk1_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] =3D &csi0phytimer_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] =3D &csi1phytimer_clk_src.clkr, + [CPP_CLK_SRC] =3D &cpp_clk_src.clkr, + [BYTE0_CLK_SRC] =3D &byte0_clk_src.clkr, + [ESC0_CLK_SRC] =3D &esc0_clk_src.clkr, + [VSYNC_CLK_SRC] =3D &vsync_clk_src.clkr, + [CAMSS_CCI_CCI_AHB_CLK] =3D &camss_cci_cci_ahb_clk.clkr, + [CAMSS_CCI_CCI_CLK] =3D &camss_cci_cci_clk.clkr, + [CAMSS_CSI0_AHB_CLK] =3D &camss_csi0_ahb_clk.clkr, + [CAMSS_CSI0_CLK] =3D &camss_csi0_clk.clkr, + [CAMSS_CSI0PHY_CLK] =3D &camss_csi0phy_clk.clkr, + [CAMSS_CSI0PIX_CLK] =3D &camss_csi0pix_clk.clkr, + [CAMSS_CSI0RDI_CLK] =3D &camss_csi0rdi_clk.clkr, + [CAMSS_CSI1_AHB_CLK] =3D &camss_csi1_ahb_clk.clkr, + [CAMSS_CSI1_CLK] =3D &camss_csi1_clk.clkr, + [CAMSS_CSI1PHY_CLK] =3D &camss_csi1phy_clk.clkr, + [CAMSS_CSI1PIX_CLK] =3D &camss_csi1pix_clk.clkr, + [CAMSS_CSI1RDI_CLK] =3D &camss_csi1rdi_clk.clkr, + [CAMSS_CSI_VFE0_CLK] =3D &camss_csi_vfe0_clk.clkr, + [CAMSS_GP0_CLK] =3D &camss_gp0_clk.clkr, + [CAMSS_GP1_CLK] =3D &camss_gp1_clk.clkr, + [CAMSS_ISPIF_AHB_CLK] =3D &camss_ispif_ahb_clk.clkr, + [CAMSS_JPEG_JPEG0_CLK] =3D &camss_jpeg_jpeg0_clk.clkr, + [CAMSS_JPEG_JPEG_AHB_CLK] =3D &camss_jpeg_jpeg_ahb_clk.clkr, + [CAMSS_JPEG_JPEG_AXI_CLK] =3D &camss_jpeg_jpeg_axi_clk.clkr, + [CAMSS_MCLK0_CLK] =3D &camss_mclk0_clk.clkr, + [CAMSS_MCLK1_CLK] =3D &camss_mclk1_clk.clkr, + [CAMSS_MICRO_AHB_CLK] =3D &camss_micro_ahb_clk.clkr, + [CAMSS_PHY0_CSI0PHYTIMER_CLK] =3D &camss_phy0_csi0phytimer_clk.clkr, + [CAMSS_PHY1_CSI1PHYTIMER_CLK] =3D &camss_phy1_csi1phytimer_clk.clkr, + [CAMSS_TOP_AHB_CLK] =3D &camss_top_ahb_clk.clkr, + [CAMSS_VFE_CPP_AHB_CLK] =3D &camss_vfe_cpp_ahb_clk.clkr, + [CAMSS_VFE_CPP_CLK] =3D &camss_vfe_cpp_clk.clkr, + [CAMSS_VFE_VFE0_CLK] =3D &camss_vfe_vfe0_clk.clkr, + [CAMSS_VFE_VFE_AHB_CLK] =3D &camss_vfe_vfe_ahb_clk.clkr, + [CAMSS_VFE_VFE_AXI_CLK] =3D &camss_vfe_vfe_axi_clk.clkr, + [MDSS_AHB_CLK] =3D &mdss_ahb_clk.clkr, + [MDSS_AXI_CLK] =3D &mdss_axi_clk.clkr, + [MDSS_BYTE0_CLK] =3D &mdss_byte0_clk.clkr, + [MDSS_ESC0_CLK] =3D &mdss_esc0_clk.clkr, + [MDSS_MDP_CLK] =3D &mdss_mdp_clk.clkr, + [MDSS_MDP_LUT_CLK] =3D &mdss_mdp_lut_clk.clkr, + [MDSS_PCLK0_CLK] =3D &mdss_pclk0_clk.clkr, + [MDSS_VSYNC_CLK] =3D &mdss_vsync_clk.clkr, + [MMSS_MISC_AHB_CLK] =3D &mmss_misc_ahb_clk.clkr, + [MMSS_MMSSNOC_AHB_CLK] =3D &mmss_mmssnoc_ahb_clk.clkr, + [MMSS_MMSSNOC_BTO_AHB_CLK] =3D &mmss_mmssnoc_bto_ahb_clk.clkr, + [MMSS_MMSSNOC_AXI_CLK] =3D &mmss_mmssnoc_axi_clk.clkr, + [MMSS_S0_AXI_CLK] =3D &mmss_s0_axi_clk.clkr, + [OCMEMCX_AHB_CLK] =3D &ocmemcx_ahb_clk.clkr, + [OXILI_OCMEMGX_CLK] =3D &oxili_ocmemgx_clk.clkr, + [OXILI_GFX3D_CLK] =3D &oxili_gfx3d_clk.clkr, + [OXILICX_AHB_CLK] =3D &oxilicx_ahb_clk.clkr, + [OXILICX_AXI_CLK] =3D &oxilicx_axi_clk.clkr, + [VENUS0_AHB_CLK] =3D &venus0_ahb_clk.clkr, + [VENUS0_AXI_CLK] =3D &venus0_axi_clk.clkr, + [VENUS0_VCODEC0_CLK] =3D &venus0_vcodec0_clk.clkr, +}; + +static const struct qcom_reset_map mmcc_msm8226_resets[] =3D { + [SPDM_RESET] =3D { 0x0200 }, + [SPDM_RM_RESET] =3D { 0x0300 }, + [VENUS0_RESET] =3D { 0x1020 }, + [MDSS_RESET] =3D { 0x2300 }, +}; + +static struct gdsc *mmcc_msm8226_gdscs[] =3D { + [VENUS0_GDSC] =3D &venus0_gdsc, + [MDSS_GDSC] =3D &mdss_gdsc, + [CAMSS_JPEG_GDSC] =3D &camss_jpeg_gdsc, + [CAMSS_VFE_GDSC] =3D &camss_vfe_gdsc, +}; + +static const struct regmap_config mmcc_msm8226_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5104, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc mmcc_msm8226_desc =3D { + .config =3D &mmcc_msm8226_regmap_config, + .clks =3D mmcc_msm8226_clocks, + .num_clks =3D ARRAY_SIZE(mmcc_msm8226_clocks), + .resets =3D mmcc_msm8226_resets, + .num_resets =3D ARRAY_SIZE(mmcc_msm8226_resets), + .gdscs =3D mmcc_msm8226_gdscs, + .num_gdscs =3D ARRAY_SIZE(mmcc_msm8226_gdscs), +}; + static struct clk_regmap *mmcc_msm8974_clocks[] =3D { [MMSS_AHB_CLK_SRC] =3D &mmss_ahb_clk_src.clkr, [MMSS_AXI_CLK_SRC] =3D &mmss_axi_clk_src.clkr, @@ -2569,23 +2744,44 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = =3D { }; =20 static const struct of_device_id mmcc_msm8974_match_table[] =3D { - { .compatible =3D "qcom,mmcc-msm8974" }, + { .compatible =3D "qcom,mmcc-msm8226", .data =3D &mmcc_msm8226_desc }, + { .compatible =3D "qcom,mmcc-msm8974", .data =3D &mmcc_msm8974_desc }, { } }; MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); =20 +static void msm8226_clock_override(void) +{ + mmss_axi_clk_src.freq_tbl =3D ftbl_mmss_axi_clk_msm8226; + vfe0_clk_src.freq_tbl =3D ftbl_camss_vfe_vfe0_clk_msm8226; + mdp_clk_src.freq_tbl =3D ftbl_mdss_mdp_clk_msm8226; + vcodec0_clk_src.freq_tbl =3D ftbl_venus0_vcodec0_clk_msm8226; + mclk0_clk_src.freq_tbl =3D ftbl_camss_mclk0_3_clk_msm8226; + mclk1_clk_src.freq_tbl =3D ftbl_camss_mclk0_3_clk_msm8226; + cpp_clk_src.freq_tbl =3D ftbl_camss_vfe_cpp_clk_msm8226; +} + static int mmcc_msm8974_probe(struct platform_device *pdev) { struct regmap *regmap; + const struct qcom_cc_desc *desc; + + desc =3D of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; =20 - regmap =3D qcom_cc_map(pdev, &mmcc_msm8974_desc); + regmap =3D qcom_cc_map(pdev, desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 - clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); - clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); + if (desc =3D=3D &mmcc_msm8974_desc) { + clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); + clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); + } else { + msm8226_clock_override(); + } =20 - return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); + return qcom_cc_really_probe(pdev, desc, regmap); } =20 static struct platform_driver mmcc_msm8974_driver =3D { --=20 2.25.1