From nobody Sun Sep 22 11:45:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 024D8C4167E for ; Mon, 7 Feb 2022 08:33:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245735AbiBGIb5 (ORCPT ); Mon, 7 Feb 2022 03:31:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243691AbiBGIaw (ORCPT ); Mon, 7 Feb 2022 03:30:52 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D8F9C043184; Mon, 7 Feb 2022 00:30:47 -0800 (PST) X-UUID: 30dbd83bb10a4cb2acca31aa59954778-20220207 X-UUID: 30dbd83bb10a4cb2acca31aa59954778-20220207 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 923001334; Mon, 07 Feb 2022 16:30:43 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Feb 2022 16:30:42 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Feb 2022 16:30:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 7 Feb 2022 16:30:42 +0800 From: Johnson Wang To: , CC: , , , , , , Johnson Wang Subject: [PATCH v3 1/2] soc: mediatek: pwrap: add pwrap driver for MT8186 SoC Date: Mon, 7 Feb 2022 16:30:33 +0800 Message-ID: <20220207083034.15327-2-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220207083034.15327-1-johnson.wang@mediatek.com> References: <20220207083034.15327-1-johnson.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno Signed-off-by: Johnson Wang --- drivers/soc/mediatek/mtk-pmic-wrap.c | 71 ++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index 952bc554f443..bf39a64f3ecc 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -30,6 +30,7 @@ #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) #define PWRAP_STATE_SYNC_IDLE0 BIT(20) #define PWRAP_STATE_INIT_DONE0 BIT(21) +#define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22) #define PWRAP_STATE_INIT_DONE1 BIT(15) =20 /* macro for WACS FSM */ @@ -77,6 +78,7 @@ #define PWRAP_CAP_INT1_EN BIT(3) #define PWRAP_CAP_WDT_SRC1 BIT(4) #define PWRAP_CAP_ARB BIT(5) +#define PWRAP_CAP_ARB_MT8186 BIT(8) =20 /* defines for slave device wrapper registers */ enum dew_regs { @@ -1063,6 +1065,55 @@ static int mt8516_regs[] =3D { [PWRAP_MSB_FIRST] =3D 0x170, }; =20 +static int mt8186_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_RDDMY] =3D 0x20, + [PWRAP_CSHEXT_WRITE] =3D 0x24, + [PWRAP_CSHEXT_READ] =3D 0x28, + [PWRAP_CSLEXT_WRITE] =3D 0x2C, + [PWRAP_CSLEXT_READ] =3D 0x30, + [PWRAP_EXT_CK_WRITE] =3D 0x34, + [PWRAP_STAUPD_CTRL] =3D 0x3C, + [PWRAP_STAUPD_GRPEN] =3D 0x40, + [PWRAP_EINT_STA0_ADR] =3D 0x44, + [PWRAP_EINT_STA1_ADR] =3D 0x48, + [PWRAP_INT_CLR] =3D 0xC8, + [PWRAP_INT_FLG] =3D 0xC4, + [PWRAP_MAN_EN] =3D 0x7C, + [PWRAP_MAN_CMD] =3D 0x80, + [PWRAP_WACS0_EN] =3D 0x8C, + [PWRAP_WACS1_EN] =3D 0x94, + [PWRAP_WACS2_EN] =3D 0x9C, + [PWRAP_INIT_DONE0] =3D 0x90, + [PWRAP_INIT_DONE1] =3D 0x98, + [PWRAP_INIT_DONE2] =3D 0xA0, + [PWRAP_INT_EN] =3D 0xBC, + [PWRAP_INT1_EN] =3D 0xCC, + [PWRAP_INT1_FLG] =3D 0xD4, + [PWRAP_INT1_CLR] =3D 0xD8, + [PWRAP_TIMER_EN] =3D 0xF0, + [PWRAP_WDT_UNIT] =3D 0xF8, + [PWRAP_WDT_SRC_EN] =3D 0xFC, + [PWRAP_WDT_SRC_EN_1] =3D 0x100, + [PWRAP_WDT_FLG] =3D 0x104, + [PWRAP_SPMINF_STA] =3D 0x1B4, + [PWRAP_DCM_EN] =3D 0x1EC, + [PWRAP_DCM_DBC_PRD] =3D 0x1F0, + [PWRAP_GPSINF_0_STA] =3D 0x204, + [PWRAP_GPSINF_1_STA] =3D 0x208, + [PWRAP_WACS0_CMD] =3D 0xC00, + [PWRAP_WACS0_RDATA] =3D 0xC04, + [PWRAP_WACS0_VLDCLR] =3D 0xC08, + [PWRAP_WACS1_CMD] =3D 0xC10, + [PWRAP_WACS1_RDATA] =3D 0xC14, + [PWRAP_WACS1_VLDCLR] =3D 0xC18, + [PWRAP_WACS2_CMD] =3D 0xC20, + [PWRAP_WACS2_RDATA] =3D 0xC24, + [PWRAP_WACS2_VLDCLR] =3D 0xC28, +}; + enum pmic_type { PMIC_MT6323, PMIC_MT6351, @@ -1083,6 +1134,7 @@ enum pwrap_type { PWRAP_MT8135, PWRAP_MT8173, PWRAP_MT8183, + PWRAP_MT8186, PWRAP_MT8195, PWRAP_MT8516, }; @@ -1535,6 +1587,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT6779: case PWRAP_MT6797: case PWRAP_MT8173: + case PWRAP_MT8186: case PWRAP_MT8516: pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); break; @@ -2069,6 +2122,19 @@ static struct pmic_wrapper_type pwrap_mt8516 =3D { .init_soc_specific =3D NULL, }; =20 +static struct pmic_wrapper_type pwrap_mt8186 =3D { + .regs =3D mt8186_regs, + .type =3D PWRAP_MT8186, + .arb_en_all =3D 0xfb27f, + .int_en_all =3D 0xfffffffe, /* disable WatchDog Timeout for bit 1 */ + .int1_en_all =3D 0x000017ff, /* disable Matching interrupt for bit 13 */ + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_ALL, + .caps =3D PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D NULL, +}; + static const struct of_device_id of_pwrap_match_tbl[] =3D { { .compatible =3D "mediatek,mt2701-pwrap", @@ -2097,6 +2163,9 @@ static const struct of_device_id of_pwrap_match_tbl[]= =3D { }, { .compatible =3D "mediatek,mt8183-pwrap", .data =3D &pwrap_mt8183, + }, { + .compatible =3D "mediatek,mt8186-pwrap", + .data =3D &pwrap_mt8186, }, { .compatible =3D "mediatek,mt8195-pwrap", .data =3D &pwrap_mt8195, @@ -2209,6 +2278,8 @@ static int pwrap_probe(struct platform_device *pdev) =20 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) mask_done =3D PWRAP_STATE_INIT_DONE1; + else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) + mask_done =3D PWRAP_STATE_INIT_DONE0_MT8186; else mask_done =3D PWRAP_STATE_INIT_DONE0; =20 --=20 2.18.0