From nobody Mon Jun 29 16:46:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43157C433F5 for ; Sun, 6 Feb 2022 13:14:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238783AbiBFNOt (ORCPT ); Sun, 6 Feb 2022 08:14:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229928AbiBFNOs (ORCPT ); Sun, 6 Feb 2022 08:14:48 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CD49C043182 for ; Sun, 6 Feb 2022 05:14:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644153287; x=1675689287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EKoP3ymBFowoLiYIS0xqrTIuAsin4prij790y32k2Js=; b=QJdOd6Zh4T/mxvZAda9s6daHdnhbOe6p4kXAjSLKDMjFEFHdD5dd0Cl9 0Bs3hzSt6z0CBlFPeDJTtPcctSpAgnO4CUitvs3xtDEjhKO4SicncLG8H cr2zmtchYrkJKZz7fiZWdVwl0lKSAcrnq2dZ49PO4S6QAOIIjt9teLc5M 9AojFh+/ZlpqUMt7CJIEN6mo/FnEySpXPjbOltLEecgYHO9pM+rHPUdvK 5xhbiuTzw9nu/61TcvG8O+u7sOqnOMk7Tu32KcHQA/U6kT4S9RgZnsNyK btLXVGBOTNsLi901BsVL7gfitI5AETyrpn+D4c4pY67SuG1RbvYWsJnU1 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="334981223" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334981223" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:44 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="539750858" Received: from sannilnx.jer.intel.com ([10.12.231.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:41 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/5] drm/i915/gsc: add gsc as a mei auxiliary device Date: Sun, 6 Feb 2022 15:13:18 +0200 Message-Id: <20220206131322.3246403-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206131322.3246403-1-alexander.usyskin@intel.com> References: <20220206131322.3246403-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin Reviewed-by: Greg Kroah-Hartman --- V4: add header to the MAINTAINERS file drop empty line V5: rebase --- MAINTAINERS | 1 + drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/gt/intel_gsc.c | 199 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gsc.h | 37 +++++ drivers/gpu/drm/i915/gt/intel_gt.c | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 + drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_device_info.h | 2 + include/linux/mei_aux.h | 19 +++ 15 files changed, 298 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h create mode 100644 include/linux/mei_aux.h diff --git a/MAINTAINERS b/MAINTAINERS index e3dad0d898f5..1e65ff4f1d58 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9792,6 +9792,7 @@ S: Supported F: Documentation/driver-api/mei/* F: drivers/misc/mei/ F: drivers/watchdog/mei_wdt.c +F: include/linux/mei_aux.h F: include/linux/mei_cl_bus.h F: include/uapi/linux/mei.h F: samples/mei/* diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 2ac220bfd0ed..3b0508e7a805 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -29,6 +29,7 @@ config DRM_I915 select VMAP_PFN select DRM_TTM select DRM_BUDDY + select AUXILIARY_BUS help Choose this option if you have a system that has "Intel Graphics Media Accelerator" or "HD Graphics" integrated graphics, diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index a26e6736bebb..f8606487b4da 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -195,6 +195,9 @@ i915-y +=3D gt/uc/intel_uc.o \ gt/uc/intel_huc_debugfs.o \ gt/uc/intel_huc_fw.o =20 +# graphics system controller (GSC) support +i915-y +=3D gt/intel_gsc.o + # modesetting core code i915-y +=3D \ display/intel_atomic.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c new file mode 100644 index 000000000000..f1870acd1866 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "i915_reg.h" +#include "i915_drv.h" +#include "gt/intel_gt.h" +#include "intel_gsc.h" + +#define GSC_BAR_LENGTH 0x00000FFC + +static void gsc_irq_mask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static void gsc_irq_unmask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static struct irq_chip gsc_irq_chip =3D { + .name =3D "gsc_irq_chip", + .irq_mask =3D gsc_irq_mask, + .irq_unmask =3D gsc_irq_unmask, +}; + +static int gsc_irq_init(struct drm_i915_private *dev_priv, int irq) +{ + irq_set_chip_and_handler_name(irq, &gsc_irq_chip, + handle_simple_irq, "gsc_irq_handler"); + + return irq_set_chip_data(irq, dev_priv); +} + +struct intel_gsc_def { + const char *name; + const unsigned long bar; + size_t bar_size; +}; + +/* gscfi (graphics system controller firmware interface) resources */ +static const struct intel_gsc_def intel_gsc_def_dg1[] =3D { + { + }, + { + .name =3D "mei-gscfi", + .bar =3D GSC_DG1_HECI2_BASE, + .bar_size =3D GSC_BAR_LENGTH, + } +}; + +static void intel_gsc_release_dev(struct device *dev) +{ + struct auxiliary_device *aux_dev =3D to_auxiliary_dev(dev); + struct mei_aux_device *adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + + kfree(adev); +} + +static void intel_gsc_destroy_one(struct intel_gsc_intf *intf) +{ + if (intf->adev) { + auxiliary_device_delete(&intf->adev->aux_dev); + auxiliary_device_uninit(&intf->adev->aux_dev); + intf->adev =3D NULL; + } + if (intf->irq >=3D 0) + irq_free_desc(intf->irq); + intf->irq =3D -1; +} + +static void intel_gsc_init_one(struct drm_i915_private *dev_priv, + struct intel_gsc_intf *intf, + unsigned int intf_id) +{ + struct pci_dev *pdev =3D to_pci_dev(dev_priv->drm.dev); + struct mei_aux_device *adev; + struct auxiliary_device *aux_dev; + const struct intel_gsc_def *def; + int ret; + + intf->irq =3D -1; + intf->id =3D intf_id; + + if (intf_id =3D=3D 0 && !HAS_HECI_PXP(dev_priv)) + return; + + def =3D &intel_gsc_def_dg1[intf_id]; + + dev_dbg(&pdev->dev, "init gsc one with id %d\n", intf_id); + intf->irq =3D irq_alloc_desc(0); + if (intf->irq < 0) { + dev_err(&pdev->dev, "gsc irq error %d\n", intf->irq); + return; + } + + ret =3D gsc_irq_init(dev_priv, intf->irq); + if (ret < 0) { + dev_err(&pdev->dev, "gsc irq init failed %d\n", ret); + goto fail; + } + + adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) { + ret =3D -ENOMEM; + goto fail; + } + aux_dev =3D &adev->aux_dev; + + adev->irq =3D intf->irq; + adev->bar.parent =3D &pdev->resource[0]; + adev->bar.start =3D def->bar + pdev->resource[0].start; + adev->bar.end =3D adev->bar.start + def->bar_size - 1; + adev->bar.flags =3D IORESOURCE_MEM; + adev->bar.desc =3D IORES_DESC_NONE; + + aux_dev =3D &adev->aux_dev; + aux_dev->name =3D def->name; + aux_dev->id =3D (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent =3D &pdev->dev; + aux_dev->dev.release =3D intel_gsc_release_dev; + + ret =3D auxiliary_device_init(aux_dev); + if (ret < 0) { + dev_err(&pdev->dev, "gsc aux init failed %d\n", ret); + kfree(adev); + goto fail; + } + + ret =3D auxiliary_device_add(aux_dev); + if (ret < 0) { + dev_err(&pdev->dev, "gsc aux add failed %d\n", ret); + /* adev will be freed with the put_device() and .release sequence */ + auxiliary_device_uninit(aux_dev); + goto fail; + } + intf->adev =3D adev; + + dev_dbg(&pdev->dev, "gsc init one done\n"); + return; +fail: + intel_gsc_destroy_one(intf); +} + +static void intel_gsc_irq_handler(struct intel_gt *gt, unsigned int intf_i= d) +{ + int ret; + + if (intf_id >=3D INTEL_GSC_NUM_INTERFACES) + return; + + if (!HAS_HECI_GSC(gt->i915)) + return; + + if (gt->gsc.intf[intf_id].irq <=3D 0) { + DRM_ERROR_RATELIMITED("error handling GSC irq: irq not set"); + return; + } + + ret =3D generic_handle_irq(gt->gsc.intf[intf_id].irq); + if (ret) + DRM_ERROR_RATELIMITED("error handling GSC irq: %d\n", ret); +} + +void gsc_irq_handler(struct intel_gt *gt, u32 iir) +{ + if (iir & GSC_IRQ_INTF(0)) + intel_gsc_irq_handler(gt, 0); + if (iir & GSC_IRQ_INTF(1)) + intel_gsc_irq_handler(gt, 1); +} + +void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_pr= iv) +{ + unsigned int i; + + if (!HAS_HECI_GSC(dev_priv)) + return; + + for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) + intel_gsc_init_one(dev_priv, &gsc->intf[i], i); +} + +void intel_gsc_fini(struct intel_gsc *gsc) +{ + struct intel_gt *gt =3D gsc_to_gt(gsc); + unsigned int i; + + if (!HAS_HECI_GSC(gt->i915)) + return; + + for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) + intel_gsc_destroy_one(&gsc->intf[i]); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/= intel_gsc.h new file mode 100644 index 000000000000..67cb2a75f839 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + */ +#ifndef __INTEL_GSC_DEV_H__ +#define __INTEL_GSC_DEV_H__ + +#include + +struct drm_i915_private; +struct intel_gt; +struct mei_aux_device; + +#define INTEL_GSC_NUM_INTERFACES 2 +/* + * The HECI1 bit corresponds to bit15 and HECI2 to bit14. + * The reason for this is to allow growth for more interfaces in the futur= e. + */ +#define GSC_IRQ_INTF(_x) BIT(15 - (_x)) + +/** + * struct intel_gsc - graphics security controller + * @intf : gsc interface + */ +struct intel_gsc { + struct intel_gsc_intf { + struct mei_aux_device *adev; + int irq; + unsigned int id; + } intf[INTEL_GSC_NUM_INTERFACES]; +}; + +void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_pr= iv); +void intel_gsc_fini(struct intel_gsc *gsc); +void gsc_irq_handler(struct intel_gt *gt, u32 iir); + +#endif /* __INTEL_GSC_DEV_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/i= ntel_gt.c index e6f6bf7c3926..7f74a2eedbc2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -445,6 +445,8 @@ void intel_gt_chipset_flush(struct intel_gt *gt) =20 void intel_gt_driver_register(struct intel_gt *gt) { + intel_gsc_init(>->gsc, gt->i915); + intel_rps_driver_register(>->rps); =20 intel_gt_debugfs_register(gt); @@ -765,6 +767,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt) intel_wakeref_t wakeref; =20 intel_rps_driver_unregister(>->rps); + intel_gsc_fini(>->gsc); =20 intel_pxp_fini(>->pxp); =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/i= ntel_gt.h index 2dad46c3eff2..6ba817c02baa 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -34,6 +34,11 @@ static inline struct intel_gt *huc_to_gt(struct intel_hu= c *huc) return container_of(huc, struct intel_gt, uc.huc); } =20 +static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc) +{ + return container_of(gsc, struct intel_gt, gsc); +} + void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i91= 5); void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i= 915); int intel_gt_assign_ggtt(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/= gt/intel_gt_irq.c index 983264e10e0a..d36f919bbdf5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -68,6 +68,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 ins= tance, if (instance =3D=3D OTHER_KCR_INSTANCE) return intel_pxp_irq_handler(>->pxp, iir); =20 + if (instance =3D=3D OTHER_GSC_INSTANCE) + return gsc_irq_handler(gt, iir); + WARN_ONCE(1, "unhandled other interrupt instance=3D0x%x, iir=3D0x%x\n", instance, iir); } @@ -182,6 +185,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) /* Disable RCS, BCS, VCS and VECS class engines. */ intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); =20 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); @@ -195,6 +200,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); =20 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); @@ -209,6 +216,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) { struct intel_uncore *uncore =3D gt->uncore; u32 irqs =3D GT_RENDER_USER_INTERRUPT; + const u32 gsc_mask =3D GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); u32 dmask; u32 smask; =20 @@ -225,6 +233,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) /* Enable RCS, BCS, VCS and VECS class interrupts. */ intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, + gsc_mask); =20 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); @@ -238,6 +249,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, 0); /* * RPS interrupts will get enabled/disabled on demand when RPS itself * is enabled/disabled. diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915= /gt/intel_gt_regs.h index a6f0220c2e9f..427f91900afc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -944,6 +944,7 @@ enum { #define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE 1 #define OTHER_KCR_INSTANCE 4 +#define OTHER_GSC_INSTANCE 6 =20 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i91= 5/gt/intel_gt_types.h index f20687796490..5556d55f76ea 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -16,6 +16,7 @@ #include =20 #include "uc/intel_uc.h" +#include "intel_gsc.h" =20 #include "i915_vma.h" #include "intel_engine_types.h" @@ -72,6 +73,7 @@ struct intel_gt { struct i915_ggtt *ggtt; =20 struct intel_uc uc; + struct intel_gsc gsc; =20 struct mutex tlb_invalidate_lock; =20 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index 8c1706fd81f9..eb7d7f074c2f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1504,6 +1504,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, =20 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) =20 +#define HAS_HECI_PXP(dev_priv) \ + (INTEL_INFO(dev_priv)->has_heci_pxp) + +#define HAS_HECI_GSCFI(dev_priv) \ + (INTEL_INFO(dev_priv)->has_heci_gscfi) + +#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(d= ev_priv)) + #define HAS_MSO(i915) (DISPLAY_VER(i915) >=3D 12) =20 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pc= i.c index 467252f885c2..8f608b03d30b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -900,7 +900,8 @@ static const struct intel_device_info rkl_info =3D { .has_llc =3D 0, \ .has_pxp =3D 0, \ .has_snoop =3D 1, \ - .is_dgfx =3D 1 + .is_dgfx =3D 1, \ + .has_heci_gscfi =3D 1 =20 static const struct intel_device_info dg1_info =3D { GEN12_FEATURES, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index 87c92314ee26..06dc89a7e4ee 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -974,6 +974,8 @@ #define GEN11_VEBOX2_RING_BASE 0x1d8000 #define XEHP_VEBOX3_RING_BASE 0x1e8000 #define XEHP_VEBOX4_RING_BASE 0x1f8000 +#define GSC_DG1_HECI1_BASE 0x00258000 +#define GSC_DG1_HECI2_BASE 0x00259000 #define BLT_RING_BASE 0x22000 =20 =20 diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i91= 5/intel_device_info.h index 27dcfe6f2429..fa75f464cb01 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -135,6 +135,8 @@ enum intel_ppgtt_type { func(has_reset_engine); \ func(has_global_mocs); \ func(has_gt_uc); \ + func(has_heci_pxp); \ + func(has_heci_gscfi); \ func(has_guc_deprivilege); \ func(has_l3_dpf); \ func(has_llc); \ diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h new file mode 100644 index 000000000000..587f25128848 --- /dev/null +++ b/include/linux/mei_aux.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Intel Corporation. All rights reserved. + */ +#ifndef _LINUX_MEI_AUX_H +#define _LINUX_MEI_AUX_H + +#include + +struct mei_aux_device { + struct auxiliary_device aux_dev; + int irq; + struct resource bar; +}; + +#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \ + container_of(auxiliary_dev, struct mei_aux_device, aux_dev) + +#endif /* _LINUX_MEI_AUX_H */ --=20 2.32.0 From nobody Mon Jun 29 16:46:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9DC1C433EF for ; Sun, 6 Feb 2022 13:14:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238947AbiBFNO4 (ORCPT ); Sun, 6 Feb 2022 08:14:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238851AbiBFNOy (ORCPT ); Sun, 6 Feb 2022 08:14:54 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35687C043187 for ; Sun, 6 Feb 2022 05:14:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644153291; x=1675689291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sqjcRFDa+jjbKDmNtY/gPD9tgL+Ze+e21tnHLPdh1DQ=; b=FW497dDRpgKGdN2q9xithsgAZ6eT4oFTdUe/Z1O3CnuklWcfGlbVByIr oO6GQX4Zx6DZIIP97mBnKzmWXEjCLhcBgEgTokARQ0mGuKcUTZtQUl2dm AWU0VlMMFeM20TfNGKhb4YaHjqBTRSJVGtb4FMouFrg6Qe98RhymdW5h1 5mYejTnDHpYdXVbarQFMmv8f4OH69mFB6kZpztPouj2YFhIgba0cBrHus URQz0veMRbBkAm39dg33roa/fFEU+SqvwLBybhdJwGF1zFWm3LKaUbVlp 01erEFwfXU9r5+r9yu7/d5Y8tPxLBt+Th5jrPV+9ieUh3jE4V7rpMcQBk g==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="334981229" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334981229" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:48 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="539750865" Received: from sannilnx.jer.intel.com ([10.12.231.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:45 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/5] mei: add support for graphics system controller (gsc) devices Date: Sun, 6 Feb 2022 15:13:19 +0200 Message-Id: <20220206131322.3246403-3-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206131322.3246403-1-alexander.usyskin@intel.com> References: <20220206131322.3246403-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC is a graphics system controller, based on CSE, it provides a chassis controller for graphics discrete cards, as well as it supports media protection on selected devices. mei_gsc binds to a auxiliary devices exposed by Intel discrete driver i915. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Greg Kroah-Hartman --- V4: drop debug prints replace selects with depends on in Kconfig V5: Rebase --- drivers/misc/mei/Kconfig | 14 +++ drivers/misc/mei/Makefile | 3 + drivers/misc/mei/gsc-me.c | 186 ++++++++++++++++++++++++++++++++++++++ drivers/misc/mei/hw-me.c | 27 +++++- drivers/misc/mei/hw-me.h | 2 + 5 files changed, 230 insertions(+), 2 deletions(-) create mode 100644 drivers/misc/mei/gsc-me.c diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 0e0bcd0da852..d21486d69df2 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -46,6 +46,20 @@ config INTEL_MEI_TXE Supported SoCs: Intel Bay Trail =20 +config INTEL_MEI_GSC + tristate "Intel MEI GSC embedded device" + depends on INTEL_MEI + depends on INTEL_MEI_ME + depends on X86 && PCI + depends on DRM_I915 + help + Intel auxiliary driver for GSC devices embedded in Intel graphics devic= es. + + An MEI device here called GSC can be embedded in an + Intel graphics devices, to support a range of chassis + tasks such as graphics card firmware update and security + tasks. + source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" =20 diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index d8e5165917f2..fb740d754900 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) +=3D mei-me.o mei-me-objs :=3D pci-me.o mei-me-objs +=3D hw-me.o =20 +obj-$(CONFIG_INTEL_MEI_GSC) +=3D mei-gsc.o +mei-gsc-objs :=3D gsc-me.o + obj-$(CONFIG_INTEL_MEI_TXE) +=3D mei-txe.o mei-txe-objs :=3D pci-txe.o mei-txe-objs +=3D hw-txe.o diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c new file mode 100644 index 000000000000..0afae70e0609 --- /dev/null +++ b/drivers/misc/mei/gsc-me.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + * + * Intel Management Engine Interface (Intel MEI) Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mei_dev.h" +#include "hw-me.h" +#include "hw-me-regs.h" + +#include "mei-trace.h" + +#define MEI_GSC_RPM_TIMEOUT 500 + +static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *= val) +{ + struct mei_me_hw *hw =3D to_me_hw(dev); + + *val =3D ioread32(hw->mem_addr + where + 0xC00); + + return 0; +} + +static int mei_gsc_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *aux_dev_id) +{ + struct mei_aux_device *adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + struct mei_device *dev; + struct mei_me_hw *hw; + struct device *device; + const struct mei_cfg *cfg; + int ret; + + cfg =3D mei_me_get_cfg(aux_dev_id->driver_data); + if (!cfg) + return -ENODEV; + + device =3D &aux_dev->dev; + + dev =3D mei_me_dev_init(device, cfg); + if (IS_ERR(dev)) { + ret =3D PTR_ERR(dev); + goto err; + } + + hw =3D to_me_hw(dev); + hw->mem_addr =3D devm_ioremap_resource(device, &adev->bar); + if (IS_ERR(hw->mem_addr)) { + dev_err(device, "mmio not mapped\n"); + ret =3D PTR_ERR(hw->mem_addr); + goto err; + } + + hw->irq =3D adev->irq; + hw->read_fws =3D mei_gsc_read_hfs; + + dev_set_drvdata(&aux_dev->dev, dev); + + ret =3D devm_request_threaded_irq(device, hw->irq, + mei_me_irq_quick_handler, + mei_me_irq_thread_handler, + IRQF_ONESHOT, KBUILD_MODNAME, dev); + if (ret) { + dev_err(device, "irq register failed %d\n", ret); + goto err; + } + + pm_runtime_get_noresume(device); + pm_runtime_set_active(device); + pm_runtime_enable(device); + + if (mei_start(dev)) { + dev_err(device, "init hw failure.\n"); + ret =3D -ENODEV; + goto err; + } + + pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT); + pm_runtime_use_autosuspend(device); + + ret =3D mei_register(dev, device); + if (ret) + goto register_err; + + pm_runtime_put_noidle(device); + return 0; + +register_err: + mei_stop(dev); + +err: + dev_err(device, "probe failed: %d\n", ret); + dev_set_drvdata(&aux_dev->dev, NULL); + return ret; +} + +static void mei_gsc_remove(struct auxiliary_device *aux_dev) +{ + struct mei_device *dev; + + dev =3D dev_get_drvdata(&aux_dev->dev); + if (!dev) + return; + + mei_stop(dev); + + mei_deregister(dev); + + pm_runtime_disable(&aux_dev->dev); +} + +static int __maybe_unused mei_gsc_pm_suspend(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + + if (!dev) + return -ENODEV; + + mei_stop(dev); + + mei_disable_interrupts(dev); + + return 0; +} + +static int __maybe_unused mei_gsc_pm_resume(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + int err; + + if (!dev) + return -ENODEV; + + err =3D mei_restart(dev); + if (err) + return err; + + /* Start timer if stopped in suspend */ + schedule_delayed_work(&dev->timer_work, HZ); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_re= sume); + +static const struct auxiliary_device_id mei_gsc_id_table[] =3D { + { + .name =3D "i915.mei-gsc", + .driver_data =3D MEI_ME_GSC_CFG, + + }, + { + .name =3D "i915.mei-gscfi", + .driver_data =3D MEI_ME_GSCFI_CFG, + }, + { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(auxiliary, mei_gsc_id_table); + +static struct auxiliary_driver mei_gsc_driver =3D { + .probe =3D mei_gsc_probe, + .remove =3D mei_gsc_remove, + .driver =3D { + /* auxiliary_driver_register() sets .name to be the modname */ + .pm =3D &mei_gsc_pm_ops, + }, + .id_table =3D mei_gsc_id_table +}; +module_auxiliary_driver(mei_gsc_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_ALIAS("auxiliary:i915.mei-gsc"); +MODULE_ALIAS("auxiliary:i915.mei-gscfi"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index d3a6c0728645..9748d14849a1 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1226,6 +1226,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *d= ev_id) me_intr_disable(dev, hcsr); return IRQ_WAKE_THREAD; } +EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler); =20 /** * mei_me_irq_thread_handler - function called after ISR to handle the int= errupt @@ -1320,6 +1321,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *= dev_id) mutex_unlock(&dev->device_lock); return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler); =20 static const struct mei_hw_ops mei_me_hw_ops =3D { =20 @@ -1433,6 +1435,12 @@ static bool mei_me_fw_type_sps(const struct pci_dev = *pdev) #define MEI_CFG_KIND_ITOUCH \ .kind =3D "itouch" =20 +#define MEI_CFG_TYPE_GSC \ + .kind =3D "gsc" + +#define MEI_CFG_TYPE_GSCFI \ + .kind =3D "gscfi" + #define MEI_CFG_FW_SPS \ .quirk_probe =3D mei_me_fw_type_sps =20 @@ -1565,6 +1573,18 @@ static const struct mei_cfg mei_me_pch15_sps_cfg =3D= { MEI_CFG_FW_SPS, }; =20 +/* Graphics System Controller */ +static const struct mei_cfg mei_me_gsc_cfg =3D { + MEI_CFG_TYPE_GSC, + MEI_CFG_PCH8_HFS, +}; + +/* Graphics System Controller Firmware Interface */ +static const struct mei_cfg mei_me_gscfi_cfg =3D { + MEI_CFG_TYPE_GSCFI, + MEI_CFG_PCH8_HFS, +}; + /* * mei_cfg_list - A list of platform platform specific configurations. * Note: has to be synchronized with enum mei_cfg_idx. @@ -1585,6 +1605,8 @@ static const struct mei_cfg *const mei_cfg_list[] =3D= { [MEI_ME_PCH12_SPS_ITOUCH_CFG] =3D &mei_me_pch12_itouch_sps_cfg, [MEI_ME_PCH15_CFG] =3D &mei_me_pch15_cfg, [MEI_ME_PCH15_SPS_CFG] =3D &mei_me_pch15_sps_cfg, + [MEI_ME_GSC_CFG] =3D &mei_me_gsc_cfg, + [MEI_ME_GSCFI_CFG] =3D &mei_me_gscfi_cfg, }; =20 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) @@ -1595,7 +1617,8 @@ const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t i= dx) return NULL; =20 return mei_cfg_list[idx]; -}; +} +EXPORT_SYMBOL_GPL(mei_me_get_cfg); =20 /** * mei_me_dev_init - allocates and initializes the mei device structure @@ -1630,4 +1653,4 @@ struct mei_device *mei_me_dev_init(struct device *par= ent, =20 return dev; } - +EXPORT_SYMBOL_GPL(mei_me_dev_init); diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index 00a7132ac7a2..a071c645e905 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -112,6 +112,8 @@ enum mei_cfg_idx { MEI_ME_PCH12_SPS_ITOUCH_CFG, MEI_ME_PCH15_CFG, MEI_ME_PCH15_SPS_CFG, + MEI_ME_GSC_CFG, + MEI_ME_GSCFI_CFG, MEI_ME_NUM_CFG, }; =20 --=20 2.32.0 From nobody Mon Jun 29 16:46:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD67C433EF for ; Sun, 6 Feb 2022 13:15:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236685AbiBFNO7 (ORCPT ); Sun, 6 Feb 2022 08:14:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238822AbiBFNOz (ORCPT ); Sun, 6 Feb 2022 08:14:55 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 127B8C06173B for ; Sun, 6 Feb 2022 05:14:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644153295; x=1675689295; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RPfAnYrchtvqrYB1kUbBqN/6hGrrdhKHKY7ccrDfJNE=; b=PeN55NotAo40LpwgmT/uZ4sFpaOvM3mrlfJI1okYG1c7lah5Usx07a// SIE3Wfzn8Fvub41GONA9XqztTWXhnNq818CgBDD3Ar/38ZFN8jJcKSV3V wtSSI08BbfFBWTFadOSiu/FEwgkNFGa7iK8QDCkUME6O8yVHok1HxkoPZ IlHC7AG8IFj9YlxtumxSZtJoipVB3O6mg3ApoNPIQsTEJt80umrwLcizC oZIQbJZAQnT33aapqXoCsKMqKAbg8XUHgA/+zJATHIX/hxJmxPwot4QcC AfgQP69eY7Lm5xXJAxJD5g28R0L07kadiyRMzlyfaf7s+h7rhszV0uCBy g==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="334981232" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334981232" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:52 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="539750877" Received: from sannilnx.jer.intel.com ([10.12.231.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:49 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/5] mei: gsc: setup char driver alive in spite of firmware handshake failure Date: Sun, 6 Feb 2022 15:13:20 +0200 Message-Id: <20220206131322.3246403-4-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206131322.3246403-1-alexander.usyskin@intel.com> References: <20220206131322.3246403-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Setup char device in spite of firmware handshake failure. In order to provide host access to the firmware status registers and other information required for the manufacturing process. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Greg Kroah-Hartman --- V5: Rebase --- drivers/misc/mei/gsc-me.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 0afae70e0609..cf427f6fdec9 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -79,11 +79,12 @@ static int mei_gsc_probe(struct auxiliary_device *aux_d= ev, pm_runtime_set_active(device); pm_runtime_enable(device); =20 - if (mei_start(dev)) { - dev_err(device, "init hw failure.\n"); - ret =3D -ENODEV; - goto err; - } + /* Continue to char device setup in spite of firmware handshake failure. + * In order to provide access to the firmware status registers to the user + * space via sysfs. + */ + if (mei_start(dev)) + dev_warn(device, "init hw failure.\n"); =20 pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT); pm_runtime_use_autosuspend(device); --=20 2.32.0 From nobody Mon Jun 29 16:46:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BCEEC433EF for ; Sun, 6 Feb 2022 13:15:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239227AbiBFNPF (ORCPT ); Sun, 6 Feb 2022 08:15:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239122AbiBFNPA (ORCPT ); Sun, 6 Feb 2022 08:15:00 -0500 X-Greylist: delayed 61 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sun, 06 Feb 2022 05:14:59 PST Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE7B7C043185 for ; Sun, 6 Feb 2022 05:14:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644153299; x=1675689299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U6BBGporoVrZr7YK63C/FFdib3p/4tlmXRfeHe6CJ2k=; b=UR4vPpGXUGqblMjQaKlG3dBOule/ZVVbhkPISgiML+cWKPfLilAelYm+ iwBepfLGYjhbau0l2hz6Xu0iwo4YrtpSV/XCp/J2MXbJgdAui4L3a6TOs 1nHNfhUL1g4bRPxTuiJEmHoKpsKR2IHa3ZNPcke/TJInG6/0kesGphHsh Nx6jKi1RrwqKjgzwzJfwClthGiu0ts5mUTJ5GkWpRJua1xgi/OSEAmNPu xqs+N4xedoUS1DFiptjoOdITREHyc/8pYNpkytW8oyxIw86dUryYsRsKV rKQ8HnVuVX+w+q9X3tki1JyV56wklMuASHolJEvyeobZwYU8gW55SqRI5 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="235980846" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="235980846" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:58 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="539750942" Received: from sannilnx.jer.intel.com ([10.12.231.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:54 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/5] mei: gsc: add runtime pm handlers Date: Sun, 6 Feb 2022 15:13:21 +0200 Message-Id: <20220206131322.3246403-5-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206131322.3246403-1-alexander.usyskin@intel.com> References: <20220206131322.3246403-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler Implement runtime handlers for mei-gsc, to track idle state of the device properly. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Greg Kroah-Hartman --- V4: drop debug prints V5: Rebase --- drivers/misc/mei/gsc-me.c | 67 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index cf427f6fdec9..dac482ddab51 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -152,7 +152,72 @@ static int __maybe_unused mei_gsc_pm_resume(struct dev= ice *device) return 0; } =20 -static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_re= sume); +static int __maybe_unused mei_gsc_pm_runtime_idle(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + + if (!dev) + return -ENODEV; + if (mei_write_is_idle(dev)) + pm_runtime_autosuspend(device); + + return -EBUSY; +} + +static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *devic= e) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + struct mei_me_hw *hw; + int ret; + + if (!dev) + return -ENODEV; + + mutex_lock(&dev->device_lock); + + if (mei_write_is_idle(dev)) { + hw =3D to_me_hw(dev); + hw->pg_state =3D MEI_PG_ON; + ret =3D 0; + } else { + ret =3D -EAGAIN; + } + + mutex_unlock(&dev->device_lock); + + return ret; +} + +static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + struct mei_me_hw *hw; + irqreturn_t irq_ret; + + if (!dev) + return -ENODEV; + + mutex_lock(&dev->device_lock); + + hw =3D to_me_hw(dev); + hw->pg_state =3D MEI_PG_OFF; + + mutex_unlock(&dev->device_lock); + + irq_ret =3D mei_me_irq_thread_handler(1, dev); + if (irq_ret !=3D IRQ_HANDLED) + dev_err(dev->dev, "thread handler fail %d\n", irq_ret); + + return 0; +} + +static const struct dev_pm_ops mei_gsc_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(mei_gsc_pm_suspend, + mei_gsc_pm_resume) + SET_RUNTIME_PM_OPS(mei_gsc_pm_runtime_suspend, + mei_gsc_pm_runtime_resume, + mei_gsc_pm_runtime_idle) +}; =20 static const struct auxiliary_device_id mei_gsc_id_table[] =3D { { --=20 2.32.0 From nobody Mon Jun 29 16:46:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15114C433EF for ; Sun, 6 Feb 2022 13:15:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239314AbiBFNPH (ORCPT ); Sun, 6 Feb 2022 08:15:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239148AbiBFNPE (ORCPT ); Sun, 6 Feb 2022 08:15:04 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5DD8C0401D4 for ; Sun, 6 Feb 2022 05:15:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644153303; x=1675689303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eGox3Yf4XWGQ1c5FMtf03cjheHt9V9zlk4JcBPEf4Xk=; b=D7+ijM4b4FzJbkrdkiIHLmMYNY1Ctr0KD56IeZ0yPi7D0fHKZB9lPgxI bVCVPQN/1cN5+w4NRoXxQ7ILR7K5Q8f7PYyQtRUp2i9gifxt4hKK00v0F ewH9jYfS5IJWBrOW3AwWgDTIOYc6YS/04yceslL9byGkSgnu+EIcEo9vB lEjDaaGtkpivHn7blkwaZVSY2x/sWxo6ontE/fXcmBiLbHIDX7qH+3bQL A1dQh7l6hZ9Ve3FsjydGqmcWK00cY71lq9uBp/uVL60oMm9TVS84MpzsC IlmSpOtSg82U51jmhjuZjKfTMqbCMrw2H+ss9oQ3NeCa6zfq/0KNA8Yjm Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="235980851" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="235980851" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:14:02 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="539750967" Received: from sannilnx.jer.intel.com ([10.12.231.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 05:13:58 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ashutosh Dixit Subject: [PATCH v5 5/5] mei: gsc: retrieve the firmware version Date: Sun, 6 Feb 2022 15:13:22 +0200 Message-Id: <20220206131322.3246403-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220206131322.3246403-1-alexander.usyskin@intel.com> References: <20220206131322.3246403-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a hook to retrieve the firmware version of the GSC devices to bus-fixup. GSC has a different MKHI clients GUIDs but the same message structure to retrieve the firmware version as MEI so mei_fwver() can be reused. CC: Ashutosh Dixit Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Greg Kroah-Hartman --- V5: Rebase --- drivers/misc/mei/bus-fixup.c | 25 +++++++++++++++++++++++++ drivers/misc/mei/hw-me.c | 2 ++ 2 files changed, 27 insertions(+) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 67844089db21..59506ba6fc48 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -30,6 +30,12 @@ static const uuid_le mei_nfc_info_guid =3D MEI_UUID_NFC_= INFO; #define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \ 0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb) =20 +#define MEI_UUID_IGSC_MKHI UUID_LE(0xE2C2AFA2, 0x3817, 0x4D19, \ + 0x9D, 0x95, 0x06, 0xB1, 0x6B, 0x58, 0x8A, 0x5D) + +#define MEI_UUID_IGSC_MKHI_FIX UUID_LE(0x46E0C1FB, 0xA546, 0x414F, \ + 0x91, 0x70, 0xB7, 0xF4, 0x6D, 0x57, 0xB4, 0xAD) + #define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \ 0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04) =20 @@ -241,6 +247,23 @@ static void mei_mkhi_fix(struct mei_cl_device *cldev) mei_cldev_disable(cldev); } =20 +static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev) +{ + int ret; + + /* No need to enable the client if nothing is needed from it */ + if (!cldev->bus->fw_f_fw_ver_supported) + return; + + ret =3D mei_cldev_enable(cldev); + if (ret) + return; + + ret =3D mei_fwver(cldev); + if (ret < 0) + dev_err(&cldev->dev, "FW version command failed %d\n", ret); + mei_cldev_disable(cldev); +} /** * mei_wd - wd client on the bus, change protocol version * as the API has changed. @@ -492,6 +515,8 @@ static struct mei_fixup { MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc), MEI_FIXUP(MEI_UUID_WD, mei_wd), MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix), + MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver), MEI_FIXUP(MEI_UUID_HDCP, whitelist), MEI_FIXUP(MEI_UUID_ANY, vt_support), MEI_FIXUP(MEI_UUID_PAVP, whitelist), diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 9748d14849a1..7e77328142ff 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1577,12 +1577,14 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = =3D { static const struct mei_cfg mei_me_gsc_cfg =3D { MEI_CFG_TYPE_GSC, MEI_CFG_PCH8_HFS, + MEI_CFG_FW_VER_SUPP, }; =20 /* Graphics System Controller Firmware Interface */ static const struct mei_cfg mei_me_gscfi_cfg =3D { MEI_CFG_TYPE_GSCFI, MEI_CFG_PCH8_HFS, + MEI_CFG_FW_VER_SUPP, }; =20 /* --=20 2.32.0