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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id m12sm1534185ejr.218.2022.02.05.04.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Feb 2022 04:00:49 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/5] dt-bindings: memory: lpddr3: convert to dtschema Date: Sat, 5 Feb 2022 13:00:39 +0100 Message-Id: <20220205120043.8337-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> References: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the LPDDR3 memory bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/ddr/jedec,lpddr3.yaml | 266 ++++++++++++++++++ .../memory-controllers/ddr/lpddr3.txt | 107 ------- 2 files changed, 266 insertions(+), 107 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,lpddr3.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/dd= r/lpddr3.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml new file mode 100644 index 000000000000..c8577186324a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -0,0 +1,266 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + items: + - enum: + - samsung,K3QF2F20DB + - const: jedec,lpddr3 + + '#address-cells': + const: 1 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density in megabits of SDRAM chip. + enum: + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip. + enum: + - 64 + - 32 + - 16 + - 8 + + manufacturer-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Manufacturer ID value read from Mode Register 5. + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + maximum: 255 + description: | + Revision value of SDRAM chip read from Mode Registers 6 and 7. + + '#size-cells': + const: 0 + + tCKE-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. + + tCKESR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. + + tDQSCK-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + DQS output data access time from CK_t/CK_c in terms of number of clo= ck + cycles. + + tFAW-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Four-bank activate window in terms of number of clock cycles. + + tMRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Mode register set command delay in terms of number of clock cycles. + + tR2R-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional READ-to-READ delay in chip-to-chip cases in terms of numb= er + of clock cycles. + + tRAS-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Row active time in terms of number of clock cycles. + + tRC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + ACTIVATE-to-ACTIVATE command period in terms of number of clock cycl= es. + + tRCD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + RAS-to-CAS delay in terms of number of clock cycles. + + tRFC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Refresh Cycle time in terms of number of clock cycles. + + tRL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + READ data latency in terms of number of clock cycles. + + tRPab-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + + tRPpb-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (single banks) in terms of number of clock cycles. + + tRRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Active bank A to active bank B in terms of number of clock cycles. + + tRTP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. + + tW2W-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of nu= mber + of clock cycles. + + tWL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE data latency in terms of number of clock cycles. + + tWR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE recovery time in terms of number of clock cycles. + + tWTR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cyc= les. + + tXP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Exit power-down to next valid command delay in terms of number of cl= ock + cycles. + + tXSR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1023 + description: | + SELF REFRESH exit to next valid command delay in terms of number of = clock + cycles. + +patternProperties: + "^timings@[0-9a-f]+$": + type: object + description: | + The lpddr3 node may have one or more child nodes with timings. + Each timing node provides AC timing parameters of the device for a g= iven + speed-bin. The user may provide the timings for as many speed-bins a= s is + required. For more information please see:: + Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timi= ngs.txt + +required: + - compatible + - '#address-cells' + - density + - io-width + - '#size-cells' + +additionalProperties: false + +examples: + - | + lpddr3 { + compatible =3D "samsung,K3QF2F20DB", "jedec,lpddr3"; + density =3D <16384>; + io-width =3D <32>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tCKE-min-tck =3D <2>; + tCKESR-min-tck =3D <2>; + tDQSCK-min-tck =3D <5>; + tFAW-min-tck =3D <5>; + tMRD-min-tck =3D <5>; + tR2R-C2C-min-tck =3D <0>; + tRAS-min-tck =3D <5>; + tRC-min-tck =3D <6>; + tRCD-min-tck =3D <3>; + tRFC-min-tck =3D <17>; + tRL-min-tck =3D <14>; + tRPab-min-tck =3D <2>; + tRPpb-min-tck =3D <2>; + tRRD-min-tck =3D <2>; + tRTP-min-tck =3D <2>; + tW2W-C2C-min-tck =3D <0>; + tWL-min-tck =3D <8>; + tWR-min-tck =3D <7>; + tWTR-min-tck =3D <2>; + tXP-min-tck =3D <2>; + tXSR-min-tck =3D <12>; + + timings@800000000 { + compatible =3D "jedec,lpddr3-timings"; + reg =3D <800000000>; + min-freq =3D <100000000>; + tCKE =3D <3750>; + tCKESR =3D <3750>; + tFAW =3D <25000>; + tMRD =3D <7000>; + tR2R-C2C =3D <0>; + tRAS =3D <23000>; + tRC =3D <33750>; + tRCD =3D <10000>; + tRFC =3D <65000>; + tRPab =3D <12000>; + tRPpb =3D <12000>; + tRRD =3D <6000>; + tRTP =3D <3750>; + tW2W-C2C =3D <0>; + tWR =3D <7500>; + tWTR =3D <3750>; + tXP =3D <3750>; + tXSR =3D <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr= 3.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt deleted file mode 100644 index 031af5fb0379..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt +++ /dev/null @@ -1,107 +0,0 @@ -* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C - -Required properties: -- compatible : Should be ",", and generic value "jedec,lpddr= 3". - Example "," values: - "samsung,K3QF2F20DB" - -- density : representing density in Mb (Mega bits) -- io-width : representing bus width. Possible values are 8, 16, 32, = 64 -- #address-cells: Must be set to 1 -- #size-cells: Must be set to 0 - -Optional properties: - -- manufacturer-id : Manufacturer ID value read from Mode Registe= r 5 -- revision-id : Revision IDs read from Mode Registers 6 and 7 - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRFC-min-tck -- tRRD-min-tck -- tRPab-min-tck -- tRPpb-min-tck -- tRCD-min-tck -- tRC-min-tck -- tRAS-min-tck -- tWTR-min-tck -- tWR-min-tck -- tRTP-min-tck -- tW2W-C2C-min-tck -- tR2R-C2C-min-tck -- tWL-min-tck -- tDQSCK-min-tck -- tRL-min-tck -- tFAW-min-tck -- tXSR-min-tck -- tXP-min-tck -- tCKE-min-tck -- tCKESR-min-tck -- tMRD-min-tck - -Child nodes: -- The lpddr3 node may have one or more child nodes of type "lpddr3-timings= ". - "lpddr3-timings" provides AC timing parameters of the device for - a given speed-bin. Please see - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.= txt - for more information on "lpddr3-timings" - -Example: - -samsung_K3QF2F20DB: lpddr3 { - compatible =3D "samsung,K3QF2F20DB", "jedec,lpddr3"; - density =3D <16384>; - io-width =3D <32>; - manufacturer-id =3D <1>; - revision-id =3D <123 234>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - tRFC-min-tck =3D <17>; - tRRD-min-tck =3D <2>; - tRPab-min-tck =3D <2>; - tRPpb-min-tck =3D <2>; - tRCD-min-tck =3D <3>; - tRC-min-tck =3D <6>; - tRAS-min-tck =3D <5>; - tWTR-min-tck =3D <2>; - tWR-min-tck =3D <7>; - tRTP-min-tck =3D <2>; - tW2W-C2C-min-tck =3D <0>; - tR2R-C2C-min-tck =3D <0>; - tWL-min-tck =3D <8>; - tDQSCK-min-tck =3D <5>; - tRL-min-tck =3D <14>; - tFAW-min-tck =3D <5>; - tXSR-min-tck =3D <12>; - tXP-min-tck =3D <2>; - tCKE-min-tck =3D <2>; - tCKESR-min-tck =3D <2>; - tMRD-min-tck =3D <5>; - - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible =3D "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg =3D <800000000>; - min-freq =3D <100000000>; - tRFC =3D <65000>; - tRRD =3D <6000>; - tRPab =3D <12000>; - tRPpb =3D <12000>; - tRCD =3D <10000>; - tRC =3D <33750>; - tRAS =3D <23000>; - tWTR =3D <3750>; - tWR =3D <7500>; - tRTP =3D <3750>; - tW2W-C2C =3D <0>; - tR2R-C2C =3D <0>; - tFAW =3D <25000>; - tXSR =3D <70000>; - tXP =3D <3750>; - tCKE =3D <3750>; - tCKESR =3D <3750>; - tMRD =3D <7000>; - }; -} --=20 2.32.0 From nobody Mon Jun 29 17:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BBC1C433F5 for ; Sat, 5 Feb 2022 12:01:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379791AbiBEMBD (ORCPT ); Sat, 5 Feb 2022 07:01:03 -0500 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]:51886 "EHLO smtp-relay-internal-0.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379131AbiBEMAz (ORCPT ); Sat, 5 Feb 2022 07:00:55 -0500 Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 8DDD53F22B for ; Sat, 5 Feb 2022 12:00:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644062454; bh=o1EGYrWsRqx/bd/p11jiwzAPNZIWt1CcXa2YB+SDcqU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QeS2HxGH7uiwxSa1PZEAYLi9o1XDqAz7+D6S6at8knYmGyV+Pi7WA1BpOXlr0yBWc AIqCR/FzaaLm++6QDlG5BpA5Y7XzshDLY6qFy9C/A6lRoZ/TbRj+OkzD50p+iy+0wn 8B29LCFXOuQDDg3y1Ehgg0MPf+Q1bUt74zFcaFBbosYGlTrbzcsJVcbjrlwh1oYW3G UTVKM40dYsORjQmLB3wi/nFTUT0bUSHpIKaH84bZn4hMwTiHB6dk3P/hlJ5ArndPks h5lEWV0O2ULhrwgYo2z6RmKjMwiB/fZYDZ5zaPCkqYDFsTIFgo5QHuRBLbBu1RH9lE HYFW19bp4onYA== Received: by mail-ed1-f70.google.com with SMTP id p17-20020aa7c891000000b004052d1936a5so4570421eds.7 for ; Sat, 05 Feb 2022 04:00:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o1EGYrWsRqx/bd/p11jiwzAPNZIWt1CcXa2YB+SDcqU=; b=ymPHLgRndgsEFbgM1F7LG48kMRU/34WW/aHgRtRH8s2k9n7ITLd1uDo9eMgS7Gb0Kh Z4eBivkgSeuTEwfyyK/q+04JKJiIokE2aU5zevsBIsiCLhZUfuvlb/5SAY7jUMc5cPP2 RD9mO4kRCPXBvGJWNmNfmxNgM2ZwngyXixbTj+svnSQyw2G4kQEIVZ1nsnRgQ9mKsYJA eRt6Df1nvNr63iQVQk9DXvibXNGmGXLd+5RJxgxovotBqkuEHms32QxSAjIvsV0dvfMN nHuLALqBinEuJJCQgp9P98QFEuCzd8svBuDv4zi2O3/wifYLvAJGs9LusvuJtpafndkI ksrQ== X-Gm-Message-State: AOAM5330PXN7X185z6um0SJqdMYhZSG9AvtWhmqfFRQCtucUVgwXLvra Bp9kSmFaCnJAYFeK1HzFcsivYate21yb6jwQPkpsI4igmOeSiNW2bNQIGrdLOiU2v9N4Aba5p+A HwPeihNJTyFbJC3XrocoZ20qdV+hMb7DhN6c5x7vZCA== X-Received: by 2002:a17:907:e86:: with SMTP id ho6mr2798333ejc.107.1644062453438; Sat, 05 Feb 2022 04:00:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJwQlCeqMz26UIEovHWLj3a0eLUbdAk51v9fPINLLN0Da01Ex++DNyWpYgFCBrBW2KGNFSgF0w== X-Received: by 2002:a17:907:e86:: with SMTP id ho6mr2798315ejc.107.1644062453210; Sat, 05 Feb 2022 04:00:53 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id m12sm1534185ejr.218.2022.02.05.04.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Feb 2022 04:00:51 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/5] dt-bindings: memory: lpddr3: adjust IO width to spec Date: Sat, 5 Feb 2022 13:00:40 +0100 Message-Id: <20220205120043.8337-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> References: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only 16- and 32-bit IO width. Drop the unsupported others. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml index c8577186324a..0c8353c11767 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -34,10 +34,8 @@ properties: description: | IO bus width in bits of SDRAM chip. enum: - - 64 - 32 - 16 - - 8 =20 manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 --=20 2.32.0 From nobody Mon Jun 29 17:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8860EC433F5 for ; Sat, 5 Feb 2022 12:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379773AbiBEMBG (ORCPT ); Sat, 5 Feb 2022 07:01:06 -0500 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:44390 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379718AbiBEMA4 (ORCPT ); Sat, 5 Feb 2022 07:00:56 -0500 Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 8B92140038 for ; Sat, 5 Feb 2022 12:00:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644062455; bh=OuVWT+OxqE323DEVUlu5DyHs7hHuGTLMdHDm6pwqNSI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N5l1jinDQVSe5Mv4Q0cYSDbESGzbhgOeCLLdhGgAc24ufCnUP6OfEv3H55IHPrJqz N1U99ue0Q87NBTGDt9xKCCD9jsc5jaVltzy/deICM4M12jSCbWzq9h93SJhWYhF7CA 2SwD48E6OYMF8xo9TdlnjzUMPLQpxDH/jY3eGHbwlMJKwKI+c4wnFgMpqZpDFq9nPb a4N42/xguDLyOfyfBn4jBl6LfrqmU3gJxIkZqT845cah0ONUu52t67g4cVzRq73bsJ oOfbVUfEE8U5/wbNo7dVaN4ZlT2UmqcZoxUcHUac+2YN8FH3jXkaMtCi0Q9Q8ncc8d XQJnH72L/QVlA== Received: by mail-ed1-f72.google.com with SMTP id k5-20020a508ac5000000b00408dec8390aso4517191edk.13 for ; Sat, 05 Feb 2022 04:00:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OuVWT+OxqE323DEVUlu5DyHs7hHuGTLMdHDm6pwqNSI=; b=XPsxMarHPCUSTNuMWHTnfwkuRLvtCbd5dpNhgvACckfvmCwDUG3scQsJ4PVnpOUjeR nde0DYLzGeoXH0XhtofWmJC0uS0mJj3ZZ2fJHOSRvq/PKcgZMYYk6eCduS+JdRY8nNsO 5BufgUVrvpq9Woghlhw5R1Xm9lVewbEhzAta8f1bIUowaPlYeXJzjahRil6vEUIKA4kQ hnS6XGuYC8sE5YAmMrgmTbdKJiZDLjw2R31RtxvN6Z8reTPrqEaWGUKA5x38oGmYmLFZ gSpBkhJtS2fQgvlaFqIQIaMSxAYlMGAYK/kdBfjnMkQkKu1ZwjCPbSdlujFkEq15Vuyp Kf3A== X-Gm-Message-State: AOAM531CVkLihlIChR1V3vaLkDhKlvaSTVkmh6IvvN7pRr+Y8VmoY1YX c6z4U/ZgiME8GbfBSfaQsOndMFJytaJ7BB9M1nd5ZLzdDsqds6D3ssZqAy0M8D1RsuCTYhB1P4W Ryf4XxRjBmE9UP1W35oWJDFFtiW9AaGje6tfY68ffyg== X-Received: by 2002:a17:906:43c9:: with SMTP id j9mr683863ejn.652.1644062455284; Sat, 05 Feb 2022 04:00:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJw1Mfepppy+jyN7m6yTpySmK5tZkCeWnsio2ctwMkbDoEsk7W8TQZsy4nTTRgAd/Wm47p/TjQ== X-Received: by 2002:a17:906:43c9:: with SMTP id j9mr683853ejn.652.1644062455141; Sat, 05 Feb 2022 04:00:55 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id m12sm1534185ejr.218.2022.02.05.04.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Feb 2022 04:00:53 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/5] dt-bindings: memory: lpddr3: deprecated manufacturer ID Date: Sat, 5 Feb 2022 13:00:41 +0100 Message-Id: <20220205120043.8337-4-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> References: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The memory manufacturer should be described in vendor part of compatible, so there is no need to duplicate it in separate property. Similarly is done in LPDDR2 bindings. Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml index 0c8353c11767..138c57d8a375 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -40,7 +40,9 @@ properties: manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | - Manufacturer ID value read from Mode Register 5. + Manufacturer ID value read from Mode Register 5. The property is + deprecated, manufacturer should be derived from the compatible. + deprecated: true =20 revision-id: $ref: /schemas/types.yaml#/definitions/uint32-array --=20 2.32.0 From nobody Mon Jun 29 17:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE2CFC433EF for ; Sat, 5 Feb 2022 12:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379792AbiBEMBK (ORCPT ); Sat, 5 Feb 2022 07:01:10 -0500 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:44404 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379748AbiBEMA6 (ORCPT ); Sat, 5 Feb 2022 07:00:58 -0500 Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 191B840039 for ; Sat, 5 Feb 2022 12:00:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644062457; bh=WADk9zGuYiMHMUgeqEWKXcx1LnePmBdOwPQaJwQS8DQ=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZxfxFSmt/TEuN2/C/oy//dCrtaBjiBmzGCb8QQylhStcOwHGV6Oa8/AtJFQDORFJT 3hg3EwAnLa2+TL9EnEJxy6WMWHvJtZOY/L0zZdD4Dlona1z52LlVaXWspJhfMTsDhC WLsg33C5Ij3d7RFnSuQEO7sqEa/JNWQA6+o21IU8uDova2ZFWOp1BRYJHcENtDtue+ oJu/+H4qy4/arv1aOwzcEteufaf0OG20qDVN+opl9ROuEvplGZGJLx/GY2IIJgBXvQ Q6Wk+GDNmAUenfFOfkYioR3HwUCsgeHs7ou0N3KNYpJZmJnpxrxy/l+Ew9VhorANYF UVit+dONuW1Mg== Received: by mail-ed1-f72.google.com with SMTP id l16-20020aa7c3d0000000b004070ea10e7fso4540144edr.3 for ; Sat, 05 Feb 2022 04:00:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WADk9zGuYiMHMUgeqEWKXcx1LnePmBdOwPQaJwQS8DQ=; b=wvEyhkvg2Y4wV2u8DUHpVHt+/Mckel5S5WRh9DKNRZKrD1m/vn6l+Y25yqMrxmk+6B kEr6BJOLdCrqY1vyJbz2zx1Z1/YkvIzdmGc7/LLR2nZcpMNjCj1gN9Jrb1uE3HWkhQk7 e3qVBHIiIdChIjOk0c13z//NXf83SWXx+FJ6eznY/E4Mqpb3ReYlOWviLUbFZ3TrTUR6 yl3OjrhPO4rFqsfpAA3HSt/5Zg/ykoNaBMMa5lG4oaTCmwgCiotAQvee/MDe6XbCjxo8 WU2HCBcuqjX668QOIgIySLstMgN/LqMdO9zwyUWNe9h9t916wsDDWB7K1NxW2T5fP+a/ phuA== X-Gm-Message-State: AOAM533E1agNuCfnXjkcp8ufIcSqArgj1FBNd/yc1pB1oiNY4PzG58Kv trIDTWaJARWWUwDE5C2FCsom8q+E1NFsQt7PRcMO72PGTO5G0RSSJkWalDdVqv7975fRByJnhzL E9DS/xu1Ar7EfA2xLtlKaTBEBpn2iPyGyoTIqovptWg== X-Received: by 2002:a17:907:1115:: with SMTP id qu21mr500660ejb.192.1644062456582; Sat, 05 Feb 2022 04:00:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJwdDb/Oy63JfThb6RHO+fcj4vWXFUEzdGR2GMzdot79rG2sem5U9YQ+tSHyyR37SQhyj/6jfw== X-Received: by 2002:a17:907:1115:: with SMTP id qu21mr500639ejb.192.1644062456285; Sat, 05 Feb 2022 04:00:56 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id m12sm1534185ejr.218.2022.02.05.04.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Feb 2022 04:00:55 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] dt-bindings: memory: lpddr3-timings: convert to dtschema Date: Sat, 5 Feb 2022 13:00:42 +0100 Message-Id: <20220205120043.8337-5-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> References: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the LPDDR3 memory timings bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Osipenko --- .../ddr/jedec,lpddr3-timings.yaml | 153 ++++++++++++++++++ .../memory-controllers/ddr/jedec,lpddr3.yaml | 5 +- .../memory-controllers/ddr/lpddr3-timings.txt | 58 ------- 3 files changed, 155 insertions(+), 61 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,lpddr3-timings.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/dd= r/lpddr3-timings.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3-timings.yaml b/Documentation/devicetree/bindings/memory-controllers= /ddr/jedec,lpddr3-timings.yaml new file mode 100644 index 000000000000..98bc219e8a25 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= -timings.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-tim= ings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr3-timings + + reg: + maxItems: 1 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKE: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tMRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Mode register set command delay in pico seconds. + + tR2R-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional READ-to-READ delay in chip-to-chip cases in pico seconds. + + tRAS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + ACTIVATE-to-ACTIVATE command period in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRFC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Refresh Cycle time in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRPpb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (single banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tW2W-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in pico second= s. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tXSR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + +required: + - compatible + - min-freq + - reg + +additionalProperties: false + +examples: + - | + lpddr3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + timings@800000000 { + compatible =3D "jedec,lpddr3-timings"; + reg =3D <800000000>; + min-freq =3D <100000000>; + tCKE =3D <3750>; + tCKESR =3D <3750>; + tFAW =3D <25000>; + tMRD =3D <7000>; + tR2R-C2C =3D <0>; + tRAS =3D <23000>; + tRC =3D <33750>; + tRCD =3D <10000>; + tRFC =3D <65000>; + tRPab =3D <12000>; + tRPpb =3D <12000>; + tRRD =3D <6000>; + tRTP =3D <3750>; + tW2W-C2C =3D <0>; + tWR =3D <7500>; + tWTR =3D <3750>; + tXP =3D <3750>; + tXSR =3D <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml index 138c57d8a375..3bcba15098ea 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -192,13 +192,12 @@ properties: =20 patternProperties: "^timings@[0-9a-f]+$": - type: object + $ref: jedec,lpddr3-timings.yaml description: | The lpddr3 node may have one or more child nodes with timings. Each timing node provides AC timing parameters of the device for a g= iven speed-bin. The user may provide the timings for as many speed-bins a= s is - required. For more information please see:: - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timi= ngs.txt + required. =20 required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr= 3-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lp= ddr3-timings.txt deleted file mode 100644 index 84705e50a3fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timin= gs.txt +++ /dev/null @@ -1,58 +0,0 @@ -* AC timing parameters of LPDDR3 memories for a given speed-bin. - -The structures are based on LPDDR2 and extended where needed. - -Required properties: -- compatible : Should be "jedec,lpddr3-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- reg : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). -- tRFC -- tRRD -- tRPab -- tRPpb -- tRCD -- tRC -- tRAS -- tWTR -- tWR -- tRTP -- tW2W-C2C -- tR2R-C2C -- tFAW -- tXSR -- tXP -- tCKE -- tCKESR -- tMRD - -Example: - -timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible =3D "jedec,lpddr3-timings"; - reg =3D <800000000>; /* workaround: it shows max-freq */ - min-freq =3D <100000000>; - tRFC =3D <65000>; - tRRD =3D <6000>; - tRPab =3D <12000>; - tRPpb =3D <12000>; - tRCD =3D <10000>; - tRC =3D <33750>; - tRAS =3D <23000>; - tWTR =3D <3750>; - tWR =3D <7500>; - tRTP =3D <3750>; - tW2W-C2C =3D <0>; - tR2R-C2C =3D <0>; - tFAW =3D <25000>; - tXSR =3D <70000>; - tXP =3D <3750>; - tCKE =3D <3750>; - tCKESR =3D <3750>; - tMRD =3D <7000>; -}; --=20 2.32.0 From nobody Mon Jun 29 17:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDC37C433EF for ; Sat, 5 Feb 2022 12:01:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379798AbiBEMBQ (ORCPT ); Sat, 5 Feb 2022 07:01:16 -0500 Received: from smtp-relay-internal-0.canonical.com ([185.125.188.122]:51924 "EHLO smtp-relay-internal-0.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379765AbiBEMA7 (ORCPT ); Sat, 5 Feb 2022 07:00:59 -0500 Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id A19073FFD5 for ; Sat, 5 Feb 2022 12:00:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1644062458; bh=g79GJtLoFuJ8U8Z2lTNpbcsjEt2E+NY0Ue5nQV27Nic=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tABg2deBDOrojsLWYyxJt4k0cRiRdRF8f8Yq8DyhZT9PFYKdoRbFSf9DYrwaQ0wSb N9CVkIAsms0Z/CmNZf1kRlE6aak/spqC5T/JSK3SFAzLLWajBwpmnMU851e1Q1+Zto DZmMG0wKcWLVo121sYl91C3TFpK5fYOfnglqG9CRm9bzSBy5CdMYM84jCUbhVqmYCE vJv2Ys5oCcB8QLcKDnw4ohiTufTR0nLPncikjtwSez4jIGDkCHbNqlr+NA97no3yBU wPaSVT7FueL1RBIQILqgDTDvFE8sLFNWIBH6lKdif5TLP/Qim+ub4zQFyVrkn/O91+ sFUKIQ+k/DRFw== Received: by mail-ed1-f71.google.com with SMTP id l16-20020aa7c3d0000000b004070ea10e7fso4540187edr.3 for ; Sat, 05 Feb 2022 04:00:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g79GJtLoFuJ8U8Z2lTNpbcsjEt2E+NY0Ue5nQV27Nic=; b=urHLIizA62jvzO0Zcwu4FM+B67MJ3ernRFAw2KPPDj+6nuYILRewtQMRJeSjnwY89r /bN+7uiMNiobOhVGmL+EJuhmOuWRHl7NLoad6m6R0anljqzJBeeBB7TUWJaogzfX8JQD 9b8ngGGPuCMkP44Mr6ubrtS1gWGWoHxDj8eQmLDg0w3MlY6ERGSwG/nMaF4HlZF0tvKB 4mmXOt/K62MqJxEYkJjvyewSywzFiXweiVer+51HbJyhmXEJVxKphsmHsXpWLx3uHKBW 6YZWbckNZyh6HO48avOm0owoU/dDGCUV0jxFyZMq03pjnRjPONAw3lPYzMkkqe59RPCT Frcw== X-Gm-Message-State: AOAM531M3ITjv6MNYV1rc0Ipal/Vc3Xv6rNqUHsLV/8XpcR9UOu71Tcf a77D16f+QHhwQ3n4/S8HAK2kX4lHjNn/+xJbSXMoro8Yz3nxA275Mcc44QbeNiWMyukok7v5vTp 1hX1qffjGZmBC+EOBr9CCLFefrz6E6C7DVyufRPL6hQ== X-Received: by 2002:a17:907:8a0b:: with SMTP id sc11mr2782012ejc.310.1644062458119; Sat, 05 Feb 2022 04:00:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJwI6v3KzvqmMl2uZY105l1wUXzopbwZdOW3CekXIXGfOpnK+CNN19iiDFIAfjEEs6/DTmgfdA== X-Received: by 2002:a17:907:8a0b:: with SMTP id sc11mr2781997ejc.310.1644062457861; Sat, 05 Feb 2022 04:00:57 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-168-84.adslplus.ch. [188.155.168.84]) by smtp.gmail.com with ESMTPSA id m12sm1534185ejr.218.2022.02.05.04.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Feb 2022 04:00:56 -0800 (PST) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Rob Herring , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/5] dt-bindings: memory: lpddr2-timings: convert to dtschema Date: Sat, 5 Feb 2022 13:00:43 +0100 Message-Id: <20220205120043.8337-6-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> References: <20220205120043.8337-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the LPDDR2 memory timings bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski --- .../ddr/jedec,lpddr2-timings.yaml | 135 ++++++++++++++++++ .../memory-controllers/ddr/jedec,lpddr2.yaml | 6 +- .../memory-controllers/ddr/lpddr2-timings.txt | 52 ------- 3 files changed, 137 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,lpddr2-timings.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/dd= r/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr2-timings.yaml b/Documentation/devicetree/bindings/memory-controllers= /ddr/jedec,lpddr2-timings.yaml new file mode 100644 index 000000000000..f3e62ee07126 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= -timings.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-tim= ings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr2-timings + + max-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tDQSCK-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c in pico seconds. + + tDQSCK-max-derated: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c, temperature de-rated, in= pico + seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tRAS-max-ns: + description: | + Row active time in nano seconds. + + tRAS-min: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tZQCL: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Long calibration time in pico seconds. + + tZQCS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Short calibration time in pico seconds. + + tZQinit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Initialization calibration time in pico seconds. + +required: + - compatible + - min-freq + - max-freq + +additionalProperties: false + +examples: + - | + timings { + compatible =3D "jedec,lpddr2-timings"; + min-freq =3D <10000000>; + max-freq =3D <400000000>; + tCKESR =3D <15000>; + tDQSCK-max =3D <5500>; + tFAW =3D <50000>; + tRAS-max-ns =3D <70000>; + tRAS-min =3D <42000>; + tRPab =3D <21000>; + tRCD =3D <18000>; + tRRD =3D <10000>; + tRTP =3D <7500>; + tWR =3D <15000>; + tWTR =3D <7500>; + tXP =3D <7500>; + tZQCL =3D <360000>; + tZQCS =3D <90000>; + tZQinit =3D <1000000>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr2.yaml index 25ed0266f6dd..2d8a701e2a05 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml @@ -142,14 +142,12 @@ properties: =20 patternProperties: "^lpddr2-timings": - type: object + $ref: jedec,lpddr2-timings.yaml description: | The lpddr2 node may have one or more child nodes of type "lpddr2-tim= ings". "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/memory-controllers/ddr/lpddr2-timings.txt for more informat= ion - on "lpddr2-timings". + speed-bins as is required. =20 required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr= 2-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lp= ddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timin= gs.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible =3D "jedec,lpddr2-timings"; - min-freq =3D <10000000>; - max-freq =3D <400000000>; - tRPab =3D <21000>; - tRCD =3D <18000>; - tWR =3D <15000>; - tRAS-min =3D <42000>; - tRRD =3D <10000>; - tWTR =3D <7500>; - tXP =3D <7500>; - tRTP =3D <7500>; - tCKESR =3D <15000>; - tDQSCK-max =3D <5500>; - tFAW =3D <50000>; - tZQCS =3D <90000>; - tZQCL =3D <360000>; - tZQinit =3D <1000000>; - tRAS-max-ns =3D <70000>; -}; --=20 2.32.0