From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF32BC433EF for ; Fri, 4 Feb 2022 21:42:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243700AbiBDVmP (ORCPT ); Fri, 4 Feb 2022 16:42:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243450AbiBDVmL (ORCPT ); Fri, 4 Feb 2022 16:42:11 -0500 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23745C061741 for ; Fri, 4 Feb 2022 13:42:10 -0800 (PST) Received: by mail-pj1-x104a.google.com with SMTP id x4-20020a17090ab00400b001b58c484826so9421885pjq.0 for ; Fri, 04 Feb 2022 13:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=jqW8hPDdRJB2oQW7EYj+6p3+zfKz+RTL9qmY/jYFQRo=; b=mxpLoHZxxceqi0+lhEctMV52m3RcDvRtmSBrb5iQNPZmk36kIhoWNYnpPLBkWg+K27 rBdNv2dsoikUnJEgFdv1P01vGeP2JV1ZFV9xJvjVHfBJSlYxAjExg1wGpYBcKt5OvbbQ 6Lg4wzTvrvDOs9R/4BB8EtBaixgrzcpu2qhhe7nwStgd5OKv0k/xsNM+T0HIKyUSE78m 0GGqLbq99uPd74uNMoKl+x0z6q/YaS+TBUJ/r9T4iDCJLPS9lXHaOnVVxNRdIe0eqKfh Ewjj0OJG8ISl90B3zHt2FufYFyJ7rFbhNs0/yZq6bFrPO2tYcUSuXBwysy0g15Ha1dZs i3+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=jqW8hPDdRJB2oQW7EYj+6p3+zfKz+RTL9qmY/jYFQRo=; b=1YE8bOaX25DlcSGRDZy23PS4bqYldMuSwR2JGADrbf8R35bHThrzB5K+g/cRSVM1+z aQEzhZZKb6Xaezx+rHQ0uzTXMztr8Sleh+eURgcI8bsIR71PrNES4xf98IYRwqqABog0 EN3KstWFx6E/INji6WjsvA14qQr70IJDOgsdQwPj1VzCpVJnlA5DtlLU2ygPNapFlb3Z NQVNJsLGJB/MGYURLGNiyiRn6nYuv8Ad2eD/AtuUxBqZr7eYaNphG8SMqVSZ5da0V39f cADOee0JqMb91dU4VauD9BzO4fcMF8k0bvUnCw8sQbisOABLS9NX+Cl1VZ87u/byQcXN +pGA== X-Gm-Message-State: AOAM5312rKoOX7eDl07dsPTJltRQpCAu2t9k8jEcoKPWg55tVvDQgkok UssP0W7obviWI/hSk4KYkFY+J0/9oFk= X-Google-Smtp-Source: ABdhPJybgJWW84dSDuUusL/JqKhOMbJauGmywX5GZ5VlYfiLzIbOHnENEI2942xqrRjXywil9uRm2TS2XJk= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:902:b403:: with SMTP id x3mr5343641plr.61.1644010929602; Fri, 04 Feb 2022 13:42:09 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:41:55 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-2-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 01/11] Revert "svm: Add warning message for AVIC IPI invalid target" From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove a WARN on an "AVIC IPI invalid target" exit, the WARN is trivial to trigger from guest as it will fail on any destination APIC ID that doesn't exist from the guest's perspective. Don't bother recording anything in the kernel log, the common tracepoint for kvm_avic_incomplete_ipi() is sufficient for debugging. This reverts commit 37ef0c4414c9743ba7f1af4392f0a27a99649f2a. Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/avic.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 90364d02f22a..ecc81c48c0ca 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -345,8 +345,6 @@ int avic_incomplete_ipi_interception(struct kvm_vcpu *v= cpu) avic_kick_target_vcpus(vcpu->kvm, apic, icrl, icrh); break; case AVIC_IPI_FAILURE_INVALID_TARGET: - WARN_ONCE(1, "Invalid IPI target: index=3D%u, vcpu=3D%d, icr=3D%#0x:%#0x= \n", - index, vcpu->vcpu_id, icrh, icrl); break; case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: WARN_ONCE(1, "Invalid backing page\n"); --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09358C433F5 for ; Fri, 4 Feb 2022 21:42:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244670AbiBDVmZ (ORCPT ); Fri, 4 Feb 2022 16:42:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243671AbiBDVmM (ORCPT ); Fri, 4 Feb 2022 16:42:12 -0500 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F303C061401 for ; Fri, 4 Feb 2022 13:42:11 -0800 (PST) Received: by mail-pj1-x104a.google.com with SMTP id s9-20020a17090aad8900b001b82d1e4dc8so4271022pjq.6 for ; Fri, 04 Feb 2022 13:42:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=SN0Z+icyOC8azJmY8lil5AT+GqrQYLTXy+CHe5R+yDA=; b=rgBolqPf4C1gRSpaHVzt97AmfFoycWf3gvpXXQU5yyTs/tcpym9X6O9sQrA/ucSv41 5T5lN3f2nuRvKSpJJNYS1yCx+8u2YSTpQzmbbIcrap7trHRAwSqnHM7pEOrWw9tWWLOz dyjBRu8VrP0ceh4TrFjN6Md2g8+zbv4kELjnpEcdBSFG5uZh9JfGnQCrZq0iAroHWq2Z CpJtvjL0+zeM5vXUorgLoE/gwK8OiwT2PH0RWtD1DLscprMZST9cc/6Yt2cwFpc9pkDK C6ufbMRd3XVsZHZBcg0t0j9hTJH4XTdmp1CqHSaIZeCJF2K7dA44dJEUYa+lqES++U+1 cPhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=SN0Z+icyOC8azJmY8lil5AT+GqrQYLTXy+CHe5R+yDA=; b=8BEZ+hZTyQUSo6N0VFgNdh4uTsxEq9swGz8wSc4WrhIxXTkvxFRTBuvHpAupjIJpSS huYLZhhfbC5eIdI8ixP0y0AwU6BsqIzboitRYNIWXdUljo8aUd83OXte7NK1TQ+NjZsq etu+ENntzNcIGHJqXCH+x6tXeq5ppMSGHsYPMSCg8uJC7z+lMKgJDnCYeYHVqGq/EUcC XeExlczhYkbSwDz5DS8yXxikfSWY8cqOBPZ+9OBISh42S4sN6OVm3A3sfmxT7K0q1q9u T40MipJuio9Rye88xqWOL1kl9HTerQvr+1R39mk/DpBF3T8lnMwGBQI3uVX6ON55f5Z2 pZbQ== X-Gm-Message-State: AOAM531UsmTM8/zxFH7vYaW3Spz+J/DFFvvNLJAIEdZ8c7n9Dy41LaRT pE0Qx3h/A/NBjb8K2oeXKADZtmolvrk= X-Google-Smtp-Source: ABdhPJzQXB3jNCCPs2r426cwfrERg3u0KFyRu3mEURa+fe/3WgXQLUz7ChRCmM2gdVmhIuMIs05DsOfhpTU= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a05:6a00:1409:: with SMTP id l9mr5033269pfu.20.1644010931015; Fri, 04 Feb 2022 13:42:11 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:41:56 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-3-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 02/11] KVM: VMX: Handle APIC-write offset wrangling in VMX code From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the vAPIC offset adjustments done in the APIC-write trap path from common x86 to VMX in anticipation of using the nodecode path for SVM's AVIC. The adjustment reflects hardware behavior, i.e. it's technically a property of VMX, no common x86. SVM's AVIC behavior is identical, so it's a bit of a moot point, the goal is purely to make it easier to understand why the adjustment is ok. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 3 --- arch/x86/kvm/vmx/vmx.c | 11 +++++++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4662469240bc..fbce455a9d17 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2188,9 +2188,6 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u= 32 offset) { u32 val =3D 0; =20 - /* hw has done the conditional check and inst decode */ - offset &=3D 0xff0; - kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); =20 /* TODO: optimize to just emulate side effect w/o one more write */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b1165bb13a5a..1b135473677b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5302,9 +5302,16 @@ static int handle_apic_eoi_induced(struct kvm_vcpu *= vcpu) static int handle_apic_write(struct kvm_vcpu *vcpu) { unsigned long exit_qualification =3D vmx_get_exit_qual(vcpu); - u32 offset =3D exit_qualification & 0xfff; =20 - /* APIC-write VM exit is trap-like and thus no need to adjust IP */ + /* + * APIC-write VM-Exit is trap-like, KVM doesn't need to advance RIP and + * hardware has done any necessary aliasing, offset adjustments, etc... + * for the access. I.e. the correct value has already been written to + * the vAPIC page for the correct 16-byte chunk. KVM needs only to + * retrieve the register value and emulate the access. + */ + u32 offset =3D exit_qualification & 0xff0; + kvm_apic_write_nodecode(vcpu, offset); return 1; } --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 042B9C433F5 for ; Fri, 4 Feb 2022 21:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244145AbiBDVmR (ORCPT ); Fri, 4 Feb 2022 16:42:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243601AbiBDVmO (ORCPT ); Fri, 4 Feb 2022 16:42:14 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27D84C061744 for ; Fri, 4 Feb 2022 13:42:13 -0800 (PST) Received: by mail-pj1-x1049.google.com with SMTP id y14-20020a17090ad70e00b001b4fc2943b3so9380638pju.8 for ; Fri, 04 Feb 2022 13:42:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=TdH95enMzJJtQ2GBUCNs/cXCeWPtOzD0p9PqnB4JpY4=; b=e8F5y4+zCpfLkf3ITn/fKXeG/MnU2wzed6XAI/1vnBN0IyKDVi5Ur8Ka4lIs/xw+Ye SnJaBqh1ZIvsiZmW4iiyI5f60WVpXtXiGl8RFEw/NdrsIj4zI/Xt6XcZjMEZW5VyBseI gQOASiGWEF0K1EyygeBP6iNRzZnIiLQCS3q3Tmr6pnvjXMcIYL1oCRqC5C0bZCAG5hG5 fWBwYjCZmB84El+8G5WCIFep5LB8G8/Oy78fc/WRDo94hH4J2TyH+8dtk+TeETM3DpBo GeDjejtXeSg3ohWAFymxUlnXCwZhWTGVZrl9+nThlTWNpcsljofJJ47WYF2v0yZ5CxFd AQmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=TdH95enMzJJtQ2GBUCNs/cXCeWPtOzD0p9PqnB4JpY4=; b=uDgkXWuFR3jrUdFoCNLDljT4O1brmRLL1ctdAYNzg68pzNWO1CSKklq2TsTMJt4sjV 3QT4We8GPwXMwjheDVmZYcaT1Z4s//Rx6pKLfVWf7SRXrp59J0HUrwnxvWWtDlxJNaib rDpyeFIc0azJo5pWhxeSUMS5DOAWbSqSxoFMUHWyh806UxL3JY5KoanA/JS+A7fk9vB4 0oNM/Ren/jTa22nOAUSU5xHi0qKIQOzNqqfiK9QXCZEQaNEqE8ss8PMK14JiC9iUs8vh vfZhnCycms64X32DOGafnD9Xzc7cD/bDPQpqhAl+A64JFQrQ/5tB6oIBfb76ZkwVkH5b quyg== X-Gm-Message-State: AOAM533+DwM0MKSKh+ESBiSLd+aM2cenhrBkPTaRvdf8T1VohyBpwvrX x3WnNUcfGpdIzRXxIKC4k4b2O65iKtk= X-Google-Smtp-Source: ABdhPJwnnfJh8326UurBNxqNtN00zf9kHpWCIxoTekltxMVnjj1SgV8TA0ZRNUkuLuhzB8/J+H0x7OkaQ00= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:902:6f10:: with SMTP id w16mr5054914plk.142.1644010932639; Fri, 04 Feb 2022 13:42:12 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:41:57 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-4-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 03/11] KVM: x86: Use "raw" APIC register read for handling APIC-write VM-Exit From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the "raw" helper to read the vAPIC register after an APIC-write trap VM-Exit. Hardware is responsible for vetting the write, and the caller is responsible for sanitizing the offset. This is a functional change, as it means KVM will consume whatever happens to be in the vAPIC page if the write was dropped by hardware. But, unless userspace deliberately wrote garbage into the vAPIC page via KVM_SET_LAPIC, the value should be zero since it's not writable by the guest. This aligns common x86 with SVM's AVIC logic, i.e. paves the way for using the nodecode path to handle APIC-write traps when AVIC is enabled. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index fbce455a9d17..2c88815657a9 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2186,9 +2186,7 @@ EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); /* emulate APIC access in a trap manner */ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) { - u32 val =3D 0; - - kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); + u32 val =3D kvm_lapic_get_reg(vcpu->arch.apic, offset); =20 /* TODO: optimize to just emulate side effect w/o one more write */ kvm_lapic_reg_write(vcpu->arch.apic, offset, val); --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7BC3C433EF for ; Fri, 4 Feb 2022 21:42:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245016AbiBDVma (ORCPT ); Fri, 4 Feb 2022 16:42:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243843AbiBDVmP (ORCPT ); Fri, 4 Feb 2022 16:42:15 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C213CC061714 for ; Fri, 4 Feb 2022 13:42:14 -0800 (PST) Received: by mail-pj1-x1049.google.com with SMTP id m21-20020a17090b069500b001b532620cd9so4288424pjz.1 for ; Fri, 04 Feb 2022 13:42:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=KKjH3zCPswTf0hjqacVy5YOkSkhUl6n6cultlDnB9r4=; b=k/aPC/mMPGHNoH20HSjvFsILeFwxVaf8/1oUATZ3gMaugfTDdwj3wM6vgZYIU4nQ3n z6bQxP45Mht4VAdettIJ9wpRGDG+RK8Iz2oi2cDaIn1dve93CYueFS85YPJDVlm7axWt S6tW7iL1CnE5gQhMKqG1P2itMRzc1GUcn6ze532LTZLNzyyCbqsnVguGtPc4Bn51JnSJ n4ALN/1fKeUEx0+rL+857zT90+n1A6KUxB7eT/gOidhwqGJMKJ6ERPHmNt+WuXCqVwwe E1J9Tw5Y5jciyjHrZaSljauRntjnYivDlYEAYd/LEYYGf6Kg/du0tG97F/s3umrm4JsG RpDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=KKjH3zCPswTf0hjqacVy5YOkSkhUl6n6cultlDnB9r4=; b=BNo8kqifKfVhlrEdX5hcR33ifFrTb8Ra1sUTk8bLjMwdlpjvVW76Yh4EMbSz3T/x3C 4rZcls4gbGCB2DKWBvUeuMdDxoD3N1ihID+VQ58zgJRGS95tzH8lJwbqqKOJCoBtCaBc Zcr3ztNL3n5SyUKH5giB8pRXO+OUXrGzu4jn/FdGX5FSj1ZVbnYWmhLMouLQCZYNrDis mm2tVEubYwJwzW073ma05VFFfo/mUSOlSIXLggThhsEuf+Il8mfpuQ7supEKdKf/whbn C1yUL/PAcF8ffEjPGfiKxC8ry3rQ1TH+k0HOxewTfNYR3pdX8xrySsCKz0D2gyHoXx6J c3DQ== X-Gm-Message-State: AOAM531zLmKLgZ1AHDxpGoyh0cdBl8ZA+cPYxNX4RGTP+e5g6+V3wjRK WChjhjxIcJkmTBDCb9redRkp9Fx4be8= X-Google-Smtp-Source: ABdhPJyO/YpOUBTWRsnzCsX1L05Kf7rSUUypro5AemY+0lFROqlrme/xEPWu2TDUq3jPILLG9FO3nC2v0QU= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:902:b495:: with SMTP id y21mr5238714plr.82.1644010934301; Fri, 04 Feb 2022 13:42:14 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:41:58 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-5-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 04/11] KVM: SVM: Use common kvm_apic_write_nodecode() for AVIC write traps From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the common kvm_apic_write_nodecode() to handle AVIC/APIC-write traps instead of open coding the same exact code. This will allow making the low level lapic helpers inaccessible outside of lapic.c code. Opportunistically clean up the params to eliminate a bunch of svm=3D>vcpu reflection. No functional change intended. Signed-off-by: Sean Christopherson Reported-by: kernel test robot --- arch/x86/kvm/svm/avic.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index ecc81c48c0ca..462ab073db38 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -476,10 +476,9 @@ static void avic_handle_dfr_update(struct kvm_vcpu *vc= pu) svm->dfr_reg =3D dfr; } =20 -static int avic_unaccel_trap_write(struct vcpu_svm *svm) +static int avic_unaccel_trap_write(struct kvm_vcpu *vcpu) { - struct kvm_lapic *apic =3D svm->vcpu.arch.apic; - u32 offset =3D svm->vmcb->control.exit_info_1 & + u32 offset =3D to_svm(vcpu)->vmcb->control.exit_info_1 & AVIC_UNACCEL_ACCESS_OFFSET_MASK; =20 switch (offset) { @@ -488,18 +487,17 @@ static int avic_unaccel_trap_write(struct vcpu_svm *s= vm) return 0; break; case APIC_LDR: - if (avic_handle_ldr_update(&svm->vcpu)) + if (avic_handle_ldr_update(vcpu)) return 0; break; case APIC_DFR: - avic_handle_dfr_update(&svm->vcpu); + avic_handle_dfr_update(vcpu); break; default: break; } =20 - kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); - + kvm_apic_write_nodecode(vcpu, offset); return 1; } =20 @@ -549,7 +547,7 @@ int avic_unaccelerated_access_interception(struct kvm_v= cpu *vcpu) if (trap) { /* Handling Trap */ WARN_ONCE(!write, "svm: Handling trap read.\n"); - ret =3D avic_unaccel_trap_write(svm); + ret =3D avic_unaccel_trap_write(vcpu); } else { /* Handling Fault */ ret =3D kvm_emulate_instruction(vcpu, 0); --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD3DFC433EF for ; Fri, 4 Feb 2022 21:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245499AbiBDVmg (ORCPT ); Fri, 4 Feb 2022 16:42:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243753AbiBDVmR (ORCPT ); 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charset="utf-8" Don't bother rewriting the ICR value into the vAPIC page on an AVIC IPI virtualization failure, the access is a trap, i.e. the value has already been written to the vAPIC page. The one caveat is if hardware left the BUSY flag set (which appears to happen somewhat arbitrarily), in which case go through the "nodecode" APIC-write path in order to clear the BUSY flag. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 1 + arch/x86/kvm/svm/avic.c | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 2c88815657a9..6e1f9e83eb68 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1298,6 +1298,7 @@ void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 ic= r_low, u32 icr_high) =20 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); } +EXPORT_SYMBOL_GPL(kvm_apic_send_ipi); =20 static u32 apic_get_tmcct(struct kvm_lapic *apic) { diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 462ab073db38..82d56f8055de 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -323,18 +323,18 @@ int avic_incomplete_ipi_interception(struct kvm_vcpu = *vcpu) switch (id) { case AVIC_IPI_FAILURE_INVALID_INT_TYPE: /* - * AVIC hardware handles the generation of - * IPIs when the specified Message Type is Fixed - * (also known as fixed delivery mode) and - * the Trigger Mode is edge-triggered. The hardware - * also supports self and broadcast delivery modes - * specified via the Destination Shorthand(DSH) - * field of the ICRL. Logical and physical APIC ID - * formats are supported. All other IPI types cause - * a #VMEXIT, which needs to emulated. + * Emulate IPIs that are not handled by AVIC hardware, which + * only virtualizes Fixed, Edge-Triggered INTRs. The exit is + * a trap, e.g. ICR holds the correct value and RIP has been + * advanced, KVM is responsible only for emulating the IPI. + * Sadly, hardware may sometimes leave the BUSY flag set, in + * which case KVM needs to emulate the ICR write as well in + * order to clear the BUSY flag. */ - kvm_lapic_reg_write(apic, APIC_ICR2, icrh); - kvm_lapic_reg_write(apic, APIC_ICR, icrl); + if (icrl & APIC_ICR_BUSY) + kvm_apic_write_nodecode(vcpu, APIC_ICR); + else + kvm_apic_send_ipi(apic, icrl, icrh); break; case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: /* --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2008C433F5 for ; Fri, 4 Feb 2022 21:42:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245025AbiBDVmv (ORCPT ); Fri, 4 Feb 2022 16:42:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245281AbiBDVmf (ORCPT ); Fri, 4 Feb 2022 16:42:35 -0500 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 607B7C061757 for ; Fri, 4 Feb 2022 13:42:21 -0800 (PST) Received: by mail-pg1-x549.google.com with SMTP id u24-20020a656718000000b0035e911d79edso3563398pgf.1 for ; Fri, 04 Feb 2022 13:42:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=sgsbkKdz2qv2FXG09nA4Dyprdi3Gq/6g5DB7ZBRJjpY=; b=LfJecY8bfswe0Obq/0ADWYxzAWtAa9m1H+L4CGphGRDFk/50SlEGXI3AgyIkX6GBYu KoVBhn6tjZNXpvuIYwT1UBV4gJXKb4Y6rgqDclKUZd9f56ygrbhZMYwppETmePaNONkd q429IvbPrJc6MXWFRoO2t5hioFu/qm+dzNcXQXyGIaxi4aOkh11eH6giARfwxAr1NyoR 2+lCTFHBy3El6OmRqjP3xMnBSTuMJFSq1Ebm/33SG04kLI/XPe+SMeDsnqikLX8Yu7a4 ht/TwwYyKTn4wqMEQjWs2zL1oSWAx0VE9CvtJ5WsrslrbqsqalSQvwdVRB//tiDOntjK vS2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=sgsbkKdz2qv2FXG09nA4Dyprdi3Gq/6g5DB7ZBRJjpY=; b=DZkiPnycdvCO1mO0UpfmuGF2LR+2uV+m/I5BxSJp/hhl5yFv+CDrSwUtYSKZB3NvGb BKvwtkFkfX/HVrRwQACWiY58M6pKf54IHtW+/zEP1qVEF0Jeq1b6waBMMwlMLRqoNcM/ NkpYWYee405o1CfmkcaVo/d8YSsMw6Cd+7SPX6TiDmVwbIwamQLHTK2u1Iy+eYl8OPKy fwiA6WcS39Q8QROi5/UF/QRTsH4sTMzMpHR7rJc98eQxpeesICZVbi9WofCxekY7houe w159ZflbuGAO/tXDNfTbQQBeitWKhqrPnzRxHR4HrByhT2Ks10XS7Bn9YeJLSpqrJCpi L1yA== X-Gm-Message-State: AOAM5306R+Ka6w8yg4coRD1kG57K/HItbuUy8oq/2O5SPfRSozmpsz/0 uftRzpYBhAnE8KB8LB6NZ2jJ6kFrEPs= X-Google-Smtp-Source: ABdhPJy7FJuqPcLbQKNHEQRuKC9U+zfC0HEdCChADyHE9+q8023qCbOXEFmL4tY7gGtspBZ4TwRkiNVHARw= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:90b:1009:: with SMTP id gm9mr1010663pjb.223.1644010937744; Fri, 04 Feb 2022 13:42:17 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:42:00 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-7-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 06/11] KVM: x86: WARN if KVM emulates an IPI without clearing the BUSY flag From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" WARN if KVM emulates an IPI without clearing the BUSY flag, failure to do so could hang the guest if it waits for the IPI be sent. Opportunistically use APIC_ICR_BUSY macro instead of open coding the magic number, and add a comment to clarify why kvm_recalculate_apic_map() is unconditionally invoked (it's really, really confusing for IPIs due to the existence of fast paths that don't trigger a potential recalc). Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 10 +++++++++- arch/x86/kvm/x86.c | 9 ++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 6e1f9e83eb68..4f57b6f5ebd4 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1282,6 +1282,9 @@ void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 ic= r_low, u32 icr_high) { struct kvm_lapic_irq irq; =20 + /* KVM has no delay and should always clear the BUSY/PENDING flag. */ + WARN_ON_ONCE(icr_low & APIC_ICR_BUSY); + irq.vector =3D icr_low & APIC_VECTOR_MASK; irq.delivery_mode =3D icr_low & APIC_MODE_MASK; irq.dest_mode =3D icr_low & APIC_DEST_MASK; @@ -2060,7 +2063,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 r= eg, u32 val) } case APIC_ICR: /* No delay here, so we always clear the pending bit */ - val &=3D ~(1 << 12); + val &=3D ~APIC_ICR_BUSY; kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); kvm_lapic_set_reg(apic, APIC_ICR, val); break; @@ -2139,6 +2142,11 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 = reg, u32 val) break; } =20 + /* + * Recalculate APIC maps if necessary, e.g. if the software enable bit + * was toggled, the APIC ID changed, etc... The maps are marked dirty + * on relevant changes, i.e. this is a nop for most writes. + */ kvm_recalculate_apic_map(apic->vcpu->kvm); =20 return ret; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c25a6ef0ff06..9024e33c2add 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2012,11 +2012,10 @@ static int handle_fastpath_set_x2apic_icr_irqoff(st= ruct kvm_vcpu *vcpu, u64 data return 1; =20 if (((data & APIC_SHORT_MASK) =3D=3D APIC_DEST_NOSHORT) && - ((data & APIC_DEST_MASK) =3D=3D APIC_DEST_PHYSICAL) && - ((data & APIC_MODE_MASK) =3D=3D APIC_DM_FIXED) && - ((u32)(data >> 32) !=3D X2APIC_BROADCAST)) { - - data &=3D ~(1 << 12); + ((data & APIC_DEST_MASK) =3D=3D APIC_DEST_PHYSICAL) && + ((data & APIC_MODE_MASK) =3D=3D APIC_DM_FIXED) && + ((u32)(data >> 32) !=3D X2APIC_BROADCAST)) { + data &=3D ~APIC_ICR_BUSY; kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57E26C433F5 for ; Fri, 4 Feb 2022 21:42:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243843AbiBDVm6 (ORCPT ); Fri, 4 Feb 2022 16:42:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245257AbiBDVmf (ORCPT ); Fri, 4 Feb 2022 16:42:35 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1224DC061756 for ; Fri, 4 Feb 2022 13:42:20 -0800 (PST) Received: by mail-pj1-x1049.google.com with SMTP id e1-20020a17090ada0100b001b83a55e809so4589955pjv.7 for ; Fri, 04 Feb 2022 13:42:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=k5UFgI2I9MLs2H4ssnRT873l7YLngEbdEt/P0KNnq10=; b=rf3nxdHlYTt9yk9qc8xQwkwU37D+FTjmdYyFbOS1P0CJyzITmO2YxxakNBUTAi09Z7 VmbnBDoG1r+DcWx23X9OgAgLLX/SgwPlURVbet91RkY4W2w9BP85AiNHD1Mx6SSY6CTv 9D18qtAH/LlN4V5MAErzYlF2ZG8mDMM6ifQWpdJCwZzELTkUgbIC4jLNcxOe2sGuc+K4 MZFIYupxHpxirfJNXPedybQj95fb0rldAC7e9pnl+DVVjXliTXlI8CVNyjbyHDTZ0Mpm Un+iqGqPLs15nsCoGBbabN0OC7IT5R/hf5v3NLvZNIA1JeuBmNk5PIuQwZpIRXjCNYRa okkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=k5UFgI2I9MLs2H4ssnRT873l7YLngEbdEt/P0KNnq10=; b=DVF5I4XyZi4GOcspsdWs5jKP21frgkPRUz750PlLzwqcpCQfYDhypbZMqTLzlpHfvy Y5cfuQtsRMTMKXbwY0EvBZlrasLXCBoRrMXAyhN92xe0QQ1ip3yRsW1aGeZ+qz/p6hYh S56ne3NVkMrR+cvyBQuqoeGjZk96GuOLVFcs2tCAkwJKfxru0XGQz0GaJ2jNW1rWTulQ TTGXejsPQediQ5vOIl/6mcKKdt4KMPs48Yn2+q9Il99jh12seFq/8QkgCtATMOhs+9aM INqFyldV3rKfRiLeJjv5HA/0oNbSQkX59Od9kknRDl2FRHVpior4GgTcjKUn/mHwPKFi oS7Q== X-Gm-Message-State: AOAM532SwFeH6+7rzXr2qu1tygBSsDHX6pYj75vCEMSCKUTZS0188nO9 kaKvQandT5UrlEuFtjpzHTTGsjqzl7k= X-Google-Smtp-Source: ABdhPJzobXBMkjgYQ5hcgjZNpX3NLiZ6BOhpRK4BZiHqfM7NniGi2ow+0kFIDeKTi+Z0wVXRqNfwwbQXHks= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:90a:c68c:: with SMTP id n12mr1024171pjt.219.1644010939400; Fri, 04 Feb 2022 13:42:19 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:42:01 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-8-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 07/11] KVM: x86: Make kvm_lapic_reg_{read,write}() static From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the low level read/write lapic helpers static, any accesses to the local APIC from vendor code or non-APIC code should be routed through proper helpers. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 8 +++----- arch/x86/kvm/lapic.h | 3 --- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4f57b6f5ebd4..deac73ce2de5 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1385,8 +1385,8 @@ static inline struct kvm_lapic *to_lapic(struct kvm_i= o_device *dev) #define APIC_REGS_MASK(first, count) \ (APIC_REG_MASK(first) * ((1ull << (count)) - 1)) =20 -int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, - void *data) +static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, + void *data) { unsigned char alignment =3D offset & 0xf; u32 result; @@ -1442,7 +1442,6 @@ int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 of= fset, int len, } return 0; } -EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); =20 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) { @@ -2003,7 +2002,7 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic= *apic, u32 lvt0_val) } } =20 -int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) +static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) { int ret =3D 0; =20 @@ -2151,7 +2150,6 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 r= eg, u32 val) =20 return ret; } -EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); =20 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *th= is, gpa_t address, int len, const void *data) diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 2b44e533fc8d..ab76896a8c3f 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -85,9 +85,6 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); void kvm_recalculate_apic_map(struct kvm *kvm); void kvm_apic_set_version(struct kvm_vcpu *vcpu); -int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); -int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, - void *data); bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, int shorthand, unsigned int dest, int dest_mode); int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2); --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B7BFC433EF for ; Fri, 4 Feb 2022 21:42:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244372AbiBDVmq (ORCPT ); Fri, 4 Feb 2022 16:42:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244203AbiBDVmf (ORCPT ); Fri, 4 Feb 2022 16:42:35 -0500 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A0A2C061759 for ; Fri, 4 Feb 2022 13:42:21 -0800 (PST) Received: by mail-pj1-x104a.google.com with SMTP id z12-20020a17090a1fcc00b001b63e477f9fso4283334pjz.3 for ; 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Fri, 04 Feb 2022 13:42:21 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:42:02 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-9-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 08/11] KVM: x86: Add helpers to handle 64-bit APIC MSR read/writes From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add helpers to handle 64-bit APIC read/writes via MSRs to deduplicate the x2APIC and Hyper-V code needed to service reads/writes to ICR. Future support for IPI virtualization will add yet another path where KVM must handle 64-bit APIC MSR reads/write (to ICR). Opportunistically fix the comment in the write path; ICR2 holds the destination (if there's no shorthand), not the vector. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 59 ++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index deac73ce2de5..f72f3043134e 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2782,6 +2782,30 @@ int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, = gpa_t vapic_addr) return 0; } =20 +static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data) +{ + u32 low, high =3D 0; + + if (kvm_lapic_reg_read(apic, reg, 4, &low)) + return 1; + + if (reg =3D=3D APIC_ICR && + WARN_ON_ONCE(kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high))) + return 1; + + *data =3D (((u64)high) << 32) | low; + + return 0; +} + +static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data) +{ + /* For 64-bit ICR writes, set ICR2 (dest) before ICR (command). */ + if (reg =3D=3D APIC_ICR) + kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); + return kvm_lapic_reg_write(apic, reg, (u32)data); +} + int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) { struct kvm_lapic *apic =3D vcpu->arch.apic; @@ -2793,16 +2817,13 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32= msr, u64 data) if (reg =3D=3D APIC_ICR2) return 1; =20 - /* if this is ICR write vector before command */ - if (reg =3D=3D APIC_ICR) - kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); - return kvm_lapic_reg_write(apic, reg, (u32)data); + return kvm_lapic_msr_write(apic, reg, data); } =20 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) { struct kvm_lapic *apic =3D vcpu->arch.apic; - u32 reg =3D (msr - APIC_BASE_MSR) << 4, low, high =3D 0; + u32 reg =3D (msr - APIC_BASE_MSR) << 4; =20 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) return 1; @@ -2810,45 +2831,23 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 = msr, u64 *data) if (reg =3D=3D APIC_DFR || reg =3D=3D APIC_ICR2) return 1; =20 - if (kvm_lapic_reg_read(apic, reg, 4, &low)) - return 1; - if (reg =3D=3D APIC_ICR) - kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); - - *data =3D (((u64)high) << 32) | low; - - return 0; + return kvm_lapic_msr_read(apic, reg, data); } =20 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) { - struct kvm_lapic *apic =3D vcpu->arch.apic; - if (!lapic_in_kernel(vcpu)) return 1; =20 - /* if this is ICR write vector before command */ - if (reg =3D=3D APIC_ICR) - kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); - return kvm_lapic_reg_write(apic, reg, (u32)data); + return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); } =20 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) { - struct kvm_lapic *apic =3D vcpu->arch.apic; - u32 low, high =3D 0; - if (!lapic_in_kernel(vcpu)) return 1; =20 - if (kvm_lapic_reg_read(apic, reg, 4, &low)) - return 1; - if (reg =3D=3D APIC_ICR) - kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); - - *data =3D (((u64)high) << 32) | low; - - return 0; + return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); } =20 int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long le= n) --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5817EC433EF for ; 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charset="utf-8" Emulate the x2APIC ICR as a single 64-bit register, as opposed to forking it across ICR and ICR2 as two 32-bit registers. This mirrors hardware behavior for Intel's upcoming IPI virtualization support, which does not split the access. Previous versions of Intel's SDM and AMD's APM don't explicitly state exactly how ICR is reflected in the vAPIC page for x2APIC, KVM just happened to speculate incorrectly. Handling the upcoming behavior is necessary in order to maintain backwards compatibility with KVM_{G,S}ET_LAPIC, e.g. failure to shuffle the 64-bit ICR to ICR+ICR2 and vice versa would break live migration if IPI virtualization support isn't symmetrical across the source and dest. Cc: Zeng Guang Cc: Chao Gao Cc: Maxim Levitsky Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 114 +++++++++++++++++++++++++++++++++---------- arch/x86/kvm/lapic.h | 8 ++- arch/x86/kvm/trace.h | 6 +-- arch/x86/kvm/x86.c | 10 +--- 4 files changed, 99 insertions(+), 39 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index f72f3043134e..dd185367a62c 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -68,6 +68,29 @@ static bool lapic_timer_advance_dynamic __read_mostly; /* step-by-step approximation to mitigate fluctuation */ #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8 =20 +static __always_inline u64 __kvm_lapic_get_reg64(char *regs, int reg) +{ + BUILD_BUG_ON(reg !=3D APIC_ICR); + return *((u64 *) (regs + reg)); +} + +static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int= reg) +{ + return __kvm_lapic_get_reg64(apic->regs, reg); +} + +static __always_inline void __kvm_lapic_set_reg64(char *regs, int reg, u64= val) +{ + BUILD_BUG_ON(reg !=3D APIC_ICR); + *((u64 *) (regs + reg)) =3D val; +} + +static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, + int reg, u64 val) +{ + __kvm_lapic_set_reg64(apic->regs, reg, val); +} + static inline int apic_test_vector(int vec, void *bitmap) { return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); @@ -1404,7 +1427,6 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic,= u32 offset, int len, APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) | APIC_REG_MASK(APIC_ESR) | APIC_REG_MASK(APIC_ICR) | - APIC_REG_MASK(APIC_ICR2) | APIC_REG_MASK(APIC_LVTT) | APIC_REG_MASK(APIC_LVTTHMR) | APIC_REG_MASK(APIC_LVTPC) | @@ -1415,9 +1437,16 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic= , u32 offset, int len, APIC_REG_MASK(APIC_TMCCT) | APIC_REG_MASK(APIC_TDCR); =20 - /* ARBPRI is not valid on x2APIC */ + /* + * ARBPRI and ICR2 are not valid in x2APIC mode. WARN if KVM reads ICR + * in x2APIC mode as it's an 8-byte register in x2APIC and needs to be + * manually handled by the caller. + */ if (!apic_x2apic_mode(apic)) - valid_reg_mask |=3D APIC_REG_MASK(APIC_ARBPRI); + valid_reg_mask |=3D APIC_REG_MASK(APIC_ARBPRI) | + APIC_REG_MASK(APIC_ICR2); + else + WARN_ON_ONCE(offset =3D=3D APIC_ICR); =20 if (alignment + len > 4) return 1; @@ -2061,16 +2090,18 @@ static int kvm_lapic_reg_write(struct kvm_lapic *ap= ic, u32 reg, u32 val) break; } case APIC_ICR: + WARN_ON_ONCE(apic_x2apic_mode(apic)); + /* No delay here, so we always clear the pending bit */ val &=3D ~APIC_ICR_BUSY; kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); kvm_lapic_set_reg(apic, APIC_ICR, val); break; - case APIC_ICR2: - if (!apic_x2apic_mode(apic)) - val &=3D 0xff000000; - kvm_lapic_set_reg(apic, APIC_ICR2, val); + if (apic_x2apic_mode(apic)) + ret =3D 1; + else + kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000); break; =20 case APIC_LVT0: @@ -2130,10 +2161,9 @@ static int kvm_lapic_reg_write(struct kvm_lapic *api= c, u32 reg, u32 val) break; =20 case APIC_SELF_IPI: - if (apic_x2apic_mode(apic)) { - kvm_lapic_reg_write(apic, APIC_ICR, - APIC_DEST_SELF | (val & APIC_VECTOR_MASK)); - } else + if (apic_x2apic_mode(apic)) + kvm_x2apic_icr_write(apic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK)); + else ret =3D 1; break; default: @@ -2359,8 +2389,12 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool ini= t_event) if (!apic_x2apic_mode(apic)) kvm_apic_set_ldr(apic, 0); kvm_lapic_set_reg(apic, APIC_ESR, 0); - kvm_lapic_set_reg(apic, APIC_ICR, 0); - kvm_lapic_set_reg(apic, APIC_ICR2, 0); + if (!apic_x2apic_mode(apic)) { + kvm_lapic_set_reg(apic, APIC_ICR, 0); + kvm_lapic_set_reg(apic, APIC_ICR2, 0); + } else { + kvm_lapic_set_reg64(apic, APIC_ICR, 0); + } kvm_lapic_set_reg(apic, APIC_TDCR, 0); kvm_lapic_set_reg(apic, APIC_TMICT, 0); for (i =3D 0; i < 8; i++) { @@ -2577,6 +2611,7 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, if (apic_x2apic_mode(vcpu->arch.apic)) { u32 *id =3D (u32 *)(s->regs + APIC_ID); u32 *ldr =3D (u32 *)(s->regs + APIC_LDR); + u64 icr; =20 if (vcpu->kvm->arch.x2apic_format) { if (*id !=3D vcpu->vcpu_id) @@ -2588,9 +2623,21 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcp= u, *id <<=3D 24; } =20 - /* In x2APIC mode, the LDR is fixed and based on the id */ - if (set) + /* + * In x2APIC mode, the LDR is fixed and based on the id. And + * ICR is internally a single 64-bit register, but needs to be + * split to ICR+ICR2 in userspace for backwards compatibility. + */ + if (set) { *ldr =3D kvm_apic_calc_x2apic_ldr(*id); + + icr =3D __kvm_lapic_get_reg(s->regs, APIC_ICR) | + (u64)__kvm_lapic_get_reg(s->regs, APIC_ICR2) << 32; + __kvm_lapic_set_reg64(s->regs, APIC_ICR, icr); + } else { + icr =3D __kvm_lapic_get_reg64(s->regs, APIC_ICR); + __kvm_lapic_set_reg(s->regs, APIC_ICR2, icr >> 32); + } } =20 return 0; @@ -2782,27 +2829,43 @@ int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu,= gpa_t vapic_addr) return 0; } =20 +int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data) +{ + data &=3D ~APIC_ICR_BUSY; + + kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32)); + kvm_lapic_set_reg64(apic, APIC_ICR, data); + trace_kvm_apic_write(APIC_ICR, data); + return 0; +} + static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data) { - u32 low, high =3D 0; + u32 low; + + if (reg =3D=3D APIC_ICR) { + *data =3D kvm_lapic_get_reg64(apic, APIC_ICR); + return 0; + } =20 if (kvm_lapic_reg_read(apic, reg, 4, &low)) return 1; =20 - if (reg =3D=3D APIC_ICR && - WARN_ON_ONCE(kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high))) - return 1; - - *data =3D (((u64)high) << 32) | low; + *data =3D low; =20 return 0; } =20 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data) { - /* For 64-bit ICR writes, set ICR2 (dest) before ICR (command). */ + /* + * ICR is a 64-bit register in x2APIC mode (and Hyper'v PV vAPIC) and + * can be written as such, all other registers remain accessible only + * through 32-bit reads/writes. + */ if (reg =3D=3D APIC_ICR) - kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); + return kvm_x2apic_icr_write(apic, data); + return kvm_lapic_reg_write(apic, reg, (u32)data); } =20 @@ -2814,9 +2877,6 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 m= sr, u64 data) if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) return 1; =20 - if (reg =3D=3D APIC_ICR2) - return 1; - return kvm_lapic_msr_write(apic, reg, data); } =20 @@ -2828,7 +2888,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 ms= r, u64 *data) if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) return 1; =20 - if (reg =3D=3D APIC_DFR || reg =3D=3D APIC_ICR2) + if (reg =3D=3D APIC_DFR) return 1; =20 return kvm_lapic_msr_read(apic, reg, data); diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index ab76896a8c3f..e39e7ec5c2b4 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -118,6 +118,7 @@ int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa= _t vapic_addr); void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); =20 +int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data); int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); =20 @@ -150,9 +151,14 @@ static inline void kvm_lapic_set_irr(int vec, struct k= vm_lapic *apic) apic->irr_pending =3D true; } =20 +static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off) +{ + return *((u32 *) (regs + reg_off)); +} + static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) { - return *((u32 *) (apic->regs + reg_off)); + return __kvm_lapic_get_reg(apic->regs, reg_off); } =20 static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val) diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index 92e6f6702f00..340394a8ce7a 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -251,13 +251,13 @@ TRACE_EVENT(kvm_cpuid, * Tracepoint for apic access. */ TRACE_EVENT(kvm_apic, - TP_PROTO(unsigned int rw, unsigned int reg, unsigned int val), + TP_PROTO(unsigned int rw, unsigned int reg, u64 val), TP_ARGS(rw, reg, val), =20 TP_STRUCT__entry( __field( unsigned int, rw ) __field( unsigned int, reg ) - __field( unsigned int, val ) + __field( u64, val ) ), =20 TP_fast_assign( @@ -266,7 +266,7 @@ TRACE_EVENT(kvm_apic, __entry->val =3D val; ), =20 - TP_printk("apic_%s %s =3D 0x%x", + TP_printk("apic_%s %s =3D 0x%llx", __entry->rw ? "write" : "read", __print_symbolic(__entry->reg, kvm_trace_symbol_apic), __entry->val) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9024e33c2add..eaad2f485b64 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2014,14 +2014,8 @@ static int handle_fastpath_set_x2apic_icr_irqoff(str= uct kvm_vcpu *vcpu, u64 data if (((data & APIC_SHORT_MASK) =3D=3D APIC_DEST_NOSHORT) && ((data & APIC_DEST_MASK) =3D=3D APIC_DEST_PHYSICAL) && ((data & APIC_MODE_MASK) =3D=3D APIC_DM_FIXED) && - ((u32)(data >> 32) !=3D X2APIC_BROADCAST)) { - data &=3D ~APIC_ICR_BUSY; - kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); - kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); - kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); - trace_kvm_apic_write(APIC_ICR, (u32)data); - return 0; - } + ((u32)(data >> 32) !=3D X2APIC_BROADCAST)) + return kvm_x2apic_icr_write(vcpu->arch.apic, data); =20 return 1; } --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2F4FC433EF for ; Fri, 4 Feb 2022 21:43:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245137AbiBDVnJ (ORCPT ); Fri, 4 Feb 2022 16:43:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244869AbiBDVmn (ORCPT ); Fri, 4 Feb 2022 16:42:43 -0500 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD1B6C061762 for ; Fri, 4 Feb 2022 13:42:24 -0800 (PST) Received: by mail-pf1-x44a.google.com with SMTP id u80-20020a627953000000b004c82105f20dso3562458pfc.11 for ; Fri, 04 Feb 2022 13:42:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=NkV3Msgch3zFwH89OWlAlvxffB+RDhruYURC7hCf3XE=; b=Y/9PcR2wxtQOu8vrJPWbtGwHBJoxjOl0ybS/BDNdEgRXAAcUadz2lhRl4+mrbYu8Cq iYrTIUq55RsxkmwX6vHqW+RujwtmEWljWDjPtgnxdlrjxVTnZYmKMEZrOhpctN4jdpS4 cMZ2IMBM1pHffQGgQh69ajLJZlrT2z1SRXag0OtSxHDXDH8W4eo0rQewi71Hso+oFlRf r20xgP7PRdiaDAeuCFWBDxmW/wwGm3seZ6eDfP6RYYG9x9jD4CpBRkfzdP8fcy5ThH5F odZCpjmtKlWAT+srUIYofAFvBWtvFlmin1xtRhDJZdwVZ1PWHVswKGjZcZhtcxtrHdKv 4B7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=NkV3Msgch3zFwH89OWlAlvxffB+RDhruYURC7hCf3XE=; b=s+V9T07NXGTlTtHN8mQvcj6QfznuMONySSpTFemMzyU3WPLl1gSYITOVPI9fD96XNr rXAvmHKtuEHQHefVlChRT7uU9j8c0/Op7dhUTWQBLwso1hdritDG0nUfTj9iiWd0mxc7 RANhjRJ471AQSxjH+zlFK0eMKyV8pfuJKUCw9uaW+/l3vgPcIe+MWjruUUUtYdDdmlKN 1aBfU7Kqg3jTPnYEGU5+lehbRz4osxCpyJHRsNYP+uH58VsykbQmr2WOfxbON3jSlb58 2C5xU8IxRJRRix87eJWy91C8kK3rMXIxdChKM9CIKWdGGu2DpwINzOghhftmGoEV5+08 x8Pw== X-Gm-Message-State: AOAM532R58GFvUuOFsSTf9T3atYNkIFWipnhlMFA5hRBUhc5xGlGQbqU MtGLI29ACjlLmIHls8E3VbkVf7gwV5w= X-Google-Smtp-Source: ABdhPJyX6AXK89iDEI3/dyJx0hocA3ZoDVNZsc/XHIavHl7kK1gj+7CoUbQMAG404RCwBFkjlfEyjx/ZgVA= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a62:7a42:: with SMTP id v63mr4994448pfc.61.1644010944420; Fri, 04 Feb 2022 13:42:24 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:42:04 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-11-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 10/11] KVM: x86: Make kvm_lapic_set_reg() a "private" xAPIC helper From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hide the lapic's "raw" write helper inside lapic.c to force non-APIC code to go through proper helpers when modification the vAPIC state. Keep the read helper visible to outsiders for now, refactoring KVM to hide it too is possible, it will just take more work to do so. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/lapic.c | 10 ++++++++++ arch/x86/kvm/lapic.h | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index dd185367a62c..d60eb6251bed 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -68,6 +68,16 @@ static bool lapic_timer_advance_dynamic __read_mostly; /* step-by-step approximation to mitigate fluctuation */ #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8 =20 +static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val) +{ + *((u32 *) (regs + reg_off)) =3D val; +} + +static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, = u32 val) +{ + __kvm_lapic_set_reg(apic->regs, reg_off, val); +} + static __always_inline u64 __kvm_lapic_get_reg64(char *regs, int reg) { BUILD_BUG_ON(reg !=3D APIC_ICR); diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index e39e7ec5c2b4..4e4f8a22754f 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -161,16 +161,6 @@ static inline u32 kvm_lapic_get_reg(struct kvm_lapic *= apic, int reg_off) return __kvm_lapic_get_reg(apic->regs, reg_off); } =20 -static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val) -{ - *((u32 *) (regs + reg_off)) =3D val; -} - -static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, = u32 val) -{ - __kvm_lapic_set_reg(apic->regs, reg_off, val); -} - DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); =20 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) --=20 2.35.0.263.gb82422642f-goog From nobody Mon Jun 29 17:36:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 189CCC433F5 for ; Fri, 4 Feb 2022 21:43:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346815AbiBDVnH (ORCPT ); Fri, 4 Feb 2022 16:43:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244978AbiBDVmo (ORCPT ); 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d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=CNC4ms+cmGbCyYnugISdjsnBp4L8PCWiPQCO+rJ8ats=; b=JmoSes/+8beQbEnxhzzRX8rXtJiT+JpjJqe8hA9CvWRc1OBmcC3UdDYCgXkFgfQeen wjPoCtEHbpmYXNh/yZMrz+Xv2d20GYUDsj2shwKCmAqlQWTH7dqqwxxJhI64slR8FN+A 8SywaOlFk+S7SnZC1rcyREo400VOQrMXizYpUofWx2CgWPYr+e9TUyKpqOyAgkAR5/kY KBAaKO5Xjdsaimm1x9rSqTw82vs/MofZTdTugxwhHlFBplCkUMEX8hWXuIYymTsvDxS/ ZKEvABoYpFO2KUBzXbZxRv5eyLLq2ysO4HxfALdNGjW7HoFs4jRebYtMDI27d/e5Vgi8 mwew== X-Gm-Message-State: AOAM5310XfAOGyVKTjX9ky8pomIQDyhcP+xFPV/LEy6fpeKsgo2D9ytx jXaePe1eLzjr98g/ro0K8i3FUnSejUk= X-Google-Smtp-Source: ABdhPJz28TUeCeBQDBB1pRTl6JKXzKJZkG+pqg5UukGC5LkjDPArPbqcgCoS5+2cnNYt4XjkBSpSSGu5Fqk= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:903:28c:: with SMTP id j12mr5025482plr.149.1644010945750; Fri, 04 Feb 2022 13:42:25 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 4 Feb 2022 21:42:05 +0000 In-Reply-To: <20220204214205.3306634-1-seanjc@google.com> Message-Id: <20220204214205.3306634-12-seanjc@google.com> Mime-Version: 1.0 References: <20220204214205.3306634-1-seanjc@google.com> X-Mailer: git-send-email 2.35.0.263.gb82422642f-goog Subject: [PATCH 11/11] KVM: selftests: Add test to verify KVM handles x2APIC ICR=>ICR2 dance From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zeng Guang , Chao Gao , Maxim Levitsky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a selftest to verify that KVM copies x2APIC's ICR[63:32] to/from ICR2 when userspace accesses the vAPIC page via KVM_{G,S}ET_LAPIC. KVM previously split x2APIC ICR to ICR+ICR2 at the time of write (from the guest), and so KVM must preserve that behavior for backwards compatibility between different versions of KVM. Opportunsitically test other invariants, e.g. that KVM clears the BUSY flag on ICR writes, that the reserved bits in ICR2 are dropped on writes from the guest, etc... Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/include/x86_64/apic.h | 1 + .../selftests/kvm/x86_64/xapic_state_test.c | 150 ++++++++++++++++++ 4 files changed, 153 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/xapic_state_test.c diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftes= ts/kvm/.gitignore index dce7de7755e6..2b0e47f420b3 100644 --- a/tools/testing/selftests/kvm/.gitignore +++ b/tools/testing/selftests/kvm/.gitignore @@ -45,6 +45,7 @@ /x86_64/vmx_tsc_adjust_test /x86_64/vmx_nested_tsc_scaling_test /x86_64/xapic_ipi_test +/x86_64/xapic_state_test /x86_64/xen_shinfo_test /x86_64/xen_vmcall_test /x86_64/xss_msr_test diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 0e4926bc9a58..4b5211afc6dc 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -76,6 +76,7 @@ TEST_GEN_PROGS_x86_64 +=3D x86_64/vmx_set_nested_state_te= st TEST_GEN_PROGS_x86_64 +=3D x86_64/vmx_tsc_adjust_test TEST_GEN_PROGS_x86_64 +=3D x86_64/vmx_nested_tsc_scaling_test TEST_GEN_PROGS_x86_64 +=3D x86_64/xapic_ipi_test +TEST_GEN_PROGS_x86_64 +=3D x86_64/xapic_state_test TEST_GEN_PROGS_x86_64 +=3D x86_64/xss_msr_test TEST_GEN_PROGS_x86_64 +=3D x86_64/debug_regs TEST_GEN_PROGS_x86_64 +=3D x86_64/tsc_msrs_test diff --git a/tools/testing/selftests/kvm/include/x86_64/apic.h b/tools/test= ing/selftests/kvm/include/x86_64/apic.h index 0be4757f1f20..ac88557dcc9a 100644 --- a/tools/testing/selftests/kvm/include/x86_64/apic.h +++ b/tools/testing/selftests/kvm/include/x86_64/apic.h @@ -33,6 +33,7 @@ #define APIC_SPIV 0xF0 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) #define APIC_SPIV_APIC_ENABLED (1 << 8) +#define APIC_IRR 0x200 #define APIC_ICR 0x300 #define APIC_DEST_SELF 0x40000 #define APIC_DEST_ALLINC 0x80000 diff --git a/tools/testing/selftests/kvm/x86_64/xapic_state_test.c b/tools/= testing/selftests/kvm/x86_64/xapic_state_test.c new file mode 100644 index 000000000000..0792334ba243 --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/xapic_state_test.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define _GNU_SOURCE /* for program_invocation_short_name */ +#include +#include +#include +#include +#include + +#include "apic.h" +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" + +struct kvm_vcpu { + uint32_t id; + bool is_x2apic; +}; + +static void xapic_guest_code(void) +{ + asm volatile("cli"); + + xapic_enable(); + + while (1) { + uint64_t val =3D (u64)xapic_read_reg(APIC_IRR) | + (u64)xapic_read_reg(APIC_IRR + 0x10) << 32; + + xapic_write_reg(APIC_ICR2, val >> 32); + xapic_write_reg(APIC_ICR, val); + GUEST_SYNC(val); + } +} + +static void x2apic_guest_code(void) +{ + asm volatile("cli"); + + x2apic_enable(); + + do { + uint64_t val =3D x2apic_read_reg(APIC_IRR) | + x2apic_read_reg(APIC_IRR + 0x10) << 32; + + x2apic_write_reg(APIC_ICR, val); + GUEST_SYNC(val); + } while (1); +} + +static void ____test_icr(struct kvm_vm *vm, struct kvm_vcpu *vcpu, uint64_= t val) +{ + struct kvm_lapic_state xapic; + struct ucall uc; + uint64_t icr; + + /* + * Tell the guest what ICR value to write. Use the IRR to pass info, + * all bits are valid and should not be modified by KVM (ignoring the + * fact that vectors 0-15 are technically illegal). + */ + vcpu_ioctl(vm, vcpu->id, KVM_GET_LAPIC, &xapic); + *((u32 *)&xapic.regs[APIC_IRR]) =3D val; + *((u32 *)&xapic.regs[APIC_IRR + 0x10]) =3D val >> 32; + vcpu_ioctl(vm, vcpu->id, KVM_SET_LAPIC, &xapic); + + vcpu_run(vm, vcpu->id); + ASSERT_EQ(get_ucall(vm, vcpu->id, &uc), UCALL_SYNC); + ASSERT_EQ(uc.args[1], val); + + vcpu_ioctl(vm, vcpu->id, KVM_GET_LAPIC, &xapic); + icr =3D (u64)(*((u32 *)&xapic.regs[APIC_ICR])) | + (u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32; + if (!vcpu->is_x2apic) + val &=3D (-1u | (0xffull << (32 + 24))); + ASSERT_EQ(icr, val & ~APIC_ICR_BUSY); +} + +static void __test_icr(struct kvm_vm *vm, struct kvm_vcpu *vcpu, uint64_t = val) +{ + ____test_icr(vm, vcpu, val | APIC_ICR_BUSY); + ____test_icr(vm, vcpu, val & ~(u64)APIC_ICR_BUSY); +} + +static void test_icr(struct kvm_vm *vm, struct kvm_vcpu *vcpu) +{ + uint64_t icr, i, j; + + icr =3D APIC_DEST_SELF | APIC_INT_ASSERT | APIC_DM_FIXED; + for (i =3D 0; i <=3D 0xff; i++) + __test_icr(vm, vcpu, icr | i); + + icr =3D APIC_INT_ASSERT | APIC_DM_FIXED; + for (i =3D 0; i <=3D 0xff; i++) + __test_icr(vm, vcpu, icr | i); + + /* + * Send all flavors of IPIs to non-existent vCPUs. TODO: use number of + * vCPUs, not vcpu.id + 1. Arbitrarily use vector 0xff. + */ + icr =3D APIC_INT_ASSERT | 0xff; + for (i =3D vcpu->id + 1; i < 0xff; i++) { + for (j =3D 0; j < 8; j++) + __test_icr(vm, vcpu, i << (32 + 24) | APIC_INT_ASSERT | (j << 8)); + } + + /* And again with a shorthand destination for all types of IPIs. */ + icr =3D APIC_DEST_ALLBUT | APIC_INT_ASSERT; + for (i =3D 0; i < 8; i++) + __test_icr(vm, vcpu, icr | (i << 8)); + + /* And a few garbage value, just make sure it's an IRQ (blocked). */ + __test_icr(vm, vcpu, 0xa5a5a5a5a5a5a5a5 & ~APIC_DM_FIXED_MASK); + __test_icr(vm, vcpu, 0x5a5a5a5a5a5a5a5a & ~APIC_DM_FIXED_MASK); + __test_icr(vm, vcpu, -1ull & ~APIC_DM_FIXED_MASK); +} + +int main(int argc, char *argv[]) +{ + struct kvm_vcpu vcpu =3D { + .id =3D 0, + .is_x2apic =3D true, + }; + struct kvm_cpuid2 *cpuid; + struct kvm_vm *vm; + int i; + + vm =3D vm_create_default(vcpu.id, 0, x2apic_guest_code); + test_icr(vm, &vcpu); + kvm_vm_free(vm); + + /* + * Use a second VM for the xAPIC test so that x2APIC can be hidden from + * the guest in order to test AVIC. KVM disallows changing CPUID after + * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. + */ + vm =3D vm_create_default(vcpu.id, 0, xapic_guest_code); + vcpu.is_x2apic =3D false; + + cpuid =3D vcpu_get_cpuid(vm, vcpu.id); + for (i =3D 0; i < cpuid->nent; i++) { + if (cpuid->entries[i].function =3D=3D 1) + break; + } + cpuid->entries[i].ecx &=3D ~BIT(21); + vcpu_set_cpuid(vm, vcpu.id, cpuid); + + virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); + test_icr(vm, &vcpu); + kvm_vm_free(vm); +} --=20 2.35.0.263.gb82422642f-goog