From nobody Mon Jun 29 19:57:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE45C433FE for ; Fri, 4 Feb 2022 08:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356602AbiBDIab (ORCPT ); Fri, 4 Feb 2022 03:30:31 -0500 Received: from mail.skyhub.de ([5.9.137.197]:42776 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235995AbiBDIa1 (ORCPT ); Fri, 4 Feb 2022 03:30:27 -0500 Received: from zn.tnic (dslb-088-067-221-104.088.067.pools.vodafone-ip.de [88.67.221.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 971ED1EC06AC; Fri, 4 Feb 2022 09:30:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1643963426; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uUxrRkm5Pxwz9YvTSj144qOQmRMXo8XRT92N+FuPrgQ=; b=I9fl7uBhSnCB+uuUXwI9B/lfErkhzXNkW+vyVDhziUHJozeIzwjCV6K4h9TA5Tz+1hUNcf rADB6BMXu55cq7z+ECnfZGQunzy30sQXAfNxyusSRxeaGIB5XDawMRQfwdKjO17LPunkGE RHADnTQlub42GvXxYgz7oz+fBtthV8E= From: Borislav Petkov To: Tony Luck Cc: Jakub Kicinski , Linus Torvalds , Marco Elver , X86 ML , LKML Subject: [PATCH 1/3] cpumask: Add a x86-specific cpumask_clear_cpu() helper Date: Fri, 4 Feb 2022 09:30:13 +0100 Message-Id: <20220204083015.17317-2-bp@alien8.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20220204083015.17317-1-bp@alien8.de> References: <20220204083015.17317-1-bp@alien8.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Borislav Petkov Add a x86-specific cpumask_clear_cpu() helper which will be used in places where the explicit KASAN-instrumentation in the *_bit() helpers is unwanted. Also, always inline two more cpumask generic helpers. allyesconfig: text data bss dec hex filename 190553143 159425889 32076404 382055436 16c5b40c vm= linux.before 190551812 159424945 32076404 382053161 16c5ab29 vm= linux.after Signed-off-by: Borislav Petkov Acked-by: Marco Elver --- arch/x86/include/asm/cpumask.h | 10 ++++++++++ include/linux/cpumask.h | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpumask.h b/arch/x86/include/asm/cpumask.h index 3afa990d756b..c5aed9e9226c 100644 --- a/arch/x86/include/asm/cpumask.h +++ b/arch/x86/include/asm/cpumask.h @@ -20,11 +20,21 @@ static __always_inline bool arch_cpu_online(int cpu) { return arch_test_bit(cpu, cpumask_bits(cpu_online_mask)); } + +static __always_inline void arch_cpumask_clear_cpu(int cpu, struct cpumask= *dstp) +{ + arch_clear_bit(cpumask_check(cpu), cpumask_bits(dstp)); +} #else static __always_inline bool arch_cpu_online(int cpu) { return cpu =3D=3D 0; } + +static __always_inline void arch_cpumask_clear_cpu(int cpu, struct cpumask= *dstp) +{ + return; +} #endif =20 #define arch_cpu_is_offline(cpu) unlikely(!arch_cpu_online(cpu)) diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index 6b06c698cd2a..fe29ac7cc469 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -102,7 +102,7 @@ extern atomic_t __num_online_cpus; =20 extern cpumask_t cpus_booted_once_mask; =20 -static inline void cpu_max_bits_warn(unsigned int cpu, unsigned int bits) +static __always_inline void cpu_max_bits_warn(unsigned int cpu, unsigned i= nt bits) { #ifdef CONFIG_DEBUG_PER_CPU_MAPS WARN_ON_ONCE(cpu >=3D bits); @@ -110,7 +110,7 @@ static inline void cpu_max_bits_warn(unsigned int cpu, = unsigned int bits) } =20 /* verify cpu argument to cpumask_* operators */ -static inline unsigned int cpumask_check(unsigned int cpu) +static __always_inline unsigned int cpumask_check(unsigned int cpu) { cpu_max_bits_warn(cpu, nr_cpumask_bits); return cpu; --=20 2.29.2 From nobody Mon Jun 29 19:57:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47D98C433EF for ; Fri, 4 Feb 2022 08:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356838AbiBDIad (ORCPT ); Fri, 4 Feb 2022 03:30:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356372AbiBDIa3 (ORCPT ); Fri, 4 Feb 2022 03:30:29 -0500 Received: from mail.skyhub.de (mail.skyhub.de [IPv6:2a01:4f8:190:11c2::b:1457]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49A96C061714 for ; Fri, 4 Feb 2022 00:30:29 -0800 (PST) Received: from zn.tnic (dslb-088-067-221-104.088.067.pools.vodafone-ip.de [88.67.221.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 8F0E91EC06BA; Fri, 4 Feb 2022 09:30:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1643963427; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+PQlCVtDGGcQX8X7rNH1W7t9Z75hoyQCmKbUBgEu6LQ=; b=WHtMVIiiPmZQc0KMC6ktN4oX1vKfCzgwFiBGE7q3e1y6vgnUNtlHMn2EXzbC9O/itg/DOr FyhebtHyyDaj23mIHesNw+PuTzYLI3aHTp+7eiwDmzxZl/siHegQsjQbGN/XvPaPKjpnGw GkTkfXQ0riDu3SlIwOX+LC2eRrgoVro= From: Borislav Petkov To: Tony Luck Cc: Jakub Kicinski , Linus Torvalds , Marco Elver , X86 ML , LKML Subject: [PATCH 2/3] x86/ptrace: Always inline v8086_mode() for instrumentation Date: Fri, 4 Feb 2022 09:30:14 +0100 Message-Id: <20220204083015.17317-3-bp@alien8.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20220204083015.17317-1-bp@alien8.de> References: <20220204083015.17317-1-bp@alien8.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Borislav Petkov Instrumentation glue like KASAN causes the following warning: vmlinux.o: warning: objtool: mce_gather_info()+0x5f: call to v8086_mode.c= onstprop.0() leaves .noinstr.text section due to gcc creating a function call for that oneliner. Force-inline it and even save some vmlinux bytes (.config is close to an allmodconfig): text data bss dec hex filename 209431677 208257651 34411048 452100376 1af28118 = vmlinux.before 209431519 208257615 34411048 452100182 1af28056 = vmlinux.after Signed-off-by: Borislav Petkov Acked-by: Marco Elver --- arch/x86/include/asm/ptrace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index 703663175a5a..4357e0f2cd5f 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -137,7 +137,7 @@ static __always_inline int user_mode(struct pt_regs *re= gs) #endif } =20 -static inline int v8086_mode(struct pt_regs *regs) +static __always_inline int v8086_mode(struct pt_regs *regs) { #ifdef CONFIG_X86_32 return (regs->flags & X86_VM_MASK); --=20 2.29.2 From nobody Mon Jun 29 19:57:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA485C433F5 for ; Fri, 4 Feb 2022 08:30:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357011AbiBDIaf (ORCPT ); Fri, 4 Feb 2022 03:30:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356405AbiBDIaa (ORCPT ); Fri, 4 Feb 2022 03:30:30 -0500 Received: from mail.skyhub.de (mail.skyhub.de [IPv6:2a01:4f8:190:11c2::b:1457]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0452AC061714 for ; Fri, 4 Feb 2022 00:30:30 -0800 (PST) Received: from zn.tnic (dslb-088-067-221-104.088.067.pools.vodafone-ip.de [88.67.221.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 7856F1EC06BB; Fri, 4 Feb 2022 09:30:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1643963428; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2Wm/vo/0N1xgCjuTyNPDV+8iEIsMJC/6KGhKiCjg6tE=; b=R8YxpdFuFS+gr1xOASUtnb+bod5Nt6rb2ekO9B7cNlmnruo4zBoWGcLPfEfr+otGcNFBPm ThHdMQHZUGOXnYkLmt7HgG6hOcG9il3MQx3pYeLnVxoj4vZbS6xWwpjnHF1e0+C18hCjf2 RrRVwU2c9wU543cf+ZyW6vAE7s66Ap8= From: Borislav Petkov To: Tony Luck Cc: Jakub Kicinski , Linus Torvalds , Marco Elver , X86 ML , LKML Subject: [PATCH 3/3] x86/mce: Use arch atomic and bit helpers Date: Fri, 4 Feb 2022 09:30:15 +0100 Message-Id: <20220204083015.17317-4-bp@alien8.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20220204083015.17317-1-bp@alien8.de> References: <20220204083015.17317-1-bp@alien8.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Borislav Petkov The arch helpers do not have explicit KASAN instrumentation. Use them in noinstr code. Inline a couple more functions with single call sites, while at it: mce_severity_amd_smca() has a single call-site which is noinstr so force the inlining and fix: vmlinux.o: warning: objtool: mce_severity_amd.constprop.0()+0xca: call to= \ mce_severity_amd_smca() leaves .noinstr.text section Always inline mca_msr_reg(): text data bss dec hex filename 16065240 128031326 36405368 180501934 ac23dae vml= inux.before 16065240 128031294 36405368 180501902 ac23d8e vml= inux.after and mce_no_way_out() as the latter one is used only once, to fix: vmlinux.o: warning: objtool: mce_read_aux()+0x53: call to mca_msr_reg() l= eaves .noinstr.text section vmlinux.o: warning: objtool: do_machine_check()+0xc9: call to mce_no_way_= out() leaves .noinstr.text section Signed-off-by: Borislav Petkov Acked-by: Marco Elver --- arch/x86/kernel/cpu/mce/core.c | 58 ++++++++++-------------------- arch/x86/kernel/cpu/mce/internal.h | 23 ++++++++++-- arch/x86/kernel/cpu/mce/severity.c | 2 +- 3 files changed, 41 insertions(+), 42 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 5818b837fd4d..0e7147430ec0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -173,27 +173,6 @@ void mce_unregister_decode_chain(struct notifier_block= *nb) } EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); =20 -u32 mca_msr_reg(int bank, enum mca_msr reg) -{ - if (mce_flags.smca) { - switch (reg) { - case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); - case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); - case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); - case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); - } - } - - switch (reg) { - case MCA_CTL: return MSR_IA32_MCx_CTL(bank); - case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); - case MCA_MISC: return MSR_IA32_MCx_MISC(bank); - case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank); - } - - return 0; -} - static void __print_mce(struct mce *m) { pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", @@ -814,7 +793,8 @@ EXPORT_SYMBOL_GPL(machine_check_poll); * the severity assessment code. Pretend that EIPV was set, and take the * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. */ -static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs = *regs) +static __always_inline void +quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) { if (bank !=3D 0) return; @@ -838,8 +818,8 @@ static void quirk_sandybridge_ifu(int bank, struct mce = *m, struct pt_regs *regs) * Do a quick check if any of the events requires a panic. * This decides if we keep the events around or clear them. */ -static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, - struct pt_regs *regs) +static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsig= ned long *validp, + struct pt_regs *regs) { char *tmp =3D *msg; int i; @@ -849,7 +829,7 @@ static int mce_no_way_out(struct mce *m, char **msg, un= signed long *validp, if (!(m->status & MCI_STATUS_VAL)) continue; =20 - __set_bit(i, validp); + arch___set_bit(i, validp); if (mce_flags.snb_ifu_quirk) quirk_sandybridge_ifu(i, m, regs); =20 @@ -1015,13 +995,13 @@ static noinstr int mce_start(int *no_way_out) if (!timeout) return ret; =20 - atomic_add(*no_way_out, &global_nwo); + arch_atomic_add(*no_way_out, &global_nwo); /* * Rely on the implied barrier below, such that global_nwo * is updated before mce_callin. */ - order =3D atomic_inc_return(&mce_callin); - cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); + order =3D arch_atomic_inc_return(&mce_callin); + arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); =20 /* Enable instrumentation around calls to external facilities */ instrumentation_begin(); @@ -1029,10 +1009,10 @@ static noinstr int mce_start(int *no_way_out) /* * Wait for everyone. */ - while (atomic_read(&mce_callin) !=3D num_online_cpus()) { + while (arch_atomic_read(&mce_callin) !=3D num_online_cpus()) { if (mce_timed_out(&timeout, "Timeout: Not all CPUs entered broadcast exception handler")) { - atomic_set(&global_nwo, 0); + arch_atomic_set(&global_nwo, 0); goto out; } ndelay(SPINUNIT); @@ -1047,7 +1027,7 @@ static noinstr int mce_start(int *no_way_out) /* * Monarch: Starts executing now, the others wait. */ - atomic_set(&mce_executing, 1); + arch_atomic_set(&mce_executing, 1); } else { /* * Subject: Now start the scanning loop one by one in @@ -1055,10 +1035,10 @@ static noinstr int mce_start(int *no_way_out) * This way when there are any shared banks it will be * only seen by one CPU before cleared, avoiding duplicates. */ - while (atomic_read(&mce_executing) < order) { + while (arch_atomic_read(&mce_executing) < order) { if (mce_timed_out(&timeout, "Timeout: Subject CPUs unable to finish machine check processing"))= { - atomic_set(&global_nwo, 0); + arch_atomic_set(&global_nwo, 0); goto out; } ndelay(SPINUNIT); @@ -1068,7 +1048,7 @@ static noinstr int mce_start(int *no_way_out) /* * Cache the global no_way_out state. */ - *no_way_out =3D atomic_read(&global_nwo); + *no_way_out =3D arch_atomic_read(&global_nwo); =20 ret =3D order; =20 @@ -1153,12 +1133,12 @@ static noinstr int mce_end(int order) return ret; } =20 -static void mce_clear_state(unsigned long *toclear) +static __always_inline void mce_clear_state(unsigned long *toclear) { int i; =20 for (i =3D 0; i < this_cpu_read(mce_num_banks); i++) { - if (test_bit(i, toclear)) + if (arch_test_bit(i, toclear)) mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); } } @@ -1208,8 +1188,8 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, = struct mce *final, int severity, i, taint =3D 0; =20 for (i =3D 0; i < this_cpu_read(mce_num_banks); i++) { - __clear_bit(i, toclear); - if (!test_bit(i, valid_banks)) + arch___clear_bit(i, toclear); + if (!arch_test_bit(i, valid_banks)) continue; =20 if (!mce_banks[i].ctl) @@ -1244,7 +1224,7 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, = struct mce *final, severity =3D=3D MCE_UCNA_SEVERITY) && !no_way_out) continue; =20 - __set_bit(i, toclear); + arch___set_bit(i, toclear); =20 /* Machine check event was not enabled. Clear, but ignore. */ if (severity =3D=3D MCE_NO_SEVERITY) diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 52c633950b38..a04b61e27827 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -182,8 +182,6 @@ enum mca_msr { MCA_MISC, }; =20 -u32 mca_msr_reg(int bank, enum mca_msr reg); - /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); =20 @@ -209,4 +207,25 @@ static inline void winchip_machine_check(struct pt_reg= s *regs) {} =20 noinstr u64 mce_rdmsrl(u32 msr); =20 +static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) +{ + if (mce_flags.smca) { + switch (reg) { + case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); + case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); + case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); + case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); + } + } + + switch (reg) { + case MCA_CTL: return MSR_IA32_MCx_CTL(bank); + case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); + case MCA_MISC: return MSR_IA32_MCx_MISC(bank); + case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank); + } + + return 0; +} + #endif /* __X86_MCE_INTERNAL_H__ */ diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/s= everity.c index 7aa2bda93cbb..ca0d775346fb 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -301,7 +301,7 @@ static noinstr int error_context(struct mce *m, struct = pt_regs *regs) } } =20 -static int mce_severity_amd_smca(struct mce *m, enum context err_ctx) +static __always_inline int mce_severity_amd_smca(struct mce *m, enum conte= xt err_ctx) { u64 mcx_cfg; =20 --=20 2.29.2