From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F101C433EF for ; Wed, 2 Feb 2022 16:02:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345659AbiBBQCo (ORCPT ); Wed, 2 Feb 2022 11:02:44 -0500 Received: from foss.arm.com ([217.140.110.172]:39692 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343957AbiBBQCm (ORCPT ); Wed, 2 Feb 2022 11:02:42 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69ED611FB; Wed, 2 Feb 2022 08:02:42 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5A6C53F73B; Wed, 2 Feb 2022 08:02:40 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:11 +0000 Message-Id: <20220202160226.37858-2-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-core.c | 37 +++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++ drivers/hwtracing/coresight/coresight-priv.h | 1 + 3 files changed, 27 insertions(+), 28 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index bf18128cf5de..8aefee4e72fd 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1091,41 +1091,22 @@ static void etm4_init_arch_data(void *info) etmidr0 =3D etm4x_relaxed_read32(csa, TRCIDR0); =20 /* INSTP0, bits[2:1] P0 tracing support field */ - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) - drvdata->instrp0 =3D true; - else - drvdata->instrp0 =3D false; - + drvdata->instrp0 =3D !!((REG_VAL(etmidr0, TRCIDR0_INSTP0) & 0b01) && + (REG_VAL(etmidr0, TRCIDR0_INSTP0) & 0b10)); /* TRCBB, bit[5] Branch broadcast tracing support bit */ - if (BMVAL(etmidr0, 5, 5)) - drvdata->trcbb =3D true; - else - drvdata->trcbb =3D false; - + drvdata->trcbb =3D !!(etmidr0 & TRCIDR0_TRCBB); /* TRCCOND, bit[6] Conditional instruction tracing support bit */ - if (BMVAL(etmidr0, 6, 6)) - drvdata->trccond =3D true; - else - drvdata->trccond =3D false; - + drvdata->trccond =3D !!(etmidr0 & TRCIDR0_TRCCOND); /* TRCCCI, bit[7] Cycle counting instruction bit */ - if (BMVAL(etmidr0, 7, 7)) - drvdata->trccci =3D true; - else - drvdata->trccci =3D false; - + drvdata->trccci =3D !!(etmidr0 & TRCIDR0_TRCCCI); /* RETSTACK, bit[9] Return stack bit */ - if (BMVAL(etmidr0, 9, 9)) - drvdata->retstack =3D true; - else - drvdata->retstack =3D false; - + drvdata->retstack =3D !!(etmidr0 & TRCIDR0_RETSTACK); /* NUMEVENT, bits[11:10] Number of events field */ - drvdata->nr_event =3D BMVAL(etmidr0, 10, 11); + drvdata->nr_event =3D REG_VAL(etmidr0, TRCIDR0_NUMEVENT); /* QSUPP, bits[16:15] Q element support field */ - drvdata->q_support =3D BMVAL(etmidr0, 15, 16); + drvdata->q_support =3D REG_VAL(etmidr0, TRCIDR0_QSUPP); /* TSSIZE, bits[28:24] Global timestamp size field */ - drvdata->ts_size =3D BMVAL(etmidr0, 24, 28); + drvdata->ts_size =3D REG_VAL(etmidr0, TRCIDR0_TSSIZE); =20 /* maximum size of resources */ etmidr2 =3D etm4x_relaxed_read32(csa, TRCIDR2); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 3c4d69b096ca..2bd8ad953b8e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -130,6 +130,23 @@ =20 #define TRCRSR_TA BIT(12) =20 +/* + * Bit positions of registers that are defined above, in the sysreg.h style + * of _MASK, _SHIFT and BIT(). + */ +#define TRCIDR0_INSTP0_SHIFT 1 +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0) +#define TRCIDR0_TRCBB BIT(5) +#define TRCIDR0_TRCCOND BIT(6) +#define TRCIDR0_TRCCCI BIT(7) +#define TRCIDR0_RETSTACK BIT(9) +#define TRCIDR0_NUMEVENT_SHIFT 10 +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0) +#define TRCIDR0_QSUPP_SHIFT 15 +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0) +#define TRCIDR0_TSSIZE_SHIFT 24 +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index ff1dd2092ac5..e22fa6184c6d 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -36,6 +36,7 @@ =20 #define TIMEOUT_US 100 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define REG_VAL(val, name) ((val & (name##_MASK << name##_SHIFT)) >> name#= #_SHIFT) =20 #define ETM_MODE_EXCL_KERN BIT(30) #define ETM_MODE_EXCL_USER BIT(31) --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33B8FC433EF for ; Wed, 2 Feb 2022 16:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345662AbiBBQCs (ORCPT ); Wed, 2 Feb 2022 11:02:48 -0500 Received: from foss.arm.com ([217.140.110.172]:39712 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345665AbiBBQCq (ORCPT ); Wed, 2 Feb 2022 11:02:46 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 183D911D4; Wed, 2 Feb 2022 08:02:46 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B6FBF3F73B; Wed, 2 Feb 2022 08:02:43 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/15] coresight: Make ETM4x TRCIDR2 register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:12 +0000 Message-Id: <20220202160226.37858-3-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++--- drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 8aefee4e72fd..4abe5444234e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1111,11 +1111,11 @@ static void etm4_init_arch_data(void *info) /* maximum size of resources */ etmidr2 =3D etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */ - drvdata->ctxid_size =3D BMVAL(etmidr2, 5, 9); + drvdata->ctxid_size =3D REG_VAL(etmidr2, TRCIDR2_CIDSIZE); /* VMIDSIZE, bits[14:10] Indicates the VMID size */ - drvdata->vmid_size =3D BMVAL(etmidr2, 10, 14); + drvdata->vmid_size =3D REG_VAL(etmidr2, TRCIDR2_VMIDSIZE); /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ - drvdata->ccsize =3D BMVAL(etmidr2, 25, 28); + drvdata->ccsize =3D REG_VAL(etmidr2, TRCIDR2_CCSIZE); =20 etmidr3 =3D etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 2bd8ad953b8e..a95df5686b4b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -147,6 +147,13 @@ #define TRCIDR0_TSSIZE_SHIFT 24 #define TRCIDR0_TSSIZE_MASK GENMASK(4, 0) =20 +#define TRCIDR2_CIDSIZE_SHIFT 5 +#define TRCIDR2_CIDSIZE_MASK GENMASK(4, 0) +#define TRCIDR2_VMIDSIZE_SHIFT 10 +#define TRCIDR2_VMIDSIZE_MASK GENMASK(4, 0) +#define TRCIDR2_CCSIZE_SHIFT 25 +#define TRCIDR2_CCSIZE_MASK GENMASK(3, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCA4FC433EF for ; Wed, 2 Feb 2022 16:02:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345674AbiBBQCv (ORCPT ); Wed, 2 Feb 2022 11:02:51 -0500 Received: from foss.arm.com ([217.140.110.172]:39730 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345661AbiBBQCt (ORCPT ); Wed, 2 Feb 2022 11:02:49 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84D2611D4; Wed, 2 Feb 2022 08:02:49 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 825E93F73B; Wed, 2 Feb 2022 08:02:47 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/15] coresight: Make ETM4x TRCIDR3 register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:13 +0000 Message-Id: <20220202160226.37858-4-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-core.c | 40 +++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++ 2 files changed, 25 insertions(+), 30 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 4abe5444234e..f973e7187b1f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1119,53 +1119,33 @@ static void etm4_init_arch_data(void *info) =20 etmidr3 =3D etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ - drvdata->ccitmin =3D BMVAL(etmidr3, 0, 11); + drvdata->ccitmin =3D REG_VAL(etmidr3, TRCIDR3_CCITMIN); /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ - drvdata->s_ex_level =3D BMVAL(etmidr3, 16, 19); + drvdata->s_ex_level =3D REG_VAL(etmidr3, TRCIDR3_EXLEVEL_S); drvdata->config.s_ex_level =3D drvdata->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ - drvdata->ns_ex_level =3D BMVAL(etmidr3, 20, 23); - + drvdata->ns_ex_level =3D REG_VAL(etmidr3, TRCIDR3_EXLEVEL_NS); /* * TRCERR, bit[24] whether a trace unit can trace a * system error exception. */ - if (BMVAL(etmidr3, 24, 24)) - drvdata->trc_error =3D true; - else - drvdata->trc_error =3D false; - + drvdata->trc_error =3D !!(etmidr3 & TRCIDR3_TRCERR); /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ - if (BMVAL(etmidr3, 25, 25)) - drvdata->syncpr =3D true; - else - drvdata->syncpr =3D false; - + drvdata->syncpr =3D !!(etmidr3 & TRCIDR3_SYNCPR); /* STALLCTL, bit[26] is stall control implemented? */ - if (BMVAL(etmidr3, 26, 26)) - drvdata->stallctl =3D true; - else - drvdata->stallctl =3D false; - + drvdata->stallctl =3D !!(etmidr3 & TRCIDR3_STALLCTL); /* SYSSTALL, bit[27] implementation can support stall control? */ - if (BMVAL(etmidr3, 27, 27)) - drvdata->sysstall =3D true; - else - drvdata->sysstall =3D false; - + drvdata->sysstall =3D !!(etmidr3 & TRCIDR3_SYSSTALL); /* * NUMPROC - the number of PEs available for tracing, 5bits * =3D TRCIDR3.bits[13:12]bits[30:28] * bits[4:3] =3D TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) * bits[3:0] =3D TRCIDR3.bits[30:28] */ - drvdata->nr_pe =3D (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30); - + drvdata->nr_pe =3D (REG_VAL(etmidr3, TRCIDR3_NUMPROC_HI) << 3) | + REG_VAL(etmidr3, TRCIDR3_NUMPROC_LO); /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ - if (BMVAL(etmidr3, 31, 31)) - drvdata->nooverflow =3D true; - else - drvdata->nooverflow =3D false; + drvdata->nooverflow =3D !!(etmidr3 & TRCIDR3_NOOVERFLOW); =20 /* number of resources trace unit supports */ etmidr4 =3D etm4x_relaxed_read32(csa, TRCIDR4); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index a95df5686b4b..051d7948f15b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -154,6 +154,21 @@ #define TRCIDR2_CCSIZE_SHIFT 25 #define TRCIDR2_CCSIZE_MASK GENMASK(3, 0) =20 +#define TRCIDR3_CCITMIN_SHIFT 0 +#define TRCIDR3_CCITMIN_MASK GENMASK(11, 0) +#define TRCIDR3_EXLEVEL_S_SHIFT 16 +#define TRCIDR3_EXLEVEL_S_MASK GENMASK(3, 0) +#define TRCIDR3_EXLEVEL_NS_SHIFT 20 +#define TRCIDR3_EXLEVEL_NS_MASK GENMASK(3, 0) +#define TRCIDR3_TRCERR BIT(24) +#define TRCIDR3_SYNCPR BIT(25) +#define TRCIDR3_STALLCTL BIT(26) +#define TRCIDR3_SYSSTALL BIT(27) +#define TRCIDR3_NUMPROC_LO_SHIFT 28 +#define TRCIDR3_NUMPROC_LO_MASK GENMASK(2, 0) +#define TRCIDR3_NUMPROC_HI_SHIFT 12 +#define TRCIDR3_NUMPROC_HI_MASK GENMASK(1, 0) +#define TRCIDR3_NOOVERFLOW BIT(31) /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7566C433F5 for ; Wed, 2 Feb 2022 16:02:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345661AbiBBQC4 (ORCPT ); Wed, 2 Feb 2022 11:02:56 -0500 Received: from foss.arm.com ([217.140.110.172]:39744 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345678AbiBBQCx (ORCPT ); Wed, 2 Feb 2022 11:02:53 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A4CBD11FB; Wed, 2 Feb 2022 08:02:52 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C6B283F73B; Wed, 2 Feb 2022 08:02:50 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/15] coresight: Make ETM4x TRCIDR4 register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:14 +0000 Message-Id: <20220202160226.37858-5-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 ++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index f973e7187b1f..78f01c9e45cb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1150,9 +1150,9 @@ static void etm4_init_arch_data(void *info) /* number of resources trace unit supports */ etmidr4 =3D etm4x_relaxed_read32(csa, TRCIDR4); /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ - drvdata->nr_addr_cmp =3D BMVAL(etmidr4, 0, 3); + drvdata->nr_addr_cmp =3D REG_VAL(etmidr4, TRCIDR4_NUMACPAIRS); /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ - drvdata->nr_pe_cmp =3D BMVAL(etmidr4, 12, 15); + drvdata->nr_pe_cmp =3D REG_VAL(etmidr4, TRCIDR4_NUMPC); /* * NUMRSPAIR, bits[19:16] * The number of resource pairs conveyed by the HW starts at 0, i.e a @@ -1163,7 +1163,7 @@ static void etm4_init_arch_data(void *info) * the default TRUE and FALSE resource selectors are omitted. * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ - drvdata->nr_resource =3D BMVAL(etmidr4, 16, 19); + drvdata->nr_resource =3D REG_VAL(etmidr4, TRCIDR4_NUMRSPAIR); if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) drvdata->nr_resource +=3D 1; /* @@ -1171,15 +1171,15 @@ static void etm4_init_arch_data(void *info) * comparator control for tracing. Read any status regs as these * also contain RO capability data. */ - drvdata->nr_ss_cmp =3D BMVAL(etmidr4, 20, 23); + drvdata->nr_ss_cmp =3D REG_VAL(etmidr4, TRCIDR4_NUMSSCC); for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { drvdata->config.ss_status[i] =3D etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ - drvdata->numcidc =3D BMVAL(etmidr4, 24, 27); + drvdata->numcidc =3D REG_VAL(etmidr4, TRCIDR4_NUMCIDC); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ - drvdata->numvmidc =3D BMVAL(etmidr4, 28, 31); + drvdata->numvmidc =3D REG_VAL(etmidr4, TRCIDR4_NUMVMIDC); =20 etmidr5 =3D etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 051d7948f15b..0b22c57a9da1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -169,6 +169,20 @@ #define TRCIDR3_NUMPROC_HI_SHIFT 12 #define TRCIDR3_NUMPROC_HI_MASK GENMASK(1, 0) #define TRCIDR3_NOOVERFLOW BIT(31) + +#define TRCIDR4_NUMACPAIRS_SHIFT 0 +#define TRCIDR4_NUMACPAIRS_MASK GENMASK(3, 0) +#define TRCIDR4_NUMPC_SHIFT 12 +#define TRCIDR4_NUMPC_MASK GENMASK(3, 0) +#define TRCIDR4_NUMRSPAIR_SHIFT 16 +#define TRCIDR4_NUMRSPAIR_MASK GENMASK(3, 0) +#define TRCIDR4_NUMSSCC_SHIFT 20 +#define TRCIDR4_NUMSSCC_MASK GENMASK(3, 0) +#define TRCIDR4_NUMCIDC_SHIFT 24 +#define TRCIDR4_NUMCIDC_MASK GENMASK(3, 0) +#define TRCIDR4_NUMVMIDC_SHIFT 28 +#define TRCIDR4_NUMVMIDC_MASK GENMASK(3, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D58BC433EF for ; Wed, 2 Feb 2022 16:03:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345683AbiBBQC7 (ORCPT ); Wed, 2 Feb 2022 11:02:59 -0500 Received: from foss.arm.com ([217.140.110.172]:39766 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbiBBQC4 (ORCPT ); Wed, 2 Feb 2022 11:02:56 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C58A11D4; Wed, 2 Feb 2022 08:02:56 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 167813F73B; Wed, 2 Feb 2022 08:02:53 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/15] coresight: Make ETM4x TRCIDR5 register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:15 +0000 Message-Id: <20220202160226.37858-6-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++------------ drivers/hwtracing/coresight/coresight-etm4x.h | 11 +++++++++++ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 78f01c9e45cb..afb1b39e3a38 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1183,26 +1183,20 @@ static void etm4_init_arch_data(void *info) =20 etmidr5 =3D etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */ - drvdata->nr_ext_inp =3D BMVAL(etmidr5, 0, 8); + drvdata->nr_ext_inp =3D REG_VAL(etmidr5, TRCIDR5_NUMEXTIN); /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ - drvdata->trcid_size =3D BMVAL(etmidr5, 16, 21); + drvdata->trcid_size =3D REG_VAL(etmidr5, TRCIDR5_TRACEIDSIZE); /* ATBTRIG, bit[22] implementation can support ATB triggers? */ - if (BMVAL(etmidr5, 22, 22)) - drvdata->atbtrig =3D true; - else - drvdata->atbtrig =3D false; + drvdata->atbtrig =3D !!(etmidr5 & TRCIDR5_ATBTRIG); /* * LPOVERRIDE, bit[23] implementation supports * low-power state override */ - if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up)) - drvdata->lpoverride =3D true; - else - drvdata->lpoverride =3D false; + drvdata->lpoverride =3D (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip= _power_up); /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ - drvdata->nrseqstate =3D BMVAL(etmidr5, 25, 27); + drvdata->nrseqstate =3D REG_VAL(etmidr5, TRCIDR5_NUMSEQSTATE); /* NUMCNTR, bits[30:28] number of counters available for tracing */ - drvdata->nr_cntr =3D BMVAL(etmidr5, 28, 30); + drvdata->nr_cntr =3D REG_VAL(etmidr5, TRCIDR5_NUMCNTR); etm4_cs_lock(drvdata, csa); cpu_detect_trace_filtering(drvdata); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 0b22c57a9da1..ca6ed39ceaf7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -183,6 +183,17 @@ #define TRCIDR4_NUMVMIDC_SHIFT 28 #define TRCIDR4_NUMVMIDC_MASK GENMASK(3, 0) =20 +#define TRCIDR5_NUMEXTIN_SHIFT 0 +#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) +#define TRCIDR5_TRACEIDSIZE_SHIFT 16 +#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(5, 0) +#define TRCIDR5_ATBTRIG BIT(22) +#define TRCIDR5_LPOVERRIDE BIT(23) +#define TRCIDR5_NUMSEQSTATE_SHIFT 25 +#define TRCIDR5_NUMSEQSTATE_MASK GENMASK(2, 0) +#define TRCIDR5_NUMCNTR_SHIFT 28 +#define TRCIDR5_NUMCNTR_MASK GENMASK(2, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3115AC433FE for ; Wed, 2 Feb 2022 16:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345696AbiBBQDB (ORCPT ); Wed, 2 Feb 2022 11:03:01 -0500 Received: from foss.arm.com ([217.140.110.172]:39782 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbiBBQC7 (ORCPT ); Wed, 2 Feb 2022 11:02:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FA7411D4; Wed, 2 Feb 2022 08:02:59 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA9433F73B; Wed, 2 Feb 2022 08:02:57 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/15] coresight: Make ETM4x TRCCONFIGR register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:16 +0000 Message-Id: <20220202160226.37858-7-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-core.c | 10 ++-- .../coresight/coresight-etm4x-sysfs.c | 46 +++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++ 3 files changed, 45 insertions(+), 28 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index afb1b39e3a38..19469546f733 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -633,7 +633,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, =20 /* Go from generic option to ETMv4 specifics */ if (attr->config & BIT(ETM_OPT_CYCACC)) { - config->cfg |=3D BIT(4); + config->cfg |=3D TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ config->ccctlr =3D ETM_CYC_THRESHOLD_DEFAULT; } @@ -653,12 +653,12 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, goto out; =20 /* bit[11], Global timestamp tracing bit */ - config->cfg |=3D BIT(11); + config->cfg |=3D TRCCONFIGR_TS; } =20 if (attr->config & BIT(ETM_OPT_CTXTID)) /* bit[6], Context ID tracing bit */ - config->cfg |=3D BIT(ETM4_CFG_BIT_CTXTID); + config->cfg |=3D TRCCONFIGR_CID; =20 /* * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID @@ -670,13 +670,13 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, ret =3D -EINVAL; goto out; } - config->cfg |=3D BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT); + config->cfg |=3D TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT; } =20 /* return stack - enable if selected and supported */ if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) /* bit[12], Return stack enable bit */ - config->cfg |=3D BIT(12); + config->cfg |=3D TRCCONFIGR_RS; =20 /* * Set any selected configuration and preset. diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 57e94424a8d6..4c29ab4464a0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -180,12 +180,12 @@ static ssize_t reset_store(struct device *dev, =20 /* Disable data tracing: do not trace load and store data transfers */ config->mode &=3D ~(ETM_MODE_LOAD | ETM_MODE_STORE); - config->cfg &=3D ~(BIT(1) | BIT(2)); + config->cfg &=3D ~(TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE); =20 /* Disable data value and data address tracing */ config->mode &=3D ~(ETM_MODE_DATA_TRACE_ADDR | ETM_MODE_DATA_TRACE_VAL); - config->cfg &=3D ~(BIT(16) | BIT(17)); + config->cfg &=3D ~(TRCCONFIGR_DA | TRCCONFIGR_DV); =20 /* Disable all events tracing */ config->eventctrl0 =3D 0x0; @@ -304,82 +304,82 @@ static ssize_t mode_store(struct device *dev, =20 if (drvdata->instrp0 =3D=3D true) { /* start by clearing instruction P0 field */ - config->cfg &=3D ~(BIT(1) | BIT(2)); + config->cfg &=3D ~TRCCONFIGR_INSTP0_LOAD_STORE; if (config->mode & ETM_MODE_LOAD) /* 0b01 Trace load instructions as P0 instructions */ - config->cfg |=3D BIT(1); + config->cfg |=3D TRCCONFIGR_INSTP0_LOAD; if (config->mode & ETM_MODE_STORE) /* 0b10 Trace store instructions as P0 instructions */ - config->cfg |=3D BIT(2); + config->cfg |=3D TRCCONFIGR_INSTP0_STORE; if (config->mode & ETM_MODE_LOAD_STORE) /* * 0b11 Trace load and store instructions * as P0 instructions */ - config->cfg |=3D BIT(1) | BIT(2); + config->cfg |=3D TRCCONFIGR_INSTP0_LOAD_STORE; } =20 /* bit[3], Branch broadcast mode */ if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb =3D=3D true)) - config->cfg |=3D BIT(3); + config->cfg |=3D TRCCONFIGR_BB; else - config->cfg &=3D ~BIT(3); + config->cfg &=3D ~TRCCONFIGR_BB; =20 /* bit[4], Cycle counting instruction trace bit */ if ((config->mode & ETMv4_MODE_CYCACC) && (drvdata->trccci =3D=3D true)) - config->cfg |=3D BIT(4); + config->cfg |=3D TRCCONFIGR_CCI; else - config->cfg &=3D ~BIT(4); + config->cfg &=3D ~TRCCONFIGR_CCI; =20 /* bit[6], Context ID tracing bit */ if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size)) - config->cfg |=3D BIT(6); + config->cfg |=3D TRCCONFIGR_CID; else - config->cfg &=3D ~BIT(6); + config->cfg &=3D ~TRCCONFIGR_CID; =20 if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size)) - config->cfg |=3D BIT(7); + config->cfg |=3D TRCCONFIGR_VMID; else - config->cfg &=3D ~BIT(7); + config->cfg &=3D ~TRCCONFIGR_VMID; =20 /* bits[10:8], Conditional instruction tracing bit */ mode =3D ETM_MODE_COND(config->mode); if (drvdata->trccond =3D=3D true) { - config->cfg &=3D ~(BIT(8) | BIT(9) | BIT(10)); - config->cfg |=3D mode << 8; + config->cfg &=3D ~(TRCCONFIGR_COND_MASK << TRCCONFIGR_COND_SHIFT); + config->cfg |=3D mode << TRCCONFIGR_COND_SHIFT; } =20 /* bit[11], Global timestamp tracing bit */ if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size)) - config->cfg |=3D BIT(11); + config->cfg |=3D TRCCONFIGR_TS; else - config->cfg &=3D ~BIT(11); + config->cfg &=3D ~TRCCONFIGR_TS; =20 /* bit[12], Return stack enable bit */ if ((config->mode & ETM_MODE_RETURNSTACK) && (drvdata->retstack =3D=3D true)) - config->cfg |=3D BIT(12); + config->cfg |=3D TRCCONFIGR_RS; else - config->cfg &=3D ~BIT(12); + config->cfg &=3D ~TRCCONFIGR_RS; =20 /* bits[14:13], Q element enable field */ mode =3D ETM_MODE_QELEM(config->mode); /* start by clearing QE bits */ - config->cfg &=3D ~(BIT(13) | BIT(14)); + config->cfg &=3D ~(TRCCONFIGR_QE_W_COUNTS | TRCCONFIGR_QE_WO_COUNTS); /* * if supported, Q elements with instruction counts are enabled. * Always set the low bit for any requested mode. Valid combos are * 0b00, 0b01 and 0b11. */ if (mode && drvdata->q_support) - config->cfg |=3D BIT(13); + config->cfg |=3D TRCCONFIGR_QE_W_COUNTS; /* * if supported, Q elements with and without instruction * counts are enabled */ if ((mode & BIT(1)) && (drvdata->q_support & BIT(1))) - config->cfg |=3D BIT(14); + config->cfg |=3D TRCCONFIGR_QE_WO_COUNTS; =20 /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ if ((config->mode & ETM_MODE_ATB_TRIGGER) && diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index ca6ed39ceaf7..55e756020a94 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -194,6 +194,23 @@ #define TRCIDR5_NUMCNTR_SHIFT 28 #define TRCIDR5_NUMCNTR_MASK GENMASK(2, 0) =20 +#define TRCCONFIGR_INSTP0_LOAD BIT(1) +#define TRCCONFIGR_INSTP0_STORE BIT(2) +#define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR= _INSTP0_STORE) +#define TRCCONFIGR_BB BIT(3) +#define TRCCONFIGR_CCI BIT(4) +#define TRCCONFIGR_CID BIT(6) +#define TRCCONFIGR_VMID BIT(7) +#define TRCCONFIGR_COND_SHIFT 8 +#define TRCCONFIGR_COND_MASK GENMASK(2, 0) +#define TRCCONFIGR_TS BIT(11) +#define TRCCONFIGR_RS BIT(12) +#define TRCCONFIGR_QE_W_COUNTS BIT(13) +#define TRCCONFIGR_QE_WO_COUNTS BIT(14) +#define TRCCONFIGR_VMIDOPT BIT(15) +#define TRCCONFIGR_DA BIT(16) +#define TRCCONFIGR_DV BIT(17) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DCBEC433F5 for ; Wed, 2 Feb 2022 16:03:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345687AbiBBQDH (ORCPT ); Wed, 2 Feb 2022 11:03:07 -0500 Received: from foss.arm.com ([217.140.110.172]:39802 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345702AbiBBQDD (ORCPT ); Wed, 2 Feb 2022 11:03:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF27012FC; Wed, 2 Feb 2022 08:03:02 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 098C23F73B; Wed, 2 Feb 2022 08:03:00 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/15] coresight: Make ETM4x TRCEVENTCTL1R register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:17 +0000 Message-Id: <20220202160226.37858-8-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-sysfs.c | 25 +++++++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++ 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 4c29ab4464a0..cfa6f72a1e39 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -384,16 +384,16 @@ static ssize_t mode_store(struct device *dev, /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ if ((config->mode & ETM_MODE_ATB_TRIGGER) && (drvdata->atbtrig =3D=3D true)) - config->eventctrl1 |=3D BIT(11); + config->eventctrl1 |=3D TRCEVENTCTL1R_ATB; else - config->eventctrl1 &=3D ~BIT(11); + config->eventctrl1 &=3D ~TRCEVENTCTL1R_ATB; =20 /* bit[12], Low-power state behavior override bit */ if ((config->mode & ETM_MODE_LPOVERRIDE) && (drvdata->lpoverride =3D=3D true)) - config->eventctrl1 |=3D BIT(12); + config->eventctrl1 |=3D TRCEVENTCTL1R_LPOVERRIDE; else - config->eventctrl1 &=3D ~BIT(12); + config->eventctrl1 &=3D ~TRCEVENTCTL1R_LPOVERRIDE; =20 /* bit[8], Instruction stall bit */ if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl =3D=3D true= )) @@ -534,7 +534,7 @@ static ssize_t event_instren_show(struct device *dev, struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etmv4_config *config =3D &drvdata->config; =20 - val =3D BMVAL(config->eventctrl1, 0, 3); + val =3D REG_VAL(config->eventctrl1, TRCEVENTCTL1R_INSTEN); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } =20 @@ -551,23 +551,28 @@ static ssize_t event_instren_store(struct device *dev, =20 spin_lock(&drvdata->spinlock); /* start by clearing all instruction event enable bits */ - config->eventctrl1 &=3D ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); + config->eventctrl1 &=3D ~(TRCEVENTCTL1R_INSTEN_MASK << TRCEVENTCTL1R_INST= EN_SHIFT); switch (drvdata->nr_event) { case 0x0: /* generate Event element for event 1 */ - config->eventctrl1 |=3D val & BIT(1); + config->eventctrl1 |=3D val & TRCEVENTCTL1R_INSTEN_1; break; case 0x1: /* generate Event element for event 1 and 2 */ - config->eventctrl1 |=3D val & (BIT(0) | BIT(1)); + config->eventctrl1 |=3D val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_IN= STEN_1); break; case 0x2: /* generate Event element for event 1, 2 and 3 */ - config->eventctrl1 |=3D val & (BIT(0) | BIT(1) | BIT(2)); + config->eventctrl1 |=3D val & (TRCEVENTCTL1R_INSTEN_0 | + TRCEVENTCTL1R_INSTEN_1 | + TRCEVENTCTL1R_INSTEN_2); break; case 0x3: /* generate Event element for all 4 events */ - config->eventctrl1 |=3D val & 0xF; + config->eventctrl1 |=3D val & (TRCEVENTCTL1R_INSTEN_0 | + TRCEVENTCTL1R_INSTEN_1 | + TRCEVENTCTL1R_INSTEN_2 | + TRCEVENTCTL1R_INSTEN_3); break; default: break; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 55e756020a94..eb72b81bbf85 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -211,6 +211,15 @@ #define TRCCONFIGR_DA BIT(16) #define TRCCONFIGR_DV BIT(17) =20 +#define TRCEVENTCTL1R_INSTEN_SHIFT 0 +#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0) +#define TRCEVENTCTL1R_INSTEN_0 BIT(0) +#define TRCEVENTCTL1R_INSTEN_1 BIT(1) +#define TRCEVENTCTL1R_INSTEN_2 BIT(2) +#define TRCEVENTCTL1R_INSTEN_3 BIT(3) +#define TRCEVENTCTL1R_ATB BIT(11) +#define TRCEVENTCTL1R_LPOVERRIDE BIT(12) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1DD1C433EF for ; Wed, 2 Feb 2022 16:03:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345720AbiBBQDK (ORCPT ); Wed, 2 Feb 2022 11:03:10 -0500 Received: from foss.arm.com ([217.140.110.172]:39822 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234720AbiBBQDG (ORCPT ); Wed, 2 Feb 2022 11:03:06 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ABDD611D4; Wed, 2 Feb 2022 08:03:06 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 82EBA3F73B; Wed, 2 Feb 2022 08:03:04 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/15] coresight: Make ETM4x TRCSTALLCTLR register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:18 +0000 Message-Id: <20220202160226.37858-9-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index cfa6f72a1e39..d808eeae8b07 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -397,22 +397,22 @@ static ssize_t mode_store(struct device *dev, =20 /* bit[8], Instruction stall bit */ if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl =3D=3D true= )) - config->stall_ctrl |=3D BIT(8); + config->stall_ctrl |=3D TRCSTALLCTLR_ISTALL; else - config->stall_ctrl &=3D ~BIT(8); + config->stall_ctrl &=3D ~TRCSTALLCTLR_ISTALL; =20 /* bit[10], Prioritize instruction trace bit */ if (config->mode & ETM_MODE_INSTPRIO) - config->stall_ctrl |=3D BIT(10); + config->stall_ctrl |=3D TRCSTALLCTLR_INSTPRIORITY; else - config->stall_ctrl &=3D ~BIT(10); + config->stall_ctrl &=3D ~TRCSTALLCTLR_INSTPRIORITY; =20 /* bit[13], Trace overflow prevention bit */ if ((config->mode & ETM_MODE_NOOVERFLOW) && (drvdata->nooverflow =3D=3D true)) - config->stall_ctrl |=3D BIT(13); + config->stall_ctrl |=3D TRCSTALLCTLR_NOOVERFLOW; else - config->stall_ctrl &=3D ~BIT(13); + config->stall_ctrl &=3D ~TRCSTALLCTLR_NOOVERFLOW; =20 /* bit[9] Start/stop logic control bit */ if (config->mode & ETM_MODE_VIEWINST_STARTSTOP) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index eb72b81bbf85..e37393934e0d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -220,6 +220,10 @@ #define TRCEVENTCTL1R_ATB BIT(11) #define TRCEVENTCTL1R_LPOVERRIDE BIT(12) =20 +#define TRCSTALLCTLR_ISTALL BIT(8) +#define TRCSTALLCTLR_INSTPRIORITY BIT(10) +#define TRCSTALLCTLR_NOOVERFLOW BIT(13) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75D35C433EF for ; Wed, 2 Feb 2022 16:03:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345691AbiBBQDP (ORCPT ); Wed, 2 Feb 2022 11:03:15 -0500 Received: from foss.arm.com ([217.140.110.172]:39844 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241077AbiBBQDK (ORCPT ); Wed, 2 Feb 2022 11:03:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 464A611D4; Wed, 2 Feb 2022 08:03:10 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 369543F73B; Wed, 2 Feb 2022 08:03:08 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/15] coresight: Make ETM4x TRCVICTLR register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:19 +0000 Message-Id: <20220202160226.37858-10-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-core.c | 10 +++--- .../coresight/coresight-etm4x-sysfs.c | 32 +++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 26 +++++++-------- 3 files changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 19469546f733..00285e2533b5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1209,7 +1209,7 @@ static inline u32 etm4_get_victlr_access_type(struct = etmv4_config *config) /* Set ELx trace filter access in the TRCVICTLR register */ static void etm4_set_victlr_access(struct etmv4_config *config) { - config->vinst_ctrl &=3D ~TRCVICTLR_EXLEVEL_MASK; + config->vinst_ctrl &=3D ~(TRCVICTLR_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHI= FT); config->vinst_ctrl |=3D etm4_get_victlr_access_type(config); } =20 @@ -1229,7 +1229,7 @@ static void etm4_set_default_config(struct etmv4_conf= ig *config) config->ts_ctrl =3D 0x0; =20 /* TRCVICTLR::EVENT =3D 0x01, select the always on logic */ - config->vinst_ctrl =3D BIT(0); + config->vinst_ctrl =3D (0x01 & TRCVICTLR_EVENT_MASK) << TRCVICTLR_EVENT_S= HIFT; =20 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ etm4_set_victlr_access(config); @@ -1338,7 +1338,7 @@ static void etm4_set_default_filter(struct etmv4_conf= ig *config) * TRCVICTLR::SSSTATUS =3D=3D 1, the start-stop logic is * in the started state */ - config->vinst_ctrl |=3D BIT(9); + config->vinst_ctrl |=3D TRCVICTLR_SSSTATUS; config->mode |=3D ETM_MODE_VIEWINST_STARTSTOP; =20 /* No start-stop filtering for ViewInst */ @@ -1442,7 +1442,7 @@ static int etm4_set_event_filters(struct etmv4_drvdat= a *drvdata, * TRCVICTLR::SSSTATUS =3D=3D 1, the start-stop logic is * in the started state */ - config->vinst_ctrl |=3D BIT(9); + config->vinst_ctrl |=3D TRCVICTLR_SSSTATUS; =20 /* No start-stop filtering for ViewInst */ config->vissctlr =3D 0x0; @@ -1470,7 +1470,7 @@ static int etm4_set_event_filters(struct etmv4_drvdat= a *drvdata, * etm4_disable_perf(). */ if (filters->ssstatus) - config->vinst_ctrl |=3D BIT(9); + config->vinst_ctrl |=3D TRCVICTLR_SSSTATUS; =20 /* No include/exclude filtering for ViewInst */ config->viiectlr =3D 0x0; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index d808eeae8b07..87e52f685f05 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -206,11 +206,11 @@ static ssize_t reset_store(struct device *dev, * started state. ARM recommends start-stop logic is set before * each trace run. */ - config->vinst_ctrl =3D BIT(0); + config->vinst_ctrl =3D (0x01 & TRCVICTLR_EVENT_MASK) << TRCVICTLR_EVENT_S= HIFT; if (drvdata->nr_addr_cmp > 0) { config->mode |=3D ETM_MODE_VIEWINST_STARTSTOP; /* SSSTATUS, bit[9] */ - config->vinst_ctrl |=3D BIT(9); + config->vinst_ctrl |=3D TRCVICTLR_SSSTATUS; } =20 /* No address range filtering for ViewInst */ @@ -416,22 +416,22 @@ static ssize_t mode_store(struct device *dev, =20 /* bit[9] Start/stop logic control bit */ if (config->mode & ETM_MODE_VIEWINST_STARTSTOP) - config->vinst_ctrl |=3D BIT(9); + config->vinst_ctrl |=3D TRCVICTLR_SSSTATUS; else - config->vinst_ctrl &=3D ~BIT(9); + config->vinst_ctrl &=3D ~TRCVICTLR_SSSTATUS; =20 /* bit[10], Whether a trace unit must trace a Reset exception */ if (config->mode & ETM_MODE_TRACE_RESET) - config->vinst_ctrl |=3D BIT(10); + config->vinst_ctrl |=3D TRCVICTLR_TRCRESET; else - config->vinst_ctrl &=3D ~BIT(10); + config->vinst_ctrl &=3D ~TRCVICTLR_TRCRESET; =20 /* bit[11], Whether a trace unit must trace a system error exception */ if ((config->mode & ETM_MODE_TRACE_ERR) && (drvdata->trc_error =3D=3D true)) - config->vinst_ctrl |=3D BIT(11); + config->vinst_ctrl |=3D TRCVICTLR_TRCERR; else - config->vinst_ctrl &=3D ~BIT(11); + config->vinst_ctrl &=3D ~TRCVICTLR_TRCERR; =20 if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) etm4_config_trace_mode(config); @@ -723,7 +723,7 @@ static ssize_t event_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etmv4_config *config =3D &drvdata->config; =20 - val =3D config->vinst_ctrl & ETMv4_EVENT_MASK; + val =3D REG_VAL(config->vinst_ctrl, TRCVICTLR_EVENT); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } =20 @@ -739,9 +739,9 @@ static ssize_t event_vinst_store(struct device *dev, return -EINVAL; =20 spin_lock(&drvdata->spinlock); - val &=3D ETMv4_EVENT_MASK; - config->vinst_ctrl &=3D ~ETMv4_EVENT_MASK; - config->vinst_ctrl |=3D val; + val &=3D TRCVICTLR_EVENT_MASK; + config->vinst_ctrl &=3D ~(TRCVICTLR_EVENT_MASK << TRCVICTLR_EVENT_SHIFT); + config->vinst_ctrl |=3D val << TRCVICTLR_EVENT_SHIFT; spin_unlock(&drvdata->spinlock); return size; } @@ -755,7 +755,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etmv4_config *config =3D &drvdata->config; =20 - val =3D (config->vinst_ctrl & TRCVICTLR_EXLEVEL_S_MASK) >> TRCVICTLR_EXLE= VEL_S_SHIFT; + val =3D REG_VAL(config->vinst_ctrl, TRCVICTLR_EXLEVEL_S); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } =20 @@ -772,7 +772,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, =20 spin_lock(&drvdata->spinlock); /* clear all EXLEVEL_S bits */ - config->vinst_ctrl &=3D ~(TRCVICTLR_EXLEVEL_S_MASK); + config->vinst_ctrl &=3D ~(TRCVICTLR_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_S= _SHIFT); /* enable instruction tracing for corresponding exception level */ val &=3D drvdata->s_ex_level; config->vinst_ctrl |=3D (val << TRCVICTLR_EXLEVEL_S_SHIFT); @@ -790,7 +790,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, struct etmv4_config *config =3D &drvdata->config; =20 /* EXLEVEL_NS, bits[23:20] */ - val =3D (config->vinst_ctrl & TRCVICTLR_EXLEVEL_NS_MASK) >> TRCVICTLR_EXL= EVEL_NS_SHIFT; + val =3D REG_VAL(config->vinst_ctrl, TRCVICTLR_EXLEVEL_NS); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } =20 @@ -807,7 +807,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *de= v, =20 spin_lock(&drvdata->spinlock); /* clear EXLEVEL_NS bits */ - config->vinst_ctrl &=3D ~(TRCVICTLR_EXLEVEL_NS_MASK); + config->vinst_ctrl &=3D ~(TRCVICTLR_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_= NS_SHIFT); /* enable instruction tracing for corresponding exception level */ val &=3D drvdata->ns_ex_level; config->vinst_ctrl |=3D (val << TRCVICTLR_EXLEVEL_NS_SHIFT); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index e37393934e0d..02afce9dcf6b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -224,6 +224,18 @@ #define TRCSTALLCTLR_INSTPRIORITY BIT(10) #define TRCSTALLCTLR_NOOVERFLOW BIT(13) =20 +#define TRCVICTLR_EVENT_SHIFT 0 +#define TRCVICTLR_EVENT_MASK GENMASK(7, 0) +#define TRCVICTLR_SSSTATUS BIT(9) +#define TRCVICTLR_TRCRESET BIT(10) +#define TRCVICTLR_TRCERR BIT(11) +#define TRCVICTLR_EXLEVEL_SHIFT 16 +#define TRCVICTLR_EXLEVEL_MASK GENMASK(6, 0) +#define TRCVICTLR_EXLEVEL_S_SHIFT 16 +#define TRCVICTLR_EXLEVEL_S_MASK GENMASK(3, 0) +#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 +#define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(2, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions @@ -724,23 +736,9 @@ #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ =20 -#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) -#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) -#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) - /* access level controls in TRCACATRn */ #define TRCACATR_EXLEVEL_SHIFT 8 =20 -/* access level control in TRCVICTLR */ -#define TRCVICTLR_EXLEVEL_SHIFT 16 -#define TRCVICTLR_EXLEVEL_S_SHIFT 16 -#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 - -/* secure / non secure masks - TRCVICTLR, IDR3 */ -#define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHI= FT) -#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_= SHIFT) -#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVE= L_SHIFT) - #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) #define ETM_TRCIDR1_ARCH_MAJOR(x) \ --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 582EAC433EF for ; Wed, 2 Feb 2022 16:03:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240116AbiBBQDU (ORCPT ); Wed, 2 Feb 2022 11:03:20 -0500 Received: from foss.arm.com ([217.140.110.172]:39858 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231594AbiBBQDO (ORCPT ); Wed, 2 Feb 2022 11:03:14 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D467A11D4; Wed, 2 Feb 2022 08:03:13 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 96A133F73B; Wed, 2 Feb 2022 08:03:11 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/15] coresight: Make ETM3x ETMTECR1 register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:20 +0000 Message-Id: <20220202160226.37858-11-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index cf64ce73a741..35e4bdee848c 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -204,7 +204,7 @@ void etm_set_default(struct etm_config *config) * set all bits in register 0x007, the ETMTECR2, to 0 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). */ - config->enable_ctrl1 =3D BIT(24); + config->enable_ctrl1 =3D ETMTECR1_INC_EXC; config->enable_ctrl2 =3D 0x0; config->enable_event =3D ETM_HARD_WIRE_RES_A; =20 diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm3x-sysfs.c index e8c7649f123e..68fcbf4ce7a8 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -474,7 +474,7 @@ static ssize_t addr_start_store(struct device *dev, config->addr_val[idx] =3D val; config->addr_type[idx] =3D ETM_ADDR_TYPE_START; config->startstop_ctrl |=3D (1 << idx); - config->enable_ctrl1 |=3D BIT(25); + config->enable_ctrl1 |=3D ETMTECR1_START_STOP; spin_unlock(&drvdata->spinlock); =20 return size; --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD2E4C433EF for ; Wed, 2 Feb 2022 16:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230295AbiBBQD0 (ORCPT ); Wed, 2 Feb 2022 11:03:26 -0500 Received: from foss.arm.com ([217.140.110.172]:39876 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238533AbiBBQDR (ORCPT ); Wed, 2 Feb 2022 11:03:17 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59EEE11FB; Wed, 2 Feb 2022 08:03:17 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4662C3F73B; Wed, 2 Feb 2022 08:03:15 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/15] coresight: Make ETM4x TRCACATRn register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:21 +0000 Message-Id: <20220202160226.37858-12-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- .../coresight/coresight-etm4x-sysfs.c | 43 ++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 18 ++++++-- 2 files changed, 36 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 87e52f685f05..51f6e13e3b29 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -22,7 +22,7 @@ static int etm4_set_mode_exclude(struct etmv4_drvdata *dr= vdata, bool exclude) * TRCACATRn.TYPE bit[1:0]: type of comparison * the trace unit performs */ - if (BMVAL(config->addr_acc[idx], 0, 1) =3D=3D ETM_INSTR_ADDR) { + if (REG_VAL(config->addr_acc[idx], TRCACATRn_TYPE) =3D=3D TRCACATRn_TYPE_= ADDR) { if (idx % 2 !=3D 0) return -EINVAL; =20 @@ -863,11 +863,11 @@ static ssize_t addr_instdatatype_show(struct device *= dev, =20 spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; - val =3D BMVAL(config->addr_acc[idx], 0, 1); + val =3D REG_VAL(config->addr_acc[idx], TRCACATRn_TYPE); len =3D scnprintf(buf, PAGE_SIZE, "%s\n", - val =3D=3D ETM_INSTR_ADDR ? "instr" : - (val =3D=3D ETM_DATA_LOAD_ADDR ? "data_load" : - (val =3D=3D ETM_DATA_STORE_ADDR ? "data_store" : + val =3D=3D TRCACATRn_TYPE_ADDR ? "instr" : + (val =3D=3D TRCACATRn_TYPE_DATA_LOAD_ADDR ? "data_load" : + (val =3D=3D TRCACATRn_TYPE_DATA_STORE_ADDR ? "data_store" : "data_load_store"))); spin_unlock(&drvdata->spinlock); return len; @@ -891,7 +891,7 @@ static ssize_t addr_instdatatype_store(struct device *d= ev, idx =3D config->addr_idx; if (!strcmp(str, "instr")) /* TYPE, bits[1:0] */ - config->addr_acc[idx] &=3D ~(BIT(0) | BIT(1)); + config->addr_acc[idx] &=3D ~(TRCACATRn_TYPE_MASK << TRCACATRn_TYPE_SHIFT= ); =20 spin_unlock(&drvdata->spinlock); return size; @@ -1149,7 +1149,7 @@ static ssize_t addr_ctxtype_show(struct device *dev, spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; /* CONTEXTTYPE, bits[3:2] */ - val =3D BMVAL(config->addr_acc[idx], 2, 3); + val =3D REG_VAL(config->addr_acc[idx], TRCACATRn_CONTEXTTYPE); len =3D scnprintf(buf, PAGE_SIZE, "%s\n", val =3D=3D ETM_CTX_NONE ? "none= " : (val =3D=3D ETM_CTX_CTXID ? "ctxid" : (val =3D=3D ETM_CTX_VMID ? "vmid" : "all"))); @@ -1175,18 +1175,19 @@ static ssize_t addr_ctxtype_store(struct device *de= v, idx =3D config->addr_idx; if (!strcmp(str, "none")) /* start by clearing context type bits */ - config->addr_acc[idx] &=3D ~(BIT(2) | BIT(3)); + config->addr_acc[idx] &=3D ~(TRCACATRn_CONTEXTTYPE_MASK << + TRCACATRn_CONTEXTTYPE_SHIFT); else if (!strcmp(str, "ctxid")) { /* 0b01 The trace unit performs a Context ID */ if (drvdata->numcidc) { - config->addr_acc[idx] |=3D BIT(2); - config->addr_acc[idx] &=3D ~BIT(3); + config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_CTXID; + config->addr_acc[idx] &=3D ~TRCACATRn_CONTEXTTYPE_VMID; } } else if (!strcmp(str, "vmid")) { /* 0b10 The trace unit performs a VMID */ if (drvdata->numvmidc) { - config->addr_acc[idx] &=3D ~BIT(2); - config->addr_acc[idx] |=3D BIT(3); + config->addr_acc[idx] &=3D ~TRCACATRn_CONTEXTTYPE_CTXID; + config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_VMID; } } else if (!strcmp(str, "all")) { /* @@ -1194,9 +1195,9 @@ static ssize_t addr_ctxtype_store(struct device *dev, * comparison and a VMID */ if (drvdata->numcidc) - config->addr_acc[idx] |=3D BIT(2); + config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_CTXID; if (drvdata->numvmidc) - config->addr_acc[idx] |=3D BIT(3); + config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_VMID; } spin_unlock(&drvdata->spinlock); return size; @@ -1215,7 +1216,7 @@ static ssize_t addr_context_show(struct device *dev, spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; /* context ID comparator bits[6:4] */ - val =3D BMVAL(config->addr_acc[idx], 4, 6); + val =3D REG_VAL(config->addr_acc[idx], TRCACATRn_CONTEXT); spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -1240,8 +1241,8 @@ static ssize_t addr_context_store(struct device *dev, spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; /* clear context ID comparator bits[6:4] */ - config->addr_acc[idx] &=3D ~(BIT(4) | BIT(5) | BIT(6)); - config->addr_acc[idx] |=3D (val << 4); + config->addr_acc[idx] &=3D ~(TRCACATRn_CONTEXT_MASK << TRCACATRn_CONTEXT_= SHIFT); + config->addr_acc[idx] |=3D (val << TRCACATRn_CONTEXT_SHIFT); spin_unlock(&drvdata->spinlock); return size; } @@ -1258,7 +1259,7 @@ static ssize_t addr_exlevel_s_ns_show(struct device *= dev, =20 spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; - val =3D BMVAL(config->addr_acc[idx], 8, 14); + val =3D REG_VAL(config->addr_acc[idx], TRCACATRn_EXLEVEL); spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -1275,14 +1276,14 @@ static ssize_t addr_exlevel_s_ns_store(struct devic= e *dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - if (val & ~((GENMASK(14, 8) >> 8))) + if (val & ~TRCACATRn_EXLEVEL_MASK) return -EINVAL; =20 spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ - config->addr_acc[idx] &=3D ~(GENMASK(14, 8)); - config->addr_acc[idx] |=3D (val << 8); + config->addr_acc[idx] &=3D ~(TRCACATRn_EXLEVEL_MASK << TRCACATRn_EXLEVEL_= SHIFT); + config->addr_acc[idx] |=3D (val << TRCACATRn_EXLEVEL_SHIFT); spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 02afce9dcf6b..5701d970d81a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -236,6 +236,16 @@ #define TRCVICTLR_EXLEVEL_NS_SHIFT 20 #define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(2, 0) =20 +#define TRCACATRn_TYPE_SHIFT 0 +#define TRCACATRn_TYPE_MASK GENMASK(1, 0) +#define TRCACATRn_CONTEXTTYPE_SHIFT 2 +#define TRCACATRn_CONTEXTTYPE_MASK GENMASK(1, 0) +#define TRCACATRn_CONTEXTTYPE_CTXID BIT(2) +#define TRCACATRn_CONTEXTTYPE_VMID BIT(3) +#define TRCACATRn_CONTEXT_SHIFT 4 +#define TRCACATRn_CONTEXT_MASK GENMASK(2, 0) +#define TRCACATRn_EXLEVEL_SHIFT 8 +#define TRCACATRn_EXLEVEL_MASK GENMASK(6, 0) /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions @@ -1078,10 +1088,10 @@ struct etmv4_drvdata { =20 /* Address comparator access types */ enum etm_addr_acctype { - ETM_INSTR_ADDR, - ETM_DATA_LOAD_ADDR, - ETM_DATA_STORE_ADDR, - ETM_DATA_LOAD_STORE_ADDR, + TRCACATRn_TYPE_ADDR, + TRCACATRn_TYPE_DATA_LOAD_ADDR, + TRCACATRn_TYPE_DATA_STORE_ADDR, + TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR, }; =20 /* Address comparator context types */ --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC524C433F5 for ; Wed, 2 Feb 2022 16:03:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345762AbiBBQDg (ORCPT ); Wed, 2 Feb 2022 11:03:36 -0500 Received: from foss.arm.com ([217.140.110.172]:39892 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345733AbiBBQDV (ORCPT ); Wed, 2 Feb 2022 11:03:21 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BF0E11D4; Wed, 2 Feb 2022 08:03:21 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BBF503F73B; Wed, 2 Feb 2022 08:03:18 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/15] coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:22 +0000 Message-Id: <20220202160226.37858-13-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +++--- drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 00285e2533b5..e7a9490c509d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) - config->ss_status[i] &=3D ~BIT(31); + config->ss_status[i] &=3D ~TRCSSCSRn_STATUS; etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 51f6e13e3b29..7d9372ba1168 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1793,9 +1793,9 @@ static ssize_t sshot_ctrl_store(struct device *dev, =20 spin_lock(&drvdata->spinlock); idx =3D config->ss_idx; - config->ss_ctrl[idx] =3D val & GENMASK(24, 0); + config->ss_ctrl[idx] =3D val & (TRCSSCCRn_SAC_ARC_RST_MASK << TRCSSCCRn_S= AC_ARC_RST_SHIFT); /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &=3D ~BIT(31); + config->ss_status[idx] &=3D ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); return size; } @@ -1845,7 +1845,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, idx =3D config->ss_idx; config->ss_pe_cmp[idx] =3D val & GENMASK(7, 0); /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &=3D ~BIT(31); + config->ss_status[idx] &=3D ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 5701d970d81a..9c22a5b0777f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -246,6 +246,11 @@ #define TRCACATRn_CONTEXT_MASK GENMASK(2, 0) #define TRCACATRn_EXLEVEL_SHIFT 8 #define TRCACATRn_EXLEVEL_MASK GENMASK(6, 0) + +#define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCCRn_SAC_ARC_RST_SHIFT 0 +#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 956B4C433F5 for ; Wed, 2 Feb 2022 16:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345734AbiBBQDa (ORCPT ); Wed, 2 Feb 2022 11:03:30 -0500 Received: from foss.arm.com ([217.140.110.172]:39910 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345710AbiBBQDZ (ORCPT ); Wed, 2 Feb 2022 11:03:25 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B75A11FB; Wed, 2 Feb 2022 08:03:25 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A18453F73B; Wed, 2 Feb 2022 08:03:22 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/15] coresight: Make ETM4x TRCSSPCICRn register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:23 +0000 Message-Id: <20220202160226.37858-14-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 7d9372ba1168..682819467755 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1843,7 +1843,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, =20 spin_lock(&drvdata->spinlock); idx =3D config->ss_idx; - config->ss_pe_cmp[idx] =3D val & GENMASK(7, 0); + config->ss_pe_cmp[idx] =3D val & (TRCSSPCICRn_PC_MASK << TRCSSPCICRn_PC_S= HIFT); /* must clear bit 31 in related status register on programming */ config->ss_status[idx] &=3D ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 9c22a5b0777f..9d0978540338 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -251,6 +251,9 @@ #define TRCSSCCRn_SAC_ARC_RST_SHIFT 0 #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) =20 +#define TRCSSPCICRn_PC_SHIFT 0 +#define TRCSSPCICRn_PC_MASK GENMASK(7, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13720C433F5 for ; Wed, 2 Feb 2022 16:03:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345727AbiBBQDp (ORCPT ); Wed, 2 Feb 2022 11:03:45 -0500 Received: from foss.arm.com ([217.140.110.172]:39928 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345722AbiBBQD3 (ORCPT ); Wed, 2 Feb 2022 11:03:29 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0646E11D4; Wed, 2 Feb 2022 08:03:29 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9FD813F73B; Wed, 2 Feb 2022 08:03:26 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/15] coresight: Make ETM4x TRCBBCTLR register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:24 +0000 Message-Id: <20220202160226.37858-15-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 5 +++-- drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 682819467755..a0cdd2cd978a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -707,10 +707,11 @@ static ssize_t bb_ctrl_store(struct device *dev, * individual range comparators. If include then at least 1 * range must be selected. */ - if ((val & BIT(8)) && (BMVAL(val, 0, 7) =3D=3D 0)) + if ((val & TRCBBCTLR_MODE) && (REG_VAL(val, TRCBBCTLR_RANGE) =3D=3D 0)) return -EINVAL; =20 - config->bb_ctrl =3D val & GENMASK(8, 0); + config->bb_ctrl =3D val & (TRCBBCTLR_MODE | + (TRCBBCTLR_RANGE_MASK << TRCBBCTLR_RANGE_SHIFT)); return size; } static DEVICE_ATTR_RW(bb_ctrl); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 9d0978540338..4d943faade33 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -254,6 +254,10 @@ #define TRCSSPCICRn_PC_SHIFT 0 #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) =20 +#define TRCBBCTLR_MODE BIT(8) +#define TRCBBCTLR_RANGE_SHIFT 0 +#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0 From nobody Mon Jun 29 21:04:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E310C433FE for ; Wed, 2 Feb 2022 16:03:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345733AbiBBQDm (ORCPT ); Wed, 2 Feb 2022 11:03:42 -0500 Received: from foss.arm.com ([217.140.110.172]:39946 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343607AbiBBQDc (ORCPT ); Wed, 2 Feb 2022 11:03:32 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E62311FB; Wed, 2 Feb 2022 08:03:32 -0800 (PST) Received: from e121896.Emea.Arm.com (e121896.Emea.Arm.com [10.32.36.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6C2423F73B; Wed, 2 Feb 2022 08:03:30 -0800 (PST) From: James Clark To: mathieu.poirier@linaro.org, coresight@lists.linaro.org Cc: suzuki.poulose@arm.com, leo.yan@linaro.com, mike.leach@linaro.org, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/15] coresight: Make ETM4x TRCRSCTLRn register accesses consistent with sysreg.h Date: Wed, 2 Feb 2022 16:02:25 +0000 Message-Id: <20220202160226.37858-16-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220202160226.37858-1-james.clark@arm.com> References: <20220202160226.37858-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index a0cdd2cd978a..c876a63fa84d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1728,8 +1728,11 @@ static ssize_t res_ctrl_store(struct device *dev, /* For odd idx pair inversal bit is RES0 */ if (idx % 2 !=3D 0) /* PAIRINV, bit[21] */ - val &=3D ~BIT(21); - config->res_ctrl[idx] =3D val & GENMASK(21, 0); + val &=3D ~TRCRSCTLRn_PAIRINV; + config->res_ctrl[idx] =3D val & (TRCRSCTLRn_PAIRINV | + TRCRSCTLRn_INV | + (TRCRSCTLRn_GROUP_MASK << TRCRSCTLRn_GROUP_SHIFT) | + (TRCRSCTLRn_SELECT_MASK << TRCRSCTLRn_SELECT_SHIFT)); spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 4d943faade33..dd2156a5e70b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -258,6 +258,15 @@ #define TRCBBCTLR_RANGE_SHIFT 0 #define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) =20 +#define TRCRSCTLRn_PAIRINV BIT(21) +#define TRCRSCTLRn_INV BIT(20) +#define TRCRSCTLRn_GROUP_SHIFT 16 +#define TRCRSCTLRn_GROUP_MASK GENMASK(3, 0) +#define TRCRSCTLRn_SELECT_SHIFT 0 +#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0) + + + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions --=20 2.28.0