From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00C27C433EF for ; Wed, 2 Feb 2022 14:59:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345265AbiBBO7E (ORCPT ); Wed, 2 Feb 2022 09:59:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231985AbiBBO7D (ORCPT ); Wed, 2 Feb 2022 09:59:03 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBA01C061714 for ; Wed, 2 Feb 2022 06:59:02 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id E661C223EA; Wed, 2 Feb 2022 15:59:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813941; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EUIHOXBwQHm3/QA8WoOrA7Z1KLYfmRbk62KHpOzNBV4=; b=ZWhTT6sJTrJpdFgN6/yNptFuqf5m3U72tOlXp95AXYnibvAC7SoXVnDo1wZZiSobeWvTUC FopPvK1P+9nnmdULxKGQFnwHHbooXY28fL/M4r5IOTd2gJlj4g+9leWktQLaeJnVUodBOe uaBhgUn3c7CpdKWbIJ5y/R68sEVItTM= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 01/14] mtd: spi-nor: export more function to be used in vendor modules Date: Wed, 2 Feb 2022 15:58:40 +0100 Message-Id: <20220202145853.4187726-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will move vendor specific code into the vendor modules and thus we will have to export these functions so they can be called. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 10 +++++----- drivers/mtd/spi-nor/core.h | 6 ++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 04ea180118e3..f05ece6018dc 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -157,8 +157,8 @@ static int spi_nor_spimem_exec_op(struct spi_nor *nor, = struct spi_mem_op *op) return spi_mem_exec_op(nor->spimem, op); } =20 -static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, - u8 *buf, size_t len) +int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, + u8 *buf, size_t len) { if (spi_nor_protocol_is_dtr(nor->reg_proto)) return -EOPNOTSUPP; @@ -166,8 +166,8 @@ static int spi_nor_controller_ops_read_reg(struct spi_n= or *nor, u8 opcode, return nor->controller_ops->read_reg(nor, opcode, buf, len); } =20 -static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, - const u8 *buf, size_t len) +int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, + const u8 *buf, size_t len) { if (spi_nor_protocol_is_dtr(nor->reg_proto)) return -EOPNOTSUPP; @@ -683,7 +683,7 @@ static void spi_nor_clear_sr(struct spi_nor *nor) * * Return: 1 if ready, 0 if not ready, -errno on errors. */ -static int spi_nor_sr_ready(struct spi_nor *nor) +int spi_nor_sr_ready(struct spi_nor *nor) { int ret =3D spi_nor_read_sr(nor, nor->bouncebuf); =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2afb610853a9..c6578d3f598b 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -554,6 +554,7 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); +int spi_nor_sr_ready(struct spi_nor *nor); int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); @@ -599,6 +600,11 @@ void spi_nor_try_unlock_all(struct spi_nor *nor); void spi_nor_set_mtd_locking_ops(struct spi_nor *nor); void spi_nor_set_mtd_otp_ops(struct spi_nor *nor); =20 +int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, + u8 *buf, size_t len); +int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, + const u8 *buf, size_t len); + static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return container_of(mtd, struct spi_nor, mtd); --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE091C433EF for ; Wed, 2 Feb 2022 14:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345359AbiBBO7N (ORCPT ); Wed, 2 Feb 2022 09:59:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345241AbiBBO7D (ORCPT ); Wed, 2 Feb 2022 09:59:03 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BA1EC061714 for ; Wed, 2 Feb 2022 06:59:03 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 735F3223ED; Wed, 2 Feb 2022 15:59:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813941; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ahJp6eTHZ3fSx9Ky9bMySI7tvw7stlyKxNn2I6oxOgI=; b=sEjJGRI2Me9A3TTseN5rEfl2HGbzJN+/O/Gq4ycjxZDDq3k4wM95OZy4bfd8yh2OIbgAi+ vqYQa0suGBCYr/Nyc3QbMzaURXqxyrJwoykKMV2Db3pc3yx4m0t0aUGvj350lVFvdxy+CM 1cjv8XfuX+WJr2GlnWYH9uUoGViAAEI= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 02/14] mtd: spi-nor: slightly refactor the spi_nor_setup() Date: Wed, 2 Feb 2022 15:58:41 +0100 Message-Id: <20220202145853.4187726-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of always using a function pointer (and initializing it to our default), just call the default function if the flash didn't set its own one. That will make the call flow easier to follow. Also mark the parameter as optional now. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 10 +++++----- drivers/mtd/spi-nor/core.h | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f05ece6018dc..c8cc906cf771 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2532,11 +2532,12 @@ static int spi_nor_setup(struct spi_nor *nor, { int ret; =20 - if (nor->params->setup) { + if (nor->params->setup) ret =3D nor->params->setup(nor, hwcaps); - if (ret) - return ret; - } + else + ret =3D spi_nor_default_setup(nor, hwcaps); + if (ret) + return ret; =20 return spi_nor_set_addr_width(nor); } @@ -2786,7 +2787,6 @@ static void spi_nor_init_default_params(struct spi_no= r *nor) =20 params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; params->set_4byte_addr_mode =3D spansion_set_4byte_addr_mode; - params->setup =3D spi_nor_default_setup; params->otp.org =3D &info->otp_org; =20 /* Default to 16-bit Write Status (01h) Command */ diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index c6578d3f598b..10f478547dc2 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -257,10 +257,10 @@ struct spi_nor_otp { * @convert_addr: converts an absolute address into something the flash * will understand. Particularly useful when pagesize= is * not a power-of-2. - * @setup: configures the SPI NOR memory. Useful for SPI NOR - * flashes that have peculiarities to the SPI NOR sta= ndard - * e.g. different opcodes, specific address calculati= on, - * page size, etc. + * @setup: (optional) configures the SPI NOR memory. Useful for + * SPI NOR flashes that have peculiarities to the SPI NOR + * standard e.g. different opcodes, specific address + * calculation, page size, etc. * @locking_ops: SPI NOR locking methods. */ struct spi_nor_flash_parameter { --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA71C433EF for ; Wed, 2 Feb 2022 14:59:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345337AbiBBO7L (ORCPT ); Wed, 2 Feb 2022 09:59:11 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:34049 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230292AbiBBO7D (ORCPT ); Wed, 2 Feb 2022 09:59:03 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id C0243223EF; Wed, 2 Feb 2022 15:59:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813942; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2iTA2jTJkIDM2vZHO2WWE0aewRctWW+RyrRZGyus5CU=; b=reHPc19WqarNxL1kXBBxXMfO9y88dz2TiXs0rt5DMooj3A2jv9PKBzPYd/Wj9r4kW8/9co yG36ff0nJiEOf0X9P2OXZGVf1yX59XBEasAsdrpQG0jpYPTwwmwCGWyfpTsgajwODG3v8y WZBNZnjzORrHH0e63oWGH6FJDnriQck= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 03/14] mtd: spi-nor: allow a flash to define its own ready() function Date: Wed, 2 Feb 2022 15:58:42 +0100 Message-Id: <20220202145853.4187726-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Xilinx and Micron flashes have their own implementation of the spi_nor_ready() function. At the moment, the core will figure out which one to call according to some flags. Lay the foundation to make it possible that a flash can register its own ready() function. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 4 ++++ drivers/mtd/spi-nor/core.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index c8cc906cf771..c181f2680df2 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -794,6 +794,10 @@ static int spi_nor_ready(struct spi_nor *nor) { int sr, fsr; =20 + /* flashes might override our standard routine */ + if (nor->params->ready) + return nor->params->ready(nor); + if (nor->flags & SNOR_F_READY_XSR_RDY) sr =3D spi_nor_xsr_ready(nor); else diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 10f478547dc2..446218b0e017 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -261,6 +261,9 @@ struct spi_nor_otp { * SPI NOR flashes that have peculiarities to the SPI NOR * standard e.g. different opcodes, specific address * calculation, page size, etc. + * @ready: (optional) flashes might use a different mechanism + * than reading the status register to indicate they + * are ready for a new command * @locking_ops: SPI NOR locking methods. */ struct spi_nor_flash_parameter { @@ -282,6 +285,7 @@ struct spi_nor_flash_parameter { int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); u32 (*convert_addr)(struct spi_nor *nor, u32 addr); int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); + int (*ready)(struct spi_nor *nor); =20 const struct spi_nor_locking_ops *locking_ops; }; --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81913C433F5 for ; Wed, 2 Feb 2022 14:59:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345383AbiBBO7T (ORCPT ); Wed, 2 Feb 2022 09:59:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345272AbiBBO7F (ORCPT ); Wed, 2 Feb 2022 09:59:05 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CEB8C061714 for ; Wed, 2 Feb 2022 06:59:04 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 3884A223F0; Wed, 2 Feb 2022 15:59:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813942; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fmAquychthIKrgzA1gE1u+HXxd7GY+EGxyYUz3rjGHo=; b=dQGwZzjVdVI200OR/VgcXl18HfdgDkZ5fdIkl43hUXjh5/U444iTp2QfsxDHijQMAaRNNb Y1qp0NnMqD8ygHrB3S1ChiSx1B5u/sblnONMRi6c+XdyuK7EhHiDLNNpxlvSRUzsz9M5dc qgKxghS9EWtHMjzYUbk+m4fe8MpwS04= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 04/14] mtd: spi-nor: move all xilinx specifics into xilinx.c Date: Wed, 2 Feb 2022 15:58:43 +0100 Message-Id: <20220202145853.4187726-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 64 +------------------------------ drivers/mtd/spi-nor/core.h | 18 --------- drivers/mtd/spi-nor/xilinx.c | 73 ++++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 9 ----- 4 files changed, 74 insertions(+), 90 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index c181f2680df2..fdc8ef623254 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -598,57 +598,6 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear) return ret; } =20 -/** - * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. - * @nor: pointer to 'struct spi_nor'. - * @sr: pointer to a DMA-able buffer where the value of the - * Status Register will be written. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr, 0)); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, - 1); - } - - if (ret) - dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); - - return ret; -} - -/** - * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to se= e if - * the flash is ready for new commands. - * @nor: pointer to 'struct spi_nor'. - * - * Return: 1 if ready, 0 if not ready, -errno on errors. - */ -static int spi_nor_xsr_ready(struct spi_nor *nor) -{ - int ret; - - ret =3D spi_nor_xread_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - return !!(nor->bouncebuf[0] & XSR_RDY); -} - /** * spi_nor_clear_sr() - Clear the Status Register. * @nor: pointer to 'struct spi_nor'. @@ -798,10 +747,7 @@ static int spi_nor_ready(struct spi_nor *nor) if (nor->params->ready) return nor->params->ready(nor); =20 - if (nor->flags & SNOR_F_READY_XSR_RDY) - sr =3D spi_nor_xsr_ready(nor); - else - sr =3D spi_nor_sr_ready(nor); + sr =3D spi_nor_sr_ready(nor); if (sr < 0) return sr; fsr =3D nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; @@ -2677,14 +2623,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) =20 if (flags & USE_FSR) nor->flags |=3D SNOR_F_USE_FSR; - - /* - * Make sure the XSR_RDY flag is set before calling - * spi_nor_wait_till_ready(). Xilinx S3AN share MFR - * with Atmel SPI NOR. - */ - if (flags & SPI_NOR_XSR_RDY) - nor->flags |=3D SNOR_F_READY_XSR_RDY; } =20 /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 446218b0e017..fabc01ae9a81 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -15,7 +15,6 @@ enum spi_nor_option_flags { SNOR_F_USE_FSR =3D BIT(0), SNOR_F_HAS_SR_TB =3D BIT(1), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(2), - SNOR_F_READY_XSR_RDY =3D BIT(3), SNOR_F_USE_CLSR =3D BIT(4), SNOR_F_BROKEN_RESET =3D BIT(5), SNOR_F_4B_OPCODES =3D BIT(6), @@ -351,8 +350,6 @@ struct spi_nor_fixups { * SPI_NOR_NO_FR: can't do fastread. * USE_CLSR: use CLSR command. * USE_FSR: use flag status register - * SPI_NOR_XSR_RDY: S3AN flashes have specific opcode to read the - * status register. * * @no_sfdp_flags: flags that indicate support that can be discovered via= SFDP. * Used when SFDP tables are not defined in the flash. Th= ese @@ -405,7 +402,6 @@ struct flash_info { #define SPI_NOR_NO_FR BIT(8) #define USE_CLSR BIT(9) #define USE_FSR BIT(10) -#define SPI_NOR_XSR_RDY BIT(11) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) @@ -462,19 +458,6 @@ struct flash_info { .addr_width =3D (_addr_width), \ .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, \ =20 -#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ - .id =3D { \ - ((_jedec_id) >> 16) & 0xff, \ - ((_jedec_id) >> 8) & 0xff, \ - (_jedec_id) & 0xff \ - }, \ - .id_len =3D 3, \ - .sector_size =3D (8*_page_size), \ - .n_sectors =3D (_n_sectors), \ - .page_size =3D _page_size, \ - .addr_width =3D 3, \ - .flags =3D SPI_NOR_NO_FR | SPI_NOR_XSR_RDY, - #define OTP_INFO(_len, _n_regions, _base, _offset) \ .otp_org =3D { \ .len =3D (_len), \ @@ -564,7 +547,6 @@ int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr,= size_t len); int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr); =20 -int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf); ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 580562bc1e45..a865dadc2e5d 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -8,6 +8,27 @@ =20 #include "core.h" =20 +#define SPINOR_OP_XSE 0x50 /* Sector erase */ +#define SPINOR_OP_XPP 0x82 /* Page program */ +#define SPINOR_OP_XRDSR 0xd7 /* Read status register */ + +#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ +#define XSR_RDY BIT(7) /* Ready */ + +#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ + .id =3D { \ + ((_jedec_id) >> 16) & 0xff, \ + ((_jedec_id) >> 8) & 0xff, \ + (_jedec_id) & 0xff \ + }, \ + .id_len =3D 3, \ + .sector_size =3D (8*_page_size), \ + .n_sectors =3D (_n_sectors), \ + .page_size =3D _page_size, \ + .addr_width =3D 3, \ + .flags =3D SPI_NOR_NO_FR + +/* Xilinx S3AN share MFR with Atmel SPI NOR */ static const struct flash_info xilinx_parts[] =3D { /* Xilinx S3AN Internal Flash */ { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, @@ -38,6 +59,57 @@ static u32 s3an_convert_addr(struct spi_nor *nor, u32 ad= dr) return page | offset; } =20 +/** + * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. + * @nor: pointer to 'struct spi_nor'. + * @sr: pointer to a DMA-able buffer where the value of the + * Status Register will be written. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, sr, 0)); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, + 1); + } + + if (ret) + dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); + + return ret; +} + +/** + * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to se= e if + * the flash is ready for new commands. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 1 if ready, 0 if not ready, -errno on errors. + */ +static int spi_nor_xsr_ready(struct spi_nor *nor) +{ + int ret; + + ret =3D spi_nor_xread_sr(nor, nor->bouncebuf); + if (ret) + return ret; + + return !!(nor->bouncebuf[0] & XSR_RDY); +} + static int xilinx_nor_setup(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps) { @@ -83,6 +155,7 @@ static int xilinx_nor_setup(struct spi_nor *nor, static void xilinx_late_init(struct spi_nor *nor) { nor->params->setup =3D xilinx_nor_setup; + nor->params->ready =3D spi_nor_xsr_ready; } =20 static const struct spi_nor_fixups xilinx_fixups =3D { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index fc90fce26e33..b44b05a6f934 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -86,15 +86,6 @@ #define SPINOR_OP_BP 0x02 /* Byte program */ #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ =20 -/* Used for S3AN flashes only */ -#define SPINOR_OP_XSE 0x50 /* Sector erase */ -#define SPINOR_OP_XPP 0x82 /* Page program */ -#define SPINOR_OP_XRDSR 0xd7 /* Read status register */ - -#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ -#define XSR_RDY BIT(7) /* Ready */ - - /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5CA1C433EF for ; Wed, 2 Feb 2022 14:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345311AbiBBO7Q (ORCPT ); Wed, 2 Feb 2022 09:59:16 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:39231 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345260AbiBBO7E (ORCPT ); Wed, 2 Feb 2022 09:59:04 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id DF802223F6; Wed, 2 Feb 2022 15:59:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813943; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3Mb7Hw57gwlsZsvaib7xEeRanv0buA9g96Lty7UwaOw=; b=lsIhkBAJku+V9hddMsy4XsCV4J5o7+uMMQvfL0vlcy+4QAdehLB1Lge7z8l0dDgYmYZeZP znNaSz8J5cKtjRYL85Lu+GyQQUMiRRqX6a6872/CvAKbJt87ljn/J0R3f+0N0LHuzU8l1v OF2BURVC8bytFjnN51LkuUzgaMDO/Bc= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 05/14] mtd: spi-nor: xilinx: rename vendor specific functions and defines Date: Wed, 2 Feb 2022 15:58:44 +0100 Message-Id: <20220202145853.4187726-6-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop the generic spi_nor prefix for all the xilinx functions. Signed-off-by: Michael Walle Reported-by: kernel test robot --- drivers/mtd/spi-nor/xilinx.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index a865dadc2e5d..3e85530df1e4 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -8,9 +8,9 @@ =20 #include "core.h" =20 -#define SPINOR_OP_XSE 0x50 /* Sector erase */ -#define SPINOR_OP_XPP 0x82 /* Page program */ -#define SPINOR_OP_XRDSR 0xd7 /* Read status register */ +#define XILINX_OP_SE 0x50 /* Sector erase */ +#define XILINX_OP_PP 0x82 /* Page program */ +#define XILINX_OP_RDSR 0xd7 /* Read status register */ =20 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ #define XSR_RDY BIT(7) /* Ready */ @@ -60,20 +60,20 @@ static u32 s3an_convert_addr(struct spi_nor *nor, u32 a= ddr) } =20 /** - * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. + * xilinx_read_sr() - Read the Status Register on S3AN flashes. * @nor: pointer to 'struct spi_nor'. * @sr: pointer to a DMA-able buffer where the value of the * Status Register will be written. * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) +static int xilinx_read_sr(struct spi_nor *nor, u8 *sr) { int ret; =20 if (nor->spimem) { struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0), + SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(1, sr, 0)); @@ -82,7 +82,7 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, + ret =3D spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr, 1); } =20 @@ -99,11 +99,11 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) * * Return: 1 if ready, 0 if not ready, -errno on errors. */ -static int spi_nor_xsr_ready(struct spi_nor *nor) +static int xilinx_sr_ready(struct spi_nor *nor) { int ret; =20 - ret =3D spi_nor_xread_sr(nor, nor->bouncebuf); + ret =3D xilinx_read_sr(nor, nor->bouncebuf); if (ret) return ret; =20 @@ -116,12 +116,12 @@ static int xilinx_nor_setup(struct spi_nor *nor, u32 page_size; int ret; =20 - ret =3D spi_nor_xread_sr(nor, nor->bouncebuf); + ret =3D xilinx_read_sr(nor, nor->bouncebuf); if (ret) return ret; =20 - nor->erase_opcode =3D SPINOR_OP_XSE; - nor->program_opcode =3D SPINOR_OP_XPP; + nor->erase_opcode =3D XILINX_OP_SE; + nor->program_opcode =3D XILINX_OP_PP; nor->read_opcode =3D SPINOR_OP_READ; nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; =20 @@ -155,7 +155,7 @@ static int xilinx_nor_setup(struct spi_nor *nor, static void xilinx_late_init(struct spi_nor *nor) { nor->params->setup =3D xilinx_nor_setup; - nor->params->ready =3D spi_nor_xsr_ready; + nor->params->ready =3D xilinx_sr_ready; } =20 static const struct spi_nor_fixups xilinx_fixups =3D { --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F3ABC433FE for ; Wed, 2 Feb 2022 14:59:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244287AbiBBO7Y (ORCPT ); Wed, 2 Feb 2022 09:59:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345271AbiBBO7F (ORCPT ); Wed, 2 Feb 2022 09:59:05 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D653CC06173B for ; Wed, 2 Feb 2022 06:59:04 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 24C56223F7; Wed, 2 Feb 2022 15:59:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813943; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p7A/4WH3Hp3ldUDbngD7NflORly3uSPDOIhgEgdq0hw=; b=kfkZ45SxsKI7TCjO+N2K7Kah85y6nqDm0YPnxFVOUSZu5fQTe63ZDUdGdKN1Is0/jH3sHA qX1+7Fld7BsLmOg+QAgcA8kzDMmWYDquRqzTBATHYIaHgXkcXZqreT2vTOJNs46bfBc6bV k3s9Un3L+Qxv0gOMSOd8uXJEPiRB6Ew= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 06/14] mtd: spi-nor: xilinx: correct the debug message Date: Wed, 2 Feb 2022 15:58:45 +0100 Message-Id: <20220202145853.4187726-7-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We are reading the status register, there is no XRDSR register. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/xilinx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 3e85530df1e4..9e3ed9609250 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -87,7 +87,7 @@ static int xilinx_read_sr(struct spi_nor *nor, u8 *sr) } =20 if (ret) - dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); + dev_dbg(nor->dev, "error %d reading SR\n", ret); =20 return ret; } --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE22FC433F5 for ; Wed, 2 Feb 2022 14:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239954AbiBBO7b (ORCPT ); Wed, 2 Feb 2022 09:59:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345274AbiBBO7F (ORCPT ); Wed, 2 Feb 2022 09:59:05 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 517E7C06173D for ; Wed, 2 Feb 2022 06:59:05 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 8226D2241C; Wed, 2 Feb 2022 15:59:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813943; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aQbgy5PEV+7BgCO3CfORiPEQmaibsGIMnV4yvc5KePo=; b=kDZp5bj2vFUaNl2WxkRZOaZ5HpFSFb4z7/vjSvkxhXj1Mt/lP5yUE1VFE2DUCDmsuf8bbs SZvPEoyG2qpjOFVu6aQcFCu7wdCrEeBv+C2n+jNBQR4qRMCDDKz+VxUGVZC2NS5DmBUjjJ 9Mjr3v2yNZvtSBFBHX+BGFWmL0UoIm0= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 07/14] mtd: spi-nor: move all micron-st specifics into micron-st.c Date: Wed, 2 Feb 2022 15:58:46 +0100 Message-Id: <20220202145853.4187726-8-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The flag status register is only available on micron flashes. Move all the functions around that into the micron module. This is almost a mechanical move except for the spi_nor_fsr_ready() which now also checks the normal status register. Previously, this was done in spi_nor_ready(). Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 123 +----------------------------- drivers/mtd/spi-nor/micron-st.c | 129 ++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 8 -- 3 files changed, 130 insertions(+), 130 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index fdc8ef623254..e9d9880149d2 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -412,50 +412,6 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) return ret; } =20 -/** - * spi_nor_read_fsr() - Read the Flag Status Register. - * @nor: pointer to 'struct spi_nor' - * @fsr: pointer to a DMA-able buffer where the value of the - * Flag Status Register will be written. Should be at least 2 - * bytes. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, fsr, 0)); - - if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { - op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; - op.dummy.nbytes =3D nor->params->rdsr_dummy; - /* - * We don't want to read only one byte in DTR mode. So, - * read 2 and then discard the second byte. - */ - op.data.nbytes =3D 2; - } - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, - 1); - } - - if (ret) - dev_dbg(nor->dev, "error %d reading FSR\n", ret); - - return ret; -} - /** * spi_nor_read_cr() - Read the Configuration Register using the * SPINOR_OP_RDCR (35h) command. @@ -664,75 +620,6 @@ int spi_nor_sr_ready(struct spi_nor *nor) return !(nor->bouncebuf[0] & SR_WIP); } =20 -/** - * spi_nor_clear_fsr() - Clear the Flag Status Register. - * @nor: pointer to 'struct spi_nor'. - */ -static void spi_nor_clear_fsr(struct spi_nor *nor) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, - NULL, 0); - } - - if (ret) - dev_dbg(nor->dev, "error %d clearing FSR\n", ret); -} - -/** - * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flas= h is - * ready for new commands. - * @nor: pointer to 'struct spi_nor'. - * - * Return: 1 if ready, 0 if not ready, -errno on errors. - */ -static int spi_nor_fsr_ready(struct spi_nor *nor) -{ - int ret =3D spi_nor_read_fsr(nor, nor->bouncebuf); - - if (ret) - return ret; - - if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { - if (nor->bouncebuf[0] & FSR_E_ERR) - dev_err(nor->dev, "Erase operation failed.\n"); - else - dev_err(nor->dev, "Program operation failed.\n"); - - if (nor->bouncebuf[0] & FSR_PT_ERR) - dev_err(nor->dev, - "Attempted to modify a protected sector.\n"); - - spi_nor_clear_fsr(nor); - - /* - * WEL bit remains set to one when an erase or page program - * error occurs. Issue a Write Disable command to protect - * against inadvertent writes that can possibly corrupt the - * contents of the memory. - */ - ret =3D spi_nor_write_disable(nor); - if (ret) - return ret; - - return -EIO; - } - - return !!(nor->bouncebuf[0] & FSR_READY); -} - /** * spi_nor_ready() - Query the flash to see if it is ready for new command= s. * @nor: pointer to 'struct spi_nor'. @@ -741,19 +628,11 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) */ static int spi_nor_ready(struct spi_nor *nor) { - int sr, fsr; - /* flashes might override our standard routine */ if (nor->params->ready) return nor->params->ready(nor); =20 - sr =3D spi_nor_sr_ready(nor); - if (sr < 0) - return sr; - fsr =3D nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; - if (fsr < 0) - return fsr; - return sr && fsr; + return spi_nor_sr_ready(nor); } =20 /** diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index bb95b1aabf74..c66580e8aa00 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -8,6 +8,8 @@ =20 #include "core.h" =20 +#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ +#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */ #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */ @@ -17,6 +19,12 @@ #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */ #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */ =20 +/* Flag Status Register bits */ +#define FSR_READY BIT(7) /* Device status, 0 =3D Busy, 1 =3D Ready */ +#define FSR_E_ERR BIT(5) /* Erase operation status */ +#define FSR_P_ERR BIT(4) /* Program operation status */ +#define FSR_PT_ERR BIT(1) /* Protection error bit */ + static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enabl= e) { struct spi_mem_op op; @@ -273,12 +281,133 @@ static int st_micron_set_4byte_addr_mode(struct spi_= nor *nor, bool enable) return spi_nor_write_disable(nor); } =20 +/** + * spi_nor_read_fsr() - Read the Flag Status Register. + * @nor: pointer to 'struct spi_nor' + * @fsr: pointer to a DMA-able buffer where the value of the + * Flag Status Register will be written. Should be at least 2 + * bytes. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, fsr, 0)); + + if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { + op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; + op.dummy.nbytes =3D nor->params->rdsr_dummy; + /* + * We don't want to read only one byte in DTR mode. So, + * read 2 and then discard the second byte. + */ + op.data.nbytes =3D 2; + } + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, + 1); + } + + if (ret) + dev_dbg(nor->dev, "error %d reading FSR\n", ret); + + return ret; +} + +/** + * spi_nor_clear_fsr() - Clear the Flag Status Register. + * @nor: pointer to 'struct spi_nor'. + */ +static void spi_nor_clear_fsr(struct spi_nor *nor) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, + NULL, 0); + } + + if (ret) + dev_dbg(nor->dev, "error %d clearing FSR\n", ret); +} + +/** + * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flas= h is + * ready for new commands. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 1 if ready, 0 if not ready, -errno on errors. + */ +static int spi_nor_fsr_ready(struct spi_nor *nor) +{ + int sr_ready, ret; + + sr_ready =3D spi_nor_sr_ready(nor); + if (sr_ready < 0) + return sr_ready; + + ret =3D spi_nor_read_fsr(nor, nor->bouncebuf); + if (ret) + return ret; + + if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { + if (nor->bouncebuf[0] & FSR_E_ERR) + dev_err(nor->dev, "Erase operation failed.\n"); + else + dev_err(nor->dev, "Program operation failed.\n"); + + if (nor->bouncebuf[0] & FSR_PT_ERR) + dev_err(nor->dev, + "Attempted to modify a protected sector.\n"); + + spi_nor_clear_fsr(nor); + + /* + * WEL bit remains set to one when an erase or page program + * error occurs. Issue a Write Disable command to protect + * against inadvertent writes that can possibly corrupt the + * contents of the memory. + */ + ret =3D spi_nor_write_disable(nor); + if (ret) + return ret; + + return -EIO; + } + + return sr_ready && !!(nor->bouncebuf[0] & FSR_READY); +} + static void micron_st_default_init(struct spi_nor *nor) { nor->flags |=3D SNOR_F_HAS_LOCK; nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params->quad_enable =3D NULL; nor->params->set_4byte_addr_mode =3D st_micron_set_4byte_addr_mode; + + if (nor->flags & SNOR_F_USE_FSR) + nor->params->ready =3D spi_nor_fsr_ready; } =20 static const struct spi_nor_fixups micron_st_fixups =3D { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b44b05a6f934..4622251a79ff 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -47,8 +47,6 @@ #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ -#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ -#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */ @@ -126,12 +124,6 @@ /* Enhanced Volatile Configuration Register bits */ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ =20 -/* Flag Status Register bits */ -#define FSR_READY BIT(7) /* Device status, 0 =3D Busy, 1 =3D Ready */ -#define FSR_E_ERR BIT(5) /* Erase operation status */ -#define FSR_P_ERR BIT(4) /* Program operation status */ -#define FSR_PT_ERR BIT(1) /* Protection error bit */ - /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT1 BIT(1) #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */ --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 142DAC433FE for ; Wed, 2 Feb 2022 14:59:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345422AbiBBO71 (ORCPT ); Wed, 2 Feb 2022 09:59:27 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:37555 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231985AbiBBO7F (ORCPT ); Wed, 2 Feb 2022 09:59:05 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id C5A2B22438; Wed, 2 Feb 2022 15:59:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813943; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vtBcnCimMV7Xpa2ypH3uM608KAj443o4ADbGW32E3Qs=; b=G69zDgilDuYnj07t7ntgfKoyYYLmoQ3hF8xKdcwLl+PbFXKLZCL4g1JCczNBGzkCRnFmmo KeCQ3aYdg8xIc6jyN0v1XELok2r/DzRKMgLWpf/WaYt+eQFkKiVHN7B6o06mgDhbJSpJzP iBwGQJM/qWmg1widK3ZgfojCaztAj88= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 08/14] mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag Date: Wed, 2 Feb 2022 15:58:47 +0100 Message-Id: <20220202145853.4187726-9-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that all functions using that flag are local to the micron module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 -- drivers/mtd/spi-nor/core.h | 3 -- drivers/mtd/spi-nor/micron-st.c | 92 +++++++++++++++++++++------------ 3 files changed, 59 insertions(+), 39 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index e9d9880149d2..be65aaa954ca 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2499,9 +2499,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) =20 if (flags & USE_CLSR) nor->flags |=3D SNOR_F_USE_CLSR; - - if (flags & USE_FSR) - nor->flags |=3D SNOR_F_USE_FSR; } =20 /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index fabc01ae9a81..a02bf54289fb 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -12,7 +12,6 @@ #define SPI_NOR_MAX_ID_LEN 6 =20 enum spi_nor_option_flags { - SNOR_F_USE_FSR =3D BIT(0), SNOR_F_HAS_SR_TB =3D BIT(1), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(2), SNOR_F_USE_CLSR =3D BIT(4), @@ -349,7 +348,6 @@ struct spi_nor_fixups { * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. * USE_CLSR: use CLSR command. - * USE_FSR: use flag status register * * @no_sfdp_flags: flags that indicate support that can be discovered via= SFDP. * Used when SFDP tables are not defined in the flash. Th= ese @@ -401,7 +399,6 @@ struct flash_info { #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) #define USE_CLSR BIT(9) -#define USE_FSR BIT(10) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index c66580e8aa00..33531c101ccb 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -8,6 +8,8 @@ =20 #include "core.h" =20 +#define USE_FSR BIT(0) + #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ @@ -140,15 +142,17 @@ static const struct spi_nor_fixups mt35xu512aba_fixup= s =3D { =20 static const struct flash_info micron_parts[] =3D { { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE) - .fixups =3D &mt35xu512aba_fixups}, + MFR_FLAGS(USE_FSR) + .fixups =3D &mt35xu512aba_fixups + }, { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ) - FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + MFR_FLAGS(USE_FSR) + }, }; =20 static const struct flash_info st_parts[] =3D { @@ -164,57 +168,79 @@ static const struct flash_info st_parts[] =3D { NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + SPI_NOR_BP3_SR_BIT6) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + SPI_NOR_BP3_SR_BIT6) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) - FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + MFR_FLAGS(USE_FSR) + }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, + SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) - FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + MFR_FLAGS(USE_FSR) + }, { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512) - FLAGS(USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) - FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + MFR_FLAGS(USE_FSR) + }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + SPI_NOR_BP3_SR_BIT6) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024) - FLAGS(USE_FSR) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) - FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + MFR_FLAGS(USE_FSR) + }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + SPI_NOR_BP3_SR_BIT6) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048) - FLAGS(NO_CHIP_ERASE | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + FLAGS(NO_CHIP_ERASE) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096) - FLAGS(NO_CHIP_ERASE | USE_FSR) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, + FLAGS(NO_CHIP_ERASE) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096) - FLAGS(NO_CHIP_ERASE | USE_FSR) + FLAGS(NO_CHIP_ERASE) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, + SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_FSR) + }, =20 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2) }, { "m25p10", INFO(0x202011, 0, 32 * 1024, 4) }, @@ -406,7 +432,7 @@ static void micron_st_default_init(struct spi_nor *nor) nor->params->quad_enable =3D NULL; nor->params->set_4byte_addr_mode =3D st_micron_set_4byte_addr_mode; =20 - if (nor->flags & SNOR_F_USE_FSR) + if (nor->info->mfr_flags & USE_FSR) nor->params->ready =3D spi_nor_fsr_ready; } =20 --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCA24C433FE for ; Wed, 2 Feb 2022 14:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345446AbiBBO7i (ORCPT ); Wed, 2 Feb 2022 09:59:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345303AbiBBO7G (ORCPT ); Wed, 2 Feb 2022 09:59:06 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9633AC061714 for ; Wed, 2 Feb 2022 06:59:06 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 64EC922441; Wed, 2 Feb 2022 15:59:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813944; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AX9pymXLzKsGtsuax1oHvt5m9WkCF5LD1CjdM1Z5nko=; b=ovdzsz/f8FaU92fqcDM09aVytUUUYN4xJoOBK6zhbPPOWkBCgcdBYzCXRXh2/GiXJVeqB4 3NjKg5CyzHhdjMrwyUNphwQT7yInJuSb19LWWY7hQ3FXQSQBUxdzrsQrE0/GOQzmIAM4sR 25GJJ1XVFA4a6+CBlpmx57a0c4ol6QE= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 09/14] mtd: spi-nor: micron-st: fix micron_st prefix Date: Wed, 2 Feb 2022 15:58:48 +0100 Message-Id: <20220202145853.4187726-10-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The usual prefix is micron_st, so use that instead of st_micron. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 33531c101ccb..ca368b48bcb0 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -284,7 +284,7 @@ static const struct flash_info st_parts[] =3D { }; =20 /** - * st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Mi= cron + * micron_st_set_4byte_addr_mode() - Set 4-byte address mode for ST and Mi= cron * flashes. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte @@ -292,7 +292,7 @@ static const struct flash_info st_parts[] =3D { * * Return: 0 on success, -errno otherwise. */ -static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +static int micron_st_set_4byte_addr_mode(struct spi_nor *nor, bool enable) { int ret; =20 @@ -430,7 +430,7 @@ static void micron_st_default_init(struct spi_nor *nor) nor->flags |=3D SNOR_F_HAS_LOCK; nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params->quad_enable =3D NULL; - nor->params->set_4byte_addr_mode =3D st_micron_set_4byte_addr_mode; + nor->params->set_4byte_addr_mode =3D micron_st_set_4byte_addr_mode; =20 if (nor->info->mfr_flags & USE_FSR) nor->params->ready =3D spi_nor_fsr_ready; --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A581EC433EF for ; Wed, 2 Feb 2022 14:59:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345325AbiBBO7V (ORCPT ); Wed, 2 Feb 2022 09:59:21 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:39231 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345270AbiBBO7F (ORCPT ); Wed, 2 Feb 2022 09:59:05 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id A1C2B2244E; Wed, 2 Feb 2022 15:59:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813944; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U5OZFdf8BUM0At6XcKxiTxaCJx1UapxDC3xB60RQ8F0=; b=bD/fYvpUj4FGyMs4buDfPGCIY0eAqj72xNrHBCK2/ercit0jk+ITiOj6ZInjZacrzA1Ehu DtMymW7NgQ7anvs42rn/xHqGH3elvDxw0Kj3J3SrZ/s2lz8pCW3MTeWKCJYDXRvEI4e5bt tUD3rgUhrt6QH6Lk37qo5J59Lg1zpk4= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 10/14] mtd: spi-nor: micron-st: rename vendor specific functions and defines Date: Wed, 2 Feb 2022 15:58:49 +0100 Message-Id: <20220202145853.4187726-11-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop the generic spi_nor prefix for all the micron-st functions. Signed-off-by: Michael Walle --- drivers/mtd/spi-nor/micron-st.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index ca368b48bcb0..988ecbffdc36 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -308,7 +308,7 @@ static int micron_st_set_4byte_addr_mode(struct spi_nor= *nor, bool enable) } =20 /** - * spi_nor_read_fsr() - Read the Flag Status Register. + * micron_st_read_fsr() - Read the Flag Status Register. * @nor: pointer to 'struct spi_nor' * @fsr: pointer to a DMA-able buffer where the value of the * Flag Status Register will be written. Should be at least 2 @@ -316,7 +316,7 @@ static int micron_st_set_4byte_addr_mode(struct spi_nor= *nor, bool enable) * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) +static int micron_st_read_fsr(struct spi_nor *nor, u8 *fsr) { int ret; =20 @@ -352,10 +352,10 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *= fsr) } =20 /** - * spi_nor_clear_fsr() - Clear the Flag Status Register. + * micron_st_clear_fsr() - Clear the Flag Status Register. * @nor: pointer to 'struct spi_nor'. */ -static void spi_nor_clear_fsr(struct spi_nor *nor) +static void micron_st_clear_fsr(struct spi_nor *nor) { int ret; =20 @@ -379,13 +379,13 @@ static void spi_nor_clear_fsr(struct spi_nor *nor) } =20 /** - * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flas= h is + * micron_st_fsr_ready() - Query the Flag Status Register to see if the fl= ash is * ready for new commands. * @nor: pointer to 'struct spi_nor'. * * Return: 1 if ready, 0 if not ready, -errno on errors. */ -static int spi_nor_fsr_ready(struct spi_nor *nor) +static int micron_st_fsr_ready(struct spi_nor *nor) { int sr_ready, ret; =20 @@ -393,7 +393,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) if (sr_ready < 0) return sr_ready; =20 - ret =3D spi_nor_read_fsr(nor, nor->bouncebuf); + ret =3D micron_st_read_fsr(nor, nor->bouncebuf); if (ret) return ret; =20 @@ -407,7 +407,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) dev_err(nor->dev, "Attempted to modify a protected sector.\n"); =20 - spi_nor_clear_fsr(nor); + micron_st_clear_fsr(nor); =20 /* * WEL bit remains set to one when an erase or page program @@ -433,7 +433,7 @@ static void micron_st_default_init(struct spi_nor *nor) nor->params->set_4byte_addr_mode =3D micron_st_set_4byte_addr_mode; =20 if (nor->info->mfr_flags & USE_FSR) - nor->params->ready =3D spi_nor_fsr_ready; + nor->params->ready =3D micron_st_fsr_ready; } =20 static const struct spi_nor_fixups micron_st_fixups =3D { --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2D58C433EF for ; Wed, 2 Feb 2022 14:59:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345474AbiBBO7n (ORCPT ); Wed, 2 Feb 2022 09:59:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345312AbiBBO7H (ORCPT ); Wed, 2 Feb 2022 09:59:07 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7F25C06173D for ; Wed, 2 Feb 2022 06:59:06 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id DB1E32244F; Wed, 2 Feb 2022 15:59:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813945; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Uy8MwJsz+qTIsy4fz0a7GwIE/hOctTmlERX+mFQWMZ8=; b=rk+b2bZ11j2dDHz+3FbBmD+NEjU4l66dF5CswP8UNsA3OZ1gAfj8yoNr3H7GmoaWBrwhI9 z+eJ0/ZC36yzHYQ6otE5BZu0nnOisv4QLhvFrVhwhw0+pFse7EYVJPMKhMUPNL6H/KvE2g ZZShwP9C/WGPib///YAos+mwFxH5kPc= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 11/14] mtd: spi-nor: spansion: slightly rework control flow in late_init() Date: Wed, 2 Feb 2022 15:58:50 +0100 Message-Id: <20220202145853.4187726-12-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Increase readability of the code. Instead of returning early if the flash size is smaller or equal than 16MiB and then do the fixups for larger flashes, do it within the condition. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 534196b1d3e7..dedc2de90cb8 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -296,13 +296,12 @@ static const struct flash_info spansion_parts[] =3D { =20 static void spansion_late_init(struct spi_nor *nor) { - if (nor->params->size <=3D SZ_16M) - return; - - nor->flags |=3D SNOR_F_4B_OPCODES; - /* No small sector erase for 4-byte command set */ - nor->erase_opcode =3D SPINOR_OP_SE; - nor->mtd.erasesize =3D nor->info->sector_size; + if (nor->params->size > SZ_16M) { + nor->flags |=3D SNOR_F_4B_OPCODES; + /* No small sector erase for 4-byte command set */ + nor->erase_opcode =3D SPINOR_OP_SE; + nor->mtd.erasesize =3D nor->info->sector_size; + } } =20 static const struct spi_nor_fixups spansion_fixups =3D { --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCCD7C433EF for ; Wed, 2 Feb 2022 14:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345456AbiBBO7j (ORCPT ); Wed, 2 Feb 2022 09:59:39 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:43019 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345289AbiBBO7G (ORCPT ); Wed, 2 Feb 2022 09:59:06 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 8D7D622450; Wed, 2 Feb 2022 15:59:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813945; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7whRIAEN3XV+TYJgN8JQzN2CwvVyIpxN+ADDsSc+jig=; b=ELnToSwbFXckAhUeV+uQx3cBa9wmSwXey1Lx8PmU1XK1GR0vqE0YPMD5gdNLD2HwMZ9vnG hBswexYmaUlGNdpVyzXv9xPjtawnBfcsL7eIGWqfNq5eOomgyvWUYX4myWh9nNAA071eRw 2Dg+3AjyBcof0pM/Vizjn8M9tcdIupY= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 12/14] mtd: spi-nor: move all spansion specifics into spansion.c Date: Wed, 2 Feb 2022 15:58:51 +0100 Message-Id: <20220202145853.4187726-13-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The clear status register flags is only available on spansion flashes. Move all the functions around that into the spanion module. Signed-off-by: Michael Walle Reported-by: kernel test robot --- drivers/mtd/spi-nor/core.c | 52 +------------------------ drivers/mtd/spi-nor/spansion.c | 70 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 - 3 files changed, 72 insertions(+), 51 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index be65aaa954ca..5b00dfab77a6 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -554,33 +554,6 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear) return ret; } =20 -/** - * spi_nor_clear_sr() - Clear the Status Register. - * @nor: pointer to 'struct spi_nor'. - */ -static void spi_nor_clear_sr(struct spi_nor *nor) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, - NULL, 0); - } - - if (ret) - dev_dbg(nor->dev, "error %d clearing SR\n", ret); -} - /** * spi_nor_sr_ready() - Query the Status Register to see if the flash is r= eady * for new commands. @@ -590,33 +563,12 @@ static void spi_nor_clear_sr(struct spi_nor *nor) */ int spi_nor_sr_ready(struct spi_nor *nor) { - int ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + int ret; =20 + ret =3D spi_nor_read_sr(nor, nor->bouncebuf); if (ret) return ret; =20 - if (nor->flags & SNOR_F_USE_CLSR && - nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { - if (nor->bouncebuf[0] & SR_E_ERR) - dev_err(nor->dev, "Erase Error occurred\n"); - else - dev_err(nor->dev, "Programming Error occurred\n"); - - spi_nor_clear_sr(nor); - - /* - * WEL bit remains set to one when an erase or page program - * error occurs. Issue a Write Disable command to protect - * against inadvertent writes that can possibly corrupt the - * contents of the memory. - */ - ret =3D spi_nor_write_disable(nor); - if (ret) - return ret; - - return -EIO; - } - return !(nor->bouncebuf[0] & SR_WIP); } =20 diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index dedc2de90cb8..4756fb88eab2 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -8,6 +8,7 @@ =20 #include "core.h" =20 +#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 @@ -294,6 +295,72 @@ static const struct flash_info spansion_parts[] =3D { }, }; =20 +/** + * spi_nor_clear_sr() - Clear the Status Register. + * @nor: pointer to 'struct spi_nor'. + */ +static void spi_nor_clear_sr(struct spi_nor *nor) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, + NULL, 0); + } + + if (ret) + dev_dbg(nor->dev, "error %d clearing SR\n", ret); +} + +/** + * spi_nor_sr_ready_and_clear() - Query the Status Register to see if the = flash + * is ready for new commands and clear it. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 1 if ready, 0 if not ready, -errno on errors. + */ +int spi_nor_sr_ready_and_clear(struct spi_nor *nor) +{ + int ret; + + ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + if (ret) + return ret; + + if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { + if (nor->bouncebuf[0] & SR_E_ERR) + dev_err(nor->dev, "Erase Error occurred\n"); + else + dev_err(nor->dev, "Programming Error occurred\n"); + + spi_nor_clear_sr(nor); + + /* + * WEL bit remains set to one when an erase or page program + * error occurs. Issue a Write Disable command to protect + * against inadvertent writes that can possibly corrupt the + * contents of the memory. + */ + ret =3D spi_nor_write_disable(nor); + if (ret) + return ret; + + return -EIO; + } + + return !(nor->bouncebuf[0] & SR_WIP); +} + static void spansion_late_init(struct spi_nor *nor) { if (nor->params->size > SZ_16M) { @@ -302,6 +369,9 @@ static void spansion_late_init(struct spi_nor *nor) nor->erase_opcode =3D SPINOR_OP_SE; nor->mtd.erasesize =3D nor->info->sector_size; } + + if (nor->flags & SNOR_F_USE_CLSR) + nor->params->ready =3D spi_nor_sr_ready_and_clear; } =20 static const struct spi_nor_fixups spansion_fixups =3D { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4622251a79ff..5e25a7b75ae2 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -90,7 +90,6 @@ =20 /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ -#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ =20 /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 078D5C433F5 for ; Wed, 2 Feb 2022 14:59:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345438AbiBBO7g (ORCPT ); Wed, 2 Feb 2022 09:59:36 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:37555 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345273AbiBBO7G (ORCPT ); Wed, 2 Feb 2022 09:59:06 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id CC10722452; Wed, 2 Feb 2022 15:59:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813945; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gMTOvkbBBg8goW+gnyG0rIabzqBaekOQoasEsdTcsls=; b=E/pse3SW6yDoJgBB2ZSXnLfViIJ/kAFpuj8s4Prfchzyk8hyZaVlEuFcKcJ0Pa92JaaaXr CVgzOrrzWCDGb7GQsTJHkiH6jh1d9Hiw5zTg/YbgS97ps1GNjXrWcf95txae0xvin0/LYP gm3p6lQua6TYN97FLDQ0Rwcs5iyN3IQ= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 13/14] mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag Date: Wed, 2 Feb 2022 15:58:52 +0100 Message-Id: <20220202145853.4187726-14-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that all functions using that flag are local to the spanion module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle Reviewed-by: Pratyush Yadav Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 -- drivers/mtd/spi-nor/core.h | 3 -- drivers/mtd/spi-nor/spansion.c | 54 +++++++++++++++++++++------------- 3 files changed, 33 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 5b00dfab77a6..2d5517b3db96 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2448,9 +2448,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) =20 if (flags & NO_CHIP_ERASE) nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; - - if (flags & USE_CLSR) - nor->flags |=3D SNOR_F_USE_CLSR; } =20 /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index a02bf54289fb..2130a96e2044 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -14,7 +14,6 @@ enum spi_nor_option_flags { SNOR_F_HAS_SR_TB =3D BIT(1), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(2), - SNOR_F_USE_CLSR =3D BIT(4), SNOR_F_BROKEN_RESET =3D BIT(5), SNOR_F_4B_OPCODES =3D BIT(6), SNOR_F_HAS_4BAIT =3D BIT(7), @@ -347,7 +346,6 @@ struct spi_nor_fixups { * SPI_NOR_NO_ERASE: no erase command needed. * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. - * USE_CLSR: use CLSR command. * * @no_sfdp_flags: flags that indicate support that can be discovered via= SFDP. * Used when SFDP tables are not defined in the flash. Th= ese @@ -398,7 +396,6 @@ struct flash_info { #define SPI_NOR_NO_ERASE BIT(6) #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) -#define USE_CLSR BIT(9) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 4756fb88eab2..c31ea11f71f2 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -8,6 +8,8 @@ =20 #include "core.h" =20 +#define USE_CLSR BIT(0) + #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ @@ -212,43 +214,53 @@ static const struct flash_info spansion_parts[] =3D { { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128) NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128) - FLAGS(USE_CLSR) NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, + SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256) - FLAGS(SPI_NOR_HAS_LOCK | USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + FLAGS(SPI_NOR_HAS_LOCK) + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256) - FLAGS(USE_CLSR) NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) .fixups =3D &s25fs_s_fixups, }, { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) - FLAGS(USE_CLSR) NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) .fixups =3D &s25fs_s_fixups, }, { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) }, { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) }, { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256) - FLAGS(USE_CLSR) - NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + MFR_FLAGS(USE_CLSR) + }, { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) }, { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) }, { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) }, @@ -370,7 +382,7 @@ static void spansion_late_init(struct spi_nor *nor) nor->mtd.erasesize =3D nor->info->sector_size; } =20 - if (nor->flags & SNOR_F_USE_CLSR) + if (nor->info->mfr_flags & USE_CLSR) nor->params->ready =3D spi_nor_sr_ready_and_clear; } =20 --=20 2.30.2 From nobody Mon Jun 29 21:05:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CF6BC433EF for ; Wed, 2 Feb 2022 14:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345241AbiBBO7r (ORCPT ); Wed, 2 Feb 2022 09:59:47 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:39231 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345293AbiBBO7H (ORCPT ); Wed, 2 Feb 2022 09:59:07 -0500 Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 1AFE722453; Wed, 2 Feb 2022 15:59:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1643813946; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yIv4VTb5VdcS3L6sdsDDVGx9xtU3Q9aCaHFNOFlKMl4=; b=IzDaFxdXy13k7GZxY4ID+OVShStO3QiiP1gNKzG19NZ4M2AmoAmC1yqNGRO13n5OUT+QiD bvXimhKt540pTmk5ziVXRNqHvS0egaaeerKftJ4BQbsJa8qd89kSQTlC4lkT4JNJmYQGEs J+QBcy//hW2N8kNR9LehmQAdkbSceR4= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Michael Walle Subject: [PATCH v1 14/14] mtd: spi-nor: renumber flags Date: Wed, 2 Feb 2022 15:58:53 +0100 Message-Id: <20220202145853.4187726-15-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220202145853.4187726-1-michael@walle.cc> References: <20220202145853.4187726-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As we have deleted some flag, lets renumber them so there are no holes. Signed-off-by: Michael Walle --- drivers/mtd/spi-nor/core.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2130a96e2044..b7fd760e3b47 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -12,20 +12,20 @@ #define SPI_NOR_MAX_ID_LEN 6 =20 enum spi_nor_option_flags { - SNOR_F_HAS_SR_TB =3D BIT(1), - SNOR_F_NO_OP_CHIP_ERASE =3D BIT(2), - SNOR_F_BROKEN_RESET =3D BIT(5), - SNOR_F_4B_OPCODES =3D BIT(6), - SNOR_F_HAS_4BAIT =3D BIT(7), - SNOR_F_HAS_LOCK =3D BIT(8), - SNOR_F_HAS_16BIT_SR =3D BIT(9), - SNOR_F_NO_READ_CR =3D BIT(10), - SNOR_F_HAS_SR_TB_BIT6 =3D BIT(11), - SNOR_F_HAS_4BIT_BP =3D BIT(12), - SNOR_F_HAS_SR_BP3_BIT6 =3D BIT(13), - SNOR_F_IO_MODE_EN_VOLATILE =3D BIT(14), - SNOR_F_SOFT_RESET =3D BIT(15), - SNOR_F_SWP_IS_VOLATILE =3D BIT(16), + SNOR_F_HAS_SR_TB =3D BIT(0), + SNOR_F_NO_OP_CHIP_ERASE =3D BIT(1), + SNOR_F_BROKEN_RESET =3D BIT(2), + SNOR_F_4B_OPCODES =3D BIT(3), + SNOR_F_HAS_4BAIT =3D BIT(4), + SNOR_F_HAS_LOCK =3D BIT(5), + SNOR_F_HAS_16BIT_SR =3D BIT(6), + SNOR_F_NO_READ_CR =3D BIT(7), + SNOR_F_HAS_SR_TB_BIT6 =3D BIT(8), + SNOR_F_HAS_4BIT_BP =3D BIT(9), + SNOR_F_HAS_SR_BP3_BIT6 =3D BIT(10), + SNOR_F_IO_MODE_EN_VOLATILE =3D BIT(11), + SNOR_F_SOFT_RESET =3D BIT(12), + SNOR_F_SWP_IS_VOLATILE =3D BIT(13), }; =20 struct spi_nor_read_command { --=20 2.30.2