From nobody Mon Jun 29 22:18:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 346B3C433EF for ; Wed, 2 Feb 2022 14:02:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344773AbiBBOCl (ORCPT ); Wed, 2 Feb 2022 09:02:41 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:60426 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236875AbiBBOCh (ORCPT ); Wed, 2 Feb 2022 09:02:37 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 212BHSnv008883; Wed, 2 Feb 2022 15:00:11 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=QO75VVUtLxytzTAB78gKyxinIEuCKxE3/gSrZc3vF48=; b=3EXTZHzWH8i/yNWoN5JmS6nmGSKab60UkUiqpgBwP0KlUJzEPnHQ4TmQ6E4RoKBPUNFH /6OoLMzz8GT9dA2laFxA5PnmjKa1/K7AX6Nf6c8XCXEyr/yVUcybKO/hVbjjcmFkdLSJ OE2QxCinekBuAaNmA/qny+KWvhWA1K41eAIBtFg7edzJZQMn+6eaqCpLP4+WNKZ7pcuZ p40C3iNHz8wBW3PPtKPGQjPJHXK97CYDHYvbKpzWUk3On/GSI3PvWmdIMZMseioJSCLg 71MecnPAew64O3nYNhcJMzpQ2DxFGduhEpnRTv3bImJpZML05ZPbS70L67orzbUhsYbS gg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dyhe9junp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Feb 2022 15:00:11 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B7297100034; Wed, 2 Feb 2022 15:00:10 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AFB0321F0D0; Wed, 2 Feb 2022 15:00:10 +0100 (CET) Received: from localhost (10.75.127.48) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 2 Feb 2022 15:00:09 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v3 1/3] dt-bindings: interrupt-controller: stm32-exti: document st,stm32mp13-exti Date: Wed, 2 Feb 2022 15:00:03 +0100 Message-ID: <20220202140005.860-2-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202140005.860-1-alexandre.torgue@foss.st.com> References: <20220202140005.860-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-02_06,2022-02-01_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support of STM32MP13 SoC implies to create a new compatible in order to manage EXTI/GIC mapping changes. Signed-off-by: Alexandre Torgue diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm3= 2-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm= 32-exti.yaml index d19c881b4abc..e44daa09b137 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.= yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.= yaml @@ -20,6 +20,7 @@ properties: - items: - enum: - st,stm32mp1-exti + - st,stm32mp13-exti - const: syscon =20 "#interrupt-cells": --=20 2.17.1 From nobody Mon Jun 29 22:18:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED3DC433EF for ; Wed, 2 Feb 2022 14:02:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344789AbiBBOCn (ORCPT ); Wed, 2 Feb 2022 09:02:43 -0500 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:41228 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344739AbiBBOCh (ORCPT ); Wed, 2 Feb 2022 09:02:37 -0500 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 212BA5Nl018975; Wed, 2 Feb 2022 15:00:11 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=E4g7nrOh/UnPPrXpcy7LXKrM7q2PxRAAMvKD/WLyTPI=; b=NYYOJbAEeTEe6NUED/DFCTXESFzBNSxDqKDaIcqLmi5GMVJV0TDDwtKFJToRAyjY90ZU 1zO+uqzQr2xrzj/w1wc/ylLGdl5P+QUP3xtOcexfdqEkEluZ1KRaF42mD0Eqo0EyLenX YpVUtb7trpAYNGjtO+BuKl6eBjVMULBkE9EkafxyyeT48dcB7nKWrsf+kzuRcgj8xgdL 9lfUWbFiKJKAW9BYnePOQE6M0uDcYEtvDR9sF7TLau+4gJzYsnLwzVvtSG/mkmRJRdvd 3Ohmfnk0b4uE4biGWR6v37iVafwnrDqKPZQvckfcV9YAxrWnRtlPtcRazyw/BN4THNsz xQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dyrujgv7k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Feb 2022 15:00:11 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5B4EF10002A; Wed, 2 Feb 2022 15:00:11 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5293B21F0D0; Wed, 2 Feb 2022 15:00:11 +0100 (CET) Received: from localhost (10.75.127.49) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 2 Feb 2022 15:00:10 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v3 2/3] irqchip/stm32-exti: add STM32MP13 support Date: Wed, 2 Feb 2022 15:00:04 +0100 Message-ID: <20220202140005.860-3-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202140005.860-1-alexandre.torgue@foss.st.com> References: <20220202140005.860-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-02_06,2022-02-01_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same hardware version than STM32MP15. Only EXTI line mapping is changed and following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8], USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2]. Signed-off-by: Alexandre Torgue diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index b7cb2da71888..9d18f47040eb 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -214,6 +214,48 @@ static const struct stm32_desc_irq stm32mp1_desc_irq[]= =3D { { .exti =3D 73, .irq_parent =3D 129, .chip =3D &stm32_exti_h_chip }, }; =20 +static const struct stm32_desc_irq stm32mp13_desc_irq[] =3D { + { .exti =3D 0, .irq_parent =3D 6, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 1, .irq_parent =3D 7, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 2, .irq_parent =3D 8, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 3, .irq_parent =3D 9, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 4, .irq_parent =3D 10, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 5, .irq_parent =3D 24, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 6, .irq_parent =3D 65, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 7, .irq_parent =3D 66, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 8, .irq_parent =3D 67, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 9, .irq_parent =3D 68, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 10, .irq_parent =3D 41, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 11, .irq_parent =3D 43, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 12, .irq_parent =3D 77, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 13, .irq_parent =3D 78, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 14, .irq_parent =3D 106, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 15, .irq_parent =3D 109, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 16, .irq_parent =3D 1, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 19, .irq_parent =3D 3, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 21, .irq_parent =3D 32, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 22, .irq_parent =3D 34, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 23, .irq_parent =3D 73, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 24, .irq_parent =3D 93, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 25, .irq_parent =3D 114, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 26, .irq_parent =3D 38, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 27, .irq_parent =3D 39, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 28, .irq_parent =3D 40, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 29, .irq_parent =3D 72, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 30, .irq_parent =3D 53, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 31, .irq_parent =3D 54, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 32, .irq_parent =3D 83, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 33, .irq_parent =3D 84, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 44, .irq_parent =3D 96, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 47, .irq_parent =3D 92, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 48, .irq_parent =3D 116, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 50, .irq_parent =3D 117, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 52, .irq_parent =3D 118, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 53, .irq_parent =3D 119, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 68, .irq_parent =3D 63, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 70, .irq_parent =3D 98, .chip =3D &stm32_exti_h_chip_direct }, +}; + static const struct stm32_exti_drv_data stm32mp1_drv_data =3D { .exti_banks =3D stm32mp1_exti_banks, .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), @@ -221,6 +263,13 @@ static const struct stm32_exti_drv_data stm32mp1_drv_d= ata =3D { .irq_nr =3D ARRAY_SIZE(stm32mp1_desc_irq), }; =20 +static const struct stm32_exti_drv_data stm32mp13_drv_data =3D { + .exti_banks =3D stm32mp1_exti_banks, + .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), + .desc_irqs =3D stm32mp13_desc_irq, + .irq_nr =3D ARRAY_SIZE(stm32mp13_desc_irq), +}; + static const struct stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_= data, irq_hw_number_t hwirq) @@ -922,6 +971,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) /* platform driver only for MP1 */ static const struct of_device_id stm32_exti_ids[] =3D { { .compatible =3D "st,stm32mp1-exti", .data =3D &stm32mp1_drv_data}, + { .compatible =3D "st,stm32mp13-exti", .data =3D &stm32mp13_drv_data}, {}, }; MODULE_DEVICE_TABLE(of, stm32_exti_ids); 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Wed, 2 Feb 2022 15:00:12 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v3 3/3] ARM: dts: stm32: Enable EXTI on stm32mp13 Date: Wed, 2 Feb 2022 15:00:05 +0100 Message-ID: <20220202140005.860-4-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202140005.860-1-alexandre.torgue@foss.st.com> References: <20220202140005.860-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-02_06,2022-02-01_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As EXTI/GIC mapping has changed between STM32MP15 and STM32MP13, a new compatible is needed to choose mp13 mapping table in stm32-exti driver. Signed-off-by: Alexandre Torgue diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp1= 31.dtsi index 86126dc0d898..c249dbe64354 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -115,6 +115,13 @@ status =3D "disabled"; }; =20 + exti: interrupt-controller@5000d000 { + compatible =3D "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells =3D <2>; + reg =3D <0x5000d000 0x400>; + }; + syscfg: syscon@50020000 { compatible =3D "st,stm32mp157-syscfg", "syscon"; reg =3D <0x50020000 0x400>; --=20 2.17.1