From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 640D2C433EF for ; Wed, 2 Feb 2022 00:05:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230521AbiBBAFl (ORCPT ); Tue, 1 Feb 2022 19:05:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243069AbiBBAEI (ORCPT ); Tue, 1 Feb 2022 19:04:08 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BABE3C061714; Tue, 1 Feb 2022 16:04:07 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id u24so37668632eds.11; Tue, 01 Feb 2022 16:04:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EcT7RfY0lDOArqDYnMVNgzN36oOwKfvUCS+TXnzFQfQ=; b=JQgEv9MfxFFgzBgIEMBw2wG6iK5AnYxGc5CHlpLTFNW7m1y8zLXSVRmM9gnmmNcCWD 7KhuDNLbnSH8PvlTYjzjO6Ur+FkpwMl+Mj4t5Uhuw4EVb6btjpPtzGg45P0s2tpDqa6c c10BKANxOfxZjRG/O7Rxn5dD1pRbDPT12SplHZKNWjU+kR/qRJLEtE9hAMVNm+1MSPz2 iL2dtfMl5jA8HcCLXP9Y1/zGvONn4bOBe+bXNY17ZsmKXhV4aOZpn1yX2Gkz01VelQds gepRj+tpWeAUdShgN7QVnrlubAcplr35OIHh8ac4Ru8wbcGPBldKNqnsGjNu0HTYcSXO ObfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EcT7RfY0lDOArqDYnMVNgzN36oOwKfvUCS+TXnzFQfQ=; b=FJ9xpf7DUFMuIvkALH5oKvPtyE+xWPdMDe+BU0jQWyaydkB/EZN+wxavoONgF0qiMT MFqTXb6JFQDZWyOUlHlfs+WifFTdtc6EGt1k0jaiTWGAp3vodxbbWri7QyxAaA/GjjM4 HBfa9+TnmVd4QJv6D9RLaOgSJUaETKZokVqumq/3kObmd2OTNEEU69UTvEipdEnu9wif p79OBT6jkgWJDeRNgc3wdzsC2U3ojuX7XI7vp0uVKZ6Alv5TgpT+4Um0YxIim6NozZ8W bV/5Rp/Qqu9ISxhHZC/u8c9wKyn3sDzoaTFMH3GQZShaWQ4aaJwdrKbkJIBTvC31AFjH pF3Q== X-Gm-Message-State: AOAM532OVt1lQtVnMiNSagSWwGvEDaXz856ez1G/fJO6bktH/SzGErPC c9+MYt01ubxLHfaxZUNHckI= X-Google-Smtp-Source: ABdhPJwnS3w81doykxQJD+LHtD/0az/J9KRLRMHuDKL0cGkczYyDN/XMGfusse+HJ0J3Yregejj2Sg== X-Received: by 2002:a05:6402:2707:: with SMTP id y7mr27887077edd.329.1643760246160; Tue, 01 Feb 2022 16:04:06 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:05 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Vladimir Oltean , Ansuel Smith Subject: [net-next PATCH v8 01/16] net: dsa: provide switch operations for tracking the master state Date: Wed, 2 Feb 2022 01:03:20 +0100 Message-Id: <20220202000335.19296-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vladimir Oltean Certain drivers may need to send management traffic to the switch for things like register access, FDB dump, etc, to accelerate what their slow bus (SPI, I2C, MDIO) can already do. Ethernet is faster (especially in bulk transactions) but is also more unreliable, since the user may decide to bring the DSA master down (or not bring it up), therefore severing the link between the host and the attached switch. Drivers needing Ethernet-based register access already should have fallback logic to the slow bus if the Ethernet method fails, but that fallback may be based on a timeout, and the I/O to the switch may slow down to a halt if the master is down, because every Ethernet packet will have to time out. The driver also doesn't have the option to turn off Ethernet-based I/O momentarily, because it wouldn't know when to turn it back on. Which is where this change comes in. By tracking NETDEV_CHANGE, NETDEV_UP and NETDEV_GOING_DOWN events on the DSA master, we should know the exact interval of time during which this interface is reliably available for traffic. Provide this information to switches so they can use it as they wish. An helper is added dsa_port_master_is_operational() to check if a master port is operational. Signed-off-by: Vladimir Oltean Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- include/net/dsa.h | 17 +++++++++++++++++ net/dsa/dsa2.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ net/dsa/dsa_priv.h | 13 +++++++++++++ net/dsa/slave.c | 32 ++++++++++++++++++++++++++++++++ net/dsa/switch.c | 15 +++++++++++++++ 5 files changed, 123 insertions(+) diff --git a/include/net/dsa.h b/include/net/dsa.h index 57b3e4e7413b..43c4153ef53a 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -278,6 +278,10 @@ struct dsa_port { =20 u8 devlink_port_setup:1; =20 + /* Master state bits, valid only on CPU ports */ + u8 master_admin_up:1; + u8 master_oper_up:1; + u8 setup:1; =20 struct device_node *dn; @@ -478,6 +482,12 @@ static inline bool dsa_port_is_unused(struct dsa_port = *dp) return dp->type =3D=3D DSA_PORT_TYPE_UNUSED; } =20 +static inline bool dsa_port_master_is_operational(struct dsa_port *dp) +{ + return dsa_port_is_cpu(dp) && dp->master_admin_up && + dp->master_oper_up; +} + static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p) { return dsa_to_port(ds, p)->type =3D=3D DSA_PORT_TYPE_UNUSED; @@ -1036,6 +1046,13 @@ struct dsa_switch_ops { int (*tag_8021q_vlan_add)(struct dsa_switch *ds, int port, u16 vid, u16 flags); int (*tag_8021q_vlan_del)(struct dsa_switch *ds, int port, u16 vid); + + /* + * DSA master tracking operations + */ + void (*master_state_change)(struct dsa_switch *ds, + const struct net_device *master, + bool operational); }; =20 #define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes) \ diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c index 3d21521453fe..ff998c0ede02 100644 --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c @@ -1279,6 +1279,52 @@ int dsa_tree_change_tag_proto(struct dsa_switch_tree= *dst, return err; } =20 +static void dsa_tree_master_state_change(struct dsa_switch_tree *dst, + struct net_device *master) +{ + struct dsa_notifier_master_state_info info; + struct dsa_port *cpu_dp =3D master->dsa_ptr; + + info.master =3D master; + info.operational =3D dsa_port_master_is_operational(cpu_dp); + + dsa_tree_notify(dst, DSA_NOTIFIER_MASTER_STATE_CHANGE, &info); +} + +void dsa_tree_master_admin_state_change(struct dsa_switch_tree *dst, + struct net_device *master, + bool up) +{ + struct dsa_port *cpu_dp =3D master->dsa_ptr; + bool notify =3D false; + + if ((dsa_port_master_is_operational(cpu_dp)) !=3D + (up && cpu_dp->master_oper_up)) + notify =3D true; + + cpu_dp->master_admin_up =3D up; + + if (notify) + dsa_tree_master_state_change(dst, master); +} + +void dsa_tree_master_oper_state_change(struct dsa_switch_tree *dst, + struct net_device *master, + bool up) +{ + struct dsa_port *cpu_dp =3D master->dsa_ptr; + bool notify =3D false; + + if ((dsa_port_master_is_operational(cpu_dp)) !=3D + (cpu_dp->master_admin_up && up)) + notify =3D true; + + cpu_dp->master_oper_up =3D up; + + if (notify) + dsa_tree_master_state_change(dst, master); +} + static struct dsa_port *dsa_port_touch(struct dsa_switch *ds, int index) { struct dsa_switch_tree *dst =3D ds->dst; diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h index 760306f0012f..2bbfa9efe9f8 100644 --- a/net/dsa/dsa_priv.h +++ b/net/dsa/dsa_priv.h @@ -40,6 +40,7 @@ enum { DSA_NOTIFIER_TAG_PROTO_DISCONNECT, DSA_NOTIFIER_TAG_8021Q_VLAN_ADD, DSA_NOTIFIER_TAG_8021Q_VLAN_DEL, + DSA_NOTIFIER_MASTER_STATE_CHANGE, }; =20 /* DSA_NOTIFIER_AGEING_TIME */ @@ -109,6 +110,12 @@ struct dsa_notifier_tag_8021q_vlan_info { u16 vid; }; =20 +/* DSA_NOTIFIER_MASTER_STATE_CHANGE */ +struct dsa_notifier_master_state_info { + const struct net_device *master; + bool operational; +}; + struct dsa_switchdev_event_work { struct dsa_switch *ds; int port; @@ -482,6 +489,12 @@ int dsa_tree_change_tag_proto(struct dsa_switch_tree *= dst, struct net_device *master, const struct dsa_device_ops *tag_ops, const struct dsa_device_ops *old_tag_ops); +void dsa_tree_master_admin_state_change(struct dsa_switch_tree *dst, + struct net_device *master, + bool up); +void dsa_tree_master_oper_state_change(struct dsa_switch_tree *dst, + struct net_device *master, + bool up); unsigned int dsa_bridge_num_get(const struct net_device *bridge_dev, int m= ax); void dsa_bridge_num_put(const struct net_device *bridge_dev, unsigned int bridge_num); diff --git a/net/dsa/slave.c b/net/dsa/slave.c index 22241afcac81..2b5b0f294233 100644 --- a/net/dsa/slave.c +++ b/net/dsa/slave.c @@ -2346,6 +2346,36 @@ static int dsa_slave_netdevice_event(struct notifier= _block *nb, err =3D dsa_port_lag_change(dp, info->lower_state_info); return notifier_from_errno(err); } + case NETDEV_CHANGE: + case NETDEV_UP: { + /* Track state of master port. + * DSA driver may require the master port (and indirectly + * the tagger) to be available for some special operation. + */ + if (netdev_uses_dsa(dev)) { + struct dsa_port *cpu_dp =3D dev->dsa_ptr; + struct dsa_switch_tree *dst =3D cpu_dp->ds->dst; + + /* Track when the master port is UP */ + dsa_tree_master_oper_state_change(dst, dev, + netif_oper_up(dev)); + + /* Track when the master port is ready and can accept + * packet. + * NETDEV_UP event is not enough to flag a port as ready. + * We also have to wait for linkwatch_do_dev to dev_activate + * and emit a NETDEV_CHANGE event. + * We check if a master port is ready by checking if the dev + * have a qdisc assigned and is not noop. + */ + dsa_tree_master_admin_state_change(dst, dev, + !qdisc_tx_is_noop(dev)); + + return NOTIFY_OK; + } + + return NOTIFY_DONE; + } case NETDEV_GOING_DOWN: { struct dsa_port *dp, *cpu_dp; struct dsa_switch_tree *dst; @@ -2357,6 +2387,8 @@ static int dsa_slave_netdevice_event(struct notifier_= block *nb, cpu_dp =3D dev->dsa_ptr; dst =3D cpu_dp->ds->dst; =20 + dsa_tree_master_admin_state_change(dst, dev, false); + list_for_each_entry(dp, &dst->ports, list) { if (!dsa_port_is_user(dp)) continue; diff --git a/net/dsa/switch.c b/net/dsa/switch.c index e3c7d2627a61..4e9cbe3a3127 100644 --- a/net/dsa/switch.c +++ b/net/dsa/switch.c @@ -683,6 +683,18 @@ dsa_switch_disconnect_tag_proto(struct dsa_switch *ds, return 0; } =20 +static int +dsa_switch_master_state_change(struct dsa_switch *ds, + struct dsa_notifier_master_state_info *info) +{ + if (!ds->ops->master_state_change) + return 0; + + ds->ops->master_state_change(ds, info->master, info->operational); + + return 0; +} + static int dsa_switch_event(struct notifier_block *nb, unsigned long event, void *info) { @@ -756,6 +768,9 @@ static int dsa_switch_event(struct notifier_block *nb, case DSA_NOTIFIER_TAG_8021Q_VLAN_DEL: err =3D dsa_switch_tag_8021q_vlan_del(ds, info); break; + case DSA_NOTIFIER_MASTER_STATE_CHANGE: + err =3D dsa_switch_master_state_change(ds, info); + break; default: err =3D -EOPNOTSUPP; break; --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEF23C433EF for ; Wed, 2 Feb 2022 00:04:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243087AbiBBAEN (ORCPT ); Tue, 1 Feb 2022 19:04:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241930AbiBBAEL (ORCPT ); Tue, 1 Feb 2022 19:04:11 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FC26C061714; Tue, 1 Feb 2022 16:04:11 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id l5so37833500edv.3; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:08 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Vladimir Oltean , Ansuel Smith Subject: [net-next PATCH v8 02/16] net: dsa: replay master state events in dsa_tree_{setup,teardown}_master Date: Wed, 2 Feb 2022 01:03:21 +0100 Message-Id: <20220202000335.19296-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vladimir Oltean In order for switch driver to be able to make simple and reliable use of the master tracking operations, they must also be notified of the initial state of the DSA master, not just of the changes. This is because they might enable certain features only during the time when they know that the DSA master is up and running. Therefore, this change explicitly checks the state of the DSA master under the same rtnl_mutex as we were holding during the dsa_master_setup() and dsa_master_teardown() call. The idea being that if the DSA master became operational in between the moment in which it became a DSA master (dsa_master_setup set dev->dsa_ptr) and the moment when we checked for the master being up, there is a chance that we would emit a ->master_state_change() call with no actual state change. We need to avoid that by serializing the concurrent netdevice event with us. If the netdevice event started before, we force it to finish before we begin, because we take rtnl_lock before making netdev_uses_dsa() return true. So we also handle that early event and do nothing on it. Similarly, if the dev_open() attempt is concurrent with us, it will attempt to take the rtnl_mutex, but we're holding it. We'll see that the master flag IFF_UP isn't set, then when we release the rtnl_mutex we'll process the NETDEV_UP notifier. Signed-off-by: Vladimir Oltean Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- net/dsa/dsa2.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c index ff998c0ede02..909b045c9b11 100644 --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include "dsa_priv.h" =20 @@ -1064,9 +1065,18 @@ static int dsa_tree_setup_master(struct dsa_switch_t= ree *dst) =20 list_for_each_entry(dp, &dst->ports, list) { if (dsa_port_is_cpu(dp)) { - err =3D dsa_master_setup(dp->master, dp); + struct net_device *master =3D dp->master; + bool admin_up =3D (master->flags & IFF_UP) && + !qdisc_tx_is_noop(master); + + err =3D dsa_master_setup(master, dp); if (err) return err; + + /* Replay master state event */ + dsa_tree_master_admin_state_change(dst, master, admin_up); + dsa_tree_master_oper_state_change(dst, master, + netif_oper_up(master)); } } =20 @@ -1081,9 +1091,19 @@ static void dsa_tree_teardown_master(struct dsa_swit= ch_tree *dst) =20 rtnl_lock(); =20 - list_for_each_entry(dp, &dst->ports, list) - if (dsa_port_is_cpu(dp)) - dsa_master_teardown(dp->master); + list_for_each_entry(dp, &dst->ports, list) { + if (dsa_port_is_cpu(dp)) { + struct net_device *master =3D dp->master; + + /* Synthesizing an "admin down" state is sufficient for + * the switches to get a notification if the master is + * currently up and running. + */ + dsa_tree_master_admin_state_change(dst, master, false); + + dsa_master_teardown(master); + } + } =20 rtnl_unlock(); } --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C89EEC433EF for ; Wed, 2 Feb 2022 00:04:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243130AbiBBAEV (ORCPT ); Tue, 1 Feb 2022 19:04:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243082AbiBBAEM (ORCPT ); Tue, 1 Feb 2022 19:04:12 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96C70C06173B; Tue, 1 Feb 2022 16:04:12 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id u24so37669067eds.11; Tue, 01 Feb 2022 16:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PBNCS2QbHogQfRAW59h5YIugEzrVS9q3EYocxM/OSkM=; b=a3YsEaI5uFYT1GLJRzyJxND6xoiQlPghij30lqcfQgLkxmYpQ5yXx9Qj4hJBapoas4 M3yUJxUnn+gkJ6kNW2390gEC5AcIYRNbPspJt3USSvQg2KhWpF3njwENzjLfH6+vEiQY 65i+gG5yk+W/FR7fcwTKFkGvd4cumlKHGGQBdBICyAe/vtU7bPkFXP5foFptKVyqaZU/ ehbMjcWIkOw6WSHZPDM9amJguv6kzMse1BDzEj/k0iN0KaFjS45ltJAF76sylkR/Mbd4 JsJuWEIDs6nxZ/X1++yXPH9ZddI6XJCZPcFHXy51a6fSeIfTT4mo1TV+/FOvIxrpRkQU Fb7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PBNCS2QbHogQfRAW59h5YIugEzrVS9q3EYocxM/OSkM=; b=v9O7FTfWAfGaAbh0wlLQYXL8yxpEY7gm5ApqfN+/cpVbxSiCWT7gnpI4UHlY6ngDfO 2ejAMu/WhnO/hUHlICAw03axINy1/dlSNSwtmTVcUz+ptdDQpPaMmPNpmt7VLpnG6rNy lQkQB8i0x3QXsKPRNm19gwCw/yT5ciqOME6Cob+XRyygJmnFIsrL0AzUsMqBoQ19yAty cfbSObdui043kmtA+gHQ4IgrhSkkpLuebv4q706vTpL1lcaPtpM2g5ik6ogP17XBlI42 xrYp7m1QrqGmA1n1ylk/g/0QXeDItnM5uCga1a7l5i9p8EpCZpmM2a53oyDWvMlojZ9s smMw== X-Gm-Message-State: AOAM5314RkRx5vTQJWozynGqhyx7Av29XH0gmeB0Ox6LGkz5DPPvOQXn PtKPh+jQbb/m4G37ZpaU7hxGlgLox7w= X-Google-Smtp-Source: ABdhPJwVUJ1ZfJlAceSBK9jUXWrAZwqzyOHYNOyYWOvO/e/JvnBeEV+tnU5xinlOozY8xW4z98xY8g== X-Received: by 2002:a05:6402:42c6:: with SMTP id i6mr28598063edc.166.1643760251035; Tue, 01 Feb 2022 16:04:11 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:10 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 03/16] net: dsa: tag_qca: convert to FIELD macro Date: Wed, 2 Feb 2022 01:03:22 +0100 Message-Id: <20220202000335.19296-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert driver to FIELD macro to drop redundant define. Signed-off-by: Ansuel Smith Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- net/dsa/tag_qca.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c index 1ea9401b8ace..55fa6b96b4eb 100644 --- a/net/dsa/tag_qca.c +++ b/net/dsa/tag_qca.c @@ -4,29 +4,24 @@ */ =20 #include +#include =20 #include "dsa_priv.h" =20 #define QCA_HDR_LEN 2 #define QCA_HDR_VERSION 0x2 =20 -#define QCA_HDR_RECV_VERSION_MASK GENMASK(15, 14) -#define QCA_HDR_RECV_VERSION_S 14 -#define QCA_HDR_RECV_PRIORITY_MASK GENMASK(13, 11) -#define QCA_HDR_RECV_PRIORITY_S 11 -#define QCA_HDR_RECV_TYPE_MASK GENMASK(10, 6) -#define QCA_HDR_RECV_TYPE_S 6 +#define QCA_HDR_RECV_VERSION GENMASK(15, 14) +#define QCA_HDR_RECV_PRIORITY GENMASK(13, 11) +#define QCA_HDR_RECV_TYPE GENMASK(10, 6) #define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3) -#define QCA_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0) - -#define QCA_HDR_XMIT_VERSION_MASK GENMASK(15, 14) -#define QCA_HDR_XMIT_VERSION_S 14 -#define QCA_HDR_XMIT_PRIORITY_MASK GENMASK(13, 11) -#define QCA_HDR_XMIT_PRIORITY_S 11 -#define QCA_HDR_XMIT_CONTROL_MASK GENMASK(10, 8) -#define QCA_HDR_XMIT_CONTROL_S 8 +#define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0) + +#define QCA_HDR_XMIT_VERSION GENMASK(15, 14) +#define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11) +#define QCA_HDR_XMIT_CONTROL GENMASK(10, 8) #define QCA_HDR_XMIT_FROM_CPU BIT(7) -#define QCA_HDR_XMIT_DP_BIT_MASK GENMASK(6, 0) +#define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0) =20 static struct sk_buff *qca_tag_xmit(struct sk_buff *skb, struct net_device= *dev) { @@ -40,8 +35,9 @@ static struct sk_buff *qca_tag_xmit(struct sk_buff *skb, = struct net_device *dev) phdr =3D dsa_etype_header_pos_tx(skb); =20 /* Set the version field, and set destination port information */ - hdr =3D QCA_HDR_VERSION << QCA_HDR_XMIT_VERSION_S | - QCA_HDR_XMIT_FROM_CPU | BIT(dp->index); + hdr =3D FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION); + hdr |=3D QCA_HDR_XMIT_FROM_CPU; + hdr |=3D FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(dp->index)); =20 *phdr =3D htons(hdr); =20 @@ -62,7 +58,7 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, s= truct net_device *dev) hdr =3D ntohs(*phdr); =20 /* Make sure the version is correct */ - ver =3D (hdr & QCA_HDR_RECV_VERSION_MASK) >> QCA_HDR_RECV_VERSION_S; + ver =3D FIELD_GET(QCA_HDR_RECV_VERSION, hdr); if (unlikely(ver !=3D QCA_HDR_VERSION)) return NULL; =20 @@ -71,7 +67,7 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, s= truct net_device *dev) dsa_strip_etype_header(skb, QCA_HDR_LEN); =20 /* Get source port information */ - port =3D (hdr & QCA_HDR_RECV_SOURCE_PORT_MASK); + port =3D FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, hdr); =20 skb->dev =3D dsa_master_find_slave(dev, 0, port); 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:12 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 04/16] net: dsa: tag_qca: move define to include linux/dsa Date: Wed, 2 Feb 2022 01:03:23 +0100 Message-Id: <20220202000335.19296-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move tag_qca define to include dir linux/dsa as the qca8k require access to the tagger define to support in-band mdio read/write using ethernet packet. Signed-off-by: Ansuel Smith Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- include/linux/dsa/tag_qca.h | 21 +++++++++++++++++++++ net/dsa/tag_qca.c | 16 +--------------- 2 files changed, 22 insertions(+), 15 deletions(-) create mode 100644 include/linux/dsa/tag_qca.h diff --git a/include/linux/dsa/tag_qca.h b/include/linux/dsa/tag_qca.h new file mode 100644 index 000000000000..c02d2d39ff4a --- /dev/null +++ b/include/linux/dsa/tag_qca.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TAG_QCA_H +#define __TAG_QCA_H + +#define QCA_HDR_LEN 2 +#define QCA_HDR_VERSION 0x2 + +#define QCA_HDR_RECV_VERSION GENMASK(15, 14) +#define QCA_HDR_RECV_PRIORITY GENMASK(13, 11) +#define QCA_HDR_RECV_TYPE GENMASK(10, 6) +#define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3) +#define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0) + +#define QCA_HDR_XMIT_VERSION GENMASK(15, 14) +#define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11) +#define QCA_HDR_XMIT_CONTROL GENMASK(10, 8) +#define QCA_HDR_XMIT_FROM_CPU BIT(7) +#define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0) + +#endif /* __TAG_QCA_H */ diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c index 55fa6b96b4eb..34e565e00ece 100644 --- a/net/dsa/tag_qca.c +++ b/net/dsa/tag_qca.c @@ -5,24 +5,10 @@ =20 #include #include +#include =20 #include "dsa_priv.h" =20 -#define QCA_HDR_LEN 2 -#define QCA_HDR_VERSION 0x2 - -#define QCA_HDR_RECV_VERSION GENMASK(15, 14) -#define QCA_HDR_RECV_PRIORITY GENMASK(13, 11) -#define QCA_HDR_RECV_TYPE GENMASK(10, 6) -#define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3) -#define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0) - -#define QCA_HDR_XMIT_VERSION GENMASK(15, 14) -#define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11) -#define QCA_HDR_XMIT_CONTROL GENMASK(10, 8) -#define QCA_HDR_XMIT_FROM_CPU BIT(7) -#define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0) - static struct sk_buff *qca_tag_xmit(struct sk_buff *skb, struct net_device= *dev) { struct dsa_port *dp =3D dsa_slave_to_port(dev); --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11AEAC433F5 for ; Wed, 2 Feb 2022 00:04:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243208AbiBBAEv (ORCPT ); Tue, 1 Feb 2022 19:04:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243110AbiBBAER (ORCPT ); Tue, 1 Feb 2022 19:04:17 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAA4FC06173B; Tue, 1 Feb 2022 16:04:16 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id p7so37891411edc.12; Tue, 01 Feb 2022 16:04:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z9VGchsPoiNssfykfKpnr6kDcC1pZ+R5aD7drdmLAPA=; b=KM9JOsJ3pWyyciBhOdnBGiUF9l0FW4I1jbD85meOFBdc9aqV2Y18RVwTeUNn3U66R/ dyLqheEMv8LQ00yPSQxuZ2ifLxDkCKaY7bEf8TqSwgnf097W+dU53XeBQnYr9A2S7q24 PmFhu/rmLw99oaB4V9mfc1ZplPkwE5tyivdu/QwaMG/CSG6Fsr94xW+gSaAmdpErYrwr s9iyC7C4YPIAQF4tXn8sTzo9LfI841/WON3nwjdiPgt62vTeZ+jPVvE+gAEoJKP6hEMv tTq4v6LZN48jxEFfGnFncCWgcU9BUEp2+mWZ1aRMsPJbST/bBAY53TXjMVvJnpYhzuE4 2EnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z9VGchsPoiNssfykfKpnr6kDcC1pZ+R5aD7drdmLAPA=; b=lFvz7uZ1oGbSQ0n9PLANFvdfMUteUmM9Ts5vnsjdNBY0rytNZf4YnlB1oOi+XW4Xxj 5g/Xs3p0cuwhltXaGnTU+2Q5R6unOHB6azL2c7Qx7eylE8wHwpmM11BsSTzwAMYMgUie XeZZesOjSmRkr8hLhFrZ0CFyyamWetDIJs46WDwbq+PHTpFFdqcAcinnXlufEHZpXdbU KHcfKk7XTvS/GslXthPcxdklXyYcDvPXmXpQQ8N1oWeYKSzndqYYMXu1jACbvVRPsDq7 i95MzYKJf4iny130M1jCekalQJU+dISSelO3D8U//9nQG+Mw/xA4be5+Q9MfLtFMswOH Txjg== X-Gm-Message-State: AOAM533zuvwkLZp8k0LRHPYQUsksynNV83W/sVMAPGkvTxjM/YNf2rF1 0NGRy0ziP37xcLGAM3ZkbpQ= X-Google-Smtp-Source: ABdhPJz+5joJ7I4Seo3Ebr8vtIviOmthgO16WXP1vN5/rD94n8BkNhbI04od638o9PXUrdLOXKRxXw== X-Received: by 2002:a05:6402:190d:: with SMTP id e13mr28068962edz.38.1643760255449; Tue, 01 Feb 2022 16:04:15 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:15 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 05/16] net: dsa: tag_qca: enable promisc_on_master flag Date: Wed, 2 Feb 2022 01:03:24 +0100 Message-Id: <20220202000335.19296-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Ethernet MDIO packets are non-standard and DSA master expects the first 6 octets to be the MAC DA. To address these kind of packet, enable promisc_on_master flag for the tagger. Signed-off-by: Ansuel Smith Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- net/dsa/tag_qca.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c index 34e565e00ece..f8df49d5956f 100644 --- a/net/dsa/tag_qca.c +++ b/net/dsa/tag_qca.c @@ -68,6 +68,7 @@ static const struct dsa_device_ops qca_netdev_ops =3D { .xmit =3D qca_tag_xmit, .rcv =3D qca_tag_rcv, .needed_headroom =3D QCA_HDR_LEN, + .promisc_on_master =3D true, }; =20 MODULE_LICENSE("GPL"); --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65A9EC433FE for ; Wed, 2 Feb 2022 00:04:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243171AbiBBAEb (ORCPT ); Tue, 1 Feb 2022 19:04:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243145AbiBBAEZ (ORCPT ); Tue, 1 Feb 2022 19:04:25 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73A1EC06174A; Tue, 1 Feb 2022 16:04:19 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id m11so38002726edi.13; Tue, 01 Feb 2022 16:04:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NWpirHr7xz0axhTCxQ8W5MwmXAc22jCIlKyLJIrm6Hc=; b=MMukD2AevWbDF/UazU0MletjOoghfvT0Y3xour8aGWT5wtxrvPL82JRSYT1GR4GD3z zCN+8QWGMA4LG12v1SsZYj8IJ1GhHCZ25KPFwtmcFFT4M9M63wo30NU2PiZ0XtKi+uX3 uRw2+cQdDxNpQskqB6N6xFJiJ6D8o/u2xVFq/Ve2nKMcCeFPY4LBYauZN2eeuJldQ/LV zG8FR6exCe/MjmH818KcETsbcqr0RwvmanLoTMBfYwgc9sSUC7qrSVyxDb/5kFWi0qrv 09b6+72GXDR+zBYju9wjq8+mLLn+IP6TLP2+42G1nPTBntc1aGJiXMivn2O7nBY+lyZz TlqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NWpirHr7xz0axhTCxQ8W5MwmXAc22jCIlKyLJIrm6Hc=; b=Vpi0SjQsC5e+nljWwFN8+w465vlAxRz8wXArOwPOPUJsTHhdtNdWgYZlhXm7FZLO98 7SCQTjM5fFrfGaNqc3Ebd+c+gnl5neoxnmGidIHOS0sFGUZ2cL34Rk6AdwDBErpwzC62 SJN7GFjy5SgUAGv4e6RZlrAGvWlPFoz9/GyO53Wow202JKJlbiYTApYnxPMCmniHkXnG ecleUtMq8avEXTgp+2UxtvxNJqwdyhwx47WZXJwHgeUxucxVKK1+bfF4kwAIPYVnflKO ikGm2Zar6L5sJlUF6O62l4M67hxbhTISDWMc2fFpY33ima2J2X4lyCspsUYUBYimxM4k 01jA== X-Gm-Message-State: AOAM532O9X4GcX3XBEfCdb61qsrvn2aLQYygfRT6qgTmpctk/BpOEWou Q0lb/JnQj05yrRDZP4VXKWg= X-Google-Smtp-Source: ABdhPJzLDZjxsK2m0Xr00ADA6dxedIo5gF1460U1oZk/GzQmFgD/EqlysQiutSb7yZvOsDjOdYLNtw== X-Received: by 2002:aa7:d856:: with SMTP id f22mr27670355eds.324.1643760257819; Tue, 01 Feb 2022 16:04:17 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:17 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 06/16] net: dsa: tag_qca: add define for handling mgmt Ethernet packet Date: Wed, 2 Feb 2022 01:03:25 +0100 Message-Id: <20220202000335.19296-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add all the required define to prepare support for mgmt read/write in Ethernet packet. Any packet of this type has to be dropped as the only use of these special packet is receive ack for an mgmt write request or receive data for an mgmt read request. A struct is used that emulates the Ethernet header but is used for a different purpose. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- include/linux/dsa/tag_qca.h | 44 +++++++++++++++++++++++++++++++++++++ net/dsa/tag_qca.c | 15 ++++++++++--- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/include/linux/dsa/tag_qca.h b/include/linux/dsa/tag_qca.h index c02d2d39ff4a..f366422ab7a0 100644 --- a/include/linux/dsa/tag_qca.h +++ b/include/linux/dsa/tag_qca.h @@ -12,10 +12,54 @@ #define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3) #define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0) =20 +/* Packet type for recv */ +#define QCA_HDR_RECV_TYPE_NORMAL 0x0 +#define QCA_HDR_RECV_TYPE_MIB 0x1 +#define QCA_HDR_RECV_TYPE_RW_REG_ACK 0x2 + #define QCA_HDR_XMIT_VERSION GENMASK(15, 14) #define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11) #define QCA_HDR_XMIT_CONTROL GENMASK(10, 8) #define QCA_HDR_XMIT_FROM_CPU BIT(7) #define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0) =20 +/* Packet type for xmit */ +#define QCA_HDR_XMIT_TYPE_NORMAL 0x0 +#define QCA_HDR_XMIT_TYPE_RW_REG 0x1 + +/* Check code for a valid mgmt packet. Switch will ignore the packet + * with this wrong. + */ +#define QCA_HDR_MGMT_CHECK_CODE_VAL 0x5 + +/* Specific define for in-band MDIO read/write with Ethernet packet */ +#define QCA_HDR_MGMT_SEQ_LEN 4 /* 4 byte for the seq */ +#define QCA_HDR_MGMT_COMMAND_LEN 4 /* 4 byte for the command */ +#define QCA_HDR_MGMT_DATA1_LEN 4 /* First 4 byte for the mdio data */ +#define QCA_HDR_MGMT_HEADER_LEN (QCA_HDR_MGMT_SEQ_LEN + \ + QCA_HDR_MGMT_COMMAND_LEN + \ + QCA_HDR_MGMT_DATA1_LEN) + +#define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */ +#define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet p= acket */ + +#define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \ + QCA_HDR_LEN + \ + QCA_HDR_MGMT_DATA2_LEN + \ + QCA_HDR_MGMT_PADDING_LEN) + +#define QCA_HDR_MGMT_SEQ_NUM GENMASK(31, 0) /* 63, 32 */ +#define QCA_HDR_MGMT_CHECK_CODE GENMASK(31, 29) /* 31, 29 */ +#define QCA_HDR_MGMT_CMD BIT(28) /* 28 */ +#define QCA_HDR_MGMT_LENGTH GENMASK(23, 20) /* 23, 20 */ +#define QCA_HDR_MGMT_ADDR GENMASK(18, 0) /* 18, 0 */ + +/* Special struct emulating a Ethernet header */ +struct qca_mgmt_ethhdr { + u32 command; /* command bit 31:0 */ + u32 seq; /* seq 63:32 */ + u32 mdio_data; /* first 4byte mdio */ + __be16 hdr; /* qca hdr */ +} __packed; + #endif /* __TAG_QCA_H */ diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c index f8df49d5956f..f17ed5be20c2 100644 --- a/net/dsa/tag_qca.c +++ b/net/dsa/tag_qca.c @@ -32,10 +32,12 @@ static struct sk_buff *qca_tag_xmit(struct sk_buff *skb= , struct net_device *dev) =20 static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, struct net_device = *dev) { - u8 ver; - u16 hdr; - int port; + u8 ver, pk_type; __be16 *phdr; + int port; + u16 hdr; + + BUILD_BUG_ON(sizeof(struct qca_mgmt_ethhdr) !=3D QCA_HDR_MGMT_HEADER_LEN = + QCA_HDR_LEN); =20 if (unlikely(!pskb_may_pull(skb, QCA_HDR_LEN))) return NULL; @@ -48,6 +50,13 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, = struct net_device *dev) if (unlikely(ver !=3D QCA_HDR_VERSION)) return NULL; =20 + /* Get pk type */ + pk_type =3D FIELD_GET(QCA_HDR_RECV_TYPE, hdr); + + /* Ethernet MDIO read/write packet */ + if (pk_type =3D=3D QCA_HDR_RECV_TYPE_RW_REG_ACK) + return NULL; + /* Remove QCA tag and recalculate checksum */ skb_pull_rcsum(skb, QCA_HDR_LEN); dsa_strip_etype_header(skb, QCA_HDR_LEN); --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 536B4C433EF for ; Wed, 2 Feb 2022 00:04:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243149AbiBBAEd (ORCPT ); Tue, 1 Feb 2022 19:04:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243089AbiBBAEZ (ORCPT ); Tue, 1 Feb 2022 19:04:25 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68899C061756; Tue, 1 Feb 2022 16:04:21 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id l5so37834372edv.3; Tue, 01 Feb 2022 16:04:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GkEFXtqNK8+fHp0XOHOlq+83wcTYuBrFojoKBiNgljc=; b=SyLHnPSQaH1Uz0tuPTnlFx/75PKG8GyE1B9ZfSIN+1Y5P5fgMSTVsx6CBbBltJaJU8 DyVRkzJsIXSCEgyRcgv2u0cfCuEHejHqL4QNkuy/y4FRKPe+Xb5nGh9eq+lgkMd8aht3 QQicN+stogfOZ8io4IUV+8FusMG8egXixRj+G3wFS0geu9YmS5lRzIe4q5HEAw2pKEZj ZA6zt6TQd50nblP9qcwT/7DoHoh+w9/9B6A2jIrGMgeHY67KpTj/G8WyVlyh7ueDDHD5 2n7VY5scj25Gn2itRtsyrl2GATdfzgk8l39blBURPOvL9htc/WL+3iXJt1UXVst3TyEr rfYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GkEFXtqNK8+fHp0XOHOlq+83wcTYuBrFojoKBiNgljc=; b=6fCRJHhWa9TjLRhBOZu9CbGf3Zcul7ZgHZT1d3TfsTUF0/ww/o9tNtSGXxzbHxjllS ZiB+n0okPfWHA0kDjSO2pQCRJmgWTc05AhdpMDF5GMudKawnxUnTn7cWrnT9aPFbtvIs iNCuqn9SV5iROVrhzzwfz11rUUJPpPWG1FRdYcf0B0Rte2dJx9uK7ZVc10U8rRXs/Ets GHuJMLXu9ghoZkTZ4ndh+DvUQidrWY4E9GiwERNTmWb0K9ljEvTSXYN5PBeiLe8cvcLo uhg9q5IAkOSYNzd8dJ38/LOxVCkVivAY4bnxnbqltp2mmyB+UmRKcwvey7mcPlNbrOkg zBCg== X-Gm-Message-State: AOAM533v8pfccZrbzoH8tiEMH1vALQRcm7COUE3GwT17HDaysUiNjnaN VD5tumpfYoqQ2EH+cSlOGzMYwHKR2IY= X-Google-Smtp-Source: ABdhPJzxYXkXwZ3v8yi6cz9qrfZfa7kqZiOBsEaON1o5Yr2Skt3o4b0jUfdtkgjodWZ9t8DfvgPc3A== X-Received: by 2002:a05:6402:50cd:: with SMTP id h13mr21890321edb.256.1643760259929; Tue, 01 Feb 2022 16:04:19 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:19 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 07/16] net: dsa: tag_qca: add define for handling MIB packet Date: Wed, 2 Feb 2022 01:03:26 +0100 Message-Id: <20220202000335.19296-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add struct to correctly parse a mib Ethernet packet. Signed-off-by: Ansuel Smith --- include/linux/dsa/tag_qca.h | 10 ++++++++++ net/dsa/tag_qca.c | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/include/linux/dsa/tag_qca.h b/include/linux/dsa/tag_qca.h index f366422ab7a0..1fff57f2937b 100644 --- a/include/linux/dsa/tag_qca.h +++ b/include/linux/dsa/tag_qca.h @@ -62,4 +62,14 @@ struct qca_mgmt_ethhdr { __be16 hdr; /* qca hdr */ } __packed; =20 +enum mdio_cmd { + MDIO_WRITE =3D 0x0, + MDIO_READ +}; + +struct mib_ethhdr { + u32 data[3]; /* first 3 mib counter */ + __be16 hdr; /* qca hdr */ +} __packed; + #endif /* __TAG_QCA_H */ diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c index f17ed5be20c2..be792cf687d9 100644 --- a/net/dsa/tag_qca.c +++ b/net/dsa/tag_qca.c @@ -57,6 +57,10 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, = struct net_device *dev) if (pk_type =3D=3D QCA_HDR_RECV_TYPE_RW_REG_ACK) return NULL; =20 + /* Ethernet MIB counter packet */ + if (pk_type =3D=3D QCA_HDR_RECV_TYPE_MIB) + return NULL; + /* Remove QCA tag and recalculate checksum */ skb_pull_rcsum(skb, QCA_HDR_LEN); dsa_strip_etype_header(skb, QCA_HDR_LEN); --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8EA7C433F5 for ; Wed, 2 Feb 2022 00:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243288AbiBBAEs (ORCPT ); Tue, 1 Feb 2022 19:04:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243150AbiBBAEZ (ORCPT ); Tue, 1 Feb 2022 19:04:25 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EEA2C061757; Tue, 1 Feb 2022 16:04:23 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id s13so59557955ejy.3; Tue, 01 Feb 2022 16:04:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y34PhNDVNLF/FkWy9gLL8vjlqns7WhueetcWJw0qPmk=; b=fVXZbpiqImdaRirT99KyibyrE1tur46RvpUZw19yR2XDWsJ5tjrZLwmjSqPiBmejd3 jWlCNwqaUXI+VhuxYQRYYqah8HBMa1eTej3L1u2jiEfqpzfFcZhqDoRAQDu1fn2xFQ/f ssxATPVJgRv3GFwrAVYkb2pzZ0Yu97bwRImpnxqaAn994yV9+/yPPD97TbBcUSZU6wH1 OVnILivu7ICoiBZyZ2QLjmBbWzqP7gyjoaERF/2w3MRX5Aup9fUPN+jK6IwfjxTEoLyo bShK+duqh9/0ygiU2cgJBueeVPghBMRP+rqxHJC77i+kB1DxAAvYElsopaCRQUYEc7CD cEoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y34PhNDVNLF/FkWy9gLL8vjlqns7WhueetcWJw0qPmk=; b=439OPODXdpjP1ai9YqgnKC7Ur66NlOY+aTzgTW9A1iZB34StXG5NctuaA2TB//ZC9O fkj0OWAJNKj4VXTLNO80lKmOJO4zU1uWkrg8xgciLZW+IbjIo2piMhgwpFcEMbEaeVZ8 Huteh9ADcRCG2tl+xY2xfP7ZgX/sG2wBFW2Lwq8bzVUaEm+R+AxAGT28YRpxWYK+J+et WGGfQMtflLJo2anUK4UbCDd5sUEGHrF85h1uha6HO2oIK0j9K0Ho7yN4NeMfluXnfUPA k8enFadtrl/jNrWH+CESlFmxra7MjKct4vBu6iq8TPsOMe74+HcUUR52X/h2RAxl+xCl mYhQ== X-Gm-Message-State: AOAM533NX4t6XuQ60pnFS+Q3xeiPLMv8t/mNAn8wWJlewi4BtglF2Jvr EJ+NfgjD3V2nofmHWhqbA9hEVSEQQlU= X-Google-Smtp-Source: ABdhPJwVfed6fk0AW28HEsi2+9jf29iazx7Upxq6MAvhwqyyG0F8D1vOEXNiv1mxbw91a4pXrPaayw== X-Received: by 2002:a17:907:9491:: with SMTP id dm17mr22547068ejc.47.1643760261805; Tue, 01 Feb 2022 16:04:21 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:21 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 08/16] net: dsa: tag_qca: add support for handling mgmt and MIB Ethernet packet Date: Wed, 2 Feb 2022 01:03:27 +0100 Message-Id: <20220202000335.19296-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add connect/disconnect helper to assign private struct to the DSA switch. Add support for Ethernet mgmt and MIB if the DSA driver provide an handler to correctly parse and elaborate the data. Signed-off-by: Ansuel Smith Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- include/linux/dsa/tag_qca.h | 7 +++++++ net/dsa/tag_qca.c | 39 ++++++++++++++++++++++++++++++++++--- 2 files changed, 43 insertions(+), 3 deletions(-) diff --git a/include/linux/dsa/tag_qca.h b/include/linux/dsa/tag_qca.h index 1fff57f2937b..4359fb0221cf 100644 --- a/include/linux/dsa/tag_qca.h +++ b/include/linux/dsa/tag_qca.h @@ -72,4 +72,11 @@ struct mib_ethhdr { __be16 hdr; /* qca hdr */ } __packed; =20 +struct qca_tagger_data { + void (*rw_reg_ack_handler)(struct dsa_switch *ds, + struct sk_buff *skb); + void (*mib_autocast_handler)(struct dsa_switch *ds, + struct sk_buff *skb); +}; + #endif /* __TAG_QCA_H */ diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c index be792cf687d9..57d2e00f1e5d 100644 --- a/net/dsa/tag_qca.c +++ b/net/dsa/tag_qca.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include =20 #include "dsa_priv.h" @@ -32,6 +33,9 @@ static struct sk_buff *qca_tag_xmit(struct sk_buff *skb, = struct net_device *dev) =20 static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, struct net_device = *dev) { + struct qca_tagger_data *tagger_data; + struct dsa_port *dp =3D dev->dsa_ptr; + struct dsa_switch *ds =3D dp->ds; u8 ver, pk_type; __be16 *phdr; int port; @@ -39,6 +43,8 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, s= truct net_device *dev) =20 BUILD_BUG_ON(sizeof(struct qca_mgmt_ethhdr) !=3D QCA_HDR_MGMT_HEADER_LEN = + QCA_HDR_LEN); =20 + tagger_data =3D ds->tagger_data; + if (unlikely(!pskb_may_pull(skb, QCA_HDR_LEN))) return NULL; =20 @@ -53,13 +59,19 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb,= struct net_device *dev) /* Get pk type */ pk_type =3D FIELD_GET(QCA_HDR_RECV_TYPE, hdr); =20 - /* Ethernet MDIO read/write packet */ - if (pk_type =3D=3D QCA_HDR_RECV_TYPE_RW_REG_ACK) + /* Ethernet mgmt read/write packet */ + if (pk_type =3D=3D QCA_HDR_RECV_TYPE_RW_REG_ACK) { + if (likely(tagger_data->rw_reg_ack_handler)) + tagger_data->rw_reg_ack_handler(ds, skb); return NULL; + } =20 /* Ethernet MIB counter packet */ - if (pk_type =3D=3D QCA_HDR_RECV_TYPE_MIB) + if (pk_type =3D=3D QCA_HDR_RECV_TYPE_MIB) { + if (likely(tagger_data->mib_autocast_handler)) + tagger_data->mib_autocast_handler(ds, skb); return NULL; + } =20 /* Remove QCA tag and recalculate checksum */ skb_pull_rcsum(skb, QCA_HDR_LEN); @@ -75,9 +87,30 @@ static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, = struct net_device *dev) return skb; } =20 +static int qca_tag_connect(struct dsa_switch *ds) +{ + struct qca_tagger_data *tagger_data; + + tagger_data =3D kzalloc(sizeof(*tagger_data), GFP_KERNEL); + if (!tagger_data) + return -ENOMEM; + + ds->tagger_data =3D tagger_data; + + return 0; +} + +static void qca_tag_disconnect(struct dsa_switch *ds) +{ + kfree(ds->tagger_data); + ds->tagger_data =3D NULL; +} + static const struct dsa_device_ops qca_netdev_ops =3D { .name =3D "qca", .proto =3D DSA_TAG_PROTO_QCA, + .connect =3D qca_tag_connect, + .disconnect =3D qca_tag_disconnect, .xmit =3D qca_tag_xmit, .rcv =3D qca_tag_rcv, .needed_headroom =3D QCA_HDR_LEN, --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 172EEC4332F for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:23 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 09/16] net: dsa: qca8k: add tracking state of master port Date: Wed, 2 Feb 2022 01:03:28 +0100 Message-Id: <20220202000335.19296-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MDIO/MIB Ethernet require the master port and the tagger availabale to correctly work. Use the new api master_state_change to track when master is operational or not and set a bool in qca8k_priv. We cache the first cached master available and we check if other cpu port are operational when the cached one goes down. This cached master will later be used by mdio read/write and mib request to correctly use the working function. qca8k implementation for MDIO/MIB Ethernet is bad. CPU port0 is the only one that answers with the ack packet or sends MIB Ethernet packets. For this reason the master_state_change ignore CPU port6 and only checks CPU port0 if it's operational and enables this mode. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 15 +++++++++++++++ drivers/net/dsa/qca8k.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 039694518788..ec062b9a918d 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -2383,6 +2383,20 @@ qca8k_port_lag_leave(struct dsa_switch *ds, int port, return qca8k_lag_refresh_portmap(ds, port, lag, true); } =20 +static void +qca8k_master_change(struct dsa_switch *ds, const struct net_device *master, + bool operational) +{ + struct dsa_port *dp =3D master->dsa_ptr; + struct qca8k_priv *priv =3D ds->priv; + + /* Ethernet MIB/MDIO is only supported for CPU port 0 */ + if (dp->index !=3D 0) + return; + + priv->mgmt_master =3D operational ? (struct net_device *)master : NULL; +} + static const struct dsa_switch_ops qca8k_switch_ops =3D { .get_tag_protocol =3D qca8k_get_tag_protocol, .setup =3D qca8k_setup, @@ -2418,6 +2432,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = =3D { .get_phy_flags =3D qca8k_get_phy_flags, .port_lag_join =3D qca8k_port_lag_join, .port_lag_leave =3D qca8k_port_lag_leave, + .master_state_change =3D qca8k_master_change, }; =20 static int qca8k_read_switch_id(struct qca8k_priv *priv) diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index ab4a417b25a9..b81aad98a116 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -353,6 +353,7 @@ struct qca8k_priv { struct dsa_switch_ops ops; struct gpio_desc *reset_gpio; unsigned int port_mtu[QCA8K_NUM_PORTS]; + struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is availabl= e */ }; =20 struct qca8k_mib_desc { --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90410C433EF for ; Wed, 2 Feb 2022 00:04:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243223AbiBBAEl (ORCPT ); Tue, 1 Feb 2022 19:04:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243148AbiBBAE1 (ORCPT ); Tue, 1 Feb 2022 19:04:27 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 179EFC06173B; Tue, 1 Feb 2022 16:04:27 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id w25so37115068edt.7; Tue, 01 Feb 2022 16:04:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6Zju0Qjh7jitXlHsu4Hx1ODeu32wY6zBMHzs4Hw62Eo=; b=jr861tBbsoPe2ky8eTVGThc6KdqF4L/MhD8NMHFxyGo1Gj8YsYAvmFEfeWll+Akp48 am1O/hPatE2doyy5iABEutQVwOXuGiXIxEarMHKkDf55diKjo7ykauwDvFV4YODe8Lt6 9+SLZ0tdCeU8sL3eLQgFFbPOMzzMfnr9m4gzDzAQxgUdOjYXM9nZi5Fnwe2Vls5VxU4k cccmBm+jFljCHDnnVXfF+cbyO7sfJv+qURi5Esq2ELuyl94EEg0F7eRaB8J5OO3jN1Cz NEXjYvKFjGLTOlvwdAy27M67miySqHkKH4fAPBJoVrg3O9TZZctAVXy57aby1987RRRi WflA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Zju0Qjh7jitXlHsu4Hx1ODeu32wY6zBMHzs4Hw62Eo=; b=kJZHGmcwnIRJCU2451kE0Nrm2nvraLp8Au+kLzz26GBLIdGvkAzOfQ/Z69xZdHSpmX sPIokS6ryCmj8ds9JaynHfzR7dtgvI67cF9aERc9VBwY3SAb4p9THDsjDmck1mcEdhwg iMztXOY2z2EADTjLjXXHgk/268XwO3MW2rgfAD/5wCg9BZ9RNh0PFNuLyENRPN2kkhPk 3sREci48KsnLlxO+mvS71336cHF7ySwKkmF4gZlLVq4wsn0kgYVrCGGZYOTlXqJTYt8H zvt18lo5QfWloyQdvUO497bSt7fvpkpmqvGYsGp+Sgh6hV+dJwk1giEpwMturY6R1uHs Rghg== X-Gm-Message-State: AOAM530wGdoVynjBjXlmvry3sBpiDah7G/0amUNRSrhv9OgHZZBpZill 4M86l4wLxkyvhWphEkgodZ0= X-Google-Smtp-Source: ABdhPJxpcOjPRHmqEDUjcrfYrApsw6+4EZV3gDQY0/dJ7rzazvLurJAOVQLbHz4t4WUwF6v+VcaPRw== X-Received: by 2002:aa7:cdc5:: with SMTP id h5mr27811834edw.293.1643760265521; Tue, 01 Feb 2022 16:04:25 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:25 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 10/16] net: dsa: qca8k: add support for mgmt read/write in Ethernet packet Date: Wed, 2 Feb 2022 01:03:29 +0100 Message-Id: <20220202000335.19296-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add qca8k side support for mgmt read/write in Ethernet packet. qca8k supports some specially crafted Ethernet packet that can be used for mgmt read/write instead of the legacy method uart/internal mdio. This add support for the qca8k side to craft the packet and enqueue it. Each port and the qca8k_priv have a special struct to put data in it. The completion API is used to wait for the packet to be received back with the requested data. The various steps are: 1. Craft the special packet with the qca hdr set to mgmt read/write mode. 2. Set the lock in the dedicated mgmt struct. 3. Increment the seq number and set it in the mgmt pkt 4. Reinit the completion. 5. Enqueue the packet. 6. Wait the packet to be received. 7. Use the data set by the tagger to complete the mdio operation. If the completion timeouts or the ack value is not true, the legacy mdio way is used. It has to be considered that in the initial setup mdio is still used and mdio is still used until DSA is ready to accept and tag packet. tag_proto_connect() is used to fill the required handler for the tagger to correctly parse and elaborate the special Ethernet mdio packet. Locking is added to qca8k_master_change() to make sure no mgmt Ethernet are in progress. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 225 ++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 13 +++ 2 files changed, 238 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index ec062b9a918d..e3a215f04559 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include "qca8k.h" =20 @@ -170,6 +171,194 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask,= u32 write_val) return regmap_update_bits(priv->regmap, reg, mask, write_val); } =20 +static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff= *skb) +{ + struct qca8k_mgmt_eth_data *mgmt_eth_data; + struct qca8k_priv *priv =3D ds->priv; + struct qca_mgmt_ethhdr *mgmt_ethhdr; + u8 len, cmd; + + mgmt_ethhdr =3D (struct qca_mgmt_ethhdr *)skb_mac_header(skb); + mgmt_eth_data =3D &priv->mgmt_eth_data; + + cmd =3D FIELD_GET(QCA_HDR_MGMT_CMD, mgmt_ethhdr->command); + len =3D FIELD_GET(QCA_HDR_MGMT_LENGTH, mgmt_ethhdr->command); + + /* Make sure the seq match the requested packet */ + if (mgmt_ethhdr->seq =3D=3D mgmt_eth_data->seq) + mgmt_eth_data->ack =3D true; + + if (cmd =3D=3D MDIO_READ) { + mgmt_eth_data->data[0] =3D mgmt_ethhdr->mdio_data; + + /* Get the rest of the 12 byte of data */ + if (len > QCA_HDR_MGMT_DATA1_LEN) + memcpy(mgmt_eth_data->data + 1, skb->data, + QCA_HDR_MGMT_DATA2_LEN); + } + + complete(&mgmt_eth_data->rw_done); +} + +static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg,= u32 *val, + int priority) +{ + struct qca_mgmt_ethhdr *mgmt_ethhdr; + struct sk_buff *skb; + u16 hdr; + + skb =3D dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN); + if (!skb) + return NULL; + + skb_reset_mac_header(skb); + skb_set_network_header(skb, skb->len); + + mgmt_ethhdr =3D skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN); + + hdr =3D FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION); + hdr |=3D FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority); + hdr |=3D QCA_HDR_XMIT_FROM_CPU; + hdr |=3D FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0)); + hdr |=3D FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG); + + mgmt_ethhdr->command =3D FIELD_PREP(QCA_HDR_MGMT_ADDR, reg); + mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_LENGTH, 4); + mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_CMD, cmd); + mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE, + QCA_HDR_MGMT_CHECK_CODE_VAL); + + if (cmd =3D=3D MDIO_WRITE) + mgmt_ethhdr->mdio_data =3D *val; + + mgmt_ethhdr->hdr =3D htons(hdr); + + skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN); + + return skb; +} + +static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_nu= m) +{ + struct qca_mgmt_ethhdr *mgmt_ethhdr; + + mgmt_ethhdr =3D (struct qca_mgmt_ethhdr *)skb->data; + mgmt_ethhdr->seq =3D FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num); +} + +static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val) +{ + struct qca8k_mgmt_eth_data *mgmt_eth_data =3D &priv->mgmt_eth_data; + struct sk_buff *skb; + bool ack; + int ret; + + skb =3D qca8k_alloc_mdio_header(MDIO_READ, reg, NULL, + QCA8K_ETHERNET_MDIO_PRIORITY); + if (!skb) + return -ENOMEM; + + mutex_lock(&mgmt_eth_data->mutex); + + /* Check mgmt_master if is operational */ + if (!priv->mgmt_master) { + kfree_skb(skb); + mutex_unlock(&mgmt_eth_data->mutex); + return -EINVAL; + } + + skb->dev =3D priv->mgmt_master; + + reinit_completion(&mgmt_eth_data->rw_done); + + /* Increment seq_num and set it in the mdio pkt */ + mgmt_eth_data->seq++; + qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); + mgmt_eth_data->ack =3D false; + + dev_queue_xmit(skb); + + ret =3D wait_for_completion_timeout(&mgmt_eth_data->rw_done, + msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); + + *val =3D mgmt_eth_data->data[0]; + ack =3D mgmt_eth_data->ack; + + mutex_unlock(&mgmt_eth_data->mutex); + + if (ret <=3D 0) + return -ETIMEDOUT; + + if (!ack) + return -EINVAL; + + return 0; +} + +static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 val) +{ + struct qca8k_mgmt_eth_data *mgmt_eth_data =3D &priv->mgmt_eth_data; + struct sk_buff *skb; + bool ack; + int ret; + + skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, reg, &val, + QCA8K_ETHERNET_MDIO_PRIORITY); + if (!skb) + return -ENOMEM; + + mutex_lock(&mgmt_eth_data->mutex); + + /* Check mgmt_master if is operational */ + if (!priv->mgmt_master) { + kfree_skb(skb); + mutex_unlock(&mgmt_eth_data->mutex); + return -EINVAL; + } + + skb->dev =3D priv->mgmt_master; + + reinit_completion(&mgmt_eth_data->rw_done); + + /* Increment seq_num and set it in the mdio pkt */ + mgmt_eth_data->seq++; + qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); + mgmt_eth_data->ack =3D false; + + dev_queue_xmit(skb); + + ret =3D wait_for_completion_timeout(&mgmt_eth_data->rw_done, + msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); + + ack =3D mgmt_eth_data->ack; + + mutex_unlock(&mgmt_eth_data->mutex); + + if (ret <=3D 0) + return -ETIMEDOUT; + + if (!ack) + return -EINVAL; + + return 0; +} + +static int +qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u= 32 write_val) +{ + u32 val =3D 0; + int ret; + + ret =3D qca8k_read_eth(priv, reg, &val); + if (ret) + return ret; + + val &=3D ~mask; + val |=3D write_val; + + return qca8k_write_eth(priv, reg, val); +} + static int qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) { @@ -178,6 +367,9 @@ qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *va= l) u16 r1, r2, page; int ret; =20 + if (!qca8k_read_eth(priv, reg, val)) + return 0; + qca8k_split_addr(reg, &r1, &r2, &page); =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); @@ -201,6 +393,9 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t va= l) u16 r1, r2, page; int ret; =20 + if (!qca8k_write_eth(priv, reg, val)) + return 0; + qca8k_split_addr(reg, &r1, &r2, &page); =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); @@ -225,6 +420,9 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint3= 2_t mask, uint32_t write_ u32 val; int ret; =20 + if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val)) + return 0; + qca8k_split_addr(reg, &r1, &r2, &page); =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); @@ -2394,7 +2592,30 @@ qca8k_master_change(struct dsa_switch *ds, const str= uct net_device *master, if (dp->index !=3D 0) return; =20 + mutex_lock(&priv->mgmt_eth_data.mutex); + priv->mgmt_master =3D operational ? (struct net_device *)master : NULL; + + mutex_unlock(&priv->mgmt_eth_data.mutex); +} + +static int qca8k_connect_tag_protocol(struct dsa_switch *ds, + enum dsa_tag_protocol proto) +{ + struct qca_tagger_data *tagger_data; + + switch (proto) { + case DSA_TAG_PROTO_QCA: + tagger_data =3D ds->tagger_data; + + tagger_data->rw_reg_ack_handler =3D qca8k_rw_reg_ack_handler; + + break; + default: + return -EOPNOTSUPP; + } + + return 0; } =20 static const struct dsa_switch_ops qca8k_switch_ops =3D { @@ -2433,6 +2654,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = =3D { .port_lag_join =3D qca8k_port_lag_join, .port_lag_leave =3D qca8k_port_lag_leave, .master_state_change =3D qca8k_master_change, + .connect_tag_protocol =3D qca8k_connect_tag_protocol, }; =20 static int qca8k_read_switch_id(struct qca8k_priv *priv) @@ -2512,6 +2734,9 @@ qca8k_sw_probe(struct mdio_device *mdiodev) if (!priv->ds) return -ENOMEM; =20 + mutex_init(&priv->mgmt_eth_data.mutex); + init_completion(&priv->mgmt_eth_data.rw_done); + priv->ds->dev =3D &mdiodev->dev; priv->ds->num_ports =3D QCA8K_NUM_PORTS; priv->ds->priv =3D priv; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index b81aad98a116..75c28689a652 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -11,6 +11,10 @@ #include #include #include +#include + +#define QCA8K_ETHERNET_MDIO_PRIORITY 7 +#define QCA8K_ETHERNET_TIMEOUT 100 =20 #define QCA8K_NUM_PORTS 7 #define QCA8K_NUM_CPU_PORTS 2 @@ -328,6 +332,14 @@ enum { QCA8K_CPU_PORT6, }; =20 +struct qca8k_mgmt_eth_data { + struct completion rw_done; + struct mutex mutex; /* Enforce one mdio read/write at time */ + bool ack; + u32 seq; + u32 data[4]; +}; + struct qca8k_ports_config { bool sgmii_rx_clk_falling_edge; bool sgmii_tx_clk_falling_edge; @@ -354,6 +366,7 @@ struct qca8k_priv { struct gpio_desc *reset_gpio; unsigned int port_mtu[QCA8K_NUM_PORTS]; struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is availabl= e */ + struct qca8k_mgmt_eth_data mgmt_eth_data; }; =20 struct qca8k_mib_desc { --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 619D7C433EF for ; Wed, 2 Feb 2022 00:04:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243255AbiBBAEp (ORCPT ); Tue, 1 Feb 2022 19:04:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243174AbiBBAE3 (ORCPT ); Tue, 1 Feb 2022 19:04:29 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB5C1C061401; Tue, 1 Feb 2022 16:04:28 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id jx6so59819231ejb.0; Tue, 01 Feb 2022 16:04:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V7BGRkfJBtKAdhh65B65CRfb3wWKV/CszDGsa2iyoYI=; b=Iemqsp6emFNa//j7isMjnPBg4OOfCSh6gWhuQevIsEZE6rtYis5uekSIeRek6ulT/B bpQbmkIHy1BRQTsxMFifmdOTNL+MM8a38DFoMN8L+FwoJoWzZp3EKYkmy2e9xTe+fTvu 81arKEbOd4Zolu3zCDnht3AtVqcN/SViapcXPIXqkIR3x5ccglqeyN47nh62sxddC2g6 /KseezqLo9ezWd6cDzFzDnmhO0QW/1hURBVe9dR+A7q6r9IDpyHoVVfHw7bZP3jnbmoN tj2sXgBZaeUNvbtaHvzcHqptJ6+kKnbM59H+ag5ZHaBqHMYWTzBNfKbNEz289Q4uLB77 mjWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V7BGRkfJBtKAdhh65B65CRfb3wWKV/CszDGsa2iyoYI=; b=N5zISTPyN8YeOR7skoTZfN4sMssbMT4PbEfXY147sFEdDQY+fqFlZSEbhD6NoDbM9r hC2yYc8innvgPAfsNnW0I8jfnjxCs3RKBwV5+iG36fySrMPqvB8Er5PWEN7ePhxXEfJg 8YjIFQlmsSS/LxFL0NhWY2spuNxtOYh8akevypKnvX0FLWx6Hk00KhwWywbfvlgrkwi2 cZxTPblZ5Y0nhmNxuALqVv4IbymI1u2ENmrSSCkqdkfjhYozexrtr9t6KWgjyfOTQAUF weq/aIBqAmPTh9ituaJdqWpYFGRaYFmaQhiUdUFOnxZjwDudaxu5fXqumG8WK2e8dFsw l8bA== X-Gm-Message-State: AOAM531ISFNIBRXYwln/W8aBCbc5C2sChKMwlxORAPoHxQouQjuusyWy /073Z2M/k4TE1HPDxvQ6mvM= X-Google-Smtp-Source: ABdhPJyMbiRhG8TCatUErKsh418uq+F3apd1FeMXgrAQy09PhK9vZdyppNTeT1Vz20sZEvUJ6N1rdA== X-Received: by 2002:a17:907:7412:: with SMTP id gj18mr23641885ejc.381.1643760267359; Tue, 01 Feb 2022 16:04:27 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:27 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 11/16] net: dsa: qca8k: add support for mib autocast in Ethernet packet Date: Wed, 2 Feb 2022 01:03:30 +0100 Message-Id: <20220202000335.19296-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The switch can autocast MIB counter using Ethernet packet. Add support for this and provide a handler for the tagger. The switch will send packet with MIB counter for each port, the switch will use completion API to wait for the correct packet to be received and will complete the task only when each packet is received. Although the handler will drop all the other packet, we still have to consume each MIB packet to complete the request. This is done to prevent mixed data with concurrent ethtool request. connect_tag_protocol() is used to add the handler to the tag_qca tagger, master_state_change() use the MIB lock to make sure no MIB Ethernet is in progress. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 106 +++++++++++++++++++++++++++++++++++++++- drivers/net/dsa/qca8k.h | 17 ++++++- 2 files changed, 121 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index e3a215f04559..199cf4f761c0 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -830,7 +830,10 @@ qca8k_mib_init(struct qca8k_priv *priv) int ret; =20 mutex_lock(&priv->reg_mutex); - ret =3D regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QC= A8K_MIB_BUSY); + ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_MIB, + QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, + FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) | + QCA8K_MIB_BUSY); if (ret) goto exit; =20 @@ -1901,6 +1904,97 @@ qca8k_get_strings(struct dsa_switch *ds, int port, u= 32 stringset, uint8_t *data) ETH_GSTRING_LEN); } =20 +static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_bu= ff *skb) +{ + const struct qca8k_match_data *match_data; + struct qca8k_mib_eth_data *mib_eth_data; + struct qca8k_priv *priv =3D ds->priv; + const struct qca8k_mib_desc *mib; + struct mib_ethhdr *mib_ethhdr; + int i, mib_len, offset =3D 0; + u64 *data; + u8 port; + + mib_ethhdr =3D (struct mib_ethhdr *)skb_mac_header(skb); + mib_eth_data =3D &priv->mib_eth_data; + + /* The switch autocast every port. Ignore other packet and + * parse only the requested one. + */ + port =3D FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr)); + if (port !=3D mib_eth_data->req_port) + goto exit; + + match_data =3D device_get_match_data(priv->dev); + data =3D mib_eth_data->data; + + for (i =3D 0; i < match_data->mib_count; i++) { + mib =3D &ar8327_mib[i]; + + /* First 3 mib are present in the skb head */ + if (i < 3) { + data[i] =3D mib_ethhdr->data[i]; + continue; + } + + mib_len =3D sizeof(uint32_t); + + /* Some mib are 64 bit wide */ + if (mib->size =3D=3D 2) + mib_len =3D sizeof(uint64_t); + + /* Copy the mib value from packet to the */ + memcpy(data + i, skb->data + offset, mib_len); + + /* Set the offset for the next mib */ + offset +=3D mib_len; + } + +exit: + /* Complete on receiving all the mib packet */ + if (refcount_dec_and_test(&mib_eth_data->port_parsed)) + complete(&mib_eth_data->rw_done); +} + +static int +qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data) +{ + struct dsa_port *dp =3D dsa_to_port(ds, port); + struct qca8k_mib_eth_data *mib_eth_data; + struct qca8k_priv *priv =3D ds->priv; + int ret; + + mib_eth_data =3D &priv->mib_eth_data; + + mutex_lock(&mib_eth_data->mutex); + + reinit_completion(&mib_eth_data->rw_done); + + mib_eth_data->req_port =3D dp->index; + mib_eth_data->data =3D data; + refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS); + + mutex_lock(&priv->reg_mutex); + + /* Send mib autocast request */ + ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_MIB, + QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, + FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) | + QCA8K_MIB_BUSY); + + mutex_unlock(&priv->reg_mutex); + + if (ret) + goto exit; + + ret =3D wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNE= T_TIMEOUT); + +exit: + mutex_unlock(&mib_eth_data->mutex); + + return ret; +} + static void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) @@ -1912,6 +2006,10 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int p= ort, u32 hi =3D 0; int ret; =20 + if (priv->mgmt_master && + qca8k_get_ethtool_stats_eth(ds, port, data) > 0) + return; + match_data =3D of_device_get_match_data(priv->dev); =20 for (i =3D 0; i < match_data->mib_count; i++) { @@ -2593,9 +2691,11 @@ qca8k_master_change(struct dsa_switch *ds, const str= uct net_device *master, return; =20 mutex_lock(&priv->mgmt_eth_data.mutex); + mutex_lock(&priv->mib_eth_data.mutex); =20 priv->mgmt_master =3D operational ? (struct net_device *)master : NULL; =20 + mutex_unlock(&priv->mib_eth_data.mutex); mutex_unlock(&priv->mgmt_eth_data.mutex); } =20 @@ -2609,6 +2709,7 @@ static int qca8k_connect_tag_protocol(struct dsa_swit= ch *ds, tagger_data =3D ds->tagger_data; =20 tagger_data->rw_reg_ack_handler =3D qca8k_rw_reg_ack_handler; + tagger_data->mib_autocast_handler =3D qca8k_mib_autocast_handler; =20 break; default: @@ -2737,6 +2838,9 @@ qca8k_sw_probe(struct mdio_device *mdiodev) mutex_init(&priv->mgmt_eth_data.mutex); init_completion(&priv->mgmt_eth_data.rw_done); =20 + mutex_init(&priv->mib_eth_data.mutex); + init_completion(&priv->mib_eth_data.rw_done); + priv->ds->dev =3D &mdiodev->dev; priv->ds->num_ports =3D QCA8K_NUM_PORTS; priv->ds->priv =3D priv; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 75c28689a652..2d7d084db089 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -67,7 +67,7 @@ #define QCA8K_REG_MODULE_EN 0x030 #define QCA8K_MODULE_EN_MIB BIT(0) #define QCA8K_REG_MIB 0x034 -#define QCA8K_MIB_FLUSH BIT(24) +#define QCA8K_MIB_FUNC GENMASK(26, 24) #define QCA8K_MIB_CPU_KEEP BIT(20) #define QCA8K_MIB_BUSY BIT(17) #define QCA8K_MDIO_MASTER_CTRL 0x3c @@ -317,6 +317,12 @@ enum qca8k_vlan_cmd { QCA8K_VLAN_READ =3D 6, }; =20 +enum qca8k_mid_cmd { + QCA8K_MIB_FLUSH =3D 1, + QCA8K_MIB_FLUSH_PORT =3D 2, + QCA8K_MIB_CAST =3D 3, +}; + struct ar8xxx_port_status { int enabled; }; @@ -340,6 +346,14 @@ struct qca8k_mgmt_eth_data { u32 data[4]; }; =20 +struct qca8k_mib_eth_data { + struct completion rw_done; + struct mutex mutex; /* Process one command at time */ + refcount_t port_parsed; /* Counter to track parsed port */ + u8 req_port; + u64 *data; /* pointer to ethtool data */ +}; + struct qca8k_ports_config { bool sgmii_rx_clk_falling_edge; bool sgmii_tx_clk_falling_edge; @@ -367,6 +381,7 @@ struct qca8k_priv { unsigned int port_mtu[QCA8K_NUM_PORTS]; struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is availabl= e */ struct qca8k_mgmt_eth_data mgmt_eth_data; + struct qca8k_mib_eth_data mib_eth_data; }; =20 struct qca8k_mib_desc { --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF81FC433EF for ; Wed, 2 Feb 2022 00:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243247AbiBBAE5 (ORCPT ); Tue, 1 Feb 2022 19:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243175AbiBBAEb (ORCPT ); Tue, 1 Feb 2022 19:04:31 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC7B9C061714; Tue, 1 Feb 2022 16:04:30 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id j2so58642647ejk.6; Tue, 01 Feb 2022 16:04:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZQKNxhvaSbHhD6tI1orgzLCmFBHOnHLtHOZFRqFIlE=; b=OLwpt5kkAhonyM6o0NWpTwCa8Zr3QQjfr/K+O8x51pebBPG7sKPYVeaWgWO7Z5ia96 ptNIfPiS55YLjBvDKIJ/eaYqIidWnUttru0Mu1qR9HkV1V8ymDAx51ThPwGaVfSfdk3G 6eAD5DgWvryGjCJPoggd63+jbtGWJL+RSiuDTVG+kOksTopNDfeWmgpghaUpMzQYFzML Y7zr3cquBRms4asSCMJ73MBxz2XJWFu9NB/zqvjHTCIzI7cL94LHnNRO/I2ZyP3DpSYu v2rG9U66sw1j2DWNukhOiux71D8o9P8yIbhDnZpEsaZ/dHjnVmNiHiG3Y7nelFZPjJAF Z/3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZQKNxhvaSbHhD6tI1orgzLCmFBHOnHLtHOZFRqFIlE=; b=xrUQdCTwpoSHwpvDRi2/KeIs6GsjjVGEIot0g6n2vFIdAK3ImjtMt7J69Xp18FFp7G vMg+AxMNmpMByKCWrR7vk1UnVGUE0XTxBq7Knj3QSSzLhoyDh5NzGmGXaxuSxFH6MaZe r8MTEWCJWFraAaLLz9uXoE6cPX6Zf6b2rUH8Hou5VZ2KVoZ7+IGu0lYQqzvz/9or0xtW T6ImYCLFBR1046jB7qO0GsZNsu3rXwXH7SzAjpHodUjNURCidq4BzJ0M6bF15uDbLY3F fmzF7apNY5YDIvRT70BpoYiO5BTPP5voQMqDy9nXgJAT6ntFe76tacPL6ZbDGQl2pBai 8L2g== X-Gm-Message-State: AOAM530MqtPlmb4r6nJ9vo+16aGX2tfhgIw7hSy1st1ex7UdbS4ntNUF AQplt0/5kGAxsCSRXdBQ4mg= X-Google-Smtp-Source: ABdhPJyhrENXfATOrmAHlQjIe6QecAYUYd+i3GQunyMW2afrrsQJZejvzku2UeCfQxN8z3L0Hjn8pQ== X-Received: by 2002:a17:907:7d8e:: with SMTP id oz14mr14841915ejc.764.1643760269199; Tue, 01 Feb 2022 16:04:29 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:28 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 12/16] net: dsa: qca8k: add support for phy read/write with mgmt Ethernet Date: Wed, 2 Feb 2022 01:03:31 +0100 Message-Id: <20220202000335.19296-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use mgmt Ethernet also for phy read/write if availabale. Use a different seq number to make sure we receive the correct packet. On any error, we fallback to the legacy mdio read/write. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 216 ++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 1 + 2 files changed, 217 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 199cf4f761c0..0ce5b7ca0b7f 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -867,6 +867,199 @@ qca8k_port_set_status(struct qca8k_priv *priv, int po= rt, int enable) regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); } =20 +static int +qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data, + struct sk_buff *read_skb, u32 *val) +{ + struct sk_buff *skb =3D skb_copy(read_skb, GFP_KERNEL); + bool ack; + int ret; + + reinit_completion(&mgmt_eth_data->rw_done); + + /* Increment seq_num and set it in the copy pkt */ + mgmt_eth_data->seq++; + qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); + mgmt_eth_data->ack =3D false; + + dev_queue_xmit(skb); + + ret =3D wait_for_completion_timeout(&mgmt_eth_data->rw_done, + QCA8K_ETHERNET_TIMEOUT); + + ack =3D mgmt_eth_data->ack; + + if (ret <=3D 0) + return -ETIMEDOUT; + + if (!ack) + return -EINVAL; + + *val =3D mgmt_eth_data->data[0]; + + return 0; +} + +static int +qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy, + int regnum, u16 data) +{ + struct sk_buff *write_skb, *clear_skb, *read_skb; + struct qca8k_mgmt_eth_data *mgmt_eth_data; + u32 write_val, clear_val =3D 0, val; + struct net_device *mgmt_master; + int ret, ret1; + bool ack; + + if (regnum >=3D QCA8K_MDIO_MASTER_MAX_REG) + return -EINVAL; + + mgmt_eth_data =3D &priv->mgmt_eth_data; + + write_val =3D QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | + QCA8K_MDIO_MASTER_PHY_ADDR(phy) | + QCA8K_MDIO_MASTER_REG_ADDR(regnum); + + if (read) { + write_val |=3D QCA8K_MDIO_MASTER_READ; + } else { + write_val |=3D QCA8K_MDIO_MASTER_WRITE; + write_val |=3D QCA8K_MDIO_MASTER_DATA(data); + } + + /* Prealloc all the needed skb before the lock */ + write_skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, + &write_val, QCA8K_ETHERNET_PHY_PRIORITY); + if (!write_skb) + return -ENOMEM; + + clear_skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, + &clear_val, QCA8K_ETHERNET_PHY_PRIORITY); + if (!write_skb) { + ret =3D -ENOMEM; + goto err_clear_skb; + } + + read_skb =3D qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, + &clear_val, QCA8K_ETHERNET_PHY_PRIORITY); + if (!write_skb) { + ret =3D -ENOMEM; + goto err_read_skb; + } + + /* Actually start the request: + * 1. Send mdio master packet + * 2. Busy Wait for mdio master command + * 3. Get the data if we are reading + * 4. Reset the mdio master (even with error) + */ + mutex_lock(&mgmt_eth_data->mutex); + + /* Check if mgmt_master is operational */ + mgmt_master =3D priv->mgmt_master; + if (!mgmt_master) { + mutex_unlock(&mgmt_eth_data->mutex); + ret =3D -EINVAL; + goto err_mgmt_master; + } + + read_skb->dev =3D mgmt_master; + clear_skb->dev =3D mgmt_master; + write_skb->dev =3D mgmt_master; + + reinit_completion(&mgmt_eth_data->rw_done); + + /* Increment seq_num and set it in the write pkt */ + mgmt_eth_data->seq++; + qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq); + mgmt_eth_data->ack =3D false; + + dev_queue_xmit(write_skb); + + ret =3D wait_for_completion_timeout(&mgmt_eth_data->rw_done, + QCA8K_ETHERNET_TIMEOUT); + + ack =3D mgmt_eth_data->ack; + + if (ret <=3D 0) { + ret =3D -ETIMEDOUT; + kfree_skb(read_skb); + goto exit; + } + + if (!ack) { + ret =3D -EINVAL; + kfree_skb(read_skb); + goto exit; + } + + ret =3D read_poll_timeout(qca8k_phy_eth_busy_wait, ret1, + !(val & QCA8K_MDIO_MASTER_BUSY), 0, + QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, + mgmt_eth_data, read_skb, &val); + + if (ret < 0 && ret1 < 0) { + ret =3D ret1; + goto exit; + } + + if (read) { + reinit_completion(&mgmt_eth_data->rw_done); + + /* Increment seq_num and set it in the read pkt */ + mgmt_eth_data->seq++; + qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq); + mgmt_eth_data->ack =3D false; + + dev_queue_xmit(read_skb); + + ret =3D wait_for_completion_timeout(&mgmt_eth_data->rw_done, + QCA8K_ETHERNET_TIMEOUT); + + ack =3D mgmt_eth_data->ack; + + if (ret <=3D 0) { + ret =3D -ETIMEDOUT; + goto exit; + } + + if (!ack) { + ret =3D -EINVAL; + goto exit; + } + + ret =3D mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK; + } else { + kfree_skb(read_skb); + } +exit: + reinit_completion(&mgmt_eth_data->rw_done); + + /* Increment seq_num and set it in the clear pkt */ + mgmt_eth_data->seq++; + qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq); + mgmt_eth_data->ack =3D false; + + dev_queue_xmit(clear_skb); + + wait_for_completion_timeout(&mgmt_eth_data->rw_done, + QCA8K_ETHERNET_TIMEOUT); + + mutex_unlock(&mgmt_eth_data->mutex); + + return ret; + + /* Error handling before lock */ +err_mgmt_master: + kfree_skb(read_skb); +err_read_skb: + kfree_skb(clear_skb); +err_clear_skb: + kfree_skb(write_skb); + + return ret; +} + static u32 qca8k_port_to_phy(int port) { @@ -989,6 +1182,12 @@ qca8k_internal_mdio_write(struct mii_bus *slave_bus, = int phy, int regnum, u16 da { struct qca8k_priv *priv =3D slave_bus->priv; struct mii_bus *bus =3D priv->bus; + int ret; + + /* Use mdio Ethernet when available, fallback to legacy one on error */ + ret =3D qca8k_phy_eth_command(priv, false, phy, regnum, data); + if (!ret) + return 0; =20 return qca8k_mdio_write(bus, phy, regnum, data); } @@ -998,6 +1197,12 @@ qca8k_internal_mdio_read(struct mii_bus *slave_bus, i= nt phy, int regnum) { struct qca8k_priv *priv =3D slave_bus->priv; struct mii_bus *bus =3D priv->bus; + int ret; + + /* Use mdio Ethernet when available, fallback to legacy one on error */ + ret =3D qca8k_phy_eth_command(priv, true, phy, regnum, 0); + if (ret >=3D 0) + return ret; =20 return qca8k_mdio_read(bus, phy, regnum); } @@ -1006,6 +1211,7 @@ static int qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data) { struct qca8k_priv *priv =3D ds->priv; + int ret; =20 /* Check if the legacy mapping should be used and the * port is not correctly mapped to the right PHY in the @@ -1014,6 +1220,11 @@ qca8k_phy_write(struct dsa_switch *ds, int port, int= regnum, u16 data) if (priv->legacy_phy_port_mapping) port =3D qca8k_port_to_phy(port) % PHY_MAX_ADDR; =20 + /* Use mdio Ethernet when available, fallback to legacy one on error */ + ret =3D qca8k_phy_eth_command(priv, false, port, regnum, 0); + if (!ret) + return ret; + return qca8k_mdio_write(priv->bus, port, regnum, data); } =20 @@ -1030,6 +1241,11 @@ qca8k_phy_read(struct dsa_switch *ds, int port, int = regnum) if (priv->legacy_phy_port_mapping) port =3D qca8k_port_to_phy(port) % PHY_MAX_ADDR; =20 + /* Use mdio Ethernet when available, fallback to legacy one on error */ + ret =3D qca8k_phy_eth_command(priv, true, port, regnum, 0); + if (ret >=3D 0) + return ret; + ret =3D qca8k_mdio_read(priv->bus, port, regnum); =20 if (ret < 0) diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 2d7d084db089..c6f6abd2108e 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -14,6 +14,7 @@ #include =20 #define QCA8K_ETHERNET_MDIO_PRIORITY 7 +#define QCA8K_ETHERNET_PHY_PRIORITY 6 #define QCA8K_ETHERNET_TIMEOUT 100 =20 #define QCA8K_NUM_PORTS 7 --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DAFEC4332F for ; Wed, 2 Feb 2022 00:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243201AbiBBAFA (ORCPT ); Tue, 1 Feb 2022 19:05:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243105AbiBBAEf (ORCPT ); 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:31 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 13/16] net: dsa: qca8k: move page cache to driver priv Date: Wed, 2 Feb 2022 01:03:32 +0100 Message-Id: <20220202000335.19296-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There can be multiple qca8k switch on the same system. Move the static qca8k_current_page to qca8k_priv and make it specific for each switch. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 42 ++++++++++++++++++++--------------------- drivers/net/dsa/qca8k.h | 9 +++++++++ 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0ce5b7ca0b7f..86d3742b1038 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -75,12 +75,6 @@ static const struct qca8k_mib_desc ar8327_mib[] =3D { MIB_DESC(1, 0xac, "TXUnicast"), }; =20 -/* The 32bit switch registers are accessed indirectly. To achieve this we = need - * to set the page of the register. Track the last page that was set to re= duce - * mdio writes - */ -static u16 qca8k_current_page =3D 0xffff; - static void qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) { @@ -134,11 +128,13 @@ qca8k_mii_write32(struct mii_bus *bus, int phy_id, u3= 2 regnum, u32 val) } =20 static int -qca8k_set_page(struct mii_bus *bus, u16 page) +qca8k_set_page(struct qca8k_priv *priv, u16 page) { + u16 *cached_page =3D &priv->mdio_cache.page; + struct mii_bus *bus =3D priv->bus; int ret; =20 - if (page =3D=3D qca8k_current_page) + if (page =3D=3D *cached_page) return 0; =20 ret =3D bus->write(bus, 0x18, 0, page); @@ -148,7 +144,7 @@ qca8k_set_page(struct mii_bus *bus, u16 page) return ret; } =20 - qca8k_current_page =3D page; + *cached_page =3D page; usleep_range(1000, 2000); return 0; } @@ -374,7 +370,7 @@ qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *va= l) =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); =20 - ret =3D qca8k_set_page(bus, page); + ret =3D qca8k_set_page(priv, page); if (ret < 0) goto exit; =20 @@ -400,7 +396,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t va= l) =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); =20 - ret =3D qca8k_set_page(bus, page); + ret =3D qca8k_set_page(priv, page); if (ret < 0) goto exit; =20 @@ -427,7 +423,7 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint3= 2_t mask, uint32_t write_ =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); =20 - ret =3D qca8k_set_page(bus, page); + ret =3D qca8k_set_page(priv, page); if (ret < 0) goto exit; =20 @@ -1098,8 +1094,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u3= 2 mask) } =20 static int -qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data) +qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data) { + struct mii_bus *bus =3D priv->bus; u16 r1, r2, page; u32 val; int ret; @@ -1116,7 +1113,7 @@ qca8k_mdio_write(struct mii_bus *bus, int phy, int re= gnum, u16 data) =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); =20 - ret =3D qca8k_set_page(bus, page); + ret =3D qca8k_set_page(priv, page); if (ret) goto exit; =20 @@ -1135,8 +1132,9 @@ qca8k_mdio_write(struct mii_bus *bus, int phy, int re= gnum, u16 data) } =20 static int -qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum) +qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum) { + struct mii_bus *bus =3D priv->bus; u16 r1, r2, page; u32 val; int ret; @@ -1152,7 +1150,7 @@ qca8k_mdio_read(struct mii_bus *bus, int phy, int reg= num) =20 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); =20 - ret =3D qca8k_set_page(bus, page); + ret =3D qca8k_set_page(priv, page); if (ret) goto exit; =20 @@ -1181,7 +1179,6 @@ static int qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, = u16 data) { struct qca8k_priv *priv =3D slave_bus->priv; - struct mii_bus *bus =3D priv->bus; int ret; =20 /* Use mdio Ethernet when available, fallback to legacy one on error */ @@ -1189,14 +1186,13 @@ qca8k_internal_mdio_write(struct mii_bus *slave_bus= , int phy, int regnum, u16 da if (!ret) return 0; =20 - return qca8k_mdio_write(bus, phy, regnum, data); + return qca8k_mdio_write(priv, phy, regnum, data); } =20 static int qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum) { struct qca8k_priv *priv =3D slave_bus->priv; - struct mii_bus *bus =3D priv->bus; int ret; =20 /* Use mdio Ethernet when available, fallback to legacy one on error */ @@ -1204,7 +1200,7 @@ qca8k_internal_mdio_read(struct mii_bus *slave_bus, i= nt phy, int regnum) if (ret >=3D 0) return ret; =20 - return qca8k_mdio_read(bus, phy, regnum); + return qca8k_mdio_read(priv, phy, regnum); } =20 static int @@ -1225,7 +1221,7 @@ qca8k_phy_write(struct dsa_switch *ds, int port, int = regnum, u16 data) if (!ret) return ret; =20 - return qca8k_mdio_write(priv->bus, port, regnum, data); + return qca8k_mdio_write(priv, port, regnum, data); } =20 static int @@ -1246,7 +1242,7 @@ qca8k_phy_read(struct dsa_switch *ds, int port, int r= egnum) if (ret >=3D 0) return ret; =20 - ret =3D qca8k_mdio_read(priv->bus, port, regnum); + ret =3D qca8k_mdio_read(priv, port, regnum); =20 if (ret < 0) return 0xffff; @@ -3042,6 +3038,8 @@ qca8k_sw_probe(struct mdio_device *mdiodev) return PTR_ERR(priv->regmap); } =20 + priv->mdio_cache.page =3D 0xffff; + /* Check the detected switch id */ ret =3D qca8k_read_switch_id(priv); if (ret) diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index c6f6abd2108e..57368acae41b 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -363,6 +363,14 @@ struct qca8k_ports_config { u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ }; =20 +struct qca8k_mdio_cache { +/* The 32bit switch registers are accessed indirectly. To achieve this we = need + * to set the page of the register. Track the last page that was set to re= duce + * mdio writes + */ + u16 page; +}; + struct qca8k_priv { u8 switch_id; u8 switch_revision; @@ -383,6 +391,7 @@ struct qca8k_priv { struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is availabl= e */ struct qca8k_mgmt_eth_data mgmt_eth_data; struct qca8k_mib_eth_data mib_eth_data; + struct qca8k_mdio_cache mdio_cache; }; =20 struct qca8k_mib_desc { --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E25FC433F5 for ; Wed, 2 Feb 2022 00:05:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231265AbiBBAE7 (ORCPT ); Tue, 1 Feb 2022 19:04:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243127AbiBBAEf (ORCPT ); Tue, 1 Feb 2022 19:04:35 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0193BC061749; Tue, 1 Feb 2022 16:04:35 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id j2so37663267edj.8; Tue, 01 Feb 2022 16:04:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/sPTO7HXKid+NzRJvJfh3Z+nIffmW3x5BFbdKbsjz+U=; b=Hj9twqOusSBMkgvopcHO49tUa/u2ZqBSJ5gLr9hq+P9C1LKt2tT46h5ozQAQv45GH7 HsRqJOkvliSW+WXvkusgDJLYuczRlpTvD41VzsFy8wqIV6H+ZjvRbGGTVVNYBnoQmVcy rNNJT/ITTfI0QblugYn/maQyXUPceNvD3fkhc5oHN4u5m418oJUJWbfWCdqlE4m/Wn/a Ot1MGdzPENgMb96yHpnROtOMkOqgbyVRzFFDIuFD4cDSmqjJUr5nHeMzPb7vL4CxvWRW qfyMo+NfEbiDWscJE9SsMvtAbZnzagETq6DZ5RBCNGTQ01Yclssc8A01Be63CCwFPDaO qv0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/sPTO7HXKid+NzRJvJfh3Z+nIffmW3x5BFbdKbsjz+U=; b=azVccaRSmEkbgtJ0FUVhPb9q34I9RhQ8DykkZ2bDoT90yAs1XQVjgiyer+9U8BxjdN EENg5ZYX5l0mZ4d8VyGsvNRe7Y4yCCy2OLyIucdOw4SB6JDPfIGT5A9c60DgpV6Xg1ah cisV2ULdz3xQrBUtBokS/h0HRNN/qQWmBk/moKtjKExNfnKIWt1wcM8j5TThB9293eOJ Y6DUbfNXiUiKNOzzz3hOpMg+xhmTgNZFKC3oh5ptbUEnmc96iLCS1zji35LIOyTwjmRH 3oJ8PLeqiX7tIbd8xyBfyI+npvFNWfcRDPZIDGzI3SsyExPEY4rAXiOIQ87wKzwTnkW5 PEYA== X-Gm-Message-State: AOAM531OhNdGM2z/5/BoQKUB8JcIwafdopwZ6KpKq15vfwCSAAZiUdvH iRlqtTYsFBDjABoKxCBNIms= X-Google-Smtp-Source: ABdhPJwOE5swVc17Sfw0Mdin4+ZhrSkEyUzplM8S+QeabTxk08OpxuqYylmnf7qs0JcoCjo3I+PHvw== X-Received: by 2002:a05:6402:50c:: with SMTP id m12mr27533779edv.141.1643760273416; Tue, 01 Feb 2022 16:04:33 -0800 (PST) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:33 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 14/16] net: dsa: qca8k: cache lo and hi for mdio write Date: Wed, 2 Feb 2022 01:03:33 +0100 Message-Id: <20220202000335.19296-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From Documentation, we can cache lo and hi the same way we do with the page. This massively reduce the mdio write as 3/4 of the time as we only require to write the lo or hi part for a mdio write. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++++++++-------- drivers/net/dsa/qca8k.h | 5 ++++ 2 files changed, 54 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 86d3742b1038..0cce3a6030af 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -88,6 +88,44 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *pag= e) *page =3D regaddr & 0x3ff; } =20 +static int +qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo) +{ + u16 *cached_lo =3D &priv->mdio_cache.lo; + struct mii_bus *bus =3D priv->bus; + int ret; + + if (lo =3D=3D *cached_lo) + return 0; + + ret =3D bus->write(bus, phy_id, regnum, lo); + if (ret < 0) + dev_err_ratelimited(&bus->dev, + "failed to write qca8k 32bit lo register\n"); + + *cached_lo =3D lo; + return 0; +} + +static int +qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi) +{ + u16 *cached_hi =3D &priv->mdio_cache.hi; + struct mii_bus *bus =3D priv->bus; + int ret; + + if (hi =3D=3D *cached_hi) + return 0; + + ret =3D bus->write(bus, phy_id, regnum, hi); + if (ret < 0) + dev_err_ratelimited(&bus->dev, + "failed to write qca8k 32bit hi register\n"); + + *cached_hi =3D hi; + return 0; +} + static int qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) { @@ -111,7 +149,7 @@ qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 r= egnum, u32 *val) } =20 static void -qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) +qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val) { u16 lo, hi; int ret; @@ -119,12 +157,9 @@ qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32= regnum, u32 val) lo =3D val & 0xffff; hi =3D (u16)(val >> 16); =20 - ret =3D bus->write(bus, phy_id, regnum, lo); + ret =3D qca8k_set_lo(priv, phy_id, regnum, lo); if (ret >=3D 0) - ret =3D bus->write(bus, phy_id, regnum + 1, hi); - if (ret < 0) - dev_err_ratelimited(&bus->dev, - "failed to write qca8k 32bit register\n"); + ret =3D qca8k_set_hi(priv, phy_id, regnum + 1, hi); } =20 static int @@ -400,7 +435,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t va= l) if (ret < 0) goto exit; =20 - qca8k_mii_write32(bus, 0x10 | r2, r1, val); + qca8k_mii_write32(priv, 0x10 | r2, r1, val); =20 exit: mutex_unlock(&bus->mdio_lock); @@ -433,7 +468,7 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint3= 2_t mask, uint32_t write_ =20 val &=3D ~mask; val |=3D write_val; - qca8k_mii_write32(bus, 0x10 | r2, r1, val); + qca8k_mii_write32(priv, 0x10 | r2, r1, val); =20 exit: mutex_unlock(&bus->mdio_lock); @@ -1117,14 +1152,14 @@ qca8k_mdio_write(struct qca8k_priv *priv, int phy, = int regnum, u16 data) if (ret) goto exit; =20 - qca8k_mii_write32(bus, 0x10 | r2, r1, val); + qca8k_mii_write32(priv, 0x10 | r2, r1, val); =20 ret =3D qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_BUSY); =20 exit: /* even if the busy_wait timeouts try to clear the MASTER_EN */ - qca8k_mii_write32(bus, 0x10 | r2, r1, 0); + qca8k_mii_write32(priv, 0x10 | r2, r1, 0); =20 mutex_unlock(&bus->mdio_lock); =20 @@ -1154,7 +1189,7 @@ qca8k_mdio_read(struct qca8k_priv *priv, int phy, int= regnum) if (ret) goto exit; =20 - qca8k_mii_write32(bus, 0x10 | r2, r1, val); + qca8k_mii_write32(priv, 0x10 | r2, r1, val); =20 ret =3D qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_BUSY); @@ -1165,7 +1200,7 @@ qca8k_mdio_read(struct qca8k_priv *priv, int phy, int= regnum) =20 exit: /* even if the busy_wait timeouts try to clear the MASTER_EN */ - qca8k_mii_write32(bus, 0x10 | r2, r1, 0); + qca8k_mii_write32(priv, 0x10 | r2, r1, 0); =20 mutex_unlock(&bus->mdio_lock); =20 @@ -3039,6 +3074,8 @@ qca8k_sw_probe(struct mdio_device *mdiodev) } =20 priv->mdio_cache.page =3D 0xffff; + priv->mdio_cache.lo =3D 0xffff; + priv->mdio_cache.hi =3D 0xffff; =20 /* Check the detected switch id */ ret =3D qca8k_read_switch_id(priv); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 57368acae41b..c3d3c2269b1d 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -369,6 +369,11 @@ struct qca8k_mdio_cache { * mdio writes */ u16 page; +/* lo and hi can also be cached and from Documentation we can skip one + * extra mdio write if lo or hi is didn't change. + */ + u16 lo; + u16 hi; }; =20 struct qca8k_priv { --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 641F6C433F5 for ; Wed, 2 Feb 2022 00:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243214AbiBBAFG (ORCPT ); Tue, 1 Feb 2022 19:05:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243203AbiBBAEh (ORCPT ); Tue, 1 Feb 2022 19:04:37 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C269DC061401; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:34 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 15/16] net: dsa: qca8k: add support for larger read/write size with mgmt Ethernet Date: Wed, 2 Feb 2022 01:03:34 +0100 Message-Id: <20220202000335.19296-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mgmt Ethernet packet can read/write up to 16byte at times. The len reg is limited to 15 (0xf). The switch actually sends and accepts data in 4 different steps of len values. Len steps: - 0: nothing - 1-4: first 4 byte - 5-6: first 12 byte - 7-15: all 16 byte In the alloc skb function we check if the len is 16 and we fix it to a len of 15. It the read/write function interest to extract the real asked data. The tagger handler will always copy the fully 16byte with a READ command. This is useful for some big regs like the fdb reg that are more than 4byte of data. This permits to introduce a bulk function that will send and request the entire entry in one go. Write function is changed and it does now require to pass the pointer to val to also handle array val. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 20 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0cce3a6030af..a1b76dcd2eb6 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -222,7 +222,9 @@ static void qca8k_rw_reg_ack_handler(struct dsa_switch = *ds, struct sk_buff *skb) if (cmd =3D=3D MDIO_READ) { mgmt_eth_data->data[0] =3D mgmt_ethhdr->mdio_data; =20 - /* Get the rest of the 12 byte of data */ + /* Get the rest of the 12 byte of data. + * The read/write function will extract the requested data. + */ if (len > QCA_HDR_MGMT_DATA1_LEN) memcpy(mgmt_eth_data->data + 1, skb->data, QCA_HDR_MGMT_DATA2_LEN); @@ -232,16 +234,30 @@ static void qca8k_rw_reg_ack_handler(struct dsa_switc= h *ds, struct sk_buff *skb) } =20 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg,= u32 *val, - int priority) + int priority, unsigned int len) { struct qca_mgmt_ethhdr *mgmt_ethhdr; + unsigned int real_len; struct sk_buff *skb; + u32 *data2; u16 hdr; =20 skb =3D dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN); if (!skb) return NULL; =20 + /* Max value for len reg is 15 (0xf) but the switch actually return 16 by= te + * Actually for some reason the steps are: + * 0: nothing + * 1-4: first 4 byte + * 5-6: first 12 byte + * 7-15: all 16 byte + */ + if (len =3D=3D 16) + real_len =3D 15; + else + real_len =3D len; + skb_reset_mac_header(skb); skb_set_network_header(skb, skb->len); =20 @@ -254,7 +270,7 @@ static struct sk_buff *qca8k_alloc_mdio_header(enum mdi= o_cmd cmd, u32 reg, u32 * hdr |=3D FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG); =20 mgmt_ethhdr->command =3D FIELD_PREP(QCA_HDR_MGMT_ADDR, reg); - mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_LENGTH, 4); + mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len); mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_CMD, cmd); mgmt_ethhdr->command |=3D FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE, QCA_HDR_MGMT_CHECK_CODE_VAL); @@ -264,7 +280,9 @@ static struct sk_buff *qca8k_alloc_mdio_header(enum mdi= o_cmd cmd, u32 reg, u32 * =20 mgmt_ethhdr->hdr =3D htons(hdr); =20 - skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN); + data2 =3D skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING= _LEN); + if (cmd =3D=3D MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) + memcpy(data2, val + 1, len - QCA_HDR_MGMT_DATA1_LEN); =20 return skb; } @@ -277,7 +295,7 @@ static void qca8k_mdio_header_fill_seq_num(struct sk_bu= ff *skb, u32 seq_num) mgmt_ethhdr->seq =3D FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num); } =20 -static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val) +static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int = len) { struct qca8k_mgmt_eth_data *mgmt_eth_data =3D &priv->mgmt_eth_data; struct sk_buff *skb; @@ -285,7 +303,7 @@ static int qca8k_read_eth(struct qca8k_priv *priv, u32 = reg, u32 *val) int ret; =20 skb =3D qca8k_alloc_mdio_header(MDIO_READ, reg, NULL, - QCA8K_ETHERNET_MDIO_PRIORITY); + QCA8K_ETHERNET_MDIO_PRIORITY, len); if (!skb) return -ENOMEM; =20 @@ -313,6 +331,9 @@ static int qca8k_read_eth(struct qca8k_priv *priv, u32 = reg, u32 *val) msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); =20 *val =3D mgmt_eth_data->data[0]; + if (len > QCA_HDR_MGMT_DATA1_LEN) + memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN); + ack =3D mgmt_eth_data->ack; =20 mutex_unlock(&mgmt_eth_data->mutex); @@ -326,15 +347,15 @@ static int qca8k_read_eth(struct qca8k_priv *priv, u3= 2 reg, u32 *val) return 0; } =20 -static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 val) +static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int= len) { struct qca8k_mgmt_eth_data *mgmt_eth_data =3D &priv->mgmt_eth_data; struct sk_buff *skb; bool ack; int ret; =20 - skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, reg, &val, - QCA8K_ETHERNET_MDIO_PRIORITY); + skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, reg, val, + QCA8K_ETHERNET_MDIO_PRIORITY, len); if (!skb) return -ENOMEM; =20 @@ -380,14 +401,14 @@ qca8k_regmap_update_bits_eth(struct qca8k_priv *priv,= u32 reg, u32 mask, u32 wri u32 val =3D 0; int ret; =20 - ret =3D qca8k_read_eth(priv, reg, &val); + ret =3D qca8k_read_eth(priv, reg, &val, sizeof(val)); if (ret) return ret; =20 val &=3D ~mask; val |=3D write_val; =20 - return qca8k_write_eth(priv, reg, val); + return qca8k_write_eth(priv, reg, &val, sizeof(val)); } =20 static int @@ -398,7 +419,7 @@ qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *va= l) u16 r1, r2, page; int ret; =20 - if (!qca8k_read_eth(priv, reg, val)) + if (!qca8k_read_eth(priv, reg, val, sizeof(val))) return 0; =20 qca8k_split_addr(reg, &r1, &r2, &page); @@ -424,7 +445,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t va= l) u16 r1, r2, page; int ret; =20 - if (!qca8k_write_eth(priv, reg, val)) + if (!qca8k_write_eth(priv, reg, &val, sizeof(val))) return 0; =20 qca8k_split_addr(reg, &r1, &r2, &page); @@ -959,21 +980,21 @@ qca8k_phy_eth_command(struct qca8k_priv *priv, bool r= ead, int phy, } =20 /* Prealloc all the needed skb before the lock */ - write_skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, - &write_val, QCA8K_ETHERNET_PHY_PRIORITY); + write_skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL,= &write_val, + QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val)); if (!write_skb) return -ENOMEM; =20 - clear_skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, - &clear_val, QCA8K_ETHERNET_PHY_PRIORITY); + clear_skb =3D qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL,= &clear_val, + QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val)); if (!write_skb) { ret =3D -ENOMEM; goto err_clear_skb; } =20 - read_skb =3D qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, - &clear_val, QCA8K_ETHERNET_PHY_PRIORITY); - if (!write_skb) { + read_skb =3D qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &= clear_val, + QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val)); + if (!read_skb) { ret =3D -ENOMEM; goto err_read_skb; } --=20 2.33.1 From nobody Mon Jun 29 22:16:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8157C433F5 for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n3sm3590451ejr.6.2022.02.01.16.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 16:04:36 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v8 16/16] net: dsa: qca8k: introduce qca8k_bulk_read/write function Date: Wed, 2 Feb 2022 01:03:35 +0100 Message-Id: <20220202000335.19296-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220202000335.19296-1-ansuelsmth@gmail.com> References: <20220202000335.19296-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce qca8k_bulk_read/write() function to use mgmt Ethernet way to read/write packet in bulk. Make use of this new function in the fdb function and while at it reduce the reg for fdb_read from 4 to 3 as the max bit for the ARL(fdb) table is 83 bits. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 55 ++++++++++++++++++++++++++++++++--------- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index a1b76dcd2eb6..52ec2800dd89 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -411,6 +411,43 @@ qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, = u32 reg, u32 mask, u32 wri return qca8k_write_eth(priv, reg, &val, sizeof(val)); } =20 +static int +qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len) +{ + int i, count =3D len / sizeof(u32), ret; + + if (priv->mgmt_master && !qca8k_read_eth(priv, reg, val, len)) + return 0; + + for (i =3D 0; i < count; i++) { + ret =3D regmap_read(priv->regmap, reg + (i * 4), val + i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int +qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len) +{ + int i, count =3D len / sizeof(u32), ret; + u32 tmp; + + if (priv->mgmt_master && !qca8k_write_eth(priv, reg, val, len)) + return 0; + + for (i =3D 0; i < count; i++) { + tmp =3D val[i]; + + ret =3D regmap_write(priv->regmap, reg + (i * 4), tmp); + if (ret < 0) + return ret; + } + + return 0; +} + static int qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) { @@ -546,17 +583,13 @@ qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32= mask) static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) { - u32 reg[4], val; - int i, ret; + u32 reg[3]; + int ret; =20 /* load the ARL table into an array */ - for (i =3D 0; i < 4; i++) { - ret =3D qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val); - if (ret < 0) - return ret; - - reg[i] =3D val; - } + ret =3D qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg)); + if (ret) + return ret; =20 /* vid - 83:72 */ fdb->vid =3D FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); @@ -580,7 +613,6 @@ qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 po= rt_mask, const u8 *mac, u8 aging) { u32 reg[3] =3D { 0 }; - int i; =20 /* vid - 83:72 */ reg[2] =3D FIELD_PREP(QCA8K_ATU_VID_MASK, vid); @@ -597,8 +629,7 @@ qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 po= rt_mask, const u8 *mac, reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]); =20 /* load the array into the ARL table */ - for (i =3D 0; i < 3; i++) - qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]); + qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg)); } =20 static int --=20 2.33.1