From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D709C433F5 for ; Tue, 1 Feb 2022 01:59:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbiBAB7L (ORCPT ); Mon, 31 Jan 2022 20:59:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232080AbiBAB7H (ORCPT ); Mon, 31 Jan 2022 20:59:07 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C7E4C06173B for ; Mon, 31 Jan 2022 17:59:07 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id o131-20020a25d789000000b00614957c60dfso30384269ybg.15 for ; Mon, 31 Jan 2022 17:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=AymeHIyeNEkJXID1khfAkGq+Ez00dJt89KKS/zaptAY=; b=DVRS25O9T7ak+jVGUIrWiNg+fYE926ffQOiOpgbtGML9OQYJnrSmRmvr3N33NUN+Cn AzBl2uAaArbdXooXe1UXgqzKliziBOBJfBgS8cC64p8rGbI5JpjUpVlYMC4iZ3Us4O7K jHhWJbyFrAsViecXR7PK0t9EfH/iRUisEY/I1ZP2YiCOqEXe03mFttBe7i/OhhCl+8dR SkCLQl9ZECjiGxVSxEWMEqfTdk2XUzRv2hcuP/XxM50MuVl0hBe9/nl0F8DETKRtyZ82 PnBl5y+IWpxUS103dsmVKr5BpCcxLSPhdTT5fCoeCWEznTkON5cMKPWby8a238SM75/x oBxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=AymeHIyeNEkJXID1khfAkGq+Ez00dJt89KKS/zaptAY=; b=ZKpV6AFg3AHyVS777hKcdd+yY5DLOXK/8oPiQuQJle9yZuH6g3Mb1etnjED1/UkeXf 1WTR4Jn5CEoYWXJopg2KLMpd7/kQS/2vr9tx00k2w3xkkA6YjtUDH80V7RI/Xkjtsm/8 Ixubv/NravfRTUK6L8l0myH8rGudKm6PMF0o22LjfpKxL6JlirAOGqnif4JAejhTwjDP +T5c0Lkp5BQGbAQ8wTV0NoIbVTcKBakOFqy6IIJRI6Qdt1gEoZmfwopru1owoRGYBEiD m87qWUKk//porm5HMERVOqwJqfiVKfI7L+BsuaREwdfjqar4ip6TDcyIQ6adYdN1Yh+h e/Vw== X-Gm-Message-State: AOAM533KITV1oz7y3xgjLR3mzjijhTuujbK6qkwJhInUgTOCnUUUltE4 EUSUW9u9c2Wzhgigvw8YWTh8AOTiiD3e X-Google-Smtp-Source: ABdhPJxA36g6yvOYrzKcHsfyxS34FLtB7j2Yn8STDG6lcr5qTDMiG4ODtKfuPSxGYbAKK3+wnkvSKIeqT1i4 X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:a89:: with SMTP id 131mr33008461ybk.234.1643680746352; Mon, 31 Jan 2022 17:59:06 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:33 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-2-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 01/26] perf test: Allow skip for all metrics test From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Intel TMA metrics compute a ratio that may divide by 0, which causes the metric not to print. This happens for metrics with FP_ARITH events. If we see these events in the result and would otherwise fail, then switch to a skip. Also, don't early exit when processing metrics. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Reviewed-by: John Garry --- tools/perf/tests/shell/stat_all_metrics.sh | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/shell/stat_all_metrics.sh b/tools/perf/tests/= shell/stat_all_metrics.sh index 7f4ba3cad632..e7c59e5a7a98 100755 --- a/tools/perf/tests/shell/stat_all_metrics.sh +++ b/tools/perf/tests/shell/stat_all_metrics.sh @@ -4,6 +4,7 @@ =20 set -e =20 +err=3D0 for m in $(perf list --raw-dump metrics); do echo "Testing $m" result=3D$(perf stat -M "$m" true 2>&1) @@ -14,9 +15,14 @@ for m in $(perf list --raw-dump metrics); do if [[ ! "$result" =3D~ "$m" ]]; then echo "Metric '$m' not printed in:" echo "$result" - exit 1 + if [[ "$result" =3D~ "FP_ARITH" && "$err" !=3D "1" ]]; then + echo "Skip, not fail, for FP issues" + err=3D2 + else + err=3D1 + fi fi fi done =20 -exit 0 +exit "$err" --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 832D0C433F5 for ; Tue, 1 Feb 2022 01:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232182AbiBAB7N (ORCPT ); Mon, 31 Jan 2022 20:59:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232101AbiBAB7K (ORCPT ); Mon, 31 Jan 2022 20:59:10 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAE29C061714 for ; Mon, 31 Jan 2022 17:59:09 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id i203-20020a253bd4000000b006195f020a0cso18591068yba.14 for ; Mon, 31 Jan 2022 17:59:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=OmdE95x04KM3/ED78GZg0AtUB2Mzv0NL09OkSdhP/uU=; b=fWjD6EZMU1PtYTshyFutxPGzfgvvImfV+bjA7oAKuJ9TnUhD2+2KNRfopQ+UE0p/BM OsLsb5yXBynX73n6WXgZrE3CfNSegyOsbCK91Esmnu2HJNUkXYjUyuUAQ33KO//4wAos DF210Vu02PiBsJYTKExbtIDIGW30NZFJ5j77sU8OgfqS+gI683yDhkUov+hqDxxSumDN gxzj61WBfnzVd6eBra86aICMqMaD1RBnujTIIAlapGxyeBXdDyBgnRuwukk/ftWwmt3J /6ERucDeQXmaAkpvHRI1/w64seAQjYDVQXAqz75ljv23z1jIVwUBpcdxwtM0zG9cGxay ELtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=OmdE95x04KM3/ED78GZg0AtUB2Mzv0NL09OkSdhP/uU=; b=NDEeTbJ3a/NS6KKDJEtZ1ZjBhKWNm+pPz2CRrfcg2OT5eocnnANO3D2AtN8o08BX0Q 7diPKut0FagDqbJZ71sS4BHGXFnImBS23W9tyuzuMoFMTPE/ouc29O0/ipLKYszD7aJ9 tKnjrdTZoZ9U+8q9EjTOPnGQ1LMQY7BZrNhwzNC5VQWn5N3bBSgrC5M4ysQqvfLB+GLc g0IT7MO70TtxEWcr6nbUdU9gOu88j2BHkq9a8UTP7kqKdPQwf9qmUxKkw64QfGgjYYe5 Ky5cTM/qwiEWIyR6l1mda37Cx4nkvtQAPXcZ+UE580NHTsxk3LDxiJq9eqj9TFiIIWkY uwhQ== X-Gm-Message-State: AOAM532vo4RYpalSJK6h2WZ+yRNyVKB2T8quEgSx3APweaHdj/dFG7Bp D4NO9hCQmJK7PnA+iHZP3UVuozMolWr7 X-Google-Smtp-Source: ABdhPJw/bJNWdcqamdWqcBIaiEo6vLNbC0BhAzpDV2dA3z8em7ZNMJYr769C4UVVlTG5GHLJv+FCENgyJknG X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:d4d7:: with SMTP id m206mr21920044ybf.28.1643680749112; Mon, 31 Jan 2022 17:59:09 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:34 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-3-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 02/26] perf vendor events: Update metrics for SkyLake Server From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 1.26: https://download.01.org/perfmon/SKX Json files generated by: https://github.com/intel/event-converter-for-linux-perf Fixes were made that allow the skx-metrics.json to successfully generate, bringing back TopdownL1 metrics. Tested: $ perf test ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : Skip 91: perf all PMU test : Ok ... 90 skips due to a lack of floating point samples, which is understandable. Fixes: c4ad8fabd03f ("perf vendor events: Update metrics for SkyLake Server= ") Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/skylakex/cache.json | 111 +++-- .../arch/x86/skylakex/floating-point.json | 24 +- .../arch/x86/skylakex/frontend.json | 18 +- .../pmu-events/arch/x86/skylakex/memory.json | 96 ++-- .../arch/x86/skylakex/pipeline.json | 11 + .../arch/x86/skylakex/skx-metrics.json | 461 ++++++++++++++++-- .../arch/x86/skylakex/uncore-other.json | 23 + 7 files changed, 591 insertions(+), 153 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/per= f/pmu-events/arch/x86/skylakex/cache.json index 9ff67206ade4..821d2f2a8f25 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json @@ -314,6 +314,19 @@ "SampleAfterValue": "2000003", "UMask": "0x82" }, + { + "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "2000003", + "UMask": "0x83" + }, { "BriefDescription": "Retired load instructions with locked access.= ", "Counter": "0,1,2,3", @@ -358,6 +371,7 @@ "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, @@ -370,6 +384,7 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -733,7 +748,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010491", + "MSRValue": "0x10491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -772,7 +787,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0491", + "MSRValue": "0x4003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -785,7 +800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", + "MSRValue": "0x1003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -798,7 +813,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0491", + "MSRValue": "0x8003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -811,7 +826,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010490", + "MSRValue": "0x10490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -850,7 +865,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0490", + "MSRValue": "0x4003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -863,7 +878,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", + "MSRValue": "0x1003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -876,7 +891,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0490", + "MSRValue": "0x8003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -889,7 +904,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -928,7 +943,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -941,7 +956,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -954,7 +969,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0120", + "MSRValue": "0x8003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -967,7 +982,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1006,7 +1021,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1019,7 +1034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1032,7 +1047,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0122", + "MSRValue": "0x8003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1045,7 +1060,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1084,7 +1099,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1097,7 +1112,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1110,7 +1125,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0004", + "MSRValue": "0x8003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1123,7 +1138,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1162,7 +1177,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1175,7 +1190,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1188,7 +1203,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0001", + "MSRValue": "0x8003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1201,7 +1216,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1240,7 +1255,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1253,7 +1268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1266,7 +1281,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0002", + "MSRValue": "0x8003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1279,7 +1294,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x10400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1318,7 +1333,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0400", + "MSRValue": "0x4003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1331,7 +1346,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x1003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1344,7 +1359,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0400", + "MSRValue": "0x8003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1357,7 +1372,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1396,7 +1411,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1409,7 +1424,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1422,7 +1437,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0010", + "MSRValue": "0x8003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1435,7 +1450,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1474,7 +1489,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1487,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1500,7 +1515,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0020", + "MSRValue": "0x8003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1513,7 +1528,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1552,7 +1567,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1565,7 +1580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1578,7 +1593,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0080", + "MSRValue": "0x8003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1591,7 +1606,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1630,7 +1645,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1643,7 +1658,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1656,7 +1671,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0100", + "MSRValue": "0x8003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/skylakex/floating-point.json index 503737ed3a83..9e873ab22450 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json @@ -1,73 +1,81 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, { - "BriefDescription": "Number of SSE/AVX computational 512-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 8 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x40" }, { - "BriefDescription": "Number of SSE/AVX computational 512-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 16 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT= DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they p= erform 16 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x80" }, { - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computation. Applies to SS= E* and AVX* scalar double precision floating-point instructions: ADD SUB MU= L DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB in= structions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computation. Applies to SS= E* and AVX* scalar single precision floating-point instructions: ADD SUB MU= L DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB in= structions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/= perf/pmu-events/arch/x86/skylakex/frontend.json index 078706a50091..ecce4273ae52 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json @@ -30,7 +30,21 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired Instructions who experienced decode s= tream buffer (DSB - the decoded instruction-cache) miss.", + "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", @@ -38,7 +52,7 @@ "MSRIndex": "0x3F7", "MSRValue": "0x11", "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/pe= rf/pmu-events/arch/x86/skylakex/memory.json index 6f29b02fa320..60c286b4fe54 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json @@ -299,7 +299,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORW= ARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00491", + "MSRValue": "0x83FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -312,7 +312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00491", + "MSRValue": "0x63FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -325,7 +325,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000491", + "MSRValue": "0x604000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -338,7 +338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNO= OP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800491", + "MSRValue": "0x63B800491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -377,7 +377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00490", + "MSRValue": "0x83FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -390,7 +390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00490", + "MSRValue": "0x63FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -403,7 +403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000490", + "MSRValue": "0x604000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -416,7 +416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800490", + "MSRValue": "0x63B800490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -455,7 +455,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00120", + "MSRValue": "0x83FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -468,7 +468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00120", + "MSRValue": "0x63FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -481,7 +481,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000120", + "MSRValue": "0x604000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -494,7 +494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800120", + "MSRValue": "0x63B800120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -533,7 +533,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00122", + "MSRValue": "0x83FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -546,7 +546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00122", + "MSRValue": "0x63FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -559,7 +559,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000122", + "MSRValue": "0x604000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -572,7 +572,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_M= ISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800122", + "MSRValue": "0x63B800122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -611,7 +611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00004", + "MSRValue": "0x83FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -624,7 +624,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00004", + "MSRValue": "0x63FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -637,7 +637,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000004", + "MSRValue": "0x604000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -650,7 +650,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800004", + "MSRValue": "0x63B800004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -689,7 +689,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00001", + "MSRValue": "0x83FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -702,7 +702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00001", + "MSRValue": "0x63FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -715,7 +715,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000001", + "MSRValue": "0x604000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800001", + "MSRValue": "0x63B800001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -767,7 +767,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00002", + "MSRValue": "0x83FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -780,7 +780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00002", + "MSRValue": "0x63FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -793,7 +793,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000002", + "MSRValue": "0x604000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -806,7 +806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800002", + "MSRValue": "0x63B800002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00400", + "MSRValue": "0x83FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -858,7 +858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00400", + "MSRValue": "0x63FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -871,7 +871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000400", + "MSRValue": "0x604000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -884,7 +884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800400", + "MSRValue": "0x63B800400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -923,7 +923,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00010", + "MSRValue": "0x83FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -936,7 +936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00010", + "MSRValue": "0x63FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -949,7 +949,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000010", + "MSRValue": "0x604000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800010", + "MSRValue": "0x63B800010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1001,7 +1001,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00020", + "MSRValue": "0x83FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1014,7 +1014,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00020", + "MSRValue": "0x63FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1027,7 +1027,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000020", + "MSRValue": "0x604000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1040,7 +1040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800020", + "MSRValue": "0x63B800020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00080", + "MSRValue": "0x83FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1092,7 +1092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00080", + "MSRValue": "0x63FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1105,7 +1105,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000080", + "MSRValue": "0x604000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1118,7 +1118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800080", + "MSRValue": "0x63B800080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1157,7 +1157,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00100", + "MSRValue": "0x83FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1170,7 +1170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00100", + "MSRValue": "0x63FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1183,7 +1183,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000100", + "MSRValue": "0x604000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800100", + "MSRValue": "0x63B800100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/skylakex/pipeline.json index ca5748120666..12eabae3e224 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json @@ -435,6 +435,17 @@ "PublicDescription": "Counts the number of instructions (EOMs) ret= ired. Counting covers macro-fused instructions individually (that is, incre= ments by two).", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", "Counter": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/too= ls/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index 863c9e103969..b016f7d1ff3d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -1,26 +1,167 @@ [ + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNH= ALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * = CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK= _UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK= _UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCL= ES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNH= ALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_= RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALT= ED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * = CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES = / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_= RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNH= ALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIR= ED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) = * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS= _NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts_SMT", + "MetricName": "Mispredictions_SMT" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_= ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALL= S_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (= ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_H= IT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1= @ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS )= / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_AC= TIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_P= ORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * E= XE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + = 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min= ( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,= cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS= / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTI= VITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_= HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (ME= M_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L= 1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVI= TY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THR= EAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MI= SS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_= ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1= _PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) *= EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UO= PS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY = + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (O= FFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIV= ITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THR= EAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_= L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_ME= M_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EX= E_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTE= D.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * = (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS= _ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD= ))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_R= ETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ / CPU_CLK_UNHAL= TED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALL= S_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK= _UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL= S_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 = + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RET= IRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ))= + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_= L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #= ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE= _ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_= SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE= _THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTI= L) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (= 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_A= CTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MIS= C.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( = 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )= * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_D= ATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALL= S_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - C= YCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RE= TIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )= ) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_= RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYC= LE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNH= ALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STA= LLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_A= NY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_A= CTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER= .SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.ST= ALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) )= ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MI= SS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY = + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTI= VITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.= THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.= REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)= ) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / = 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK = ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4= * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_AC= TIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( M= EM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB= _FULL\\,cmask\\=3D1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.S= TALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD = , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore_SMT", + "MetricName": "Memory_Bandwidth_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_= ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALL= S_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (= ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_H= IT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1= @ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS )= / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_AC= TIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_P= ORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * E= XE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + = 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min= ( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_R= D ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE= _REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREA= D)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_= ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALT= ED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT /= MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL= \\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.ST= ALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_= L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #(((= CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_AC= TIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLO= TS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTI= VITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 = * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / C= PU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 *= ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000= 000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CY= CLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNH= ALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (= MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.= FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTI= VITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STA= LLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL= + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_U= NHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORE= S)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - = ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.= THREAD))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK= _UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL= S_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 = + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RET= IRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ))= + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_= L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #= ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE= _ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_= SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE= _THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTI= L) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (= 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_A= CTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MIS= C.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( = 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )= * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WI= TH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cp= u@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHAL= TED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + = (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_C= LK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 += (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MIS= S.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_AC= TIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVIT= Y.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREA= D) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / = (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.R= ETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALT= ED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_POR= TS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CO= RE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_TH= READ_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( I= NT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC)= * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THRE= AD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) = * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRE= D.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_M= ISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (= MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED= .L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT = / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ )= ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / = CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVI= TY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS= _UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (ID= Q_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + = CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UO= PS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) )))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore_SMT", + "MetricName": "Memory_Latency_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( (= CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK= _UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * c= pu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE = , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 )= ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYC= LE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_A= CTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTL= B_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BO= UND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Memory_Data_TLBs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - = CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (m= in( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WAL= K_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_M= ISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_= ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) += ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * = cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_STORE_MISSES.WALK_ACTI= VE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREA= D_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES = / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricName": "Memory_Data_TLBs_SMT" + }, + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_= RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITI= ONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 = * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_= RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITI= ONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "Ret_SMT", + "MetricName": "Branching_Overhead_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_= CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDA= TA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS= .ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_ST= ALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACH= E_16B.IFDATA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 = * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.= CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + C= PU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT", + "MetricName": "Big_Code_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK= _UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE /= (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MIS= P_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT= _DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (I= CACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STA= LL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHA= LTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_U= OPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))= )", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DE= LIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.= ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL= _BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_= MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_D= ELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) = * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))= ) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNH= ALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STAL= L\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / = CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "Fed;FetchBW;Frontend_SMT", + "MetricName": "Instruction_Fetch_BW_SMT" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -30,39 +171,84 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", + "MetricName": "SLOTS_SMT" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHAL= TED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "Flops_SMT", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -86,122 +272,249 @@ { "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.25= 6B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARI= TH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SI= NGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.C= ORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 *= CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELI= V.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS = - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_D= ELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NO= T_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_= 0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "DSBmiss;Fed_SMT", + "MetricName": "DSB_Misses_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT= _TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_= RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CON= DITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / B= R_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CORE_= CLKS )", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Offcore", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_C= LK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_Silent_PKI" }, { "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, { @@ -219,7 +532,7 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -228,6 +541,48 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License0_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. SMT versio= n; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1. SMT version; use when SMT is= enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License1_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions. = SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX). SMT vers= ion; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License2_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions. SMT version; use when SMT is= enabled and measuring per logical CPU." + }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", @@ -240,34 +595,46 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", "MetricExpr": "1000000000 * ( cha@event\\=3D0x36\\,umask\\=3D0x21\= \,config\\=3D0x40433@ / cha@event\\=3D0x35\\,umask\\=3D0x21\\,config\\=3D0x= 40433@ ) / ( cha_0@event\\=3D0x0@ / duration_time )", - "MetricGroup": "MemoryLat;SoC", + "MetricGroup": "Mem;MemoryLat;SoC", "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cha@event\\=3D0x36\\,umask\\=3D0x21\\,config\\=3D0x= 40433@ / cha@event\\=3D0x36\\,umask\\=3D0x21\\,config\\=3D0x40433\\,thresh\= \=3D1@", - "MetricGroup": "MemoryBW;SoC", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, + { + "BriefDescription": "Average latency of data read request to exter= nal DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-= read prefetches", + "MetricExpr": "1000000000 * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSE= RTS ) / imc_0@event\\=3D0x0@", + "MetricGroup": "Mem;MemoryLat;SoC;Server", + "MetricName": "MEM_DRAM_Read_Latency" + }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Writes [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_= DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + U= NC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Reads [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO= _DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 = + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / 1000000000 / duration_tim= e", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Read_BW" }, { diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/skylakex/uncore-other.json index 6ed92bc5c129..06c5ca26ca3f 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json @@ -537,6 +537,18 @@ "PublicDescription": "Counts clockticks of the 1GHz trafiic contro= ller clock in the IIO unit.", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data: Part 0-3", + "UMask": "0x03", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", "Counter": "0,1,2,3", @@ -585,6 +597,17 @@ "UMask": "0x03", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0-3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer occupancy of completi= ons with data: Part 0-3", + "UMask": "0x0f", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0", "Counter": "2,3", --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2BFCC433FE for ; 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charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are still at version 7: https://download.01.org/perfmon/BDW-DE Json files generated by: https://github.com/intel/event-converter-for-linux-perf This adds TopdownL1_SMT metrics to bdwde-metrics.json. A discussed in: https://lore.kernel.org/all/20220129080929.837293-4-irogers@google.com/ The TMA_Metrics-full.csv was modified so that BDW-DE is in the server column with BDX, the Page_Walks_Utilization and Page_Walks_Utilization_SMT metrics are then copied from BDW. Tested: ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : Skip 91: perf all PMU test : Ok ... 90 skips due to a lack of floating point samples, which is understandable. Suggested-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/broadwellde/bdwde-metrics.json | 407 +++- .../arch/x86/broadwellde/cache.json | 1122 +++++----- .../arch/x86/broadwellde/floating-point.json | 222 +- .../arch/x86/broadwellde/frontend.json | 335 +-- .../arch/x86/broadwellde/memory.json | 608 +++--- .../arch/x86/broadwellde/other.json | 28 +- .../arch/x86/broadwellde/pipeline.json | 1892 ++++++++--------- .../arch/x86/broadwellde/virtual-memory.json | 394 ++-- 8 files changed, 2652 insertions(+), 2356 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json = b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index 16fd8a7490fc..73b6865a769d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -1,104 +1,369 @@ [ { - "BriefDescription": "Instructions Per Cycle (per logical thread)", + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided." + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( UOPS_RETIRED.RETIRE_SLOT= S / INST_RETIRED.ANY * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "Frontend", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded Icache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE= _UOPS + IDQ.MS_UOPS )", - "MetricGroup": "DSB; Frontend_Bandwidth", - "MetricName": "DSB_Coverage" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "BriefDescription": "Cycles Per Instruction (threaded)", - "MetricExpr": "1 / INST_RETIRED.ANY / cycles", - "MetricGroup": "Pipeline;Summary", + "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { - "BriefDescription": "Per-thread actual clocks when the logical pro= cessor is active. This is called 'Clockticks' in VTune.", + "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots", - "MetricExpr": "4*( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on el= se cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", + "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD_ANY / = 2 ) if #SMT_on else cycles", - "MetricGroup": "SMT", + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", + "MetricName": "CoreIPC_SMT" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", + "MetricName": "FLOPc" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIV= E / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", + "MetricName": "FLOPc_SMT" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", - "MetricExpr": "UOPS_EXECUTED.THREAD / ( cpu@uops_executed.core\\,c= mask\\=3D1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "MetricGroup": "Pipeline;Ports_Utilization", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Average Branch Address Clear Cost (fraction o= f cycles)", - "MetricExpr": "2* ( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL - ( 14 = * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + 7* = ITLB_MISSES.WALK_COMPLETED ) ) / RS_EVENTS.EMPTY_END", - "MetricGroup": "Unknown_Branches", - "MetricName": "BAClear_Cost" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THR= EAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CL= K_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.= THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.= ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.AL= L_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DE= LIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.= ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_= BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BA= CLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + = MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLE= S_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" }, { - "BriefDescription": "Core actual clocks when any thread is active = on the physical core", - "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else= CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads", + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B= _PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE= _UOPS + IDQ.MS_UOPS )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least 1 such miss)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( cpu@l1d_pend_miss.pending= _cycles\\,any\\=3D1@ / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, + { + "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", + "MetricGroup": "Mem;Backend;CacheMisses", + "MetricName": "L2MPKI" + }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", + "MetricName": "L2MPKI_All" + }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_All" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" + }, { "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_= LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WALK_DURAT= ION\\,cmask\\=3D1@ + 7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.W= ALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED)) / ( CPU_CLK_UNHALTED.THREAD_ANY = / 2 ) if #SMT_on else cycles", - "MetricGroup": "TLB", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cp= u@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WAL= K_DURATION\\,cmask\\=3D1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_L= OAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALT= ED.THREAD", + "MetricGroup": "Mem;MemoryTLB", "MetricName": "Page_Walks_Utilization" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cp= u@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WAL= K_DURATION\\,cmask\\=3D1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_L= OAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARIT= H_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBL= E + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.25= 6B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 100000= 0000 / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -108,17 +373,53 @@ "MetricName": "Turbo_Utilization" }, { - "BriefDescription": "Fraction of cycles where both hardware thread= s were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", + "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "DRAM_BW_Use" + }, + { + "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", + "MetricExpr": "1000000000 * ( cbox@event\\=3D0x36\\,umask\\=3D0x3\= \,filter_opc\\=3D0x182@ / cbox@event\\=3D0x35\\,umask\\=3D0x3\\,filter_opc\= \=3D0x182@ ) / ( cbox_0@event\\=3D0x0@ / duration_time )", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" + }, + { + "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "cbox@event\\=3D0x36\\,umask\\=3D0x3\\,filter_opc\\= =3D0x182@ / cbox@event\\=3D0x36\\,umask\\=3D0x3\\,filter_opc\\=3D0x182\\,th= resh\\=3D1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" + }, + { + "BriefDescription": "Socket actual clocks when any core is active = on that socket", + "MetricExpr": "cbox_0@event\\=3D0x0@", + "MetricGroup": "SoC", + "MetricName": "Socket_CLKS" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/= perf/pmu-events/arch/x86/broadwellde/cache.json index bf243fe2a0ec..0f4de912d099 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -1,809 +1,809 @@ [ { + "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outst= anding in cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x50" + }, + { + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x7" + }, + { + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x5" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 cod= e requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe1" }, { + "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache.", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe2" }, { + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x44" + }, + { "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache.", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "This event counts the number of demand Data = Read requests that hit L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x21" }, { + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x30", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0x50" + }, + { "BriefDescription": "L2 prefetch requests that miss L2 cache", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x24", - "UMask": "0x3f", "BriefDescription": "All requests that miss L2 cache.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3f" }, { - "EventCode": "0x24", - "UMask": "0x41", - "BriefDescription": "Demand Data Read requests that hit L2 cache", + "BriefDescription": "All L2 requests.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "This event counts the number of demand Data = Read requests that hit L2 cache. Only not rejected loads are counted.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x24", - "UMask": "0x42", "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x42" }, { - "EventCode": "0x24", - "UMask": "0x44", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x22" }, { - "EventCode": "0x24", - "UMask": "0x50", - "BriefDescription": "L2 prefetch requests that hit L2 cache", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x24", - "UMask": "0xe1", - "BriefDescription": "Demand Data Read requests", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "This event counts the total number of L2 cod= e requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0xe7", - "BriefDescription": "Demand requests to L2 cache.", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x24", - "UMask": "0xf8", - "BriefDescription": "Requests from L2 hardware prefetchers", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests.", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x2E", - "UMask": "0x41", "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x2E", - "UMask": "0x4f", "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts duration of L1D miss outst= anding in cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", - "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "UMask": "0x1", - "BriefDescription": "L1D data line replacements", - "Counter": "0,1,2,3", - "EventName": "L1D.REPLACEMENT", - "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding Demand Data Read transactions in the super queue (SQ) every cycle. = A transaction is considered to be in the Offcore outstanding state between = L2 miss and transaction completion sent to requestor. See the corresponding= Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is coun= ted from the promotion point.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outsta= nding Demand Data Read transactions are present in the super queue (SQ). A = transaction is considered to be in the Offcore outstanding state between L2= miss and transaction completion sent to requestor (SQ de-allocation).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "BDM76", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding Code Reads transactions in the super queue every cycle. The Offcore= outstanding state of the transaction lasts from the L2 miss until the send= ing transaction completion to requestor (SQ deallocation). See the correspo= nding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding RFO (store) transactions in the super queue (SQ) every cycle. A tra= nsaction is considered to be in the Offcore outstanding state between L2 mi= ss and transaction completion sent to requestor (SQ de-allocation). See cor= responding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding demand rfo Reads transactions in the super queue every cycle. The O= ffcore outstanding state of the transaction lasts from the L2 miss until th= e sending transaction completion to requestor (SQ deallocation). See the co= rresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding cacheable Core Data Read transactions in the super queue every cycl= e. A transaction is considered to be in the Offcore outstanding state betwe= en L2 miss and transaction completion sent to requestor (SQ de-allocation).= See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outsta= nding cacheable Core Data Read transactions are present in the super queue.= A transaction is considered to be in the Offcore outstanding state between= L2 miss and transaction completion sent to requestor (SQ de-allocation). S= ee corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x63", - "UMask": "0x2", - "BriefDescription": "Cycles when L1D is locked", - "Counter": "0,1,2,3", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 hi= t and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were HitM = responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS= )", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 Hi= t and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", + "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the last-level (L3) cache without snoops required.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS)", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with true STLB miss retired to the ar= chitected path. True STLB miss is an uop triggering page walk that gets com= pleted without blocks, and later gets retired. This page walk can end up wi= th or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches. Thi= s is a precise event.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS)", + "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops true STLB miss retired to the archit= ected path. True STLB miss is an uop triggering page walk that gets complet= ed without blocks, and later gets retired. This page walk can end up with o= r without a fault.", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x4" }, { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS)", + "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "BDM35", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with locked access retired to the arc= hitected path.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.(Precise Event - PEBS)", + "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted load uops retired to the architec= ted path. A line split is across 64B cache-line which includes a page split= (4K).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x10" }, { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted store uops retired to the archite= cted path. A line split is across 64B cache-line which includes a page spli= t (4K).", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were load = uops missed L1 but hit a fill buffer due to a preceding miss to the same ca= che line with the data not ready.\nNote: Only two data-sources of L1/FB are= applicable for AVX-256bit even though the corresponding AVX load could be= serviced by a deeper level in the memory hierarchy. Data source is reporte= d for the Low-half load.", "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops. (Precise Event - PEBS)= ", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops retired to the architected path with = a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/= store double-pump memory uops as a single uop at retirement. This event als= o counts SW prefetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops retired to the architected path with= a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load= /store double-pump memory uops as a single uop at retirement.", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data source were hits i= n the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are a= pplicable for AVX-256bit even though the corresponding AVX load could be s= erviced by a deeper level in the memory hierarchy. Data source is reported = for the Low-half load. This event also counts SW prefetches independent of = the actual data source.", "SampleAfterValue": "2000003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xD1", - "UMask": "0x1", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops misses in L1 cache as data = sources. Uses PEBS.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data source were hits i= n the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are a= pplicable for AVX-256bit even though the corresponding AVX load could be s= erviced by a deeper level in the memory hierarchy. Data source is reported = for the Low-half load. This event also counts SW prefetches independent of = the actual data source.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the nearest-level (L1) cache. Counting excludes unknown and UC data so= urce.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xD1", - "UMask": "0x2", "BriefDescription": "Retired load uops with L2 cache hits as data = sources. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM35", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the mid-level (L2) cache.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknow= n data-source. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources. Uses PEBS.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were data = hits in the last-level (L3) cache without snoops required.", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the mid-level (L2) cache. Counting excludes unknown and UC data source= .", "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xD1", - "UMask": "0x8", - "BriefDescription": "Retired load uops misses in L1 cache as data = sources. Uses PEBS.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknow= n data-source. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the nearest-level (L1) cache. Counting excludes unknown and UC data so= urce.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x10", - "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources. Uses PEBS.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the mid-level (L2) cache. Counting excludes unknown and UC data source= .", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were data = hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xD1", - "UMask": "0x20", "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source. (Precise Event - PEBS).", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM100, BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS)", - "Data_LA": "1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were load = uops missed L1 but hit a fill buffer due to a preceding miss to the same ca= che line with the data not ready.\nNote: Only two data-sources of L1/FB are= applicable for AVX-256bit even though the corresponding AVX load could be= serviced by a deeper level in the memory hierarchy. Data source is reporte= d for the Low-half load.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x20" }, { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS= )", + "BriefDescription": "All retired load uops. (Precise Event - PEBS)= ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 Hi= t and a cross-core snoop missed in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops retired to the architected path with = a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/= store double-pump memory uops as a single uop at retirement. This event als= o counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 hi= t and a cross-core snoop hit in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops retired to the architected path with= a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load= /store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were HitM = responses from a core on same socket (shared L3).", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with locked access retired to the arc= hitected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.(Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the last-level (L3) cache without snoops required.", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted load uops retired to the architec= ted path. A line split is across 64B cache-line which includes a page split= (4K).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "EventCode": "0xD3", - "UMask": "0x1", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "BDE70, BDM100", - "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches. Thi= s is a precise event.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted store uops retired to the archite= cted path. A line split is across 64B cache-line which includes a page spli= t (4K).", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", + "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with true STLB miss retired to the ar= chitected path. True STLB miss is an uop triggering page walk that gets com= pleted without blocks, and later gets retired. This page walk can end up wi= th or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM (Precise Event)", + "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops true STLB miss retired to the archit= ected path. True STLB miss is an uop triggering page walk that gets complet= ed without blocks, and later gets retired. This page walk can end up with o= r without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache (Precise Event)", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xF0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding cacheable Core Data Read transactions in the super queue every cycl= e. A transaction is considered to be in the Offcore outstanding state betwe= en L2 miss and transaction completion sent to requestor (SQ de-allocation).= See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outsta= nding cacheable Core Data Read transactions are present in the super queue.= A transaction is considered to be in the Offcore outstanding state between= L2 miss and transaction completion sent to requestor (SQ de-allocation). S= ee corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "PublicDescription": "This event counts cycles when offcore outsta= nding Demand Data Read transactions are present in the super queue (SQ). A = transaction is considered to be in the Offcore outstanding state between L2= miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outs= tanding demand rfo Reads transactions in the super queue every cycle. The O= ffcore outstanding state of the transaction lasts from the L2 miss until th= e sending transaction completion to requestor (SQ deallocation). See the co= rresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding Code Reads transactions in the super queue every cycle. The Offcore= outstanding state of the transaction lasts from the L2 miss until the send= ing transaction completion to requestor (SQ deallocation). See the correspo= nding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding Demand Data Read transactions in the super queue (SQ) every cycle. = A transaction is considered to be in the Offcore outstanding state between = L2 miss and transaction completion sent to requestor. See the corresponding= Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is coun= ted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x7", - "BriefDescription": "L2 cache lines filling L2", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.ALL", - "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outs= tanding RFO (store) transactions in the super queue (SQ) every cycle. A tra= nsaction is considered to be in the Offcore outstanding state between L2 mi= ss and transaction completion sent to requestor (SQ de-allocation). See cor= responding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF2", - "UMask": "0x5", - "BriefDescription": "Clean L2 cache lines evicted by demand.", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xf4", - "UMask": "0x10", "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "This event counts the number of split locks = in the super queue.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json= b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json index d7b9d9c9c518..fdf5dc40b835 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -1,165 +1,193 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired. Each count represe= nts 2 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP = and FM(N)ADD/SUB instructions count twice as they perform multiple calculat= ions per element.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions = from AVX-256 to legacy SSE when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/= SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multipl= e calculations per element.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions = from legacy SSE to AVX-256 when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xC7", - "UMask": "0x1", - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar double precision floating-point = instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB inst= ructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xC7", - "UMask": "0x2", - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar single precision floating-point = instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)AD= D/SUB instructions count twice as they perform multiple calculations per el= ement.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP = and FM(N)ADD/SUB instructions count twice as they perform multiple calculat= ions per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", - "UMask": "0x3", - "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired. Applies to SSE* and AVX* scalar, double and = single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(= N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired. Each count represe= nts 8 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/= SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multipl= e calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", - "UMask": "0x4", - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired. Each count represe= nts 2 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP = and FM(N)ADD/SUB instructions count twice as they perform multiple calculat= ions per element.", + "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP = FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perfor= m multiple calculations per element. ?.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", - "UMask": "0x8", - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/= SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multipl= e calculations per element.", + "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired. Applies to SSE* and AVX*, packed, double and= single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "UMask": "0x3c" }, { - "EventCode": "0xC7", - "UMask": "0x10", - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP = and FM(N)ADD/SUB instructions count twice as they perform multiple calculat= ions per element.", + "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired. Applies to SSE* and AVX* scalar, double and = single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(= N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xC7", - "UMask": "0x15", - "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP = FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perfor= m multiple calculations per element. ?.", + "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar double precision floating-point = instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB inst= ructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xc7", - "UMask": "0x20", - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired. Each count represe= nts 8 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/= SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multipl= e calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar single precision floating-point = instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)AD= D/SUB instructions count twice as they perform multiple calculations per el= ement.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC7", - "UMask": "0x2a", "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT= SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as t= hey perform multiple calculations per element. ?.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2a" }, { - "EventCode": "0xC7", - "UMask": "0x3c", - "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired. Applies to SSE* and AVX*, packed, double and= single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm multiple calculations per element.", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.PACKED", - "SampleAfterValue": "2000004", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and = output SSE or x87 FP assist. If an input and output assist are detected on = the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { + "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCA", - "UMask": "0x4", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "This event counts x87 floating point (FP) mi= cro-code assist (invalid operation, denormal operand, SNaN operand) when th= e input value (one of the source operands to an FP instruction) is invalid.= ", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCA", - "UMask": "0x10", - "BriefDescription": "Number of SIMD FP assists due to input values= ", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_INPUT", - "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions = from AVX-256 to legacy SSE when penalty is applicable.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "This event counts cycles with any input and = output SSE or x87 FP assist. If an input and output assist are detected on = the same cycle the event increments by 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions = from legacy SSE to AVX-256 when penalty is applicable.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/frontend.json index 72781e1e3362..f0bcb945ff76 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -1,286 +1,295 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops i= nitiated by Decode Stream Buffer (DSB) are being delivered to Instruction D= ecode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting incl= udes uops that may bypass the IDQ.", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the Decode Stream B= uffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", - "CounterMask": "1", - "PublicDescription": "This event counts the number of deliveries t= o Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) wh= ile the Microcode Sequencer (MS) is busy. Counting includes uops that may b= ypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the MITE path. Count= ing includes uops that may bypass the IDQ. This also means that uops are no= t being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the Decode Stream B= uffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the MITE path. Count= ing includes uops that may bypass the IDQ. This also means that uops are no= t being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops i= nitiated by Decode Stream Buffer (DSB) are being delivered to Instruction D= ecode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting incl= udes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries t= o Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) wh= ile the Microcode Sequencer (MS) is busy. Counting includes uops that may b= ypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x80", - "UMask": "0x1", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.HIT", - "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x80", - "UMask": "0x2", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "EventName": "ICACHE.MISSES", - "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", - "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding 4 x when Resou= rce Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ= ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0= ,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation = Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (R= AT) is stalled for the thread (including uop drops and clear BE conditions)= ; \n c. Instruction Decode Queue (IDQ) delivers four uops.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "PublicDescription": "This event counts, on the per-thread basis, = cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_U= ops_Not_Delivered.core =3D4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x9C", - "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "PublicDescription": "This event counts, on the per-thread basis, = cycles when less than 1 uop is delivered to Resource Allocation Table (RAT= ). IDQ_Uops_Not_Delivered.core >=3D3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xAB", - "UMask": "0x2", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "Counter": "0,1,2,3", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools= /perf/pmu-events/arch/x86/broadwellde/memory.json index e44f73c24ac8..604059e7eb58 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,432 +1,432 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "BriefDescription": "Number of times HLE abort was triggered (PEBS= )", "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered (PEB= S).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a TSX line had a cache confli= ct", + "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache confl= ict.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", + "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", + "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", + "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", + "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock B= uffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 128", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above 128.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 16", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above 256.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 32", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above four.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above 512.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times HLE commit succeeded", + "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value b= eing above eight.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x4", - "BriefDescription": "Number of times HLE abort was triggered (PEBS= )", - "PEBS": "1", + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED", - "PublicDescription": "Number of times HLE abort was triggered (PEB= S).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xc8", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Number of times RTM abort was triggered (PEBS= )", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered (PEB= S).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC2", - "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC3", - "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x40", - "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC4", - "PublicDescription": "Number of times HLE caused a fault.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x80", - "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc9", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", + "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xc9", - "UMask": "0x2", "BriefDescription": "Number of times RTM commit succeeded", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x4", - "BriefDescription": "Number of times RTM abort was triggered (PEBS= )", - "PEBS": "1", + "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED", - "PublicDescription": "Number of times RTM abort was triggered (PEB= S).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x8", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x10", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x20", - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xc9", - "UMask": "0x40", - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "PublicDescription": "Number of times a RTM caused a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xc9", - "UMask": "0x80", - "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 4", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above four.", - "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" + "UMask": "0x10" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 8", - "PEBS": "2", - "MSRValue": "0x8", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above eight.", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 16", - "PEBS": "2", - "MSRValue": "0x10", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above 16.", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX line had a cache confli= ct", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache confl= ict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 32", - "PEBS": "2", - "MSRValue": "0x20", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above 32.", - "TakenAlone": "1", - "SampleAfterValue": "100007", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 64", - "PEBS": "2", - "MSRValue": "0x40", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above 64.", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 128", - "PEBS": "2", - "MSRValue": "0x80", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above 128.", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 256", - "PEBS": "2", - "MSRValue": "0x100", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above 256.", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 512", - "PEBS": "2", - "MSRValue": "0x200", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value b= eing above 512.", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" + "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock B= uffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/= perf/pmu-events/arch/x86/broadwellde/other.json index 4475249ea9da..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json @@ -1,44 +1,44 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "PublicDescription": "This event counts when there is a transition= from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/pipeline.json index e2f0540625a2..7580b8af0d13 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -1,1423 +1,1381 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial comp= are", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "Cycles checkpoints in Resource Allocation Ta= ble (RAT) are recovering from JEClear or machine clear.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "BriefDescription": "Cycles when divider is busy executing divide = operations", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x0D", - "UMask": "0x8", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "BriefDescription": "Speculative and retired macro-conditional bra= nches", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which the Re= source Allocation Table (RAT) does not issue any Uops to the reservation st= ation (RS) for the current thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "EventCode": "0x14", - "UMask": "0x1", - "BriefDescription": "Cycles when divider is busy executing divide = operations", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "BriefDescription": "Taken speculative and retired macro-condition= al branches", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired direct near cal= ls", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x4C", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions re= tired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect near call instructions= retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect macro near call instru= ctions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "BriefDescription": "Return instructions retired. (Precise Event -= PEBS)", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS)", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructi= ons retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near cal= ls", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted conditional branch instructions re= tired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken. (Precise Event - PEBS).", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branc= hes.", + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired.(Precise Event)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "UMask": "0xff", - "BriefDescription": "Speculative and retired branches", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xA0", - "UMask": "0x3", - "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", - "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request (that is cycles with non-completed load w= aiting for its data from memory subsystem).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest missing the L1 data cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand* load re= quest missing the L2 cache.(as a footprint) * includes also L1 HW prefetch = requests that may or may not be required by demands.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions= (EOMs) retired. Counting covers macro-fused instructions individually (tha= t is, increments by two).", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts instructions retired.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Ta= ble (RAT) are recovering from JEClear or machine clear.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "BriefDescription": "False dependencies in MOB due to partial comp= are", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x1", - "BriefDescription": "Resource-related stall cycles", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cyc= les. Reasons for stalls can be as follows:\n - *any* u-arch structure got f= ull (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or P= hysical History Table (PHT) slots)\n - *any* u-arch structure got empty (li= ke INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This= counts cycles that the pipeline backend blocked uop delivery from the fron= t end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x4", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.RS", - "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x8", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", - "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand* load request missing the L2 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request (that is cycles with non-completed load w= aiting for its data from memory subsystem).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cyc= les. Reasons for stalls can be as follows:\n - *any* u-arch structure got f= ull (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or P= hysical History Table (PHT) slots)\n - *any* u-arch structure got empty (li= ke INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This= counts cycles that the pipeline backend blocked uop delivery from the fron= t end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "Total execution stalls.", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand* load re= quest missing the L2 cache.(as a footprint) * includes also L1 HW prefetch = requests that may or may not be required by demands.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "CounterMask": "5", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "CounterMask": "6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request missing the L1 data cache.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "CounterMask": "8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x2" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest missing the L1 data cache.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "CounterMask": "12", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x8" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which no uop= s were dispatched from the Reservation Station (RS) per thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x2", - "BriefDescription": "Number of uops executed on the core.", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE", - "PublicDescription": "Number of uops executed from any thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uop= s were dispatched from the Reservation Station (RS) per thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "BDM61", - "PublicDescription": "This event counts the number of instructions= (EOMs) retired. Counting covers macro-fused instructions individually (tha= t is, increments by two).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "BDM11, BDM55", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", "SampleAfterValue": "2000003", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= ", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts all actually retired uops. Counting increments = by two for micro-fused uops, and by one for macro-fused and other uops. Max= imal increment value for one cycle is eight.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles without actually re= tired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", - "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= ", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", - "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x0", - "BriefDescription": "All (macro) branch instructions retired.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS)", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS)", - "PEBS": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect near call instructions= retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS)", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect macro near call instru= ctions retired (captured in ring 3).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x4", - "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", - "PEBS": "2", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "Errata": "BDW98", - "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired. (Precise Event -= PEBS)", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts return instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC4", - "UMask": "0x10", - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "This event counts not taken branch instructi= ons retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS)", - "PEBS": "1", + "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x40", - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "Errata": "BDW98", - "PublicDescription": "This event counts far branch instructions re= tired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC5", - "UMask": "0x0", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS)", - "PEBS": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted conditional branch instructions re= tired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Re= source Allocation Table (RAT) does not issue any Uops to the reservation st= ation (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x4", - "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", - "PEBS": "2", + "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= ", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC5", - "UMask": "0x8", - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired.(Precise Event)", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted return instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts all actually retired uops. Counting increments = by two for micro-fused uops, and by one for macro-fused and other uops. Max= imal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x20", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken. (Precise Event - PEBS).", - "PEBS": "1", + "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= ", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken. (Precise Event - PEBS).", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCC", - "UMask": "0x20", - "BriefDescription": "Count cases of saving new LBR", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually re= tired uops.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json index 7d79c707c6d1..818a8b132c08 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts load misses in all DTLB le= vels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (4K page size). The page walk can end= with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (2M and 4M page sizes). The page walk= can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (1G page size). The page walk can en= d with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x08", - "UMask": "0xe", "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (1G page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (2M and 4M page sizes). The page walk= can end with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (4K page size). The page walk can end= with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x08", - "UMask": "0x60", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x1", "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x49", - "UMask": "0xe", "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x49", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x49", - "UMask": "0x60", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x4F", - "UMask": "0x10", "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x1", "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x85", - "UMask": "0xe", "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x85", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xAE", - "UMask": "0x1", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "ITLB.ITLB_FLUSH", - "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", - "UMask": "0x21", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", - "UMask": "0x22", "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", - "UMask": "0x24", "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BF1FC433EF for ; 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charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 1.14: https://download.01.org/perfmon/CLX Json files generated by: https://github.com/intel/event-converter-for-linux-perf Tested: ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : FAIL= ED! 91: perf all PMU test : Ok ... Test 90 failed due to MEM_PMM_Read_Latency as the test machine lacks optane memory, and the divide by 0 causes the metric not to print - which is intended behavior. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/cascadelakex/cache.json | 967 ++++++++-------- .../arch/x86/cascadelakex/clx-metrics.json | 469 +++++++- .../arch/x86/cascadelakex/floating-point.json | 50 +- .../arch/x86/cascadelakex/frontend.json | 18 +- .../arch/x86/cascadelakex/memory.json | 1008 ++++++++--------- .../arch/x86/cascadelakex/other.json | 952 ++++++++-------- .../arch/x86/cascadelakex/pipeline.json | 11 + .../arch/x86/cascadelakex/uncore-other.json | 23 + 8 files changed, 1983 insertions(+), 1515 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools= /perf/pmu-events/arch/x86/cascadelakex/cache.json index ffafb9f284d2..732bf51e35af 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json @@ -314,6 +314,19 @@ "SampleAfterValue": "2000003", "UMask": "0x82" }, + { + "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "2000003", + "UMask": "0x83" + }, { "BriefDescription": "Retired load instructions with locked access.= ", "Counter": "0,1,2,3", @@ -358,6 +371,7 @@ "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, @@ -370,6 +384,7 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -759,7 +774,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010491", + "MSRValue": "0x10491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -801,7 +816,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0491", + "MSRValue": "0x8003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -815,7 +830,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0491", + "MSRValue": "0x4003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -829,7 +844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", + "MSRValue": "0x1003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -843,7 +858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0491", + "MSRValue": "0x8007C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -857,7 +872,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0491", + "MSRValue": "0x2003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -871,7 +886,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0491", + "MSRValue": "0x803C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -913,7 +928,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080491", + "MSRValue": "0x800080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -927,7 +942,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080491", + "MSRValue": "0x400080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -941,7 +956,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080491", + "MSRValue": "0x100080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -955,7 +970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080491", + "MSRValue": "0x200080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -969,7 +984,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080491", + "MSRValue": "0x80080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1011,7 +1026,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200491", + "MSRValue": "0x800200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1025,7 +1040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200491", + "MSRValue": "0x400200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1039,7 +1054,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200491", + "MSRValue": "0x100200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1053,7 +1068,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200491", + "MSRValue": "0x200200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1067,7 +1082,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200491", + "MSRValue": "0x80200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1109,7 +1124,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040491", + "MSRValue": "0x800040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1123,7 +1138,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040491", + "MSRValue": "0x400040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1137,7 +1152,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040491", + "MSRValue": "0x100040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1151,7 +1166,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040491", + "MSRValue": "0x200040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1165,7 +1180,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040491", + "MSRValue": "0x80040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1207,7 +1222,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100491", + "MSRValue": "0x800100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1221,7 +1236,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100491", + "MSRValue": "0x400100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1235,7 +1250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100491", + "MSRValue": "0x100100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1249,7 +1264,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100491", + "MSRValue": "0x200100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1263,7 +1278,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100491", + "MSRValue": "0x80100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1291,7 +1306,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400491", + "MSRValue": "0x80400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1305,7 +1320,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP= _NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400491", + "MSRValue": "0x100400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1347,7 +1362,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020491", + "MSRValue": "0x800020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1361,7 +1376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020491", + "MSRValue": "0x400020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1375,7 +1390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020491", + "MSRValue": "0x100020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1389,7 +1404,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020491", + "MSRValue": "0x200020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1403,7 +1418,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020491", + "MSRValue": "0x80020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1417,7 +1432,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010490", + "MSRValue": "0x10490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1459,7 +1474,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0490", + "MSRValue": "0x8003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1473,7 +1488,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0490", + "MSRValue": "0x4003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1487,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", + "MSRValue": "0x1003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1501,7 +1516,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0490", + "MSRValue": "0x8007C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1515,7 +1530,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0490", + "MSRValue": "0x2003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1529,7 +1544,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0490", + "MSRValue": "0x803C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1571,7 +1586,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080490", + "MSRValue": "0x800080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1585,7 +1600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080490", + "MSRValue": "0x400080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1599,7 +1614,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080490", + "MSRValue": "0x100080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1613,7 +1628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080490", + "MSRValue": "0x200080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1627,7 +1642,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080490", + "MSRValue": "0x80080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1669,7 +1684,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200490", + "MSRValue": "0x800200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1683,7 +1698,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200490", + "MSRValue": "0x400200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1697,7 +1712,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200490", + "MSRValue": "0x100200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1711,7 +1726,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200490", + "MSRValue": "0x200200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1725,7 +1740,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200490", + "MSRValue": "0x80200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1767,7 +1782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040490", + "MSRValue": "0x800040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1781,7 +1796,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040490", + "MSRValue": "0x400040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1795,7 +1810,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040490", + "MSRValue": "0x100040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1809,7 +1824,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040490", + "MSRValue": "0x200040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1823,7 +1838,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040490", + "MSRValue": "0x80040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1865,7 +1880,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100490", + "MSRValue": "0x800100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1879,7 +1894,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100490", + "MSRValue": "0x400100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1893,7 +1908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100490", + "MSRValue": "0x100100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1907,7 +1922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100490", + "MSRValue": "0x200100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1921,7 +1936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100490", + "MSRValue": "0x80100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1949,7 +1964,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400490", + "MSRValue": "0x80400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1963,7 +1978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400490", + "MSRValue": "0x100400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2005,7 +2020,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020490", + "MSRValue": "0x800020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2019,7 +2034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020490", + "MSRValue": "0x400020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2033,7 +2048,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020490", + "MSRValue": "0x100020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2047,7 +2062,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020490", + "MSRValue": "0x200020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2061,7 +2076,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020490", + "MSRValue": "0x80020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2075,7 +2090,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2117,7 +2132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0120", + "MSRValue": "0x8003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2131,7 +2146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2145,7 +2160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2159,7 +2174,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0120", + "MSRValue": "0x8007C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2173,7 +2188,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0120", + "MSRValue": "0x2003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2187,7 +2202,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0120", + "MSRValue": "0x803C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2229,7 +2244,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080120", + "MSRValue": "0x800080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2243,7 +2258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080120", + "MSRValue": "0x400080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2257,7 +2272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080120", + "MSRValue": "0x100080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2271,7 +2286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080120", + "MSRValue": "0x200080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2285,7 +2300,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080120", + "MSRValue": "0x80080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2327,7 +2342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200120", + "MSRValue": "0x800200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2341,7 +2356,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200120", + "MSRValue": "0x400200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2355,7 +2370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200120", + "MSRValue": "0x100200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2369,7 +2384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200120", + "MSRValue": "0x200200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2383,7 +2398,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200120", + "MSRValue": "0x80200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2425,7 +2440,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040120", + "MSRValue": "0x800040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2439,7 +2454,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040120", + "MSRValue": "0x400040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2453,7 +2468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040120", + "MSRValue": "0x100040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2467,7 +2482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040120", + "MSRValue": "0x200040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2481,7 +2496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040120", + "MSRValue": "0x80040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2523,7 +2538,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100120", + "MSRValue": "0x800100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2537,7 +2552,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100120", + "MSRValue": "0x400100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2551,7 +2566,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100120", + "MSRValue": "0x100100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2565,7 +2580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100120", + "MSRValue": "0x200100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2579,7 +2594,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100120", + "MSRValue": "0x80100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2607,7 +2622,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400120", + "MSRValue": "0x80400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2621,7 +2636,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400120", + "MSRValue": "0x100400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2663,7 +2678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020120", + "MSRValue": "0x800020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2677,7 +2692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020120", + "MSRValue": "0x400020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2691,7 +2706,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020120", + "MSRValue": "0x100020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2705,7 +2720,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020120", + "MSRValue": "0x200020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2719,7 +2734,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020120", + "MSRValue": "0x80020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2733,7 +2748,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00000107F7", + "MSRValue": "0x107F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2775,7 +2790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C07F7", + "MSRValue": "0x8003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2789,7 +2804,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C07F7", + "MSRValue": "0x4003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2803,7 +2818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C07F7", + "MSRValue": "0x1003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2817,7 +2832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C07F7", + "MSRValue": "0x8007C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2831,7 +2846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C07F7", + "MSRValue": "0x2003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2845,7 +2860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C07F7", + "MSRValue": "0x803C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2887,7 +2902,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000807F7", + "MSRValue": "0x8000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2901,7 +2916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000807F7", + "MSRValue": "0x4000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2915,7 +2930,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000807F7", + "MSRValue": "0x1000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2929,7 +2944,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000807F7", + "MSRValue": "0x2000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2943,7 +2958,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800807F7", + "MSRValue": "0x800807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2985,7 +3000,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08002007F7", + "MSRValue": "0x8002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2999,7 +3014,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04002007F7", + "MSRValue": "0x4002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3013,7 +3028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01002007F7", + "MSRValue": "0x1002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3027,7 +3042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02002007F7", + "MSRValue": "0x2002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3041,7 +3056,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00802007F7", + "MSRValue": "0x802007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3083,7 +3098,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000407F7", + "MSRValue": "0x8000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3097,7 +3112,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000407F7", + "MSRValue": "0x4000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3111,7 +3126,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000407F7", + "MSRValue": "0x1000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3125,7 +3140,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000407F7", + "MSRValue": "0x2000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3139,7 +3154,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800407F7", + "MSRValue": "0x800407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3181,7 +3196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08001007F7", + "MSRValue": "0x8001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3195,7 +3210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001007F7", + "MSRValue": "0x4001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3209,7 +3224,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001007F7", + "MSRValue": "0x1001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3223,7 +3238,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001007F7", + "MSRValue": "0x2001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3237,7 +3252,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801007F7", + "MSRValue": "0x801007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3265,7 +3280,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00804007F7", + "MSRValue": "0x804007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3279,7 +3294,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01004007F7", + "MSRValue": "0x1004007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3321,7 +3336,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000207F7", + "MSRValue": "0x8000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3335,7 +3350,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000207F7", + "MSRValue": "0x4000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3349,7 +3364,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000207F7", + "MSRValue": "0x1000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3363,7 +3378,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000207F7", + "MSRValue": "0x2000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3377,7 +3392,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800207F7", + "MSRValue": "0x800207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3391,7 +3406,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3433,7 +3448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0122", + "MSRValue": "0x8003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3447,7 +3462,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3461,7 +3476,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3475,7 +3490,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0122", + "MSRValue": "0x8007C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3489,7 +3504,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0122", + "MSRValue": "0x2003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3503,7 +3518,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0122", + "MSRValue": "0x803C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3545,7 +3560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080122", + "MSRValue": "0x800080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3559,7 +3574,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080122", + "MSRValue": "0x400080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3573,7 +3588,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080122", + "MSRValue": "0x100080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3587,7 +3602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080122", + "MSRValue": "0x200080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3601,7 +3616,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080122", + "MSRValue": "0x80080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3643,7 +3658,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200122", + "MSRValue": "0x800200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3657,7 +3672,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200122", + "MSRValue": "0x400200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3671,7 +3686,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200122", + "MSRValue": "0x100200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3685,7 +3700,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200122", + "MSRValue": "0x200200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3699,7 +3714,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200122", + "MSRValue": "0x80200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3741,7 +3756,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040122", + "MSRValue": "0x800040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3755,7 +3770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040122", + "MSRValue": "0x400040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3769,7 +3784,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040122", + "MSRValue": "0x100040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3783,7 +3798,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040122", + "MSRValue": "0x200040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3797,7 +3812,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040122", + "MSRValue": "0x80040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3839,7 +3854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100122", + "MSRValue": "0x800100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3853,7 +3868,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100122", + "MSRValue": "0x400100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3867,7 +3882,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100122", + "MSRValue": "0x100100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3881,7 +3896,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100122", + "MSRValue": "0x200100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3895,7 +3910,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100122", + "MSRValue": "0x80100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3923,7 +3938,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400122", + "MSRValue": "0x80400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3937,7 +3952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400122", + "MSRValue": "0x100400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3979,7 +3994,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020122", + "MSRValue": "0x800020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3993,7 +4008,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020122", + "MSRValue": "0x400020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4007,7 +4022,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020122", + "MSRValue": "0x100020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4021,7 +4036,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020122", + "MSRValue": "0x200020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4035,7 +4050,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020122", + "MSRValue": "0x80020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4049,7 +4064,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4091,7 +4106,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0004", + "MSRValue": "0x8003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4105,7 +4120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4119,7 +4134,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4133,7 +4148,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0004", + "MSRValue": "0x8007C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4147,7 +4162,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", + "MSRValue": "0x2003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4161,7 +4176,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0004", + "MSRValue": "0x803C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4203,7 +4218,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080004", + "MSRValue": "0x800080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4217,7 +4232,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080004", + "MSRValue": "0x400080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4231,7 +4246,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080004", + "MSRValue": "0x100080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4245,7 +4260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080004", + "MSRValue": "0x200080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4259,7 +4274,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080004", + "MSRValue": "0x80080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4301,7 +4316,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200004", + "MSRValue": "0x800200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4315,7 +4330,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200004", + "MSRValue": "0x400200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4329,7 +4344,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200004", + "MSRValue": "0x100200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4343,7 +4358,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200004", + "MSRValue": "0x200200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4357,7 +4372,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200004", + "MSRValue": "0x80200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4399,7 +4414,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040004", + "MSRValue": "0x800040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4413,7 +4428,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040004", + "MSRValue": "0x400040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4427,7 +4442,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040004", + "MSRValue": "0x100040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4441,7 +4456,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040004", + "MSRValue": "0x200040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4455,7 +4470,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040004", + "MSRValue": "0x80040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4497,7 +4512,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100004", + "MSRValue": "0x800100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4511,7 +4526,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100004", + "MSRValue": "0x400100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4525,7 +4540,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100004", + "MSRValue": "0x100100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4539,7 +4554,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100004", + "MSRValue": "0x200100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4553,7 +4568,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100004", + "MSRValue": "0x80100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4581,7 +4596,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400004", + "MSRValue": "0x80400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4595,7 +4610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", + "MSRValue": "0x100400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4637,7 +4652,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020004", + "MSRValue": "0x800020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4651,7 +4666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x400020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4665,7 +4680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x100020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4679,7 +4694,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x200020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4693,7 +4708,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4707,7 +4722,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4749,7 +4764,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0001", + "MSRValue": "0x8003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4763,7 +4778,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4777,7 +4792,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4791,7 +4806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0001", + "MSRValue": "0x8007C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4805,7 +4820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x2003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4819,7 +4834,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0001", + "MSRValue": "0x803C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4861,7 +4876,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080001", + "MSRValue": "0x800080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4875,7 +4890,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080001", + "MSRValue": "0x400080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4889,7 +4904,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080001", + "MSRValue": "0x100080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4903,7 +4918,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080001", + "MSRValue": "0x200080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4917,7 +4932,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080001", + "MSRValue": "0x80080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4959,7 +4974,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200001", + "MSRValue": "0x800200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4973,7 +4988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200001", + "MSRValue": "0x400200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4987,7 +5002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200001", + "MSRValue": "0x100200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5001,7 +5016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200001", + "MSRValue": "0x200200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5015,7 +5030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200001", + "MSRValue": "0x80200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5057,7 +5072,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040001", + "MSRValue": "0x800040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5071,7 +5086,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040001", + "MSRValue": "0x400040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5085,7 +5100,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040001", + "MSRValue": "0x100040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5099,7 +5114,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040001", + "MSRValue": "0x200040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5113,7 +5128,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040001", + "MSRValue": "0x80040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5155,7 +5170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100001", + "MSRValue": "0x800100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5169,7 +5184,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100001", + "MSRValue": "0x400100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5183,7 +5198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100001", + "MSRValue": "0x100100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5197,7 +5212,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100001", + "MSRValue": "0x200100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5211,7 +5226,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100001", + "MSRValue": "0x80100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5239,7 +5254,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400001", + "MSRValue": "0x80400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5253,7 +5268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", + "MSRValue": "0x100400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5295,7 +5310,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020001", + "MSRValue": "0x800020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5309,7 +5324,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x400020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5323,7 +5338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x100020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5337,7 +5352,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x200020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5351,7 +5366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x80020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5365,7 +5380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5407,7 +5422,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0002", + "MSRValue": "0x8003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5421,7 +5436,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5435,7 +5450,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5449,7 +5464,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0002", + "MSRValue": "0x8007C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5463,7 +5478,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x2003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5477,7 +5492,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0002", + "MSRValue": "0x803C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5519,7 +5534,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080002", + "MSRValue": "0x800080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5533,7 +5548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080002", + "MSRValue": "0x400080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5547,7 +5562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080002", + "MSRValue": "0x100080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5561,7 +5576,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080002", + "MSRValue": "0x200080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5575,7 +5590,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080002", + "MSRValue": "0x80080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5617,7 +5632,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200002", + "MSRValue": "0x800200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5631,7 +5646,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200002", + "MSRValue": "0x400200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5645,7 +5660,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200002", + "MSRValue": "0x100200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5659,7 +5674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200002", + "MSRValue": "0x200200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5673,7 +5688,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200002", + "MSRValue": "0x80200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5715,7 +5730,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040002", + "MSRValue": "0x800040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5729,7 +5744,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040002", + "MSRValue": "0x400040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5743,7 +5758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040002", + "MSRValue": "0x100040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5757,7 +5772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040002", + "MSRValue": "0x200040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5771,7 +5786,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040002", + "MSRValue": "0x80040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5813,7 +5828,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100002", + "MSRValue": "0x800100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5827,7 +5842,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100002", + "MSRValue": "0x400100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5841,7 +5856,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100002", + "MSRValue": "0x100100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5855,7 +5870,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100002", + "MSRValue": "0x200100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5869,7 +5884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100002", + "MSRValue": "0x80100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5897,7 +5912,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400002", + "MSRValue": "0x80400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5911,7 +5926,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", + "MSRValue": "0x100400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5953,7 +5968,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020002", + "MSRValue": "0x800020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5967,7 +5982,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020002", + "MSRValue": "0x400020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5981,7 +5996,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020002", + "MSRValue": "0x100020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5995,7 +6010,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020002", + "MSRValue": "0x200020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6009,7 +6024,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020002", + "MSRValue": "0x80020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6023,7 +6038,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x18000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6065,7 +6080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C8000", + "MSRValue": "0x8003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6079,7 +6094,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x4003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6093,7 +6108,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", + "MSRValue": "0x1003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6107,7 +6122,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C8000", + "MSRValue": "0x8007C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6121,7 +6136,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x2003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6135,7 +6150,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C8000", + "MSRValue": "0x803C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6177,7 +6192,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800088000", + "MSRValue": "0x800088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6191,7 +6206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400088000", + "MSRValue": "0x400088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6205,7 +6220,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100088000", + "MSRValue": "0x100088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6219,7 +6234,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200088000", + "MSRValue": "0x200088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6233,7 +6248,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080088000", + "MSRValue": "0x80088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6275,7 +6290,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800208000", + "MSRValue": "0x800208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6289,7 +6304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400208000", + "MSRValue": "0x400208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6303,7 +6318,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100208000", + "MSRValue": "0x100208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6317,7 +6332,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200208000", + "MSRValue": "0x200208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6331,7 +6346,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080208000", + "MSRValue": "0x80208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6373,7 +6388,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800048000", + "MSRValue": "0x800048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6387,7 +6402,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400048000", + "MSRValue": "0x400048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6401,7 +6416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100048000", + "MSRValue": "0x100048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6415,7 +6430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200048000", + "MSRValue": "0x200048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6429,7 +6444,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080048000", + "MSRValue": "0x80048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6471,7 +6486,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800108000", + "MSRValue": "0x800108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6485,7 +6500,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400108000", + "MSRValue": "0x400108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6499,7 +6514,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100108000", + "MSRValue": "0x100108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6513,7 +6528,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200108000", + "MSRValue": "0x200108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6527,7 +6542,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080108000", + "MSRValue": "0x80108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6555,7 +6570,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080408000", + "MSRValue": "0x80408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6569,7 +6584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100408000", + "MSRValue": "0x100408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6611,7 +6626,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800028000", + "MSRValue": "0x800028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6625,7 +6640,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x400028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6639,7 +6654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x100028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6653,7 +6668,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x200028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6667,7 +6682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x80028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6681,7 +6696,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x10400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6723,7 +6738,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0400", + "MSRValue": "0x8003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6737,7 +6752,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0400", + "MSRValue": "0x4003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6751,7 +6766,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x1003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6765,7 +6780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0400", + "MSRValue": "0x8007C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6779,7 +6794,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", + "MSRValue": "0x2003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6793,7 +6808,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0400", + "MSRValue": "0x803C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6835,7 +6850,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080400", + "MSRValue": "0x800080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6849,7 +6864,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080400", + "MSRValue": "0x400080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6863,7 +6878,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080400", + "MSRValue": "0x100080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6877,7 +6892,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080400", + "MSRValue": "0x200080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6891,7 +6906,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080400", + "MSRValue": "0x80080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6933,7 +6948,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200400", + "MSRValue": "0x800200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6947,7 +6962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200400", + "MSRValue": "0x400200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6961,7 +6976,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200400", + "MSRValue": "0x100200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6975,7 +6990,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200400", + "MSRValue": "0x200200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6989,7 +7004,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200400", + "MSRValue": "0x80200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7031,7 +7046,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040400", + "MSRValue": "0x800040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7045,7 +7060,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040400", + "MSRValue": "0x400040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7059,7 +7074,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040400", + "MSRValue": "0x100040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7073,7 +7088,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040400", + "MSRValue": "0x200040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7087,7 +7102,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040400", + "MSRValue": "0x80040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7129,7 +7144,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100400", + "MSRValue": "0x800100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7143,7 +7158,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100400", + "MSRValue": "0x400100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7157,7 +7172,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100400", + "MSRValue": "0x100100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7171,7 +7186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100400", + "MSRValue": "0x200100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7185,7 +7200,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100400", + "MSRValue": "0x80100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7213,7 +7228,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNO= OP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400400", + "MSRValue": "0x80400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7227,7 +7242,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNO= OP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400400", + "MSRValue": "0x100400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7269,7 +7284,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTH= ER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020400", + "MSRValue": "0x800020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7283,7 +7298,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTH= ER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020400", + "MSRValue": "0x400020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7297,7 +7312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOO= P_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020400", + "MSRValue": "0x100020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7311,7 +7326,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020400", + "MSRValue": "0x200020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7325,7 +7340,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020400", + "MSRValue": "0x80020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7339,7 +7354,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7381,7 +7396,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0010", + "MSRValue": "0x8003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7395,7 +7410,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7409,7 +7424,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7423,7 +7438,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0010", + "MSRValue": "0x8007C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7437,7 +7452,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x2003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7451,7 +7466,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0010", + "MSRValue": "0x803C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7493,7 +7508,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080010", + "MSRValue": "0x800080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7507,7 +7522,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080010", + "MSRValue": "0x400080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7521,7 +7536,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080010", + "MSRValue": "0x100080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7535,7 +7550,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080010", + "MSRValue": "0x200080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7549,7 +7564,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080010", + "MSRValue": "0x80080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7591,7 +7606,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200010", + "MSRValue": "0x800200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7605,7 +7620,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200010", + "MSRValue": "0x400200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7619,7 +7634,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200010", + "MSRValue": "0x100200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7633,7 +7648,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200010", + "MSRValue": "0x200200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7647,7 +7662,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200010", + "MSRValue": "0x80200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7689,7 +7704,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040010", + "MSRValue": "0x800040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7703,7 +7718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040010", + "MSRValue": "0x400040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7717,7 +7732,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040010", + "MSRValue": "0x100040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7731,7 +7746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040010", + "MSRValue": "0x200040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7745,7 +7760,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040010", + "MSRValue": "0x80040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7787,7 +7802,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100010", + "MSRValue": "0x800100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7801,7 +7816,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100010", + "MSRValue": "0x400100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7815,7 +7830,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100010", + "MSRValue": "0x100100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7829,7 +7844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100010", + "MSRValue": "0x200100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7843,7 +7858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100010", + "MSRValue": "0x80100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7871,7 +7886,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400010", + "MSRValue": "0x80400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7885,7 +7900,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400010", + "MSRValue": "0x100400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7927,7 +7942,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020010", + "MSRValue": "0x800020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7941,7 +7956,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020010", + "MSRValue": "0x400020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7955,7 +7970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOO= P_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020010", + "MSRValue": "0x100020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7969,7 +7984,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020010", + "MSRValue": "0x200020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7983,7 +7998,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020010", + "MSRValue": "0x80020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7997,7 +8012,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8039,7 +8054,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0020", + "MSRValue": "0x8003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8053,7 +8068,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8067,7 +8082,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8081,7 +8096,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0020", + "MSRValue": "0x8007C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8095,7 +8110,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8109,7 +8124,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0020", + "MSRValue": "0x803C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8151,7 +8166,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080020", + "MSRValue": "0x800080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8165,7 +8180,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080020", + "MSRValue": "0x400080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8179,7 +8194,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080020", + "MSRValue": "0x100080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8193,7 +8208,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080020", + "MSRValue": "0x200080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8207,7 +8222,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080020", + "MSRValue": "0x80080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8249,7 +8264,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200020", + "MSRValue": "0x800200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8263,7 +8278,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200020", + "MSRValue": "0x400200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8277,7 +8292,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200020", + "MSRValue": "0x100200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8291,7 +8306,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200020", + "MSRValue": "0x200200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8305,7 +8320,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200020", + "MSRValue": "0x80200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8347,7 +8362,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040020", + "MSRValue": "0x800040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8361,7 +8376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040020", + "MSRValue": "0x400040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8375,7 +8390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040020", + "MSRValue": "0x100040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8389,7 +8404,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040020", + "MSRValue": "0x200040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8403,7 +8418,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040020", + "MSRValue": "0x80040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8445,7 +8460,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100020", + "MSRValue": "0x800100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8459,7 +8474,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100020", + "MSRValue": "0x400100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8473,7 +8488,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100020", + "MSRValue": "0x100100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8487,7 +8502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100020", + "MSRValue": "0x200100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8501,7 +8516,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100020", + "MSRValue": "0x80100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8529,7 +8544,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400020", + "MSRValue": "0x80400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8543,7 +8558,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400020", + "MSRValue": "0x100400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8585,7 +8600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020020", + "MSRValue": "0x800020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8599,7 +8614,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020020", + "MSRValue": "0x400020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8613,7 +8628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020020", + "MSRValue": "0x100020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8627,7 +8642,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020020", + "MSRValue": "0x200020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8641,7 +8656,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020020", + "MSRValue": "0x80020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8655,7 +8670,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8697,7 +8712,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0080", + "MSRValue": "0x8003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8711,7 +8726,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8725,7 +8740,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8739,7 +8754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0080", + "MSRValue": "0x8007C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8753,7 +8768,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0080", + "MSRValue": "0x2003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8767,7 +8782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0080", + "MSRValue": "0x803C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8809,7 +8824,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080080", + "MSRValue": "0x800080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8823,7 +8838,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080080", + "MSRValue": "0x400080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8837,7 +8852,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080080", + "MSRValue": "0x100080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8851,7 +8866,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080080", + "MSRValue": "0x200080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8865,7 +8880,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080080", + "MSRValue": "0x80080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8907,7 +8922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200080", + "MSRValue": "0x800200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8921,7 +8936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200080", + "MSRValue": "0x400200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8935,7 +8950,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200080", + "MSRValue": "0x100200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8949,7 +8964,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200080", + "MSRValue": "0x200200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8963,7 +8978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200080", + "MSRValue": "0x80200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9005,7 +9020,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040080", + "MSRValue": "0x800040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9019,7 +9034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040080", + "MSRValue": "0x400040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9033,7 +9048,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040080", + "MSRValue": "0x100040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9047,7 +9062,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040080", + "MSRValue": "0x200040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9061,7 +9076,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040080", + "MSRValue": "0x80040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9103,7 +9118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100080", + "MSRValue": "0x800100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9117,7 +9132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100080", + "MSRValue": "0x400100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9131,7 +9146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100080", + "MSRValue": "0x100100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9145,7 +9160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100080", + "MSRValue": "0x200100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9159,7 +9174,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100080", + "MSRValue": "0x80100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9187,7 +9202,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400080", + "MSRValue": "0x80400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9201,7 +9216,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400080", + "MSRValue": "0x100400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9243,7 +9258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020080", + "MSRValue": "0x800020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9257,7 +9272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020080", + "MSRValue": "0x400020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9271,7 +9286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOO= P_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020080", + "MSRValue": "0x100020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9285,7 +9300,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020080", + "MSRValue": "0x200020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9299,7 +9314,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020080", + "MSRValue": "0x80020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9313,7 +9328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9355,7 +9370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0100", + "MSRValue": "0x8003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9369,7 +9384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9383,7 +9398,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9397,7 +9412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0100", + "MSRValue": "0x8007C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9411,7 +9426,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0100", + "MSRValue": "0x2003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9425,7 +9440,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0100", + "MSRValue": "0x803C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9467,7 +9482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080100", + "MSRValue": "0x800080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9481,7 +9496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080100", + "MSRValue": "0x400080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9495,7 +9510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080100", + "MSRValue": "0x100080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9509,7 +9524,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080100", + "MSRValue": "0x200080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9523,7 +9538,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080100", + "MSRValue": "0x80080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9565,7 +9580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200100", + "MSRValue": "0x800200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9579,7 +9594,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200100", + "MSRValue": "0x400200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9593,7 +9608,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200100", + "MSRValue": "0x100200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9607,7 +9622,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200100", + "MSRValue": "0x200200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9621,7 +9636,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200100", + "MSRValue": "0x80200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9663,7 +9678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040100", + "MSRValue": "0x800040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9677,7 +9692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040100", + "MSRValue": "0x400040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9691,7 +9706,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040100", + "MSRValue": "0x100040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9705,7 +9720,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040100", + "MSRValue": "0x200040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9719,7 +9734,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040100", + "MSRValue": "0x80040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9761,7 +9776,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100100", + "MSRValue": "0x800100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9775,7 +9790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100100", + "MSRValue": "0x400100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9789,7 +9804,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100100", + "MSRValue": "0x100100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9803,7 +9818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100100", + "MSRValue": "0x200100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9817,7 +9832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100100", + "MSRValue": "0x80100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9845,7 +9860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400100", + "MSRValue": "0x80400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9859,7 +9874,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400100", + "MSRValue": "0x100400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9901,7 +9916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020100", + "MSRValue": "0x800020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9915,7 +9930,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020100", + "MSRValue": "0x400020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9929,7 +9944,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020100", + "MSRValue": "0x100020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9943,7 +9958,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020100", + "MSRValue": "0x200020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9957,7 +9972,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020100", + "MSRValue": "0x80020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b= /tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 5d6b2e6fcb7b..5a1631448b46 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -1,26 +1,167 @@ [ + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNH= ALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * = CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK= _UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK= _UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCL= ES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNH= ALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_= RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALT= ED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * = CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES = / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_= RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNH= ALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIR= ED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) = * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS= _NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts_SMT", + "MetricName": "Mispredictions_SMT" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCL= E_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STA= LLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) -= (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RE= TIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB= _HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\= =3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MI= SS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RE= TIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MI= SS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETI= RED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOT= E_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (ME= M_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_L= OAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRA= M * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( = (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM= _LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (M= EM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_R= ETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_M= ISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.R= EMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) = ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYC= LE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNH= ALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HI= T / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_= LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_F= ULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY= .STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_= L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRE= D.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_C= LK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\= =3D4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CP= U_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.= STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT *= ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOA= D_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MIS= S) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.ST= ALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))= ) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_L= OAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MIS= S_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1= _MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HI= TM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( = ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_H= IT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_= DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM= _LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOA= D_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_= LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_= RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MI= SS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETI= RED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS= _L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CY= CLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RET= IRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ))= / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCL= E_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHA= LTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM= _LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( = CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_U= NHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_O= N_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (U= OPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_= PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED= .CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.R= ECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_= BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MI= SS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (ma= x( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU= _CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTI= VITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_POR= TS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE= _ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_N= OT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 = * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_= PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ))= * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ / CPU_CLK_UNHALTED.THREAD) / #(= max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / C= PU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_C= LK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STA= LLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( = 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_R= ETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) = )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALL= S_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) -= ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD= _RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_R= ETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MI= SS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM = * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 1= 9 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT = / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRA= M * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LO= AD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RET= IRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)= ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3= _MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE= _ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRE= D.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / = ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_A= CTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTE= D.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LO= AD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE= _ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY= .STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (= 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_A= CTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_= ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVER= Y_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min= ( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,= cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MI= SS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_AC= TIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L= 2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (= MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED= .L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTI= VITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.T= HREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 += (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD= _L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_R= ETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.RE= MOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) )= ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIR= ED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED= .LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ))= + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / = MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 = + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( ME= M_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRE= D.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LO= AD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY= .STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MI= SS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_L= OAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_M= ISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM= _LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * = (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_C= LK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PM= M + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) = + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CP= U_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * = ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) = * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_U= OPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_= ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_= UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_= UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / (= ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE= / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYC= LE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYC= LE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNH= ALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOU= ND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL = + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1= + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * E= XE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISS= UED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1= _MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D= 1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CY= CLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore_SMT", + "MetricName": "Memory_Bandwidth_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCL= E_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STA= LLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) -= (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RE= TIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB= _HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\= =3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MI= SS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RE= TIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MI= SS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETI= RED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOT= E_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (ME= M_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_L= OAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRA= M * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( = (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM= _LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (M= EM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_R= ETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_M= ISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.R= EMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) = ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYC= LE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNH= ALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HI= T / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_= LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_F= ULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY= .STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_= L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRE= D.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_C= LK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / C= PU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUES= TS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREAD)) / #= ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIV= ITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.TH= READ) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_= LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RET= IRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cm= ask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_= L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MI= SS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.= L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD= _RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.= REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) = + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / = MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOT= E_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10= * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT = / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1= + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_M= ISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED= .L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RE= TIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETI= RED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)= ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (= ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CL= K_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + = (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS= .FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACT= IVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_= LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_R= ETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_= ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.= STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TO= TAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CL= K_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_ST= ORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD))= - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALT= ED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.= REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHAL= TED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_t= ime)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOA= D_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STA= LLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) = + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD= _RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\= \=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_M= ISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EX= E_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY= .1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD))= * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_= UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.AN= Y + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_C= LK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STA= LLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( = 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_R= ETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) = )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALL= S_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) -= ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD= _RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_R= ETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MI= SS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM = * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 1= 9 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT = / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRA= M * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LO= AD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RET= IRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)= ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3= _MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE= _ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRE= D.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / = ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_A= CTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTE= D.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LO= AD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE= _ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY= .STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (= 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_A= CTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_= ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVER= Y_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min= ( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_R= D ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE= _REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREA= D)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCL= E_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHA= LTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT= / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_L= OAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FU= LL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.= STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOA= D_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (M= EM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_R= ETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MI= SS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB= _HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRE= D.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) = )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FW= D * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LO= AD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_= RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_= LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MI= SS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L= 1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THR= EAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) /= CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_R= ETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT *= ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CY= CLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 *= ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM= _LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS -= CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.= 5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000= 000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHAL= TED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED= .L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / = CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVI= TY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L= 2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (= MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED= .L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTI= VITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.T= HREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES= ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETI= RED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.= 2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVER= ED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 = * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) )))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore_SMT", + "MetricName": "Memory_Latency_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( (= CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK= _UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * c= pu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE = , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 )= ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYC= LE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_A= CTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTL= B_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BO= UND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Memory_Data_TLBs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - = CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (m= in( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WAL= K_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_M= ISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_= ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) += ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * = cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_STORE_MISSES.WALK_ACTI= VE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREA= D_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES = / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricName": "Memory_Data_TLBs_SMT" + }, + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_= RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITI= ONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 = * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_= RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITI= ONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "Ret_SMT", + "MetricName": "Branching_Overhead_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_= CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDA= TA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS= .ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_ST= ALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACH= E_16B.IFDATA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 = * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.= CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + C= PU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT", + "MetricName": "Big_Code_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK= _UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE /= (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MIS= P_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT= _DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (I= CACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STA= LL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHA= LTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_U= OPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))= )", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DE= LIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.= ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL= _BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_= MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_D= ELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) = * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))= ) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNH= ALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STAL= L\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / = CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "Fed;FetchBW;Frontend_SMT", + "MetricName": "Instruction_Fetch_BW_SMT" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -30,39 +171,84 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", + "MetricName": "SLOTS_SMT" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHAL= TED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "Flops_SMT", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -86,128 +272,255 @@ { "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.25= 6B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARI= TH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SI= NGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", - "MetricGroup": "LSD", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.C= ORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 *= CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELI= V.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS = - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_D= ELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NO= T_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_= 0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "DSBmiss;Fed_SMT", + "MetricName": "DSB_Misses_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT= _TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_= RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CON= DITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / B= R_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CORE_= CLKS )", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Offcore", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_C= LK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_Silent_PKI" }, { "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, { @@ -225,7 +538,7 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -234,6 +547,48 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License0_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. SMT versio= n; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1. SMT version; use when SMT is= enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License1_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions. = SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX). SMT vers= ion; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License2_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions. SMT version; use when SMT is= enabled and measuring per logical CPU." + }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", @@ -246,52 +601,64 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", "MetricExpr": "1000000000 * ( cha@event\\=3D0x36\\,umask\\=3D0x21\= \,config\\=3D0x40433@ / cha@event\\=3D0x35\\,umask\\=3D0x21\\,config\\=3D0x= 40433@ ) / ( cha_0@event\\=3D0x0@ / duration_time )", - "MetricGroup": "MemoryLat;SoC", + "MetricGroup": "Mem;MemoryLat;SoC", "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cha@event\\=3D0x36\\,umask\\=3D0x21\\,config\\=3D0x= 40433@ / cha@event\\=3D0x36\\,umask\\=3D0x21\\,config\\=3D0x40433\\,thresh\= \=3D1@", - "MetricGroup": "MemoryBW;SoC", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Average latency of data read request to exter= nal 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2= data-read prefetches", "MetricExpr": "( 1000000000 * ( imc@event\\=3D0xe0\\,umask\\=3D0x1= @ / imc@event\\=3D0xe3@ ) / imc_0@event\\=3D0x0@ )", - "MetricGroup": "MemoryLat;SoC;Server", + "MetricGroup": "Mem;MemoryLat;SoC;Server", "MetricName": "MEM_PMM_Read_Latency" }, + { + "BriefDescription": "Average latency of data read request to exter= nal DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-= read prefetches", + "MetricExpr": "1000000000 * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSE= RTS ) / imc_0@event\\=3D0x0@", + "MetricGroup": "Mem;MemoryLat;SoC;Server", + "MetricName": "MEM_DRAM_Read_Latency" + }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [= GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=3D0xe3@ / 1000000000 ) / durat= ion_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Read_BW" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes = [GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=3D0xe7@ / 1000000000 ) / durat= ion_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Writes [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_= DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + U= NC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Reads [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO= _DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 = + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / 1000000000 / duration_tim= e", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Read_BW" }, { diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json index ade925d7a68c..41a3d13fc4b2 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json @@ -1,37 +1,41 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -41,6 +45,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT= DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they p= erform 2 calculations per element. The DAZ and FTZ flags in the MXCSR regi= ster need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x40" }, @@ -50,27 +55,60 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR regi= ster need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x80" }, { - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computation. Applies to SS= E* and AVX* scalar double precision floating-point instructions: ADD SUB MU= L DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB in= structions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computation. Applies to SS= E* and AVX* scalar single precision floating-point instructions: ADD SUB MU= L DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB in= structions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Intel AVX-512 computational 512-bit packed BF= loat16 instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCF", + "EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16", + "PublicDescription": "Counts once for each Intel AVX-512 computati= onal 512-bit packed BFloat16 floating-point instruction retired. Applies to= the ZMM based VDPBF16PS instruction. Each count represents 64 computation= operations. This event is only supported on products formerly named Cooper= Lake and is not supported on products formerly named Cascade Lake.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Intel AVX-512 computational 128-bit packed BF= loat16 instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCF", + "EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16", + "PublicDescription": "Counts once for each Intel AVX-512 computati= onal 128-bit packed BFloat16 floating-point instruction retired. Applies to= the XMM based VDPBF16PS instruction. Each count represents 16 computation = operations. This event is only supported on products formerly named Cooper = Lake and is not supported on products formerly named Cascade Lake.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Intel AVX-512 computational 256-bit packed BF= loat16 instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCF", + "EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16", + "PublicDescription": "Counts once for each Intel AVX-512 computati= onal 256-bit packed BFloat16 floating-point instruction retired. Applies to= the YMM based VDPBF16PS instruction. Each count represents 32 computation= operations. This event is only supported on products formerly named Cooper= Lake and is not supported on products formerly named Cascade Lake.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/to= ols/perf/pmu-events/arch/x86/cascadelakex/frontend.json index 078706a50091..ecce4273ae52 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json @@ -30,7 +30,21 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired Instructions who experienced decode s= tream buffer (DSB - the decoded instruction-cache) miss.", + "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", @@ -38,7 +52,7 @@ "MSRIndex": "0x3F7", "MSRValue": "0x11", "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json b/tool= s/perf/pmu-events/arch/x86/cascadelakex/memory.json index 7c2adadca87e..ae55c35c2f19 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json @@ -260,7 +260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000491", + "MSRValue": "0x83C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -273,7 +273,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000491", + "MSRValue": "0x43C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -286,7 +286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000491", + "MSRValue": "0x13C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -312,7 +312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00491", + "MSRValue": "0x83FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -325,7 +325,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000491", + "MSRValue": "0x23C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -338,7 +338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000491", + "MSRValue": "0xBC000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -377,7 +377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000491", + "MSRValue": "0x804000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -390,7 +390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000491", + "MSRValue": "0x404000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -403,7 +403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000491", + "MSRValue": "0x104000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -416,7 +416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000491", + "MSRValue": "0x204000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -429,7 +429,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000491", + "MSRValue": "0x604000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -442,7 +442,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000491", + "MSRValue": "0x84000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -455,7 +455,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800491", + "MSRValue": "0x63B800491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -494,7 +494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000491", + "MSRValue": "0x810000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -507,7 +507,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000491", + "MSRValue": "0x410000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -520,7 +520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000491", + "MSRValue": "0x110000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -533,7 +533,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000491", + "MSRValue": "0x210000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -546,7 +546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000491", + "MSRValue": "0x90000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -585,7 +585,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000490", + "MSRValue": "0x83C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -598,7 +598,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000490", + "MSRValue": "0x43C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -611,7 +611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000490", + "MSRValue": "0x13C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -637,7 +637,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00490", + "MSRValue": "0x83FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -650,7 +650,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000490", + "MSRValue": "0x23C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -663,7 +663,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000490", + "MSRValue": "0xBC000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -702,7 +702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000490", + "MSRValue": "0x804000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -715,7 +715,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000490", + "MSRValue": "0x404000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000490", + "MSRValue": "0x104000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -741,7 +741,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000490", + "MSRValue": "0x204000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -754,7 +754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000490", + "MSRValue": "0x604000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -767,7 +767,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000490", + "MSRValue": "0x84000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -780,7 +780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800490", + "MSRValue": "0x63B800490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -819,7 +819,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000490", + "MSRValue": "0x810000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -832,7 +832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000490", + "MSRValue": "0x410000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000490", + "MSRValue": "0x110000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -858,7 +858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000490", + "MSRValue": "0x210000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -871,7 +871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000490", + "MSRValue": "0x90000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -910,7 +910,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000120", + "MSRValue": "0x83C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -923,7 +923,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000120", + "MSRValue": "0x43C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -936,7 +936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000120", + "MSRValue": "0x13C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00120", + "MSRValue": "0x83FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -975,7 +975,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000120", + "MSRValue": "0x23C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -988,7 +988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000120", + "MSRValue": "0xBC000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1027,7 +1027,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000120", + "MSRValue": "0x804000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1040,7 +1040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000120", + "MSRValue": "0x404000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1053,7 +1053,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000120", + "MSRValue": "0x104000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1066,7 +1066,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000120", + "MSRValue": "0x204000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000120", + "MSRValue": "0x604000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1092,7 +1092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000120", + "MSRValue": "0x84000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1105,7 +1105,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800120", + "MSRValue": "0x63B800120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1144,7 +1144,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000120", + "MSRValue": "0x810000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1157,7 +1157,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000120", + "MSRValue": "0x410000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1170,7 +1170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000120", + "MSRValue": "0x110000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1183,7 +1183,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000120", + "MSRValue": "0x210000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000120", + "MSRValue": "0x90000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1235,7 +1235,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C0007F7", + "MSRValue": "0x83C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1248,7 +1248,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C0007F7", + "MSRValue": "0x43C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1261,7 +1261,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C0007F7", + "MSRValue": "0x13C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1287,7 +1287,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC007F7", + "MSRValue": "0x83FC007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1300,7 +1300,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C0007F7", + "MSRValue": "0x23C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1313,7 +1313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC0007F7", + "MSRValue": "0xBC0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1352,7 +1352,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08040007F7", + "MSRValue": "0x8040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1365,7 +1365,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04040007F7", + "MSRValue": "0x4040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1378,7 +1378,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01040007F7", + "MSRValue": "0x1040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1391,7 +1391,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02040007F7", + "MSRValue": "0x2040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1404,7 +1404,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x06040007F7", + "MSRValue": "0x6040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1417,7 +1417,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00840007F7", + "MSRValue": "0x840007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1430,7 +1430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B8007F7", + "MSRValue": "0x63B8007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1469,7 +1469,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08100007F7", + "MSRValue": "0x8100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1482,7 +1482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04100007F7", + "MSRValue": "0x4100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1495,7 +1495,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01100007F7", + "MSRValue": "0x1100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1508,7 +1508,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02100007F7", + "MSRValue": "0x2100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1521,7 +1521,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00900007F7", + "MSRValue": "0x900007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1560,7 +1560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000122", + "MSRValue": "0x83C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1573,7 +1573,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000122", + "MSRValue": "0x43C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1586,7 +1586,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000122", + "MSRValue": "0x13C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1612,7 +1612,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00122", + "MSRValue": "0x83FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1625,7 +1625,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000122", + "MSRValue": "0x23C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1638,7 +1638,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000122", + "MSRValue": "0xBC000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1677,7 +1677,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000122", + "MSRValue": "0x804000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1690,7 +1690,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000122", + "MSRValue": "0x404000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1703,7 +1703,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000122", + "MSRValue": "0x104000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1716,7 +1716,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000122", + "MSRValue": "0x204000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1729,7 +1729,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000122", + "MSRValue": "0x604000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1742,7 +1742,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000122", + "MSRValue": "0x84000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1755,7 +1755,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800122", + "MSRValue": "0x63B800122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1794,7 +1794,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000122", + "MSRValue": "0x810000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1807,7 +1807,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000122", + "MSRValue": "0x410000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1820,7 +1820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000122", + "MSRValue": "0x110000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1833,7 +1833,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000122", + "MSRValue": "0x210000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1846,7 +1846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000122", + "MSRValue": "0x90000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1885,7 +1885,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000004", + "MSRValue": "0x83C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1898,7 +1898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000004", + "MSRValue": "0x43C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1911,7 +1911,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000004", + "MSRValue": "0x13C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1937,7 +1937,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00004", + "MSRValue": "0x83FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1950,7 +1950,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000004", + "MSRValue": "0x23C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1963,7 +1963,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000004", + "MSRValue": "0xBC000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2002,7 +2002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000004", + "MSRValue": "0x804000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2015,7 +2015,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x404000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2028,7 +2028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x104000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2041,7 +2041,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x204000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2054,7 +2054,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000004", + "MSRValue": "0x604000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2067,7 +2067,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x84000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2080,7 +2080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800004", + "MSRValue": "0x63B800004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2119,7 +2119,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000004", + "MSRValue": "0x810000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2132,7 +2132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000004", + "MSRValue": "0x410000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2145,7 +2145,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000004", + "MSRValue": "0x110000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2158,7 +2158,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000004", + "MSRValue": "0x210000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2171,7 +2171,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000004", + "MSRValue": "0x90000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2210,7 +2210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000001", + "MSRValue": "0x83C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2223,7 +2223,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000001", + "MSRValue": "0x43C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2236,7 +2236,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000001", + "MSRValue": "0x13C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2262,7 +2262,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00001", + "MSRValue": "0x83FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2275,7 +2275,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000001", + "MSRValue": "0x23C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2288,7 +2288,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000001", + "MSRValue": "0xBC000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2327,7 +2327,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000001", + "MSRValue": "0x804000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2340,7 +2340,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x404000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2353,7 +2353,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x104000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2366,7 +2366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x204000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2379,7 +2379,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000001", + "MSRValue": "0x604000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2392,7 +2392,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0x84000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2405,7 +2405,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800001", + "MSRValue": "0x63B800001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2444,7 +2444,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000001", + "MSRValue": "0x810000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2457,7 +2457,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000001", + "MSRValue": "0x410000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2470,7 +2470,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000001", + "MSRValue": "0x110000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2483,7 +2483,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000001", + "MSRValue": "0x210000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2496,7 +2496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000001", + "MSRValue": "0x90000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2535,7 +2535,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000002", + "MSRValue": "0x83C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2548,7 +2548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000002", + "MSRValue": "0x43C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2561,7 +2561,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000002", + "MSRValue": "0x13C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2587,7 +2587,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00002", + "MSRValue": "0x83FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2600,7 +2600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000002", + "MSRValue": "0x23C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2613,7 +2613,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000002", + "MSRValue": "0xBC000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2652,7 +2652,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000002", + "MSRValue": "0x804000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2665,7 +2665,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000002", + "MSRValue": "0x404000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2678,7 +2678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000002", + "MSRValue": "0x104000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2691,7 +2691,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000002", + "MSRValue": "0x204000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2704,7 +2704,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000002", + "MSRValue": "0x604000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2717,7 +2717,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000002", + "MSRValue": "0x84000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2730,7 +2730,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800002", + "MSRValue": "0x63B800002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2769,7 +2769,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000002", + "MSRValue": "0x810000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2782,7 +2782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000002", + "MSRValue": "0x410000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2795,7 +2795,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000002", + "MSRValue": "0x110000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2808,7 +2808,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000002", + "MSRValue": "0x210000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2821,7 +2821,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000002", + "MSRValue": "0x90000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2860,7 +2860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C008000", + "MSRValue": "0x83C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2873,7 +2873,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C008000", + "MSRValue": "0x43C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2886,7 +2886,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C008000", + "MSRValue": "0x13C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2912,7 +2912,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC08000", + "MSRValue": "0x83FC08000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2925,7 +2925,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C008000", + "MSRValue": "0x23C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2938,7 +2938,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC008000", + "MSRValue": "0xBC008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2977,7 +2977,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804008000", + "MSRValue": "0x804008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2990,7 +2990,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x404008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3003,7 +3003,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x104008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3016,7 +3016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x204008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3029,7 +3029,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604008000", + "MSRValue": "0x604008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3042,7 +3042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x84008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3055,7 +3055,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B808000", + "MSRValue": "0x63B808000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3094,7 +3094,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810008000", + "MSRValue": "0x810008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3107,7 +3107,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410008000", + "MSRValue": "0x410008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3120,7 +3120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110008000", + "MSRValue": "0x110008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3133,7 +3133,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210008000", + "MSRValue": "0x210008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3146,7 +3146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090008000", + "MSRValue": "0x90008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3185,7 +3185,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000400", + "MSRValue": "0x83C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3198,7 +3198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000400", + "MSRValue": "0x43C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3211,7 +3211,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000400", + "MSRValue": "0x13C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3237,7 +3237,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00400", + "MSRValue": "0x83FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3250,7 +3250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000400", + "MSRValue": "0x23C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3263,7 +3263,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000400", + "MSRValue": "0xBC000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3302,7 +3302,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000400", + "MSRValue": "0x804000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3315,7 +3315,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000400", + "MSRValue": "0x404000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3328,7 +3328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000400", + "MSRValue": "0x104000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3341,7 +3341,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000400", + "MSRValue": "0x204000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3354,7 +3354,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000400", + "MSRValue": "0x604000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3367,7 +3367,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000400", + "MSRValue": "0x84000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3380,7 +3380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800400", + "MSRValue": "0x63B800400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3419,7 +3419,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000400", + "MSRValue": "0x810000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3432,7 +3432,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000400", + "MSRValue": "0x410000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3445,7 +3445,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000400", + "MSRValue": "0x110000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3458,7 +3458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000400", + "MSRValue": "0x210000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3471,7 +3471,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000400", + "MSRValue": "0x90000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3510,7 +3510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000010", + "MSRValue": "0x83C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3523,7 +3523,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000010", + "MSRValue": "0x43C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3536,7 +3536,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000010", + "MSRValue": "0x13C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3562,7 +3562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00010", + "MSRValue": "0x83FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3575,7 +3575,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000010", + "MSRValue": "0x23C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3588,7 +3588,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000010", + "MSRValue": "0xBC000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3627,7 +3627,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000010", + "MSRValue": "0x804000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3640,7 +3640,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000010", + "MSRValue": "0x404000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3653,7 +3653,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000010", + "MSRValue": "0x104000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3666,7 +3666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000010", + "MSRValue": "0x204000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3679,7 +3679,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000010", + "MSRValue": "0x604000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3692,7 +3692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000010", + "MSRValue": "0x84000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3705,7 +3705,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800010", + "MSRValue": "0x63B800010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3744,7 +3744,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000010", + "MSRValue": "0x810000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3757,7 +3757,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000010", + "MSRValue": "0x410000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3770,7 +3770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000010", + "MSRValue": "0x110000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3783,7 +3783,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000010", + "MSRValue": "0x210000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3796,7 +3796,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000010", + "MSRValue": "0x90000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3835,7 +3835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000020", + "MSRValue": "0x83C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3848,7 +3848,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000020", + "MSRValue": "0x43C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3861,7 +3861,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000020", + "MSRValue": "0x13C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3887,7 +3887,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00020", + "MSRValue": "0x83FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3900,7 +3900,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000020", + "MSRValue": "0x23C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3913,7 +3913,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000020", + "MSRValue": "0xBC000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3952,7 +3952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000020", + "MSRValue": "0x804000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3965,7 +3965,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000020", + "MSRValue": "0x404000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3978,7 +3978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000020", + "MSRValue": "0x104000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3991,7 +3991,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000020", + "MSRValue": "0x204000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4004,7 +4004,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000020", + "MSRValue": "0x604000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4017,7 +4017,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000020", + "MSRValue": "0x84000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4030,7 +4030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800020", + "MSRValue": "0x63B800020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4069,7 +4069,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000020", + "MSRValue": "0x810000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4082,7 +4082,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000020", + "MSRValue": "0x410000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4095,7 +4095,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000020", + "MSRValue": "0x110000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4108,7 +4108,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000020", + "MSRValue": "0x210000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4121,7 +4121,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000020", + "MSRValue": "0x90000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4160,7 +4160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000080", + "MSRValue": "0x83C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4173,7 +4173,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000080", + "MSRValue": "0x43C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4186,7 +4186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000080", + "MSRValue": "0x13C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4212,7 +4212,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00080", + "MSRValue": "0x83FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4225,7 +4225,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000080", + "MSRValue": "0x23C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4238,7 +4238,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000080", + "MSRValue": "0xBC000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4277,7 +4277,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000080", + "MSRValue": "0x804000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4290,7 +4290,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000080", + "MSRValue": "0x404000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4303,7 +4303,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000080", + "MSRValue": "0x104000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4316,7 +4316,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000080", + "MSRValue": "0x204000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4329,7 +4329,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000080", + "MSRValue": "0x604000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4342,7 +4342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000080", + "MSRValue": "0x84000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4355,7 +4355,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800080", + "MSRValue": "0x63B800080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4394,7 +4394,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000080", + "MSRValue": "0x810000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4407,7 +4407,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000080", + "MSRValue": "0x410000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4420,7 +4420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000080", + "MSRValue": "0x110000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4433,7 +4433,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000080", + "MSRValue": "0x210000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4446,7 +4446,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000080", + "MSRValue": "0x90000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4485,7 +4485,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000100", + "MSRValue": "0x83C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4498,7 +4498,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000100", + "MSRValue": "0x43C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4511,7 +4511,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000100", + "MSRValue": "0x13C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4537,7 +4537,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00100", + "MSRValue": "0x83FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4550,7 +4550,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000100", + "MSRValue": "0x23C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4563,7 +4563,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000100", + "MSRValue": "0xBC000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4602,7 +4602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000100", + "MSRValue": "0x804000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4615,7 +4615,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000100", + "MSRValue": "0x404000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4628,7 +4628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000100", + "MSRValue": "0x104000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4641,7 +4641,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000100", + "MSRValue": "0x204000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4654,7 +4654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000100", + "MSRValue": "0x604000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4667,7 +4667,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000100", + "MSRValue": "0x84000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4680,7 +4680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800100", + "MSRValue": "0x63B800100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4719,7 +4719,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000100", + "MSRValue": "0x810000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4732,7 +4732,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000100", + "MSRValue": "0x410000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4745,7 +4745,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000100", + "MSRValue": "0x110000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4758,7 +4758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000100", + "MSRValue": "0x210000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4771,7 +4771,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000100", + "MSRValue": "0x90000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4852,7 +4852,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000491", + "MSRValue": "0x83C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4866,7 +4866,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000491", + "MSRValue": "0x43C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4880,7 +4880,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000491", + "MSRValue": "0x13C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4908,7 +4908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORW= ARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00491", + "MSRValue": "0x83FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4922,7 +4922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000491", + "MSRValue": "0x23C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4936,7 +4936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000491", + "MSRValue": "0xBC000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4978,7 +4978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_= OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000491", + "MSRValue": "0x804000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4992,7 +4992,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_= OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000491", + "MSRValue": "0x404000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5006,7 +5006,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_S= NOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000491", + "MSRValue": "0x104000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5020,7 +5020,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000491", + "MSRValue": "0x204000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5034,7 +5034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000491", + "MSRValue": "0x604000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5048,7 +5048,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000491", + "MSRValue": "0x84000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5062,7 +5062,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNO= OP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800491", + "MSRValue": "0x63B800491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5104,7 +5104,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000491", + "MSRValue": "0x810000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5118,7 +5118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000491", + "MSRValue": "0x410000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5132,7 +5132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000491", + "MSRValue": "0x110000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5146,7 +5146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000491", + "MSRValue": "0x210000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5160,7 +5160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000491", + "MSRValue": "0x90000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5202,7 +5202,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000490", + "MSRValue": "0x83C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5216,7 +5216,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000490", + "MSRValue": "0x43C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5230,7 +5230,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000490", + "MSRValue": "0x13C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5258,7 +5258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00490", + "MSRValue": "0x83FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5272,7 +5272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000490", + "MSRValue": "0x23C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5286,7 +5286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000490", + "MSRValue": "0xBC000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5328,7 +5328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000490", + "MSRValue": "0x804000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5342,7 +5342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000490", + "MSRValue": "0x404000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5356,7 +5356,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000490", + "MSRValue": "0x104000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5370,7 +5370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000490", + "MSRValue": "0x204000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5384,7 +5384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000490", + "MSRValue": "0x604000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5398,7 +5398,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000490", + "MSRValue": "0x84000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5412,7 +5412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800490", + "MSRValue": "0x63B800490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5454,7 +5454,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000490", + "MSRValue": "0x810000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5468,7 +5468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000490", + "MSRValue": "0x410000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5482,7 +5482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000490", + "MSRValue": "0x110000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5496,7 +5496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000490", + "MSRValue": "0x210000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5510,7 +5510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000490", + "MSRValue": "0x90000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5552,7 +5552,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000120", + "MSRValue": "0x83C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5566,7 +5566,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000120", + "MSRValue": "0x43C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5580,7 +5580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000120", + "MSRValue": "0x13C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5608,7 +5608,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00120", + "MSRValue": "0x83FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5622,7 +5622,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000120", + "MSRValue": "0x23C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5636,7 +5636,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000120", + "MSRValue": "0xBC000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5678,7 +5678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000120", + "MSRValue": "0x804000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5692,7 +5692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000120", + "MSRValue": "0x404000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5706,7 +5706,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SN= OOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000120", + "MSRValue": "0x104000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5720,7 +5720,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000120", + "MSRValue": "0x204000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5734,7 +5734,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000120", + "MSRValue": "0x604000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5748,7 +5748,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000120", + "MSRValue": "0x84000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5762,7 +5762,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800120", + "MSRValue": "0x63B800120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5804,7 +5804,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000120", + "MSRValue": "0x810000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5818,7 +5818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000120", + "MSRValue": "0x410000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5832,7 +5832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000120", + "MSRValue": "0x110000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5846,7 +5846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000120", + "MSRValue": "0x210000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5860,7 +5860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000120", + "MSRValue": "0x90000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5902,7 +5902,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C0007F7", + "MSRValue": "0x83C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5916,7 +5916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C0007F7", + "MSRValue": "0x43C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5930,7 +5930,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C0007F7", + "MSRValue": "0x13C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5958,7 +5958,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC007F7", + "MSRValue": "0x83FC007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5972,7 +5972,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C0007F7", + "MSRValue": "0x23C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5986,7 +5986,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC0007F7", + "MSRValue": "0xBC0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6028,7 +6028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08040007F7", + "MSRValue": "0x8040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6042,7 +6042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04040007F7", + "MSRValue": "0x4040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6056,7 +6056,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01040007F7", + "MSRValue": "0x1040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6070,7 +6070,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02040007F7", + "MSRValue": "0x2040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6084,7 +6084,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x06040007F7", + "MSRValue": "0x6040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6098,7 +6098,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00840007F7", + "MSRValue": "0x840007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6112,7 +6112,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B8007F7", + "MSRValue": "0x63B8007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6154,7 +6154,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08100007F7", + "MSRValue": "0x8100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6168,7 +6168,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04100007F7", + "MSRValue": "0x4100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6182,7 +6182,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01100007F7", + "MSRValue": "0x1100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6196,7 +6196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02100007F7", + "MSRValue": "0x2100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6210,7 +6210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00900007F7", + "MSRValue": "0x900007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6252,7 +6252,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000122", + "MSRValue": "0x83C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6266,7 +6266,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000122", + "MSRValue": "0x43C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6280,7 +6280,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000122", + "MSRValue": "0x13C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6308,7 +6308,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00122", + "MSRValue": "0x83FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6322,7 +6322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000122", + "MSRValue": "0x23C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6336,7 +6336,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000122", + "MSRValue": "0xBC000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6378,7 +6378,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000122", + "MSRValue": "0x804000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6392,7 +6392,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000122", + "MSRValue": "0x404000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6406,7 +6406,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000122", + "MSRValue": "0x104000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6420,7 +6420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000122", + "MSRValue": "0x204000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6434,7 +6434,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000122", + "MSRValue": "0x604000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6448,7 +6448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000122", + "MSRValue": "0x84000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6462,7 +6462,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_M= ISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800122", + "MSRValue": "0x63B800122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6504,7 +6504,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HI= T_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000122", + "MSRValue": "0x810000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6518,7 +6518,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HI= T_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000122", + "MSRValue": "0x410000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6532,7 +6532,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000122", + "MSRValue": "0x110000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6546,7 +6546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000122", + "MSRValue": "0x210000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6560,7 +6560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000122", + "MSRValue": "0x90000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6602,7 +6602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000004", + "MSRValue": "0x83C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6616,7 +6616,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000004", + "MSRValue": "0x43C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6630,7 +6630,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000004", + "MSRValue": "0x13C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6658,7 +6658,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00004", + "MSRValue": "0x83FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6672,7 +6672,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000004", + "MSRValue": "0x23C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6686,7 +6686,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000004", + "MSRValue": "0xBC000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6728,7 +6728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000004", + "MSRValue": "0x804000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6742,7 +6742,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x404000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6756,7 +6756,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x104000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6770,7 +6770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x204000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6784,7 +6784,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000004", + "MSRValue": "0x604000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6798,7 +6798,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x84000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6812,7 +6812,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800004", + "MSRValue": "0x63B800004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6854,7 +6854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000004", + "MSRValue": "0x810000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6868,7 +6868,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000004", + "MSRValue": "0x410000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6882,7 +6882,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000004", + "MSRValue": "0x110000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6896,7 +6896,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000004", + "MSRValue": "0x210000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6910,7 +6910,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000004", + "MSRValue": "0x90000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6952,7 +6952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000001", + "MSRValue": "0x83C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6966,7 +6966,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000001", + "MSRValue": "0x43C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6980,7 +6980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000001", + "MSRValue": "0x13C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7008,7 +7008,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00001", + "MSRValue": "0x83FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7022,7 +7022,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000001", + "MSRValue": "0x23C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7036,7 +7036,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000001", + "MSRValue": "0xBC000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7078,7 +7078,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000001", + "MSRValue": "0x804000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7092,7 +7092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x404000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7106,7 +7106,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x104000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7120,7 +7120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x204000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7134,7 +7134,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000001", + "MSRValue": "0x604000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7148,7 +7148,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0x84000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7162,7 +7162,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800001", + "MSRValue": "0x63B800001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7204,7 +7204,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000001", + "MSRValue": "0x810000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7218,7 +7218,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000001", + "MSRValue": "0x410000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7232,7 +7232,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000001", + "MSRValue": "0x110000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7246,7 +7246,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000001", + "MSRValue": "0x210000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7260,7 +7260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000001", + "MSRValue": "0x90000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7302,7 +7302,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000002", + "MSRValue": "0x83C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7316,7 +7316,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000002", + "MSRValue": "0x43C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7330,7 +7330,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000002", + "MSRValue": "0x13C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7358,7 +7358,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00002", + "MSRValue": "0x83FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7372,7 +7372,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000002", + "MSRValue": "0x23C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7386,7 +7386,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000002", + "MSRValue": "0xBC000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7428,7 +7428,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000002", + "MSRValue": "0x804000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7442,7 +7442,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000002", + "MSRValue": "0x404000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7456,7 +7456,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SN= OOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000002", + "MSRValue": "0x104000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7470,7 +7470,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000002", + "MSRValue": "0x204000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7484,7 +7484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000002", + "MSRValue": "0x604000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7498,7 +7498,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000002", + "MSRValue": "0x84000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7512,7 +7512,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800002", + "MSRValue": "0x63B800002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7554,7 +7554,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000002", + "MSRValue": "0x810000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7568,7 +7568,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000002", + "MSRValue": "0x410000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7582,7 +7582,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000002", + "MSRValue": "0x110000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7596,7 +7596,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000002", + "MSRValue": "0x210000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7610,7 +7610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000002", + "MSRValue": "0x90000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7652,7 +7652,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C008000", + "MSRValue": "0x83C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7666,7 +7666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C008000", + "MSRValue": "0x43C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7680,7 +7680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C008000", + "MSRValue": "0x13C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7708,7 +7708,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC08000", + "MSRValue": "0x83FC08000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7722,7 +7722,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C008000", + "MSRValue": "0x23C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7736,7 +7736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC008000", + "MSRValue": "0xBC008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7778,7 +7778,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_= CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804008000", + "MSRValue": "0x804008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7792,7 +7792,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_= CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x404008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7806,7 +7806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x104008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7820,7 +7820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x204008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7834,7 +7834,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= _OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604008000", + "MSRValue": "0x604008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7848,7 +7848,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x84008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7862,7 +7862,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MIS= S_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B808000", + "MSRValue": "0x63B808000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7904,7 +7904,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_= OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810008000", + "MSRValue": "0x810008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7918,7 +7918,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_= OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410008000", + "MSRValue": "0x410008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7932,7 +7932,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_S= NOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110008000", + "MSRValue": "0x110008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7946,7 +7946,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210008000", + "MSRValue": "0x210008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7960,7 +7960,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090008000", + "MSRValue": "0x90008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8002,7 +8002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000400", + "MSRValue": "0x83C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8016,7 +8016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000400", + "MSRValue": "0x43C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8030,7 +8030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000400", + "MSRValue": "0x13C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8058,7 +8058,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00400", + "MSRValue": "0x83FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8072,7 +8072,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000400", + "MSRValue": "0x23C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8086,7 +8086,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000400", + "MSRValue": "0xBC000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8128,7 +8128,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000400", + "MSRValue": "0x804000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8142,7 +8142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000400", + "MSRValue": "0x404000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8156,7 +8156,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000400", + "MSRValue": "0x104000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8170,7 +8170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000400", + "MSRValue": "0x204000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8184,7 +8184,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000400", + "MSRValue": "0x604000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8198,7 +8198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000400", + "MSRValue": "0x84000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8212,7 +8212,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800400", + "MSRValue": "0x63B800400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8254,7 +8254,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000400", + "MSRValue": "0x810000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8268,7 +8268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000400", + "MSRValue": "0x410000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8282,7 +8282,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000400", + "MSRValue": "0x110000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8296,7 +8296,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000400", + "MSRValue": "0x210000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8310,7 +8310,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000400", + "MSRValue": "0x90000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8352,7 +8352,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000010", + "MSRValue": "0x83C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8366,7 +8366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000010", + "MSRValue": "0x43C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8380,7 +8380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000010", + "MSRValue": "0x13C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8408,7 +8408,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00010", + "MSRValue": "0x83FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8422,7 +8422,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000010", + "MSRValue": "0x23C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8436,7 +8436,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000010", + "MSRValue": "0xBC000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8478,7 +8478,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000010", + "MSRValue": "0x804000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8492,7 +8492,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000010", + "MSRValue": "0x404000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8506,7 +8506,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000010", + "MSRValue": "0x104000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8520,7 +8520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000010", + "MSRValue": "0x204000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8534,7 +8534,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000010", + "MSRValue": "0x604000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8548,7 +8548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000010", + "MSRValue": "0x84000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8562,7 +8562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800010", + "MSRValue": "0x63B800010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8604,7 +8604,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000010", + "MSRValue": "0x810000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8618,7 +8618,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000010", + "MSRValue": "0x410000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8632,7 +8632,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000010", + "MSRValue": "0x110000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8646,7 +8646,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000010", + "MSRValue": "0x210000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8660,7 +8660,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000010", + "MSRValue": "0x90000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8702,7 +8702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000020", + "MSRValue": "0x83C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8716,7 +8716,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000020", + "MSRValue": "0x43C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8730,7 +8730,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000020", + "MSRValue": "0x13C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8758,7 +8758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00020", + "MSRValue": "0x83FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8772,7 +8772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000020", + "MSRValue": "0x23C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8786,7 +8786,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000020", + "MSRValue": "0xBC000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8828,7 +8828,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000020", + "MSRValue": "0x804000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8842,7 +8842,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000020", + "MSRValue": "0x404000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8856,7 +8856,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000020", + "MSRValue": "0x104000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8870,7 +8870,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000020", + "MSRValue": "0x204000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8884,7 +8884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000020", + "MSRValue": "0x604000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8898,7 +8898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000020", + "MSRValue": "0x84000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8912,7 +8912,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800020", + "MSRValue": "0x63B800020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8954,7 +8954,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000020", + "MSRValue": "0x810000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8968,7 +8968,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000020", + "MSRValue": "0x410000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8982,7 +8982,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000020", + "MSRValue": "0x110000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8996,7 +8996,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000020", + "MSRValue": "0x210000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9010,7 +9010,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000020", + "MSRValue": "0x90000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9052,7 +9052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000080", + "MSRValue": "0x83C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9066,7 +9066,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000080", + "MSRValue": "0x43C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9080,7 +9080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000080", + "MSRValue": "0x13C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9108,7 +9108,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00080", + "MSRValue": "0x83FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9122,7 +9122,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000080", + "MSRValue": "0x23C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9136,7 +9136,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000080", + "MSRValue": "0xBC000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9178,7 +9178,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000080", + "MSRValue": "0x804000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9192,7 +9192,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000080", + "MSRValue": "0x404000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9206,7 +9206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000080", + "MSRValue": "0x104000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9220,7 +9220,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000080", + "MSRValue": "0x204000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9234,7 +9234,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000080", + "MSRValue": "0x604000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9248,7 +9248,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000080", + "MSRValue": "0x84000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9262,7 +9262,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800080", + "MSRValue": "0x63B800080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9304,7 +9304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000080", + "MSRValue": "0x810000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9318,7 +9318,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000080", + "MSRValue": "0x410000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9332,7 +9332,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000080", + "MSRValue": "0x110000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9346,7 +9346,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000080", + "MSRValue": "0x210000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9360,7 +9360,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000080", + "MSRValue": "0x90000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9402,7 +9402,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000100", + "MSRValue": "0x83C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9416,7 +9416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000100", + "MSRValue": "0x43C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9430,7 +9430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000100", + "MSRValue": "0x13C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9458,7 +9458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00100", + "MSRValue": "0x83FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9472,7 +9472,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000100", + "MSRValue": "0x23C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9486,7 +9486,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000100", + "MSRValue": "0xBC000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9528,7 +9528,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000100", + "MSRValue": "0x804000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9542,7 +9542,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000100", + "MSRValue": "0x404000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9556,7 +9556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000100", + "MSRValue": "0x104000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9570,7 +9570,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000100", + "MSRValue": "0x204000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9584,7 +9584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000100", + "MSRValue": "0x604000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9598,7 +9598,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000100", + "MSRValue": "0x84000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9612,7 +9612,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800100", + "MSRValue": "0x63B800100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9654,7 +9654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000100", + "MSRValue": "0x810000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9668,7 +9668,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000100", + "MSRValue": "0x410000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9682,7 +9682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000100", + "MSRValue": "0x110000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9696,7 +9696,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000100", + "MSRValue": "0x210000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -9710,7 +9710,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000100", + "MSRValue": "0x90000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools= /perf/pmu-events/arch/x86/cascadelakex/other.json index 2f111a22d81f..d8b145a7d303 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json @@ -76,7 +76,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010491", + "MSRValue": "0x10491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -115,7 +115,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0491", + "MSRValue": "0x8003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -128,7 +128,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0491", + "MSRValue": "0x4003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -141,7 +141,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", + "MSRValue": "0x1003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -154,7 +154,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0491", + "MSRValue": "0x8007C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -167,7 +167,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0491", + "MSRValue": "0x2003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -180,7 +180,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0491", + "MSRValue": "0x803C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -219,7 +219,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080491", + "MSRValue": "0x800080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -232,7 +232,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080491", + "MSRValue": "0x400080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -245,7 +245,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080491", + "MSRValue": "0x100080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -258,7 +258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080491", + "MSRValue": "0x200080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -271,7 +271,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080491", + "MSRValue": "0x80080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -310,7 +310,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200491", + "MSRValue": "0x800200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -323,7 +323,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200491", + "MSRValue": "0x400200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -336,7 +336,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200491", + "MSRValue": "0x100200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -349,7 +349,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200491", + "MSRValue": "0x200200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -362,7 +362,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200491", + "MSRValue": "0x80200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -401,7 +401,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040491", + "MSRValue": "0x800040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -414,7 +414,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040491", + "MSRValue": "0x400040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -427,7 +427,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040491", + "MSRValue": "0x100040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -440,7 +440,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040491", + "MSRValue": "0x200040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -453,7 +453,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040491", + "MSRValue": "0x80040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -492,7 +492,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100491", + "MSRValue": "0x800100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -505,7 +505,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100491", + "MSRValue": "0x400100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -518,7 +518,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100491", + "MSRValue": "0x100100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -531,7 +531,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100491", + "MSRValue": "0x200100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -544,7 +544,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100491", + "MSRValue": "0x80100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -570,7 +570,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400491", + "MSRValue": "0x80400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -583,7 +583,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400491", + "MSRValue": "0x100400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -622,7 +622,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020491", + "MSRValue": "0x800020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -635,7 +635,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020491", + "MSRValue": "0x400020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -648,7 +648,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020491", + "MSRValue": "0x100020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -661,7 +661,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020491", + "MSRValue": "0x200020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -674,7 +674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020491", + "MSRValue": "0x80020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -687,7 +687,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010490", + "MSRValue": "0x10490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -726,7 +726,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0490", + "MSRValue": "0x8003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -739,7 +739,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0490", + "MSRValue": "0x4003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -752,7 +752,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", + "MSRValue": "0x1003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -765,7 +765,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0490", + "MSRValue": "0x8007C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -778,7 +778,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0490", + "MSRValue": "0x2003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -791,7 +791,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0490", + "MSRValue": "0x803C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -830,7 +830,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080490", + "MSRValue": "0x800080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -843,7 +843,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080490", + "MSRValue": "0x400080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -856,7 +856,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080490", + "MSRValue": "0x100080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -869,7 +869,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080490", + "MSRValue": "0x200080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -882,7 +882,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080490", + "MSRValue": "0x80080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -921,7 +921,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200490", + "MSRValue": "0x800200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -934,7 +934,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200490", + "MSRValue": "0x400200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -947,7 +947,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200490", + "MSRValue": "0x100200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -960,7 +960,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200490", + "MSRValue": "0x200200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -973,7 +973,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200490", + "MSRValue": "0x80200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1012,7 +1012,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040490", + "MSRValue": "0x800040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1025,7 +1025,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040490", + "MSRValue": "0x400040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1038,7 +1038,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040490", + "MSRValue": "0x100040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1051,7 +1051,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040490", + "MSRValue": "0x200040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1064,7 +1064,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040490", + "MSRValue": "0x80040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1103,7 +1103,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100490", + "MSRValue": "0x800100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1116,7 +1116,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100490", + "MSRValue": "0x400100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1129,7 +1129,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100490", + "MSRValue": "0x100100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1142,7 +1142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100490", + "MSRValue": "0x200100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1155,7 +1155,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100490", + "MSRValue": "0x80100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1181,7 +1181,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400490", + "MSRValue": "0x80400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1194,7 +1194,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400490", + "MSRValue": "0x100400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1233,7 +1233,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020490", + "MSRValue": "0x800020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1246,7 +1246,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020490", + "MSRValue": "0x400020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1259,7 +1259,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020490", + "MSRValue": "0x100020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1272,7 +1272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020490", + "MSRValue": "0x200020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1285,7 +1285,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020490", + "MSRValue": "0x80020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1298,7 +1298,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1337,7 +1337,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0120", + "MSRValue": "0x8003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1350,7 +1350,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1363,7 +1363,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1376,7 +1376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0120", + "MSRValue": "0x8007C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1389,7 +1389,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0120", + "MSRValue": "0x2003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1402,7 +1402,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0120", + "MSRValue": "0x803C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1441,7 +1441,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080120", + "MSRValue": "0x800080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1454,7 +1454,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080120", + "MSRValue": "0x400080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1467,7 +1467,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080120", + "MSRValue": "0x100080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1480,7 +1480,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080120", + "MSRValue": "0x200080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1493,7 +1493,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080120", + "MSRValue": "0x80080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1532,7 +1532,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200120", + "MSRValue": "0x800200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1545,7 +1545,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200120", + "MSRValue": "0x400200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1558,7 +1558,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200120", + "MSRValue": "0x100200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1571,7 +1571,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200120", + "MSRValue": "0x200200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1584,7 +1584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200120", + "MSRValue": "0x80200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1623,7 +1623,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040120", + "MSRValue": "0x800040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1636,7 +1636,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040120", + "MSRValue": "0x400040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1649,7 +1649,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040120", + "MSRValue": "0x100040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1662,7 +1662,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040120", + "MSRValue": "0x200040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1675,7 +1675,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040120", + "MSRValue": "0x80040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1714,7 +1714,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100120", + "MSRValue": "0x800100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1727,7 +1727,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100120", + "MSRValue": "0x400100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1740,7 +1740,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100120", + "MSRValue": "0x100100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1753,7 +1753,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100120", + "MSRValue": "0x200100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1766,7 +1766,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100120", + "MSRValue": "0x80100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1792,7 +1792,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400120", + "MSRValue": "0x80400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1805,7 +1805,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400120", + "MSRValue": "0x100400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1844,7 +1844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020120", + "MSRValue": "0x800020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1857,7 +1857,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020120", + "MSRValue": "0x400020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1870,7 +1870,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020120", + "MSRValue": "0x100020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1883,7 +1883,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020120", + "MSRValue": "0x200020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1896,7 +1896,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020120", + "MSRValue": "0x80020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1909,7 +1909,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00000107F7", + "MSRValue": "0x107F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1948,7 +1948,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C07F7", + "MSRValue": "0x8003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1961,7 +1961,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C07F7", + "MSRValue": "0x4003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1974,7 +1974,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C07F7", + "MSRValue": "0x1003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -1987,7 +1987,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C07F7", + "MSRValue": "0x8007C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2000,7 +2000,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C07F7", + "MSRValue": "0x2003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2013,7 +2013,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C07F7", + "MSRValue": "0x803C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2052,7 +2052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000807F7", + "MSRValue": "0x8000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2065,7 +2065,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000807F7", + "MSRValue": "0x4000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2078,7 +2078,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000807F7", + "MSRValue": "0x1000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2091,7 +2091,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000807F7", + "MSRValue": "0x2000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2104,7 +2104,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800807F7", + "MSRValue": "0x800807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2143,7 +2143,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08002007F7", + "MSRValue": "0x8002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2156,7 +2156,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04002007F7", + "MSRValue": "0x4002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2169,7 +2169,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01002007F7", + "MSRValue": "0x1002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2182,7 +2182,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02002007F7", + "MSRValue": "0x2002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2195,7 +2195,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00802007F7", + "MSRValue": "0x802007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2234,7 +2234,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000407F7", + "MSRValue": "0x8000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2247,7 +2247,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000407F7", + "MSRValue": "0x4000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2260,7 +2260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000407F7", + "MSRValue": "0x1000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2273,7 +2273,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000407F7", + "MSRValue": "0x2000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2286,7 +2286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800407F7", + "MSRValue": "0x800407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2325,7 +2325,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08001007F7", + "MSRValue": "0x8001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2338,7 +2338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001007F7", + "MSRValue": "0x4001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2351,7 +2351,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001007F7", + "MSRValue": "0x1001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2364,7 +2364,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001007F7", + "MSRValue": "0x2001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2377,7 +2377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801007F7", + "MSRValue": "0x801007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2403,7 +2403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00804007F7", + "MSRValue": "0x804007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2416,7 +2416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01004007F7", + "MSRValue": "0x1004007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2455,7 +2455,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000207F7", + "MSRValue": "0x8000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2468,7 +2468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000207F7", + "MSRValue": "0x4000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2481,7 +2481,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000207F7", + "MSRValue": "0x1000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2494,7 +2494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000207F7", + "MSRValue": "0x2000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2507,7 +2507,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800207F7", + "MSRValue": "0x800207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2520,7 +2520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2559,7 +2559,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0122", + "MSRValue": "0x8003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2572,7 +2572,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2585,7 +2585,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2598,7 +2598,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0122", + "MSRValue": "0x8007C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2611,7 +2611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0122", + "MSRValue": "0x2003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2624,7 +2624,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0122", + "MSRValue": "0x803C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2663,7 +2663,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080122", + "MSRValue": "0x800080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2676,7 +2676,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080122", + "MSRValue": "0x400080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2689,7 +2689,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080122", + "MSRValue": "0x100080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2702,7 +2702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080122", + "MSRValue": "0x200080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2715,7 +2715,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080122", + "MSRValue": "0x80080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2754,7 +2754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200122", + "MSRValue": "0x800200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2767,7 +2767,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200122", + "MSRValue": "0x400200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2780,7 +2780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200122", + "MSRValue": "0x100200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2793,7 +2793,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200122", + "MSRValue": "0x200200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2806,7 +2806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200122", + "MSRValue": "0x80200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2845,7 +2845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040122", + "MSRValue": "0x800040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2858,7 +2858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040122", + "MSRValue": "0x400040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2871,7 +2871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040122", + "MSRValue": "0x100040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2884,7 +2884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040122", + "MSRValue": "0x200040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2897,7 +2897,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040122", + "MSRValue": "0x80040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2936,7 +2936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100122", + "MSRValue": "0x800100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2949,7 +2949,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100122", + "MSRValue": "0x400100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2962,7 +2962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100122", + "MSRValue": "0x100100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2975,7 +2975,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100122", + "MSRValue": "0x200100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -2988,7 +2988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100122", + "MSRValue": "0x80100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3014,7 +3014,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400122", + "MSRValue": "0x80400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3027,7 +3027,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400122", + "MSRValue": "0x100400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3066,7 +3066,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020122", + "MSRValue": "0x800020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3079,7 +3079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020122", + "MSRValue": "0x400020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3092,7 +3092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020122", + "MSRValue": "0x100020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3105,7 +3105,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020122", + "MSRValue": "0x200020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3118,7 +3118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020122", + "MSRValue": "0x80020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3131,7 +3131,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3170,7 +3170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0004", + "MSRValue": "0x8003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3183,7 +3183,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3196,7 +3196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3209,7 +3209,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0004", + "MSRValue": "0x8007C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3222,7 +3222,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", + "MSRValue": "0x2003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3235,7 +3235,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0004", + "MSRValue": "0x803C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3274,7 +3274,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080004", + "MSRValue": "0x800080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3287,7 +3287,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080004", + "MSRValue": "0x400080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3300,7 +3300,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080004", + "MSRValue": "0x100080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3313,7 +3313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080004", + "MSRValue": "0x200080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3326,7 +3326,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080004", + "MSRValue": "0x80080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3365,7 +3365,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200004", + "MSRValue": "0x800200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3378,7 +3378,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200004", + "MSRValue": "0x400200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3391,7 +3391,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200004", + "MSRValue": "0x100200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3404,7 +3404,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200004", + "MSRValue": "0x200200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3417,7 +3417,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200004", + "MSRValue": "0x80200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3456,7 +3456,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040004", + "MSRValue": "0x800040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3469,7 +3469,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040004", + "MSRValue": "0x400040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3482,7 +3482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040004", + "MSRValue": "0x100040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3495,7 +3495,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040004", + "MSRValue": "0x200040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3508,7 +3508,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040004", + "MSRValue": "0x80040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3547,7 +3547,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100004", + "MSRValue": "0x800100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3560,7 +3560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100004", + "MSRValue": "0x400100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3573,7 +3573,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100004", + "MSRValue": "0x100100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3586,7 +3586,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100004", + "MSRValue": "0x200100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3599,7 +3599,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100004", + "MSRValue": "0x80100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3625,7 +3625,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400004", + "MSRValue": "0x80400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3638,7 +3638,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", + "MSRValue": "0x100400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3677,7 +3677,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020004", + "MSRValue": "0x800020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3690,7 +3690,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x400020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3703,7 +3703,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x100020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3716,7 +3716,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x200020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3729,7 +3729,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3742,7 +3742,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3781,7 +3781,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0001", + "MSRValue": "0x8003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3794,7 +3794,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3807,7 +3807,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3820,7 +3820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0001", + "MSRValue": "0x8007C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3833,7 +3833,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x2003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3846,7 +3846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0001", + "MSRValue": "0x803C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3885,7 +3885,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080001", + "MSRValue": "0x800080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3898,7 +3898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080001", + "MSRValue": "0x400080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3911,7 +3911,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080001", + "MSRValue": "0x100080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3924,7 +3924,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080001", + "MSRValue": "0x200080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3937,7 +3937,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080001", + "MSRValue": "0x80080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3976,7 +3976,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200001", + "MSRValue": "0x800200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -3989,7 +3989,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200001", + "MSRValue": "0x400200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4002,7 +4002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200001", + "MSRValue": "0x100200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4015,7 +4015,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200001", + "MSRValue": "0x200200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4028,7 +4028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200001", + "MSRValue": "0x80200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4067,7 +4067,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040001", + "MSRValue": "0x800040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4080,7 +4080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040001", + "MSRValue": "0x400040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4093,7 +4093,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040001", + "MSRValue": "0x100040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4106,7 +4106,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040001", + "MSRValue": "0x200040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4119,7 +4119,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040001", + "MSRValue": "0x80040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4158,7 +4158,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100001", + "MSRValue": "0x800100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4171,7 +4171,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100001", + "MSRValue": "0x400100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4184,7 +4184,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100001", + "MSRValue": "0x100100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4197,7 +4197,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100001", + "MSRValue": "0x200100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4210,7 +4210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100001", + "MSRValue": "0x80100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4236,7 +4236,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400001", + "MSRValue": "0x80400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4249,7 +4249,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", + "MSRValue": "0x100400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4288,7 +4288,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020001", + "MSRValue": "0x800020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4301,7 +4301,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x400020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4314,7 +4314,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x100020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4327,7 +4327,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x200020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4340,7 +4340,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x80020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4353,7 +4353,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4392,7 +4392,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0002", + "MSRValue": "0x8003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4405,7 +4405,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4418,7 +4418,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4431,7 +4431,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0002", + "MSRValue": "0x8007C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4444,7 +4444,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x2003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4457,7 +4457,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0002", + "MSRValue": "0x803C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4496,7 +4496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080002", + "MSRValue": "0x800080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4509,7 +4509,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080002", + "MSRValue": "0x400080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4522,7 +4522,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080002", + "MSRValue": "0x100080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4535,7 +4535,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080002", + "MSRValue": "0x200080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4548,7 +4548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080002", + "MSRValue": "0x80080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4587,7 +4587,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200002", + "MSRValue": "0x800200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4600,7 +4600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200002", + "MSRValue": "0x400200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4613,7 +4613,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200002", + "MSRValue": "0x100200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4626,7 +4626,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200002", + "MSRValue": "0x200200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4639,7 +4639,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200002", + "MSRValue": "0x80200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4678,7 +4678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040002", + "MSRValue": "0x800040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4691,7 +4691,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040002", + "MSRValue": "0x400040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4704,7 +4704,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040002", + "MSRValue": "0x100040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4717,7 +4717,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040002", + "MSRValue": "0x200040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4730,7 +4730,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040002", + "MSRValue": "0x80040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4769,7 +4769,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100002", + "MSRValue": "0x800100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4782,7 +4782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100002", + "MSRValue": "0x400100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4795,7 +4795,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100002", + "MSRValue": "0x100100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4808,7 +4808,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100002", + "MSRValue": "0x200100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4821,7 +4821,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100002", + "MSRValue": "0x80100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4847,7 +4847,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400002", + "MSRValue": "0x80400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4860,7 +4860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", + "MSRValue": "0x100400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4899,7 +4899,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020002", + "MSRValue": "0x800020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4912,7 +4912,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020002", + "MSRValue": "0x400020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4925,7 +4925,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020002", + "MSRValue": "0x100020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4938,7 +4938,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020002", + "MSRValue": "0x200020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4951,7 +4951,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020002", + "MSRValue": "0x80020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -4964,7 +4964,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x18000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5003,7 +5003,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C8000", + "MSRValue": "0x8003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5016,7 +5016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x4003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5029,7 +5029,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", + "MSRValue": "0x1003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5042,7 +5042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C8000", + "MSRValue": "0x8007C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5055,7 +5055,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x2003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5068,7 +5068,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C8000", + "MSRValue": "0x803C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5107,7 +5107,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800088000", + "MSRValue": "0x800088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5120,7 +5120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400088000", + "MSRValue": "0x400088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5133,7 +5133,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100088000", + "MSRValue": "0x100088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5146,7 +5146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200088000", + "MSRValue": "0x200088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5159,7 +5159,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080088000", + "MSRValue": "0x80088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5198,7 +5198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800208000", + "MSRValue": "0x800208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5211,7 +5211,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400208000", + "MSRValue": "0x400208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5224,7 +5224,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100208000", + "MSRValue": "0x100208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5237,7 +5237,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200208000", + "MSRValue": "0x200208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5250,7 +5250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080208000", + "MSRValue": "0x80208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5289,7 +5289,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800048000", + "MSRValue": "0x800048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5302,7 +5302,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400048000", + "MSRValue": "0x400048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5315,7 +5315,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100048000", + "MSRValue": "0x100048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5328,7 +5328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200048000", + "MSRValue": "0x200048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5341,7 +5341,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080048000", + "MSRValue": "0x80048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5380,7 +5380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800108000", + "MSRValue": "0x800108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5393,7 +5393,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400108000", + "MSRValue": "0x400108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5406,7 +5406,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100108000", + "MSRValue": "0x100108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5419,7 +5419,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200108000", + "MSRValue": "0x200108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5432,7 +5432,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080108000", + "MSRValue": "0x80108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5458,7 +5458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080408000", + "MSRValue": "0x80408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5471,7 +5471,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100408000", + "MSRValue": "0x100408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5510,7 +5510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800028000", + "MSRValue": "0x800028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5523,7 +5523,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x400028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5536,7 +5536,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x100028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5549,7 +5549,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x200028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5562,7 +5562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x80028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5575,7 +5575,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x10400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5614,7 +5614,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0400", + "MSRValue": "0x8003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5627,7 +5627,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0400", + "MSRValue": "0x4003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5640,7 +5640,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x1003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5653,7 +5653,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0400", + "MSRValue": "0x8007C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5666,7 +5666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", + "MSRValue": "0x2003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5679,7 +5679,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0400", + "MSRValue": "0x803C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5718,7 +5718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080400", + "MSRValue": "0x800080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5731,7 +5731,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080400", + "MSRValue": "0x400080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5744,7 +5744,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080400", + "MSRValue": "0x100080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5757,7 +5757,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080400", + "MSRValue": "0x200080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5770,7 +5770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080400", + "MSRValue": "0x80080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5809,7 +5809,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200400", + "MSRValue": "0x800200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5822,7 +5822,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200400", + "MSRValue": "0x400200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5835,7 +5835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200400", + "MSRValue": "0x100200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5848,7 +5848,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200400", + "MSRValue": "0x200200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5861,7 +5861,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200400", + "MSRValue": "0x80200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5900,7 +5900,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040400", + "MSRValue": "0x800040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5913,7 +5913,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040400", + "MSRValue": "0x400040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5926,7 +5926,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040400", + "MSRValue": "0x100040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5939,7 +5939,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040400", + "MSRValue": "0x200040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5952,7 +5952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040400", + "MSRValue": "0x80040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -5991,7 +5991,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100400", + "MSRValue": "0x800100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6004,7 +6004,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100400", + "MSRValue": "0x400100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6017,7 +6017,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100400", + "MSRValue": "0x100100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6030,7 +6030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100400", + "MSRValue": "0x200100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6043,7 +6043,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100400", + "MSRValue": "0x80100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6069,7 +6069,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400400", + "MSRValue": "0x80400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6082,7 +6082,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400400", + "MSRValue": "0x100400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6121,7 +6121,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020400", + "MSRValue": "0x800020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6134,7 +6134,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020400", + "MSRValue": "0x400020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6147,7 +6147,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020400", + "MSRValue": "0x100020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6160,7 +6160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020400", + "MSRValue": "0x200020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6173,7 +6173,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020400", + "MSRValue": "0x80020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6186,7 +6186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6225,7 +6225,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0010", + "MSRValue": "0x8003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6238,7 +6238,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6251,7 +6251,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6264,7 +6264,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0010", + "MSRValue": "0x8007C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6277,7 +6277,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x2003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6290,7 +6290,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0010", + "MSRValue": "0x803C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6329,7 +6329,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080010", + "MSRValue": "0x800080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6342,7 +6342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080010", + "MSRValue": "0x400080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6355,7 +6355,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080010", + "MSRValue": "0x100080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6368,7 +6368,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080010", + "MSRValue": "0x200080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6381,7 +6381,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080010", + "MSRValue": "0x80080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6420,7 +6420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200010", + "MSRValue": "0x800200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6433,7 +6433,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200010", + "MSRValue": "0x400200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6446,7 +6446,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200010", + "MSRValue": "0x100200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6459,7 +6459,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200010", + "MSRValue": "0x200200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6472,7 +6472,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200010", + "MSRValue": "0x80200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6511,7 +6511,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040010", + "MSRValue": "0x800040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6524,7 +6524,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040010", + "MSRValue": "0x400040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6537,7 +6537,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040010", + "MSRValue": "0x100040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6550,7 +6550,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040010", + "MSRValue": "0x200040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6563,7 +6563,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040010", + "MSRValue": "0x80040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6602,7 +6602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100010", + "MSRValue": "0x800100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6615,7 +6615,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100010", + "MSRValue": "0x400100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6628,7 +6628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100010", + "MSRValue": "0x100100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6641,7 +6641,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100010", + "MSRValue": "0x200100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6654,7 +6654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100010", + "MSRValue": "0x80100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6680,7 +6680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400010", + "MSRValue": "0x80400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6693,7 +6693,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400010", + "MSRValue": "0x100400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6732,7 +6732,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020010", + "MSRValue": "0x800020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6745,7 +6745,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020010", + "MSRValue": "0x400020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6758,7 +6758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020010", + "MSRValue": "0x100020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6771,7 +6771,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020010", + "MSRValue": "0x200020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6784,7 +6784,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020010", + "MSRValue": "0x80020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6797,7 +6797,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6836,7 +6836,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0020", + "MSRValue": "0x8003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6849,7 +6849,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6862,7 +6862,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6875,7 +6875,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0020", + "MSRValue": "0x8007C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6888,7 +6888,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6901,7 +6901,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0020", + "MSRValue": "0x803C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6940,7 +6940,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080020", + "MSRValue": "0x800080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6953,7 +6953,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080020", + "MSRValue": "0x400080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6966,7 +6966,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080020", + "MSRValue": "0x100080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6979,7 +6979,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080020", + "MSRValue": "0x200080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -6992,7 +6992,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080020", + "MSRValue": "0x80080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7031,7 +7031,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200020", + "MSRValue": "0x800200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7044,7 +7044,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200020", + "MSRValue": "0x400200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7057,7 +7057,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200020", + "MSRValue": "0x100200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7070,7 +7070,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200020", + "MSRValue": "0x200200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7083,7 +7083,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200020", + "MSRValue": "0x80200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7122,7 +7122,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040020", + "MSRValue": "0x800040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7135,7 +7135,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040020", + "MSRValue": "0x400040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7148,7 +7148,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040020", + "MSRValue": "0x100040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7161,7 +7161,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040020", + "MSRValue": "0x200040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7174,7 +7174,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040020", + "MSRValue": "0x80040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7213,7 +7213,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100020", + "MSRValue": "0x800100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7226,7 +7226,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100020", + "MSRValue": "0x400100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7239,7 +7239,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100020", + "MSRValue": "0x100100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7252,7 +7252,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100020", + "MSRValue": "0x200100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7265,7 +7265,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100020", + "MSRValue": "0x80100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7291,7 +7291,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400020", + "MSRValue": "0x80400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7304,7 +7304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400020", + "MSRValue": "0x100400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7343,7 +7343,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020020", + "MSRValue": "0x800020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7356,7 +7356,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020020", + "MSRValue": "0x400020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7369,7 +7369,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020020", + "MSRValue": "0x100020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7382,7 +7382,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020020", + "MSRValue": "0x200020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7395,7 +7395,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020020", + "MSRValue": "0x80020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7408,7 +7408,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7447,7 +7447,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0080", + "MSRValue": "0x8003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7460,7 +7460,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7473,7 +7473,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7486,7 +7486,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0080", + "MSRValue": "0x8007C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7499,7 +7499,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0080", + "MSRValue": "0x2003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7512,7 +7512,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0080", + "MSRValue": "0x803C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7551,7 +7551,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080080", + "MSRValue": "0x800080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7564,7 +7564,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080080", + "MSRValue": "0x400080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7577,7 +7577,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080080", + "MSRValue": "0x100080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7590,7 +7590,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080080", + "MSRValue": "0x200080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7603,7 +7603,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080080", + "MSRValue": "0x80080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7642,7 +7642,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200080", + "MSRValue": "0x800200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7655,7 +7655,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200080", + "MSRValue": "0x400200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7668,7 +7668,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200080", + "MSRValue": "0x100200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7681,7 +7681,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200080", + "MSRValue": "0x200200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7694,7 +7694,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200080", + "MSRValue": "0x80200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7733,7 +7733,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040080", + "MSRValue": "0x800040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7746,7 +7746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040080", + "MSRValue": "0x400040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7759,7 +7759,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040080", + "MSRValue": "0x100040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7772,7 +7772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040080", + "MSRValue": "0x200040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7785,7 +7785,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040080", + "MSRValue": "0x80040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7824,7 +7824,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100080", + "MSRValue": "0x800100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7837,7 +7837,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100080", + "MSRValue": "0x400100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7850,7 +7850,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100080", + "MSRValue": "0x100100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7863,7 +7863,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100080", + "MSRValue": "0x200100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7876,7 +7876,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100080", + "MSRValue": "0x80100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7902,7 +7902,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400080", + "MSRValue": "0x80400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7915,7 +7915,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400080", + "MSRValue": "0x100400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7954,7 +7954,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020080", + "MSRValue": "0x800020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7967,7 +7967,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020080", + "MSRValue": "0x400020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7980,7 +7980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020080", + "MSRValue": "0x100020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -7993,7 +7993,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020080", + "MSRValue": "0x200020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8006,7 +8006,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020080", + "MSRValue": "0x80020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8019,7 +8019,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8058,7 +8058,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0100", + "MSRValue": "0x8003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8071,7 +8071,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8084,7 +8084,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8097,7 +8097,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0100", + "MSRValue": "0x8007C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8110,7 +8110,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0100", + "MSRValue": "0x2003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8123,7 +8123,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0100", + "MSRValue": "0x803C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8162,7 +8162,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080100", + "MSRValue": "0x800080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8175,7 +8175,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080100", + "MSRValue": "0x400080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8188,7 +8188,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080100", + "MSRValue": "0x100080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8201,7 +8201,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080100", + "MSRValue": "0x200080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8214,7 +8214,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080100", + "MSRValue": "0x80080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8253,7 +8253,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200100", + "MSRValue": "0x800200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8266,7 +8266,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200100", + "MSRValue": "0x400200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8279,7 +8279,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200100", + "MSRValue": "0x100200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8292,7 +8292,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200100", + "MSRValue": "0x200200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8305,7 +8305,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200100", + "MSRValue": "0x80200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8344,7 +8344,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040100", + "MSRValue": "0x800040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8357,7 +8357,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040100", + "MSRValue": "0x400040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8370,7 +8370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040100", + "MSRValue": "0x100040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8383,7 +8383,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040100", + "MSRValue": "0x200040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8396,7 +8396,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040100", + "MSRValue": "0x80040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8435,7 +8435,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100100", + "MSRValue": "0x800100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8448,7 +8448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100100", + "MSRValue": "0x400100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8461,7 +8461,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100100", + "MSRValue": "0x100100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8474,7 +8474,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100100", + "MSRValue": "0x200100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8487,7 +8487,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100100", + "MSRValue": "0x80100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8513,7 +8513,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400100", + "MSRValue": "0x80400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8526,7 +8526,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400100", + "MSRValue": "0x100400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8565,7 +8565,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020100", + "MSRValue": "0x800020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8578,7 +8578,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020100", + "MSRValue": "0x400020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8591,7 +8591,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020100", + "MSRValue": "0x100020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8604,7 +8604,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020100", + "MSRValue": "0x200020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", @@ -8617,7 +8617,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020100", + "MSRValue": "0x80020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/to= ols/perf/pmu-events/arch/x86/cascadelakex/pipeline.json index ca5748120666..12eabae3e224 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json @@ -435,6 +435,17 @@ "PublicDescription": "Counts the number of instructions (EOMs) ret= ired. Counting covers macro-fused instructions individually (that is, incre= ments by two).", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", "Counter": "1", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json = b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json index 3be09986ce8b..7f1cf4d8f0fa 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json @@ -558,6 +558,18 @@ "PublicDescription": "Counts clockticks of the 1GHz trafiic contro= ller clock in the IIO unit.", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data: Part 0-3", + "UMask": "0x03", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", "Counter": "0,1,2,3", @@ -606,6 +618,17 @@ "UMask": "0x03", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0-3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer occupancy of completi= ons with data: Part 0-3", + "UMask": "0x0f", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0", "Counter": "2,3", --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9138AC433F5 for ; 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charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 22: https://download.01.org/perfmon/HSX Json files generated by: https://github.com/intel/event-converter-for-linux-perf Tested: ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : FAIL= ED! 91: perf all PMU test : Ok ... Test 90 failed for Load_Miss_Real_Latency with events: Performance counter stats for 'system wide': mem_load_uops_retired.hit_lfb = (0.00%) MEM_LOAD_UOPS_RETIRED.L1_MISS = (0.00%) L1D_PEND_MISS.PENDING = (0.00%) 1002638743 ns duration_time This is exposing a somewhat known issue with weak groups that can be worked around with: $ perf stat --metric-no-group -M Load_Miss_Real_Latency -a sleep 1 Performance counter stats for 'system wide': 9539883 mem_load_uops_retired.hit_lfb # 25.87 Load_Miss_= Real_Latency (83.24%) 10876212 MEM_LOAD_UOPS_RETIRED.L1_MISS = (66.68%) 528172960 L1D_PEND_MISS.PENDING = (83.26%) 1001964165 ns duration_time Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/haswellx/cache.json | 1434 +++++++------- .../arch/x86/haswellx/floating-point.json | 116 +- .../arch/x86/haswellx/frontend.json | 336 ++-- .../arch/x86/haswellx/hsx-metrics.json | 263 +-- .../pmu-events/arch/x86/haswellx/memory.json | 1070 +++++----- .../pmu-events/arch/x86/haswellx/other.json | 28 +- .../arch/x86/haswellx/pipeline.json | 1763 ++++++++--------- .../arch/x86/haswellx/virtual-memory.json | 512 ++--- 8 files changed, 2767 insertions(+), 2755 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/per= f/pmu-events/arch/x86/haswellx/cache.json index a9e62d4357af..85eb998dd39e 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -1,1097 +1,1097 @@ [ { - "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "Errata": "HSD78", - "PublicDescription": "Demand data read requests that missed L2, no= rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts when new data lines are br= ought into the L1 Data cache, which cause other lines to be evicted from th= e cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", - "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "UMask": "0x24", - "BriefDescription": "L2 cache misses when fetching instructions", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch. HWP are e.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "Errata": "HSD78", - "PublicDescription": "Demand requests that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "Not rejected writebacks that hit L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "EventCode": "0x24", - "UMask": "0x30", - "BriefDescription": "L2 prefetch requests that miss L2 cache", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_MISS", - "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "EventCode": "0x24", - "UMask": "0x3f", - "BriefDescription": "All requests that miss L2 cache", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.MISS", - "Errata": "HSD78", - "PublicDescription": "All requests that missed L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x24", - "UMask": "0xc1", - "BriefDescription": "Demand Data Read requests that hit L2 cache", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "Errata": "HSD78", - "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0xc2", - "BriefDescription": "RFO requests that hit L2 cache", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_HIT", - "PublicDescription": "Counts the number of store RFO requests that= hit the L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "UMask": "0xc4", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x5" }, { - "EventCode": "0x24", - "UMask": "0xd0", - "BriefDescription": "L2 prefetch requests that hit L2 cache", + "BriefDescription": "Dirty L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x6" }, { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0xe1", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "Errata": "HSD78", "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe1" }, { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", + "BriefDescription": "Demand requests that miss L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "Counts all L2 store RFO requests.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "Counts all L2 code requests.", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Demand requests that miss L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x27" }, { - "EventCode": "0x24", - "UMask": "0xe7", "BriefDescription": "Demand requests to L2 cache", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "Errata": "HSD78", "PublicDescription": "Demand requests to L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe7" }, { - "EventCode": "0x24", - "UMask": "0xf8", "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts all L2 HW prefetcher requests.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf8" }, { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", - "Errata": "HSD78", - "PublicDescription": "All requests to L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", + "BriefDescription": "L2 cache misses when fetching instructions", "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "Not rejected writebacks that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x2E", - "UMask": "0x41", - "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x2E", - "UMask": "0x4f", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Demand data read requests that missed L2, no= rejects.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "All requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch. HWP are e.", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "All requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "BriefDescription": "RFO requests that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the number of store RFO requests that= hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x51", - "UMask": "0x1", - "BriefDescription": "L1D data line replacements", + "BriefDescription": "RFO requests that miss L2 cache", "Counter": "0,1,2,3", - "EventName": "L1D.REPLACEMENT", - "PublicDescription": "This event counts when new data lines are br= ought into the L1 Data cache, which cause other lines to be evicted from th= e cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "HSD78, HSD62, HSD61", - "PublicDescription": "Offcore outstanding demand data read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, incl= uding rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "CounterMask": "1", - "Errata": "HSD78, HSD62, HSD61", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "HSD78, HSD62, HSD61", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions= .", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "HSD62, HSD61", - "PublicDescription": "Offcore outstanding Demand code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests that access L2 cac= he.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "HSD62, HSD61", - "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "CounterMask": "1", - "Errata": "HSD62, HSD61", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "HSD62, HSD61", - "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "CounterMask": "1", - "Errata": "HSD62, HSD61", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x2", "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D is locked.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "Errata": "HSD78", - "PublicDescription": "Demand data read requests sent to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "Demand code read requests sent to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "Errata": "HSD29, HSM30", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB.", + "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "Errata": "HSD29, HSM30", - "L1_Hit_Indication": "1", + "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access.", + "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "HSD76, HSD29, HSM30", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "Errata": "HSD29, HSM30", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "Errata": "HSD29, HSM30", - "L1_Hit_Indication": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "Errata": "HSD29, HSM30", - "L1_Hit_Indication": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xD1", - "UMask": "0x1", "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x2", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "Errata": "HSD76, HSD29, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { + "Errata": "HSD29, HSM30", "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", - "Data_LA": "1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "PublicDescription": "Retired load uops with L3 cache hits as data= sources.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xD1", - "UMask": "0x8", "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "Errata": "HSM30", + "PEBS": "1", "PublicDescription": "Retired load uops missed L1 cache as data so= urces.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xD1", - "UMask": "0x10", - "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", "PublicDescription": "Retired load uops missed L2. Unknown data so= urce excluded.", "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xD1", - "UMask": "0x20", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "PublicDescription": "Retired load uops missed L3. Excludes unknow= n data source .", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", - "Data_LA": "1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "Errata": "HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Retired load uops with L3 cache hits as data= sources.", + "SampleAfterValue": "50021", + "UMask": "0x4" }, { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Retired load uops missed L3. Excludes unknow= n data source .", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xD3", - "UMask": "0x1", - "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "HSD74, HSD29, HSD25, HSM30", - "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "HSM30", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", + "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "HSM30", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xf0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "Demand data read requests that access L2 cac= he.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xf0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "RFO requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xf0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "L2 cache accesses when fetching instructions= .", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xf0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, incl= uding rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xf0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", + "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "L1D writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xf0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "L2 fill requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xf0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xf0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "Transactions accessing L2 pipe.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "L2 cache lines in I state filling L2.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "L2 cache lines in S state filling L2.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "L2 cache lines in E state filling L2.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding demand data read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x7", - "BriefDescription": "L2 cache lines filling L2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.ALL", - "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF2", - "UMask": "0x5", - "BriefDescription": "Clean L2 cache lines evicted by demand", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF2", - "UMask": "0x6", - "BriefDescription": "Dirty L2 cache lines evicted by demand", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xf4", - "UMask": "0x10", - "BriefDescription": "Split locks in SQ", + "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "Counter": "0,1,2,3", - "EventName": "SQ_MISC.SPLIT_LOCK", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", - "MSRValue": "0x04003C0001", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoops to sibling cores hit in either E/S state and the line is not forw= arded", + "MSRValue": "0x10003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", - "MSRValue": "0x10003C0001", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded", + "MSRValue": "0x04003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", - "MSRValue": "0x04003C0002", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoops to sibling cores hit in either E/S state and the line= is not forwarded", + "MSRValue": "0x10003C07F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) hit in the L3 and the snoop to one of the sibling cores hits the lin= e in M state and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", - "MSRValue": "0x10003C0002", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoops to sibling cores hit in either E/S state= and the line is not forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", + "MSRValue": "0x04003C07F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) hit in the L3 and the snoops to sibling cores hit in either E/S stat= e and the line is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", - "MSRValue": "0x04003C0004", + "BriefDescription": "Counts all requests hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoops to sibling cores hit in either E/S state and the line is not = forwarded", + "MSRValue": "0x3F803C8FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", - "MSRValue": "0x10003C0004", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded", + "MSRValue": "0x10003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoop to one of the sibling cores hits the line in M state and = the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", - "MSRValue": "0x3F803C0010", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads hit in the L3", + "MSRValue": "0x04003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", - "MSRValue": "0x3F803C0020", + "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs hit in the L3", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", - "MSRValue": "0x3F803C0040", + "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads hit in the L3", + "MSRValue": "0x04003C0004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoops to sibling cores hit in either E/S state and the line is not = forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", - "MSRValue": "0x3F803C0080", + "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads hit in the L3", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", - "MSRValue": "0x3F803C0100", + "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", + "MSRValue": "0x04003C0001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoops to sibling cores hit in either E/S state and the line is not forw= arded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", - "MSRValue": "0x3F803C0200", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads hit in the L3", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", - "MSRValue": "0x04003C0091", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", + "MSRValue": "0x04003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoops to sibling cores hit in either E/S state and the line= is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", - "MSRValue": "0x10003C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", + "MSRValue": "0x3F803C0040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", - "MSRValue": "0x04003C0122", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded", + "MSRValue": "0x3F803C0010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", - "MSRValue": "0x10003C0122", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoop to one of the sibling cores hits the line in M state and = the line is forwarded", + "MSRValue": "0x3F803C0020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", - "MSRValue": "0x04003C0244", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", + "MSRValue": "0x3F803C0200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoops to sibling cores hit in either E/S state= and the line is not forwarded", - "MSRValue": "0x04003C07F7", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) hit in the L3 and the snoops to sibling cores hit in either E/S stat= e and the line is not forwarded", + "MSRValue": "0x3F803C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded", - "MSRValue": "0x10003C07F7", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) hit in the L3 and the snoop to one of the sibling cores hits the lin= e in M state and the line is forwarded", + "MSRValue": "0x3F803C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests hit in the L3", - "MSRValue": "0x3F803C8FFF", + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests hit in the L3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/= tools/perf/pmu-events/arch/x86/haswellx/floating-point.json index bc08cc1f2f7e..55cf5b96464e 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json @@ -1,83 +1,103 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "BriefDescription": "Approximate counts of AVX & AVX2 256-bit inst= ructions, including non-arithmetic instructions, loads, and stores. May co= unt non-AVX instructions that employ 256-bit operations, including (but not= necessarily limited to) rep string instructions that use 256-bit loads and= stores for optimized performance, XSAVE* and XRSTOR*, and operations that = transition the x87 FPU data registers between x87 and MMX.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "HSD56, HSM57", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC6", + "EventName": "AVX_INSTS.ALL", + "PublicDescription": "Note that a whole rep string only counts AVX= _INST.ALL once.", + "SampleAfterValue": "2000003", + "UMask": "0x7" }, { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "HSD56, HSM57", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1e" }, { - "EventCode": "0xC6", - "UMask": "0x7", - "BriefDescription": "Approximate counts of AVX & AVX2 256-bit inst= ructions, including non-arithmetic instructions, loads, and stores. May co= unt non-AVX instructions that employ 256-bit operations, including (but not= necessarily limited to) rep string instructions that use 256-bit loads and= stores for optimized performance, XSAVE* and XRSTOR*, and operations that = transition the x87 FPU data registers between x87 and MMX.", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "EventName": "AVX_INSTS.ALL", - "PublicDescription": "Note that a whole rep string only counts AVX= _INST.ALL once.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input value= s.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Number of SIMD FP assists due to Output value= s", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "Number of X87 FP assists due to output value= s.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output valu= es.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", - "UMask": "0x4", "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "Number of X87 FP assists due to input values= .", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "Number of SIMD FP assists due to output valu= es.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output value= s.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCA", - "UMask": "0x10", - "BriefDescription": "Number of SIMD FP assists due to input values= ", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_INPUT", - "PublicDescription": "Number of SIMD FP assists due to input value= s.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD56, HSM57", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD56, HSM57", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json b/tools/= perf/pmu-events/arch/x86/haswellx/frontend.json index a4d9f1fcf940..0c8d5ccf1276 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json @@ -1,294 +1,304 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "Errata": "HSD135", - "PublicDescription": "Counts cycles the IDQ is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts Instruction Cache (ICACHE)= misses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", - "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one= uop. Set Cmask =3D 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD135", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "Counts cycles MITE is delivered at least one= uop. Set Cmask =3D 1.", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts uops delivered by the Fron= t-end with the assistance of the microcode sequencer. Microcode assists ar= e used for complex instructions or scenarios that can't be handled by the s= tandard decoder. Using other instructions, if possible, will usually impro= ve performance.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the Front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x80", - "UMask": "0x1", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x80", - "UMask": "0x2", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.MISSES", - "PublicDescription": "This event counts Instruction Cache (ICACHE)= misses.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFETCH_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts uops delivered by the Fron= t-end with the assistance of the microcode sequencer. Microcode assists ar= e used for complex instructions or scenarios that can't be handled by the s= tandard decoder. Using other instructions, if possible, will usually impro= ve performance.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event count the number of undelivered (= unallocated) uops from the Front-end to the Resource Allocation Table (RAT)= while the Back-end of the processor is not stalled. The Front-end can allo= cate up to 4 uops per cycle so this event can increment 0-4 times per cycle= depending on the number of unallocated uops. This event is counted on a pe= r-core basis.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "PublicDescription": "This event counts the number cycles during w= hich the Front-end allocated exactly zero uops to the Resource Allocation T= able (RAT) while the Back-end of the processor is not stalled. This event = is counted on a per-core basis.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD135", "EventCode": "0x9C", - "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", "Errata": "HSD135", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "CounterMask": "1", - "Errata": "HSD135", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xAB", - "UMask": "0x2", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "Counter": "0,1,2,3", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/too= ls/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 311a005dc35b..c99734fd907d 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -1,172 +1,125 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLO= TS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1= @) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask= \\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -176,83 +129,127 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREA= D / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_X= CLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L3MPKI" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", @@ -261,40 +258,52 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", "MetricExpr": "1000000000 * ( cbox@event\\=3D0x36\\,umask\\=3D0x3\= \,filter_opc\\=3D0x182@ / cbox@event\\=3D0x35\\,umask\\=3D0x3\\,filter_opc\= \=3D0x182@ ) / ( cbox_0@event\\=3D0x0@ / duration_time )", - "MetricGroup": "Memory_Lat", - "MetricName": "DRAM_Read_Latency" + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cbox@event\\=3D0x36\\,umask\\=3D0x3\\,filter_opc\\= =3D0x182@ / cbox@event\\=3D0x36\\,umask\\=3D0x3\\,filter_opc\\=3D0x182\\,th= resh\\=3D1@", - "MetricGroup": "Memory_BW", - "MetricName": "DRAM_Parallel_Reads" + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Socket actual clocks when any core is active = on that socket", "MetricExpr": "cbox_0@event\\=3D0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/pe= rf/pmu-events/arch/x86/haswellx/memory.json index a42d5ce86b6f..6ffb5067f4eb 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json @@ -1,767 +1,775 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "Speculative cache-line split store-address u= ops dispatched to L1D.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address.", + "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional writes.", + "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer.", + "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer.", + "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD65", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an HLE execution aborted due= to none of the previous 4 categories (e.g. interrupts).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "BriefDescription": "Number of times an HLE execution successfully= committed.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "BriefDescription": "Number of times an HLE execution started.", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region.", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing machine clears detected. Memory ordering machine clears can result from= memory address aliasing or snoops from another hardware thread or core to = data inflight in the pipeline. Machine clears can have a significant perfo= rmance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 128.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 16.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 256.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory order= ing machine clears detected. Memory ordering machine clears can result from= memory address aliasing or snoops from another hardware thread or core to = data inflight in the pipeline. Machine clears can have a significant perfo= rmance impact if they are happening frequently.", + "BriefDescription": "Randomly selected loads with latency value be= ing above 32.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC8", - "UMask": "0x1", - "BriefDescription": "Number of times an HLE execution started.", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times an HLE execution successfully= committed.", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x4", - "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 4.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 512.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions.", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 64.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions.", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 8.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x40", - "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type.", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC4", - "Errata": "HSD65", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x80", - "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times an HLE execution aborted due= to none of the previous 4 categories (e.g. interrupts).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split store-address u= ops dispatched to L1D.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xC9", - "UMask": "0x1", - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x2", - "BriefDescription": "Number of times an RTM execution successfully= committed.", + "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x4", - "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", - "PEBS": "1", + "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x8", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x10", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from remote dram", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x063F800091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from remote dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x20", - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions.", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the modified data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x40", - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type.", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and clean or shared data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "Errata": "HSD65", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x083FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and clean or shared data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x80", - "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss in the L3", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 4.", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x06004007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 8.", - "PEBS": "2", - "MSRValue": "0x8", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x063F8007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from remote dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 16.", - "PEBS": "2", - "MSRValue": "0x10", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 32.", - "PEBS": "2", - "MSRValue": "0x20", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and clean or shared data is transferred from remote cache= ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x083FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and clean or shared data is transferred from remote cach= e", "SampleAfterValue": "100003", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 64.", - "PEBS": "2", - "MSRValue": "0x40", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" + "BriefDescription": "Counts all requests miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC08FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 128.", - "PEBS": "2", - "MSRValue": "0x80", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" + "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 256.", - "PEBS": "2", - "MSRValue": "0x100", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 512.", - "PEBS": "2", - "MSRValue": "0x200", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" + "BriefDescription": "Counts all demand code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "Offcore": "1", + "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads miss the L3 and= the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts demand data reads miss in the L3", - "MSRValue": "0x3FBFC00001", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Offcore": "1", "PublicDescription": "Counts demand data reads miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", - "MSRValue": "0x0600400001", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400001", + "Offcore": "1", "PublicDescription": "Counts demand data reads miss the L3 and the= data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", - "MSRValue": "0x3FBFC00002", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "Offcore": "1", "PublicDescription": "Counts all demand data writes (RFOs) miss in= the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", - "MSRValue": "0x0600400002", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400002", + "Offcore": "1", "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00002", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00002", + "Offcore": "1", "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the modified data is transferred from remote cache", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads miss in the L3", - "MSRValue": "0x3FBFC00004", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", - "MSRValue": "0x0600400004", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads miss the L3 and= the data is returned from local dram", + "MSRValue": "0x3FBFC00040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", - "MSRValue": "0x3FBFC00010", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00010", + "Offcore": "1", "PublicDescription": "Counts prefetch (that bring data to L2) data= reads miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", - "MSRValue": "0x3FBFC00020", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00020", + "Offcore": "1", "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", - "MSRValue": "0x3FBFC00040", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads miss in the L3", + "MSRValue": "0x3FBFC00200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", - "MSRValue": "0x3FBFC00080", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00080", + "Offcore": "1", "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", - "MSRValue": "0x3FBFC00100", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00100", + "Offcore": "1", "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", - "MSRValue": "0x3FBFC00200", + "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", - "MSRValue": "0x3FBFC00091", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", - "MSRValue": "0x0600400091", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from remote dram", - "MSRValue": "0x063F800091", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from remote dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00091", + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Errata": "HSD65", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x083FC00091", + "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and clean or shared data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", - "MSRValue": "0x3FBFC00122", + "BriefDescription": "Number of times an RTM execution successfully= committed.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", - "MSRValue": "0x0600400122", + "BriefDescription": "Number of times an RTM execution started.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", - "MSRValue": "0x3FBFC00244", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", - "MSRValue": "0x0600400244", + "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss in the L3", - "MSRValue": "0x3FBFC007F7", + "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from local dram", - "MSRValue": "0x06004007F7", + "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063F8007F7", + "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from remote dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC007F7", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional writes.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and clean or shared data is transferred from remote cache= ", - "MSRValue": "0x083FC007F7", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and clean or shared data is transferred from remote cach= e", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests miss in the L3", - "MSRValue": "0x3FBFC08FFF", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/per= f/pmu-events/arch/x86/haswellx/other.json index 800e65df31bc..4c6b9d34325a 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/other.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json @@ -1,43 +1,43 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/= perf/pmu-events/arch/x86/haswellx/pipeline.json index 26f2888341ee..a53f28ec9270 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -1,1340 +1,1305 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "Errata": "HSD140, HSD143", - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leav= ing the programmable counters available for other events. Faulting executio= ns of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.= ", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of thread cycle= s while the thread is not in a halt state. The thread enters the halt state= when it is running the HLT instruction. The core frequency may change from= time to time due to power or thermal throttling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "loads blocked by overlapping with store buffe= r that cannot be forwarded", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. The penalty for blocked store forwarding is t= hat the load must wait for the store to write its value to the cache before= it can be issued.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "BriefDescription": "Any uop executed by the Divider. (This includ= es all divide uops, sqrt, ...)", "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline which can have a performance impact.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "BriefDescription": "Speculative and retired macro-conditional bra= nches.", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles spent= waiting for a recovery after an event such as a processor nuke, JEClear, a= ssist, hle/rtm abort etc.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke)", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "PublicDescription": "Core cycles the allocator was stalled due to= recovery from earlier clear event for any thread running on the physical c= ore (e.g. misprediction or memory nuke).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "BriefDescription": "Speculative and retired direct near calls.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of uops issued = by the Front-end of the pipeline to the Back-end. This event is counted at = the allocation stage and will count both retired and non-retired uops.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "BriefDescription": "Not taken macro-conditional branches.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops allocated. Such u= ops add delay.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "BriefDescription": "Taken speculative and retired macro-condition= al branches.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (for example, 2 sources + immediate) regardless of= whether it is a result of LEA instruction or not.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x14", - "UMask": "0x2", - "BriefDescription": "Any uop executed by the Divider. (This includ= es all divide uops, sqrt, ...)", + "BriefDescription": "Taken speculative and retired direct near cal= ls.", "Counter": "0,1,2,3", - "EventName": "ARITH.DIVIDER_UOPS", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "BriefDescription": "Taken speculative and retired indirect calls.= ", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch inst= ructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x4c", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "Counts the number of near return instruction= s retired.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "PublicDescription": "Number of integer move elimination candidate= uops that were eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "PublicDescription": "Number of integer move elimination candidate= uops that were not eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were not eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles when the Reservatio= n Station ( RS ) is empty for the thread. The RS is a structure that buffer= s allocated micro-ops from the Front-end. If there are many cycles when the= RS is empty, it may represent an underflow of instructions delivered from = the Front-end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts cycles where the decoder i= s stalled on an instruction with a length changing prefix (LCP).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x87", - "UMask": "0x4", - "BriefDescription": "Stall cycles because IQ is full", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", "Counter": "0,1,2,3", - "EventName": "ILD_STALL.IQ_FULL", - "PublicDescription": "Stall cycles due to IQ is full.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches.", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-condition= al branches.", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retireme= nt.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", + "BriefDescription": "Mispredicted macro branch instructions retire= d.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This event counts all mispredicted branch in= structions retired. This is a precise event.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near cal= ls.", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired t= hat were taken but mispredicted.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls.= ", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional bra= nches.", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls.", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xff", - "BriefDescription": "Speculative and retired branches", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of thread cycle= s while the thread is not in a halt state. The thread enters the halt state= when it is running the HLT instruction. The core frequency may change from= time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 data cache miss loads= . Set Cmask=3D8 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", + "BriefDescription": "Cycles with pending L2 cache miss loads.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask= =3D2 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "BriefDescription": "Cycles with pending memory loads.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set Cmask= =3D2 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", + "SampleAfterValue": "2000003", + "UMask": "0xc" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "BriefDescription": "Execution stalls due to L2 cache misses.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "Errata": "HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", + "SampleAfterValue": "2000003", + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "BriefDescription": "Execution stalls due to memory subsystem.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "Cycles which a uop is dispatched on port 0 i= n this thread.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline and there we= re memory instructions pending (waiting for data).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "BriefDescription": "Stall cycles because IQ is full", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0.", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts cycles where the decoder i= s stalled on an instruction with a length changing prefix (LCP).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "Cycles which a uop is dispatched on port 1 i= n this thread.", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "Errata": "HSD140, HSD143", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leav= ing the programmable counters available for other events. Faulting executio= ns of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.= ", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are executed in por= t 1.", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD11, HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "BriefDescription": "FP operations retired. X87 FP operations that= have no exceptions: Counts also flows that have several X87 or flows that = use X87 uops in the exception handling.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "Cycles which a uop is dispatched on port 2 i= n this thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts FP operations retired. For X87 FP o= perations that have no exceptions counting also includes flows that have se= veral X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "This event counts the number of cycles spent= waiting for a recovery after an event such as a processor nuke, JEClear, a= ssist, hle/rtm abort etc.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2.", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke)", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "PublicDescription": "Core cycles the allocator was stalled due to= recovery from earlier clear event for any thread running on the physical c= ore (e.g. misprediction or memory nuke).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "Cycles which a uop is dispatched on port 3 i= n this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", + "BriefDescription": "loads blocked by overlapping with store buffe= r that cannot be forwarded", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. The penalty for blocked store forwarding is t= hat the load must wait for the store to write its value to the cache before= it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3.", + "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline which can have a performance impact.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "Cycles which a uop is dispatched on port 4 i= n this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are executed in por= t 4.", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4.", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "Cycles which a uop is dispatched on port 5 i= n this thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are executed in por= t 5.", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered by the LSD.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5.", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "Cycles which a uop is dispatched on port 6 i= n this thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are executed in por= t 6.", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6.", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "Cycles which a uop is dispatched on port 7 i= n this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate= uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate= uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7.", + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "PublicDescription": "Number of microcode assists invoked by HW up= on uop writeback.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xA2", - "UMask": "0x1", "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD135", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Cycles allocation is stalled due to resource= related reason.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA2", - "UMask": "0x4", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA2", - "UMask": "0x8", "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "This event counts cycles during which no ins= tructions were allocated because no Store Buffers (SB) were available.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by har= dware.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles with pending L2 cache miss loads.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "Errata": "HSD78", - "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask= =3D2 to count cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles when the Reservatio= n Station ( RS ) is empty for the thread. The RS is a structure that buffer= s allocated micro-ops from the Front-end. If there are many cycles when the= RS is empty, it may represent an underflow of instructions delivered from = the Front-end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles with pending memory loads.", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Cycles with pending memory loads. Set Cmask= =3D2 to count cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls due to L2 cache misses.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Number of loads missed L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls due to memory subsystem.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline and there we= re memory instructions pending (waiting for data).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Cycles with pending L1 data cache miss loads= . Set Cmask=3D8 to count cycle.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x8" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x10" }, { - "EventCode": "0xa8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5.", "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", - "PublicDescription": "Number of uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6.", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7.", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "Errata": "HSD144, HSD30, HSM31", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "Errata": "HSD144, HSD30, HSM31", - "PublicDescription": "This events counts the cycles where at least= one uop was executed. It is counted per thread.", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", - "Errata": "HSD144, HSD30, HSM31", - "PublicDescription": "This events counts the cycles where at least= two uop were executed. It is counted per thread.", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", - "Errata": "HSD144, HSD30, HSM31", - "PublicDescription": "This events counts the cycles where at least= three uop were executed. It is counted per thread.", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", - "Errata": "HSD144, HSD30, HSM31", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x2", - "BriefDescription": "Number of uops executed on the core.", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD30, HSM31", - "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "Errata": "HSD30, HSM31", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "This events counts the cycles where at least= one uop was executed. It is counted per thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", - "Errata": "HSD30, HSM31", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least= two uop were executed. It is counted per thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", - "Errata": "HSD30, HSM31", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least= three uop were executed. It is counted per thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", - "Errata": "HSD30, HSM31", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "Errata": "HSD30, HSM31", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "HSD11, HSD140", - "PublicDescription": "Number of instructions at retirement.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "HSD140", - "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "Cycles which a uop is dispatched on port 0 i= n this thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations that= have no exceptions: Counts also flows that have several X87 or flows that = use X87 uops in the exception handling.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 0.", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts FP operations retired. For X87 FP o= perations that have no exceptions counting also includes flows that have se= veral X87, or flows that use X87 uops in the exception handling.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "PublicDescription": "Number of microcode assists invoked by HW up= on uop writeback.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "Cycles which a uop is dispatched on port 1 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops.", - "Data_LA": "1", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 1.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "Counts the number of micro-ops retired. Use = Cmask=3D1 and invert to count active cycles or stalled cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "Cycles which a uop is dispatched on port 2 i= n this thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "AnyThread": "1", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "Cycles which a uop is dispatched on port 3 i= n this thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "Cycles which a uop is dispatched on port 4 i= n this thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 4.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "Cycles which a uop is dispatched on port 5 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 5.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x0", - "BriefDescription": "All (macro) branch instructions retired.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PublicDescription": "Branch instructions at retirement.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "Cycles which a uop is dispatched on port 6 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 6.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PublicDescription": "Counts the number of conditional branch inst= ructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions re= tired.", - "PEBS": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "Cycles which a uop is dispatched on port 7 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC4", - "UMask": "0x4", - "BriefDescription": "All (macro) branch instructions retired.", - "PEBS": "2", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of uops issued = by the Front-end of the pipeline to the Back-end. This event is counted at = the allocation stage and will count both retired and non-retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PublicDescription": "Counts the number of near return instruction= s retired.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC4", - "UMask": "0x10", - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such u= ops add delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired.", - "PEBS": "1", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "Number of near taken branches retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x40", - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PublicDescription": "Number of far branches retired.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (for example, 2 sources + immediate) regardless of= whether it is a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC5", - "UMask": "0x0", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PublicDescription": "Mispredicted branch instructions at retireme= nt.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "PEBS": "1", + "BriefDescription": "Actually retired uops.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired. Use = Cmask=3D1 and invert to count active cycles or stalled cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x4", - "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "PEBS": "2", + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "PublicDescription": "This event counts all mispredicted branch in= structions retired. This is a precise event.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x20", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", - "PEBS": "1", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PublicDescription": "Number of near branch instructions retired t= hat were taken but mispredicted.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCC", - "UMask": "0x20", - "BriefDescription": "Count cases of saving new LBR", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "PublicDescription": "Count cases of saving new LBR records by har= dware.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json index 168df552b1a8..ba3e77a9f9a0 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json @@ -1,484 +1,484 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { + "BriefDescription": "DTLB demand load misses with low part of line= ar-to-physical address translation missed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB demand load misses with low part of lin= ear-to-physical address translation missed.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Completed page walks due to demand load miss= es that caused 4K page walks in any TLB levels.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk= .", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M)", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Completed page walks due to demand load miss= es that caused 2M/4M page walks in any TLB levels.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts load operations from a 2M = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K)", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts load operations from a 4K = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x08", - "UMask": "0xe", "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in any TLB of any page = size due to demand load misses.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K)", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", - "PublicDescription": "This event counts load operations from a 4K = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M)", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "PublicDescription": "This event counts load operations from a 2M = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to demand load miss= es that caused 2M/4M page walks in any TLB levels.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x08", - "UMask": "0x60", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "PublicDescription": "Number of cache load STLB hits. No page walk= .", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to demand load miss= es that caused 4K page walks in any TLB levels.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x08", - "UMask": "0x80", - "BriefDescription": "DTLB demand load misses with low part of line= ar-to-physical address translation missed", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", - "PublicDescription": "DTLB demand load misses with low part of lin= ear-to-physical address translation missed.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x1", "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "BriefDescription": "DTLB store misses with low part of linear-to-= physical address translation missed", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 4K page structure.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB store misses with low part of linear-to= -physical address translation missed.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 2M/4M page structure.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks. (1G)", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts store operations from a 2M= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "UMask": "0xe", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts store operations from a 4K= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks due to store miss in an= y TLB levels of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x49", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB store misses.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K)", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", - "PublicDescription": "This event counts store operations from a 4K= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M)", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", - "PublicDescription": "This event counts store operations from a 2M= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 2M/4M page structure.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x49", - "UMask": "0x60", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 4K page structure.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x49", - "UMask": "0x80", - "BriefDescription": "DTLB store misses with low part of linear-to-= physical address translation missed", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", - "PublicDescription": "DTLB store misses with low part of linear-to= -physical address translation missed.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB store misses.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x4f", - "UMask": "0x10", "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4f", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xae", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x1", "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in ITLB that causes a page walk of an= y page size.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Completed page walks due to misses in ITLB 4= K page entries.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "ITLB misses that hit STLB. No page walk.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Completed page walks due to misses in ITLB 2= M/4M page entries.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "PublicDescription": "ITLB misses that hit STLB (2M).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "PublicDescription": "ITLB misses that hit STLB (4K).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x85", - "UMask": "0xe", "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in ITLB of any page siz= e.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x85", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by ITLB misses.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", - "PublicDescription": "ITLB misses that hit STLB (4K).", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M)", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", - "PublicDescription": "ITLB misses that hit STLB (2M).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to misses in ITLB 2= M/4M page entries.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", - "PublicDescription": "ITLB misses that hit STLB. No page walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to misses in ITLB 4= K page entries.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xae", - "UMask": "0x1", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "ITLB.ITLB_FLUSH", - "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by ITLB misses.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "PublicDescription": "Number of DTLB page walker loads that hit in= the L1+FB.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "PublicDescription": "Number of DTLB page walker loads that hit in= the L2.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "PublicDescription": "Number of DTLB page walker loads that hit in= the L3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", - "Errata": "HSD25", - "PublicDescription": "Number of DTLB page walker loads from memory= .", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x21", - "BriefDescription": "Number of ITLB page walker hits in the L1+FB", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", - "PublicDescription": "Number of ITLB page walker loads that hit in= the L1+FB.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x22", - "BriefDescription": "Number of ITLB page walker hits in the L2", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", - "PublicDescription": "Number of ITLB page walker loads that hit in= the L2.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x24", - "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", - "PublicDescription": "Number of ITLB page walker loads that hit in= the L3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { "EventCode": "0xBC", - "UMask": "0x28", - "BriefDescription": "Number of ITLB page walker hits in Memory", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", - "Errata": "HSD25", - "PublicDescription": "Number of ITLB page walker loads from memory= .", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "PublicDescription": "Number of DTLB page walker loads from memory= .", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", - "UMask": "0x41", "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L1 and FB.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "EventCode": "0xBC", - "UMask": "0x42", "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L2.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "EventCode": "0xBC", - "UMask": "0x44", "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L3.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x44" }, { - "EventCode": "0xBC", - "UMask": "0x48", "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in memory.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x48" }, { - "EventCode": "0xBC", - "UMask": "0x81", "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L1 and FB.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x81" }, { - "EventCode": "0xBC", - "UMask": "0x82", "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x82" }, { - "EventCode": "0xBC", - "UMask": "0x84", "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x84" }, { - "EventCode": "0xBC", - "UMask": "0x88", "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in memory.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x88" + }, + { + "BriefDescription": "Number of ITLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "PublicDescription": "Number of ITLB page walker loads that hit in= the L1+FB.", + "SampleAfterValue": "2000003", + "UMask": "0x21" + }, + { + "BriefDescription": "Number of ITLB page walker hits in the L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "PublicDescription": "Number of ITLB page walker loads that hit in= the L2.", + "SampleAfterValue": "2000003", + "UMask": "0x22" + }, + { + "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "PublicDescription": "Number of ITLB page walker loads that hit in= the L3.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Number of ITLB page walker hits in Memory", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "PublicDescription": "Number of ITLB page walker loads from memory= .", + "SampleAfterValue": "2000003", + "UMask": "0x28" }, { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", "SampleAfterValue": "100003", - "CounterHTOff": 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<20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 06/26] perf vendor events: Update metrics for Ivybridge From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are still at version 21: https://download.01.org/perfmon/IVB Json files generated by: https://github.com/intel/event-converter-for-linux-perf Tested: ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : FAIL= ED! 91: perf all PMU test : Ok ... Test 90 failed for Load_Miss_Real_Latency with events: Performance counter stats for 'perf bench internals synthesize': mem_load_uops_retired.hit_lfb = (0.00%) MEM_LOAD_UOPS_RETIRED.L1_MISS = (0.00%) L1D_PEND_MISS.PENDING = (0.00%) 558185217 ns duration_time This is exposing a somewhat known issue with weak groups that can be worked around with: $ perf stat --metric-no-group -M Load_Miss_Real_Latency -a sleep 1 Performance counter stats for 'system wide': 14935022 mem_load_uops_retired.hit_lfb # 23.55 Load_Miss_= Real_Latency (83.23%) 4716714 MEM_LOAD_UOPS_RETIRED.L1_MISS = (66.68%) 462705675 L1D_PEND_MISS.PENDING = (83.22%) 1001548340 ns duration_time 1.001548340 seconds time elapsed Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/ivybridge/cache.json | 1446 +++++++------- .../arch/x86/ivybridge/floating-point.json | 212 +- .../arch/x86/ivybridge/frontend.json | 386 ++-- .../arch/x86/ivybridge/ivb-metrics.json | 287 +-- .../pmu-events/arch/x86/ivybridge/memory.json | 290 +-- .../pmu-events/arch/x86/ivybridge/other.json | 42 +- .../arch/x86/ivybridge/pipeline.json | 1769 ++++++++--------- .../arch/x86/ivybridge/uncore-cache.json | 252 +++ .../arch/x86/ivybridge/uncore-other.json | 91 + .../pmu-events/arch/x86/ivybridge/uncore.json | 314 --- .../arch/x86/ivybridge/virtual-memory.json | 208 +- 11 files changed, 2678 insertions(+), 2619 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.j= son create mode 100644 tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.j= son delete mode 100644 tools/perf/pmu-events/arch/x86/ivybridge/uncore.json diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/pe= rf/pmu-events/arch/x86/ivybridge/cache.json index 5f6cb2abc384..62e9705daa19 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json @@ -1,1102 +1,1102 @@ [ { - "PublicDescription": "Demand Data Read requests that hit L2 cache.= ", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "Counts the number of lines brought into the = L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", - "EventCode": "0x24", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Cycles a demand request was blocked due to F= ill Buffers inavailability.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "RFO requests that hit L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all L2 store RFO requests.", - "EventCode": "0x24", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "PublicDescription": "Cycles with L1D load Misses outstanding from= any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in E state.", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in M state.", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Counts all L2 code requests.", - "EventCode": "0x24", + "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.)", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "PublicDescription": "Not rejected writebacks that missed LLC.", "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "L2 cache lines filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "RFOs that miss cache lines.", - "EventCode": "0x27", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "RFOs that hit cache lines in M state.", - "EventCode": "0x27", + "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "RFOs that access cache lines in any state.", - "EventCode": "0x27", + "BriefDescription": "Dirty L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Not rejected writebacks that missed LLC.", - "EventCode": "0x28", + "BriefDescription": "Dirty L2 cache lines filling the L2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "PublicDescription": "Dirty L2 cache lines filling the L2.", + "SampleAfterValue": "100003", + "UMask": "0xa" }, { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in E state.", - "EventCode": "0x28", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by the MLC pref= etcher.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in M state.", - "EventCode": "0x28", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by the MLC pref= etcher.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0x28", + "BriefDescription": "L2 code requests", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", - "EventCode": "0x2E", + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", - "EventCode": "0x2E", + "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "SampleAfterValue": "200003", + "UMask": "0xc0" }, { - "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xc" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PublicDescription": "Cycles with L1D load Misses outstanding from= any thread on physical core.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "Cycles a demand request was blocked due to F= ill Buffers inavailability.", - "EventCode": "0x48", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Demand Data Read requests that hit L2 cache.= ", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of lines brought into the = L1 data cache.", - "EventCode": "0x51", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "Offcore outstanding Demand Data Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "PublicDescription": "Cycles when offcore outstanding Demand Data = Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", + "BriefDescription": "RFO requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "RFO requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles with at least 6 offcore outstanding D= emand Data Read transactions in uncore queue.", - "EventCode": "0x60", + "BriefDescription": "RFO requests that miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Offcore outstanding Demand Code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "RFOs that access cache lines in any state", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "PublicDescription": "RFOs that access cache lines in any state.", + "SampleAfterValue": "200003", + "UMask": "0xf" }, { - "PublicDescription": "Offcore outstanding code reads transactions = in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", + "BriefDescription": "RFOs that hit cache lines in M state", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "PublicDescription": "RFOs that hit cache lines in M state.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "RFOs that miss cache lines", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "PublicDescription": "RFOs that miss cache lines.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Offcore outstanding demand rfo reads transac= tions in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, inc= luding rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "PublicDescription": "Cycles when offcore outstanding cacheable Co= re Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions= .", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles in which the L1D is locked.", - "EventCode": "0x63", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests that access L2 cac= he.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Demand data read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PublicDescription": "Demand code read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", - "EventCode": "0xB0", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", - "EventCode": "0xB0", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "Cases when offcore requests buffer cannot ta= ke more entries for core.", - "EventCode": "0xB2", + "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precis= e Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { + "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", - "EventCode": "0xD0", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources missed L= LC but serviced from local dram.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "PublicDescription": "Retired load uops whose data source was loca= l memory (cross-socket snoop not needed or missed).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops which data sources followin= g L1 data-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", + "CounterHTOff": "0,1,2,3", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources followin= g L1 data-cache miss.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "PEBS": "1", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "PEBS": "1", "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "All retired load uops. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "All retired store uops. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops with locked access. (Precis= e Event)", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PublicDescription": "Retired load uops whose data source was loca= l memory (cross-socket snoop not needed or missed).", - "EventCode": "0xD3", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops which data sources missed L= LC but serviced from local dram.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { - "PublicDescription": "Demand Data Read requests that access L2 cac= he.", - "EventCode": "0xF0", + "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "PublicDescription": "RFO requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "PublicDescription": "L2 cache accesses when fetching instructions= .", - "EventCode": "0xF0", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, inc= luding rejects.", - "EventCode": "0xF0", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "L1D writebacks that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "L2 fill requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "L2 writebacks that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "Cases when offcore requests buffer cannot ta= ke more entries for core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Transactions accessing L2 pipe.", - "EventCode": "0xF0", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "L2 cache lines in I state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Cycles when offcore outstanding cacheable Co= re Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "L2 cache lines in S state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Offcore outstanding code reads transactions = in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "L2 cache lines in E state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "PublicDescription": "Cycles when offcore outstanding Demand Data = Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "L2 cache lines filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Offcore outstanding demand rfo reads transac= tions in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand Code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Dirty L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding Demand Data Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Clean L2 cache lines evicted by the MLC pref= etcher.", - "EventCode": "0xF2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "PublicDescription": "Cycles with at least 6 offcore outstanding D= emand Data Read transactions in uncore queue.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Dirty L2 cache lines evicted by the MLC pref= etcher.", - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Dirty L2 cache lines filling the L2.", - "EventCode": "0xF2", + "BriefDescription": "Counts all demand & prefetch code reads that = hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF4", + "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0244", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that = hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0244", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000105B3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0091", + "BriefDescription": "Counts all demand & prefetch data reads that = hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that = hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0122", + "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch)", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000107F7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0122", + "BriefDescription": "Counts all demand & prefetch prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all writebacks from the core to the LL= C", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the = LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0004", + "BriefDescription": "Counts all writebacks from the core to the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the = LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", + "BriefDescription": "Counts all demand code reads that hit in the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", + "BriefDescription": "Counts demand code reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", + "BriefDescription": "Counts all demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0002", + "BriefDescription": "Counts all demand data reads that hit in the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0002", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18000", + "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sen= t to LLC to keep a line from being evicted out of the core caches", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", + "BriefDescription": "Counts all demand rfo's", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", + "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010001", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010002", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand rfo's", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010004", + "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sen= t to LLC to keep a line from being evicted out of the core caches", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000105B3", + "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010122", + "BriefDescription": "Counts non-temporal stores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch prefetch RFOs", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000107F7", + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b= /tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json index 950b62c0908e..db8b1c4fceb0 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json @@ -1,151 +1,169 @@ [ { - "PublicDescription": "Counts number of X87 uops executed.", - "EventCode": "0x10", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked double-precision uops issued this cycle.", - "EventCode": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input value= s.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational s= calar single-precision uops issued this cycle.", - "EventCode": "0x10", + "BriefDescription": "Number of SIMD FP assists due to Output value= s", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output valu= es.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked single-precision uops issued this cycle.", - "EventCode": "0x10", + "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values= .", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Counts number of SSE* or AVX-128 double prec= ision FP scalar uops executed.", + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output value= s.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked double-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked single-precision uops issued this cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Counts 256-bit packed single-precision float= ing-point instructions.", - "EventCode": "0x11", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "PublicDescription": "Counts number of SSE* or AVX-128 double prec= ision FP scalar uops executed.", "SampleAfterValue": "2000003", - "BriefDescription": "number of GSSE-256 Computational FP single pr= ecision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PublicDescription": "Counts 256-bit packed double-precision float= ing-point instructions.", - "EventCode": "0x11", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational s= calar single-precision uops issued this cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "number of AVX-256 Computational FP double pre= cision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of assists associated with 256-bit AV= X store operations.", - "EventCode": "0xC1", + "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "PublicDescription": "Counts number of X87 uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" }, { - "PublicDescription": "Number of X87 FP assists due to output value= s.", - "EventCode": "0xCA", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "PublicDescription": "Number of assists associated with 256-bit AV= X store operations.", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of X87 FP assists due to input values= .", - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Number of SIMD FP assists due to output valu= es.", - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output value= s", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of SIMD FP assists due to input value= s.", - "EventCode": "0xCA", + "BriefDescription": "number of AVX-256 Computational FP double pre= cision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "PublicDescription": "Counts 256-bit packed double-precision float= ing-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", - "EventCode": "0xCA", + "BriefDescription": "number of GSSE-256 Computational FP single pr= ecision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist= ", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "PublicDescription": "Counts 256-bit packed single-precision float= ing-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools= /perf/pmu-events/arch/x86/ivybridge/frontend.json index efaa949ead31..c956a0a51312 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json @@ -1,305 +1,315 @@ [ { - "PublicDescription": "Counts cycles the IDQ is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PublicDescription": "Number of DSB to MITE switches.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from MITE path.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Cycles DSB to MITE switches caused delay.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Reads. both cacheable and noncacheable, including UC fet= ches.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", - "EventCode": "0x79", + "BriefDescription": "Cycles where a code-fetch stalled due to L1 i= nstruction-cache miss or an iTLB miss", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", + "PublicDescription": "Cycles where a code-fetch stalled due to L1 = instruction-cache miss or an iTLB miss.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles when uops initiated by Decode Stream = Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mi= crocode Sequenser (MS) is busy.", - "EventCode": "0x79", + "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Misses. Includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ)= initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is = busy.", - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "Counts cycles MITE is delivered at least one= uops. Set Cmask =3D 1.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one= uops. Set Cmask =3D 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MS by either DSB or MITE. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "EventCode": "0x79", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x3c", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Reads. both cacheable and noncacheable, including UC fet= ches.", - "EventCode": "0x80", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from MITE path.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Misses. Includes UC accesses.", - "EventCode": "0x80", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles where a code-fetch stalled due to L1 = instruction-cache miss or an iTLB miss.", - "EventCode": "0x80", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFETCH_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code-fetch stalled due to L1 i= nstruction-cache miss or an iTLB miss", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "Count issue pipeline slots where no uop was = delivered from the front end to the back end when there is no back-end stal= l.", - "EventCode": "0x9C", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "Cycles when uops initiated by Decode Stream = Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mi= crocode Sequenser (MS) is busy.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ)= initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is = busy.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0x9C", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MS by either DSB or MITE. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0x9C", - "Invert": "1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Count issue pipeline slots where no uop was = delivered from the front end to the back end when there is no back-end stal= l.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Number of DSB to MITE switches.", - "EventCode": "0xAB", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DSB2MITE_SWITCHES.COUNT", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles DSB to MITE switches caused delay.", - "EventCode": "0xAB", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "DSB Fill encountered > 3 DSB lines.", - "EventCode": "0xAC", + "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/to= ols/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 28e25447d3ef..87670226f52d 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -1,184 +1,144 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_S= LOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -188,87 +148,138 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREA= D / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_X= CLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "1 / ( ((FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD) + ((FP_COMP_OPS_EXE.SSE= _PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SIN= GLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRE= D.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRE= D.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L3MPKI" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_C= OMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4= * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * = SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -279,22 +290,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external m= emory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/p= erf/pmu-events/arch/x86/ivybridge/memory.json index a74d54f56192..5f98f7746cf7 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -1,236 +1,236 @@ [ { - "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative cache-line split Store-address u= ops dispatched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xBE", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.LLC_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Number of any page walk that had a miss in LL= C.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 4.", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", + "SampleAfterValue": "1009", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 8.", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 16", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "SampleAfterValue": "20011", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", + "BriefDescription": "Loads with latency value being above 256", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", + "SampleAfterValue": "503", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", + "BriefDescription": "Loads with latency value being above 32", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", + "BriefDescription": "Loads with latency value being above 4", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "SampleAfterValue": "100003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", + "BriefDescription": "Loads with latency value being above 512", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 64", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "SampleAfterValue": "2003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 8", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "SampleAfterValue": "50021", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", + "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only.", "Counter": "3", - "UMask": "0x2", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only.", + "PEBS": "2", "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400244", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split Store-address u= ops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400091", + "BriefDescription": "Counts all demand & prefetch data reads that = miss the LLC and the data returned from dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that = miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3004003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400004", + "BriefDescription": "Counts LLC replacements", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004001b3", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that miss the LLC an= d the data returned from dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that miss the LLC an= d the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400001", + "BriefDescription": "Counts demand data reads that miss the LLC an= d the data returned from dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC an= d the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004001b3", + "BriefDescription": "Number of any page walk that had a miss in LL= C.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBE", + "EventName": "PAGE_WALKS.LLC_MISS", "SampleAfterValue": "100003", - "BriefDescription": "Counts LLC replacements", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/pe= rf/pmu-events/arch/x86/ivybridge/other.json index 4eb83ee40412..83fe8f79adc6 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json @@ -1,44 +1,44 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of intervals between processor halts = while thread is in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", + "PublicDescription": "Number of intervals between processor halts = while thread is in ring 0.", "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools= /perf/pmu-events/arch/x86/ivybridge/pipeline.json index 2a0aad91d83d..2de31c56c2a5 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -1,1305 +1,1272 @@ [ { - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "Loads blocked by overlapping with store buff= er that cannot be forwarded.", - "EventCode": "0x03", + "BriefDescription": "Divide operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "Divide operations executed.", "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", - "EventCode": "0x03", + "BriefDescription": "Cycles when divider is busy executing divide = operations", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "Cycles that the divider is active, includes = INT and FP. Set 'edge =3D1, cmask=3D1' to count the number of divides.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "False dependencies in MOB due to partial com= pare on address.", - "EventCode": "0x07", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial comp= are on address", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired macro-conditional bra= nches", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired macro-conditional br= anches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "Speculative and retired macro-unconditional = branches excluding calls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "Speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Increments each cycle the # of Uops issued b= y the RAT to RS. Set Cmask =3D 1, Inv =3D 1, Any=3D 1to count stalled cycle= s of this core.", - "EventCode": "0x0E", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Speculative and retired indirect branches ex= cluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for the thread.", - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for all threads.", - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken macro-conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "Number of flags-merge uops allocated. Such u= ops adds delay.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired macro-condition= al branches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired macro-conditio= nal branches.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a re= sult of LEA instruction or not.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "Taken speculative and retired macro-conditio= nal branch instructions excluding calls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired direct near cal= ls", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired direct near ca= lls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "PublicDescription": "Cycles that the divider is active, includes = INT and FP. Set 'edge =3D1, cmask=3D1' to count the number of divides.", - "EventCode": "0x14", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide = operations", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired indirect branc= hes excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "PublicDescription": "Divide operations executed.", - "EventCode": "0x14", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "UMask": "0x4", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", - "BriefDescription": "Divide operations executed", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired indirect calls= .", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "Taken speculative and retired indirect branc= hes with return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" }, { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", - "EventCode": "0x3C", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", - "EventCode": "0x4C", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", - "EventCode": "0x4C", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x58", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x58", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired mispredicted macro c= onditional branches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x58", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Mispredicted indirect branches excluding cal= ls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x58", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken speculative and retired mispredict= ed macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "Cycles the RS is empty for the thread.", - "EventCode": "0x5E", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired mispredicted m= acro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x5E", - "Invert": "1", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired mispredicted i= ndirect calls.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches with return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "PublicDescription": "Not taken macro-conditional branches.", - "EventCode": "0x88", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retireme= nt.", + "SampleAfterValue": "400009" }, { - "PublicDescription": "Taken speculative and retired macro-conditio= nal branches.", - "EventCode": "0x88", + "BriefDescription": "Mispredicted macro branch instructions retire= d.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "PublicDescription": "Taken speculative and retired macro-conditio= nal branch instructions excluding calls and indirects.", - "EventCode": "0x88", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Taken speculative and retired indirect branc= hes excluding calls and returns.", - "EventCode": "0x88", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "Taken speculative and retired indirect branc= hes with return mnemonic.", - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Taken speculative and retired direct near ca= lls.", - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near cal= ls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Taken speculative and retired indirect calls= .", - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Speculative and retired macro-conditional br= anches.", - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional bra= nches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Speculative and retired macro-unconditional = branches excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PublicDescription": "Speculative and retired indirect branches ex= cluding calls and returns.", - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Speculative and retired direct near calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Not taken speculative and retired mispredict= ed macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Taken speculative and retired mispredicted m= acro conditional branches.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches excluding calls and returns.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches with return mnemonic.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 cache miss loads. Set= AnyThread to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Taken speculative and retired mispredicted i= ndirect calls.", - "EventCode": "0x89", + "BriefDescription": "Cycles while L2 cache miss load* is outstandi= ng.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Speculative and retired mispredicted macro c= onditional branches.", - "EventCode": "0x89", + "BriefDescription": "Cycles with pending L2 cache miss loads.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyTh= read to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Mispredicted indirect branches excluding cal= ls and returns.", - "EventCode": "0x89", + "BriefDescription": "Cycles with pending memory loads.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set AnyThr= ead to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "EventCode": "0x89", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 0.", - "EventCode": "0xA1", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Total execution stalls.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 1.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while L2 cache miss load* is= outstanding.", "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 2.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls due to L2 cache misses.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", + "BriefDescription": "Execution stalls due to memory subsystem.", "Counter": "0,1,2,3", - "UMask": "0xc", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched to port 2, loads and stores p= er core (speculative and retired).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 3.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "PublicDescription": "Cycles per core when load or STA uops are di= spatched to port 3.", - "EventCode": "0xA1", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", - "UMask": "0x30", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 4.", - "EventCode": "0xA1", + "BriefDescription": "Stall cycles because IQ is full", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 4.", - "EventCode": "0xA1", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 5.", - "EventCode": "0xA1", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles Allocation is stalled due to Resource= Related reason.", - "EventCode": "0xA2", + "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA2", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "Cycles stalled due to no store buffers avail= able (not including draining form sync).", - "EventCode": "0xA2", + "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA2", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Cycles with pending L2 miss loads. Set AnyTh= read to count per core.", - "EventCode": "0xA3", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Loads blocked by overlapping with store buff= er that cannot be forwarded.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA3", + "BriefDescription": "False dependencies in MOB due to partial comp= are on address", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss load* is outstandi= ng.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "False dependencies in MOB due to partial com= pare on address.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles with pending memory loads. Set AnyThr= ead to count per core.", - "EventCode": "0xA3", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn= 't come from the decoder.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Total execution stalls.", - "EventCode": "0xA3", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't= come from the decoder.", "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Total execution stalls.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss load* is= outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Counts the number of executed AVX masked loa= d operations that refer to an illegal address range with the mask bits set = to 0.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA3", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Number of self-modifying-code machine clears= detected.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles with pending L1 cache miss loads. Set= AnyThread to count per core.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "CounterMask": "8", - "CounterHTOff": "2" + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "CounterMask": "8", - "CounterHTOff": "2" + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x80" }, { - "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles Allocation is stalled due to Resource= Related reason.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x10" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles Uops delivered by the LSD, but didn't= come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "Cycles stalled due to no store buffers avail= able (not including draining form sync).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn= 't come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by har= dware.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Counts total number of uops to be executed p= er-thread each cycle. Set Cmask =3D 1, INV =3D1 to count stall cycles.", - "EventCode": "0xB1", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.THREAD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "Cycles the RS is empty for the thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 0", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles at least 1 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Uops dispatched to port 2, loads and stores p= er core (speculative and retired).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles at least 2 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "Cycles at least 3 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "PublicDescription": "Cycles per core when load or STA uops are di= spatched to port 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "Cycles at least 4 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 4", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Cycles with no micro-ops executed from any t= hread on physical core.", - "EventCode": "0xB1", - "Invert": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 5", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PEBS": "2", - "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 5.", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x80" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PublicDescription": "Cycles at least 1 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PublicDescription": "Cycles at least 2 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PublicDescription": "Cycles at least 3 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PublicDescription": "Cycles at least 4 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "PublicDescription": "Cycles with no micro-ops executed from any t= hread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Number of self-modifying-code machine clears= detected.", - "EventCode": "0xC3", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of executed AVX masked loa= d operations that refer to an illegal address range with the mask bits set = to 0.", - "EventCode": "0xC3", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Counts total number of uops to be executed p= er-thread each cycle. Set Cmask =3D 1, INV =3D1 to count stall cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Increments each cycle the # of Uops issued b= y the RAT to RS. Set Cmask =3D 1, Inv =3D 1, Any=3D 1to count stalled cycle= s of this core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for all threads.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Number of flags-merge uops being allocated.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such u= ops adds delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", - "EventCode": "0xC4", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a re= sult of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Number of far branches retired.", - "EventCode": "0xC4", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for the thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Mispredicted branch instructions at retireme= nt.", - "EventCode": "0xC5", + "BriefDescription": "Retired uops.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC5", + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Count cases of saving new LBR records by har= dware.", - "EventCode": "0xCC", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", - "EventCode": "0xE6", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/t= ools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json new file mode 100644 index 000000000000..6b0639944d78 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json @@ -0,0 +1,252 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in E or S-state.", + "UMask": "0x46", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in I-state.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in M-state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in MESI-state.", + "UMask": "0x4f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in I-state.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which hits a modified line in some processor core.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a modified line in som= e processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a modified line in so= me processor core.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a modified line in some proce= ssor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which hits a non-modified line in some processor core.", + "UMask": "0x84", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a non-modified line in= some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a non-modified line i= n some processor core.", + "UMask": "0x24", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a non-modified line in some p= rocessor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop misses in some processor co= re.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop misses in some processor c= ore.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json new file mode 100644 index 000000000000..6278068908cf --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json @@ -0,0 +1,91 @@ +[ + { + "BriefDescription": "Cycles weighted by number of requests pending= in Coherency Tracker.", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Cycles weighted by number of requests pendin= g in Coherency Tracker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tra= cker.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of requests allocated in Coherency Tr= acker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts cycles weighted by the number of reque= sts waiting for data returning from the memory controller. Accounts for coh= erent and non-coherent requests initiated by IA cores, processor graphic un= its, or LLC.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Counts cycles weighted by the number of requ= ests waiting for data returning from the memory controller. Accounts for co= herent and non-coherent requests initiated by IA cores, processor graphic u= nits, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least half of the requests out= standing are waiting for data return from memory controller. Account for co= herent and non-coherent requests initiated by IA Cores, Processor Graphics = Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "10", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "PerPkg": "1", + "PublicDescription": "Cycles with at least half of the requests ou= tstanding are waiting for data return from memory controller. Account for c= oherent and non-coherent requests initiated by IA Cores, Processor Graphics= Unit, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0,1", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding= is waiting for data return from memory controller. Account for coherent an= d non-coherent requests initiated by IA Cores, Processor Graphics Unit, or = LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherent and in-coheren= t requests initiated by IA cores, processor graphic units, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of LLC evictions allocated.= ", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "PerPkg": "1", + "PublicDescription": "Counts the number of LLC evictions allocated= .", + "UMask": "0x80", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of allocated write entries,= include full, partial, and LLC evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocated write entries= , include full, partial, and LLC evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "Fixed", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "UMask": "0x01", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json b/tools/p= erf/pmu-events/arch/x86/ivybridge/uncore.json deleted file mode 100644 index 42c70eed05a2..000000000000 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json +++ /dev/null @@ -1,314 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x01", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS", - "BriefDescription": "A snoop misses in some processor core.", - "PublicDescription": "A snoop misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x02", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL", - "BriefDescription": "A snoop invalidates a non-modified line in some p= rocessor core.", - "PublicDescription": "A snoop invalidates a non-modified line in some = processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x04", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT", - "BriefDescription": "A snoop hits a non-modified line in some processo= r core.", - "PublicDescription": "A snoop hits a non-modified line in some process= or core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x08", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM", - "BriefDescription": "A snoop hits a modified line in some processor co= re.", - "PublicDescription": "A snoop hits a modified line in some processor c= ore.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x10", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M", - "BriefDescription": "A snoop invalidates a modified line in some proce= ssor core.", - "PublicDescription": "A snoop invalidates a modified line in some proc= essor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x20", - "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbo= x due to external snoop request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cb= ox due to external snoop request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x40", - "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbo= x due to processor core memory request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cb= ox due to processor core memory request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x80", - "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbo= x due to LLC eviction.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cb= ox due to LLC eviction.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x01", - "EventName": "UNC_CBO_CACHE_LOOKUP.M", - "BriefDescription": "LLC lookup request that access cache and found li= ne in M-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x02", - "EventName": "UNC_CBO_CACHE_LOOKUP.E", - "BriefDescription": "LLC lookup request that access cache and found li= ne in E-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in E-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x04", - "EventName": "UNC_CBO_CACHE_LOOKUP.S", - "BriefDescription": "LLC lookup request that access cache and found li= ne in S-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x08", - "EventName": "UNC_CBO_CACHE_LOOKUP.I", - "BriefDescription": "LLC lookup request that access cache and found li= ne in I-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x10", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable read= requests.", - "PublicDescription": "Filter on processor core initiated cacheable rea= d requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x20", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable writ= e requests.", - "PublicDescription": "Filter on processor core initiated cacheable wri= te requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x40", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", - "BriefDescription": "Filter on external snoop requests.", - "PublicDescription": "Filter on external snoop requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x80", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", - "BriefDescription": "Filter on any IRQ or IPQ initiated requests inclu= ding uncacheable, non-coherent requests.", - "PublicDescription": "Filter on any IRQ or IPQ initiated requests incl= uding uncacheable, non-coherent requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Counts cycles weighted by the number of requests = waiting for data returning from the memory controller. Accounts for coheren= t and non-coherent requests initiated by IA cores, processor graphic units,= or LLC.", - "PublicDescription": "Counts cycles weighted by the number of requests= waiting for data returning from the memory controller. Accounts for cohere= nt and non-coherent requests initiated by IA cores, processor graphic units= , or LLC.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Counts the number of coherent and in-coherent req= uests initiated by IA cores, processor graphic units, or LLC.", - "PublicDescription": "Counts the number of coherent and in-coherent re= quests initiated by IA cores, processor graphic units, or LLC.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Counts the number of allocated write entries, inc= lude full, partial, and LLC evictions.", - "PublicDescription": "Counts the number of allocated write entries, in= clude full, partial, and LLC evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x80", - "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", - "BriefDescription": "Counts the number of LLC evictions allocated.", - "PublicDescription": "Counts the number of LLC evictions allocated.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x83", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", - "BriefDescription": "Cycles weighted by number of requests pending in = Coherency Tracker.", - "PublicDescription": "Cycles weighted by number of requests pending in= Coherency Tracker.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of requests allocated in Coherency Tracker= .", - "PublicDescription": "Number of requests allocated in Coherency Tracke= r.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "BriefDescription": "Cycles with at least one request outstanding is w= aiting for data return from memory controller. Account for coherent and non= -coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "PublicDescription": "Cycles with at least one request outstanding is = waiting for data return from memory controller. Account for coherent and no= n-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.= ", - "Counter": "0,1", - "CounterMask": "1", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", - "BriefDescription": "Cycles with at least half of the requests outstan= ding are waiting for data return from memory controller. Account for cohere= nt and non-coherent requests initiated by IA Cores, Processor Graphics Unit= , or LLC.", - "PublicDescription": "Cycles with at least half of the requests outsta= nding are waiting for data return from memory controller. Account for coher= ent and non-coherent requests initiated by IA Cores, Processor Graphics Uni= t, or LLC.", - "Counter": "0,1", - "CounterMask": "10", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.= ", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles= .", - "Counter": "Fixed", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x06", - "EventName": "UNC_CBO_CACHE_LOOKUP.ES", - "BriefDescription": "LLC lookup request that access cache and found li= ne in E-state or S-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in E-state or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json index f243551b4d12..8cf1549797b0 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json @@ -1,180 +1,180 @@ [ { - "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size from demand loads.", + "BriefDescription": "Page walk for a large page completed for Dema= nd load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0x88" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes an page walk of any page size.", "Counter": "0,1,2,3", - "UMask": "0x81", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size from demand loads.", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes an page walk of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "PublicDescription": "Misses in all TLB levels that caused page wa= lk completed of any size by demand loads.", - "EventCode": "0x08", + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5F", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Counts load operations that missed 1st level= DTLB but hit the 2nd level.", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycle PMH is busy with a walk due to demand = loads.", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all TLB levels that caused page wa= lk completed of any size by demand loads.", + "SampleAfterValue": "100003", + "UMask": "0x82" + }, + { + "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", "Counter": "0,1,2,3", - "UMask": "0x84", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk due to demand = loads.", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x08", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Page walk for a large page completed for Dema= nd load.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk th= at completes of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Miss in all TLB levels causes a page walk th= at completes of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles PMH is busy with this walk.", - "EventCode": "0x49", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "Cycles PMH is busy with this walk.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", - "EventCode": "0x49", + "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4F", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Counts load operations that missed 1st level= DTLB but hit the 2nd level.", - "EventCode": "0x5F", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Misses in all ITLB levels that cause page wa= lks.", - "EventCode": "0x85", + "BriefDescription": "Completed page walks in ITLB due to STLB load= misses for large pages", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB due to STLB loa= d misses for large pages.", "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PublicDescription": "Misses in all ITLB levels that cause complet= ed page walks.", - "EventCode": "0x85", + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all ITLB levels that cause page wa= lks.", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycle PMH is busy with a walk.", - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of cache load STLB hits. No page walk= .", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk= .", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Completed page walks in ITLB due to STLB loa= d misses for large pages.", - "EventCode": "0x85", + "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all ITLB levels that cause complet= ed page walks.", "SampleAfterValue": "100003", - "BriefDescription": "Completed page walks in ITLB due to STLB load= misses for large pages", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", - "EventCode": "0xAE", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", - "EventCode": "0xBD", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39690C433F5 for ; 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charset="utf-8" Events are still at version 2: https://download.01.org/perfmon/WSM-EP-DP Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : Ok 91: perf all PMU test : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/westmereep-dp/cache.json | 2734 ++++++++--------- .../x86/westmereep-dp/floating-point.json | 180 +- .../arch/x86/westmereep-dp/frontend.json | 18 +- .../arch/x86/westmereep-dp/memory.json | 686 ++--- .../arch/x86/westmereep-dp/other.json | 238 +- .../arch/x86/westmereep-dp/pipeline.json | 780 ++--- .../x86/westmereep-dp/virtual-memory.json | 138 +- 7 files changed, 2387 insertions(+), 2387 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tool= s/perf/pmu-events/arch/x86/westmereep-dp/cache.json index 6e61ae20d01a..0f01cf223777 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -1,2817 +1,2817 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0x8" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0x8" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0x80" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch reque= st" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" + "UMask": "0x10" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x20" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { + "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "UMask": "0xc0" + }, + { + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" + "UMask": "0x40" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch misses", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" + "UMask": "0x80" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xc" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO misses", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 transactions", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" - }, - { "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0x80" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0x8" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (= Precise Event)" + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "100", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)" + "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)" + "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "10000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)" + "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", + "SampleAfterValue": "5", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)" + "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "SampleAfterValue": "50", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)" + "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "500", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "5000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", + "SampleAfterValue": "3", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "50000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", + "SampleAfterValue": "20", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "200", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "20000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", + "SampleAfterValue": "10", + "UMask": "0x10" + }, + { + "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)" + "UMask": "0x4" }, { - "EventCode": "0xB0", + "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" + "UMask": "0x80" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore read requests", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" + "UMask": "0x8" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore RFO requests", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" + "UMask": "0x10" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand code read requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" + "UMask": "0x2" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand data read requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" + "UMask": "0x1" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" + "UMask": "0x4" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore L1 data cache writebacks", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" + "UMask": "0x40" }, { + "BriefDescription": "Outstanding offcore reads", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" + "UMask": "0x8" }, { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" + "UMask": "0x8" }, { + "BriefDescription": "Outstanding offcore demand code reads", "EventCode": "0x60", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" + "UMask": "0x2" }, { + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding offcore demand data reads", "EventCode": "0x60", - "UMask": "0x1", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" + "UMask": "0x1" }, { + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x1", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding offcore demand RFOs", "EventCode": "0x60", - "UMask": "0x4", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" + "UMask": "0x4" }, { + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x4", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" + "UMask": "0x4" }, { - "EventCode": "0xB2", + "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue f= ull" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" + "UMask": "0x1" }, { - "EventCode": "0x6", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AL= L_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", - "MSRIndex": "0x3F6", - "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)" - }, - { "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5011", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_= CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AL= L_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f11", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff11", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8011", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D IO= _CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D IO= _CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x111", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x211", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x411", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x711", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LO= CAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LO= CAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1011", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LO= CAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACH= E_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LO= CAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x811", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D RE= MOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D RE= MOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5044", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f44", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_C= ACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_C= ACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff44", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_L= OCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_L= OCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8044", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D IO_CS= R_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D IO_CS= R_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x144", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x244", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x444", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x744", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LOCAL= _CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LOCAL= _CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1044", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x844", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D REMOT= E_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D REMOT= E_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x50ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMO= TE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x50ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7fff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7fff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xffff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xffff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x80ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D IO_C= SR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D IO_C= SR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LOCA= L_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LOCA= L_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D REMO= TE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D REMO= TE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5022", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f22", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_CACH= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_CACH= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff22", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_LOCA= TION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_LOCA= TION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8022", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D IO_CSR_M= MIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D IO_CSR_M= MIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x122", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x222", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x422", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x722", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LOCAL_CA= CHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LOCAL_CA= CHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1022", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE= _HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x822", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D REMOTE_C= ACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D REMOTE_C= ACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5008", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f08", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_CACH= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_CACH= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff08", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_LOCA= TION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_LOCA= TION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8008", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D IO_CSR_M= MIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D IO_CSR_M= MIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x108", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x208", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x208", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x408", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x708", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LOCAL_CA= CHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LOCAL_CA= CHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1008", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_= HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x808", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D REMOTE_C= ACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D REMOTE_C= ACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5077", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMO= TE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f77", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff77", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8077", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D IO_C= SR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D IO_C= SR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x177", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x277", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x477", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x777", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LOCA= L_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LOCA= L_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1077", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x877", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D REMO= TE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D REMO= TE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5033", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f33", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_CACH= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_CACH= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff33", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_LOCA= TION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_LOCA= TION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8033", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D IO_CSR_M= MIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D IO_CSR_M= MIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x133", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x233", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x433", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x733", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LOCAL_CA= CHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LOCAL_CA= CHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1033", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE= _HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x833", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D REMOTE_C= ACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D REMOTE_C= ACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5003", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMO= TE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f03", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff03", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8003", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D IO_C= SR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D IO_C= SR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x103", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x203", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x403", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x703", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LOCA= L_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LOCA= L_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D REMO= TE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D REMO= TE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5001", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= LL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_R= EMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= LL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f01", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff01", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8001", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D I= O_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D I= O_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x101", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x201", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x401", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x701", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= OCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= OCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1001", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= OCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= OCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x801", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D R= EMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D R= EMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5004", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AL= L_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_RE= MOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AL= L_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f04", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff04", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8004", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D IO= _CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D IO= _CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x104", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x204", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x404", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x704", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LO= CAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LO= CAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LO= CAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE= _CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LO= CAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x804", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D RE= MOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D RE= MOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5002", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f02", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_C= ACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_C= ACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff02", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_L= OCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_L= OCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8002", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D IO_CS= R_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D IO_CS= R_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x102", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x202", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x402", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x702", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LOCAL= _CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LOCAL= _CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1002", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x802", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D REMOT= E_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D REMOT= E_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5080", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ALL_LOCAL_= DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CAC= HE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ALL_LOCAL_= DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f80", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_CACHE_= DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_CACHE_= DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff80", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_LOCATI= ON", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_LOCATI= ON", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8080", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D IO_CSR_MMI= O", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D IO_CSR_MMI= O", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x180", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_NO= _OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_NO= _OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x280", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_OT= HER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_OT= HER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x480", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_OT= HER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_OT= HER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x780", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LOCAL_CACH= E", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LOCAL_CACH= E", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1080", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LOCAL_DRAM= AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_H= IT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LOCAL_DRAM= AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x880", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D REMOTE_CAC= HE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D REMOTE_CAC= HE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5050", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f50", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_CACH= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_CACH= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff50", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_LOCA= TION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_LOCA= TION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8050", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D IO_CSR_M= MIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D IO_CSR_M= MIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x150", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x150", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x250", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x250", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x450", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x450", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x750", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LOCAL_CA= CHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x750", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LOCAL_CA= CHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1050", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE= _HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x850", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D REMOTE_C= ACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D REMOTE_C= ACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5010", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f10", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_C= ACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_C= ACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff10", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_L= OCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_L= OCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8010", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D IO_CS= R_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D IO_CS= R_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x110", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x210", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x410", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x710", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LOCAL= _CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LOCAL= _CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1010", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x810", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D REMOT= E_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D REMOT= E_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5040", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ALL_LOCAL= _DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE= _CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ALL_LOCAL= _DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f40", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_CACHE= _DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_CACHE= _DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff40", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_LOCAT= ION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_LOCAT= ION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8040", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D IO_CSR_MM= IO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D IO_CSR_MM= IO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x140", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_N= O_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_N= O_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x240", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_O= THER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_O= THER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x440", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_O= THER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_O= THER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x740", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LOCAL_CAC= HE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LOCAL_CAC= HE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1040", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LOCAL_DRA= M AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CAC= HE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LOCAL_DRA= M AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x840", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D REMOTE_CA= CHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D REMOTE_CA= CHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5020", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ALL_LO= CAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ALL_LO= CAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f20", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_CA= CHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_CA= CHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff20", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_LO= CATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_LO= CATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8020", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D IO_CSR= _MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D IO_CSR= _MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x120", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x220", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x420", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x720", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LOCAL_= CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LOCAL_= CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1020", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LOCAL_= DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_= HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LOCAL_= DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x820", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D REMOTE= _CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D REMOTE= _CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5070", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ALL_LOC= AL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_= CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ALL_LOC= AL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f70", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_CAC= HE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_CAC= HE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff70", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_LOC= ATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_LOC= ATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8070", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D IO_CSR_= MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D IO_CSR_= MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x170", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x270", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x470", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x770", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LOCAL_C= ACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LOCAL_C= ACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1070", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LOCAL_D= RAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACH= E_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LOCAL_D= RAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x870", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D REMOTE_= CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D REMOTE_= CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.js= on b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "MMX Uops", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { + "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" + "UMask": "0x80" }, { - "EventCode": "0x10", + "BriefDescription": "SSE and SSE2 FP Uops", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP packed Uops", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP scalar Uops", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" + "UMask": "0x20" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP single precision Uops", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" + "UMask": "0x40" }, { - "EventCode": "0x10", + "BriefDescription": "Computational floating-point operations execu= ted", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations execu= ted" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transition= s", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transition= s" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instru= ctions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instru= ctions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operation= s" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/t= ools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/too= ls/perf/pmu-events/arch/x86/westmereep-dp/memory.json index 6e0829b7617f..36fbea313c6f 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json @@ -1,758 +1,758 @@ [ { - "EventCode": "0x5", + "BriefDescription": "Misaligned store references", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", - "BriefDescription": "Misaligned store references" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3011", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf811", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4011", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D OT= HER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D OT= HER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2011", + "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D RE= MOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D RE= MOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3044", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf844", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_L= LC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_L= LC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4044", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D OTHER= _LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D OTHER= _LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2044", + "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D REMOT= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D REMOT= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x30ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x30ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf8ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf8ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x40ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D OTHE= R_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D OTHE= R_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20ff", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D REMO= TE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D REMO= TE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3022", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf822", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_LLC_= MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_LLC_= MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4022", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D OTHER_LO= CAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D OTHER_LO= CAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2022", + "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D REMOTE_D= RAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D REMOTE_D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3008", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf808", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_LLC_= MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_LLC_= MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4008", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D OTHER_LO= CAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D OTHER_LO= CAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2008", + "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D REMOTE_D= RAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D REMOTE_D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3077", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf877", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4077", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D OTHE= R_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D OTHE= R_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2077", + "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D REMO= TE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D REMO= TE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3033", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf833", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_LLC_= MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_LLC_= MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4033", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D OTHER_LO= CAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D OTHER_LO= CAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2033", + "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D REMOTE_D= RAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D REMOTE_D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3003", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf803", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D OTHE= R_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D OTHE= R_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003", + "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D REMO= TE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D REMO= TE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3001", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_= FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf801", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4001", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D O= THER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D O= THER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2001", + "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D R= EMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D R= EMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_F= WD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf804", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4004", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D OT= HER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D OT= HER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D RE= MOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D RE= MOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3002", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf802", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_L= LC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_L= LC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4002", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D OTHER= _LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D OTHER= _LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2002", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D REMOT= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D REMOT= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3080", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_DRAM A= ND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_DRAM A= ND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf880", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_LLC_MI= SS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_LLC_MI= SS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4080", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D OTHER_LOCA= L_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D OTHER_LOCA= L_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2080", + "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D REMOTE_DRA= M", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D REMOTE_DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3050", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf850", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_LLC_= MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_LLC_= MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4050", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D OTHER_LO= CAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D OTHER_LO= CAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2050", + "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D REMOTE_D= RAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D REMOTE_D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3010", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf810", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_L= LC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_L= LC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4010", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D OTHER= _LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D OTHER= _LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2010", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D REMOT= E_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D REMOT= E_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3040", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_DRAM = AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_DRAM = AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf840", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_LLC_M= ISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_LLC_M= ISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4040", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D OTHER_LOC= AL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D OTHER_LOC= AL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2040", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D REMOTE_DR= AM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D REMOTE_DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3020", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_DR= AM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_DR= AM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf820", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_LL= C_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_LL= C_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4020", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D OTHER_= LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D OTHER_= LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2020", + "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D REMOTE= _DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D REMOTE= _DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3070", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_DRA= M AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_DRA= M AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf870", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_LLC= _MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_LLC= _MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4070", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D OTHER_L= OCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D OTHER_L= OCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2070", + "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D REMOTE_= DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D REMOTE_= DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tool= s/perf/pmu-events/arch/x86/westmereep-dp/other.json index 85133d6a5ce0..23dcd554728c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json @@ -1,287 +1,287 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Loads that partially overlap an earlier store= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" + "UMask": "0x2" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address ali= asing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address ali= asing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Snoop code requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" + "UMask": "0x4" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" + "UMask": "0x1" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop invalidate requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding snoop code requests", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" + "UMask": "0x4" }, { + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Outstanding snoop data requests", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding snoop invalidate requests", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xF6", + "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Thread responded HITE to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/t= ools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json index f130510f7616..10140f460fbb 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json @@ -1,899 +1,899 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", + "BriefDescription": "Divide Operations executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", "EventName": "ARITH.DIV", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Divide Operations executed", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired near call instructions (Precise Event= )", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event= )" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted branches executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches execu= ted", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches execu= ted" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Even= t)" + "UMask": "0x2" }, { - "EventCode": "0x0", + "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed count= er)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed count= er)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", + "BriefDescription": "Total CPU cycles", "Counter": "0,1,2,3", - "UMask": "0x0", + "CounterMask": "2", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder = 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder = 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", + "EventCode": "0x17", + "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instru= ction queue" + "UMask": "0x1" }, { - "EventCode": "0x17", + "BriefDescription": "Cycles instructions are written to the instru= ction queue", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITES", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Ev= ent)" + "UMask": "0x2" }, { - "EventCode": "0x4C", + "BriefDescription": "Load operations conflicting with software pre= fetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software pre= fetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", + "BriefDescription": "Cycles no uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.INACTIVE", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction = queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction = queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)" + "UMask": "0x10" }, { - "EventCode": "0xDB", + "BriefDescription": "Stack pointer instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", + "BriefDescription": "Cycles no Uops are decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)= ", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" - }, - { + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on ports 0-4 (core count)", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x3f" }, { + "AnyThread": "1", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on any port (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", + "SampleAfterValue": "2000000", + "UMask": "0x3f" + }, + { "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", + "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x80", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT234_CORE", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", + "BriefDescription": "Cycles no Uops were issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles Uops are being retired", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Uop unfusions due to FP exceptions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index 57b53562e2bd..d63e469a43e1 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -1,173 +1,173 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses casued by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses casued by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x4F", + "BriefDescription": "Extended Page Table walk cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" + "UMask": "0x10" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" + "UMask": "0x4" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", - "EventCode": "0xCB", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)" + "UMask": "0x1" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2628C4332F for ; Tue, 1 Feb 2022 01:59:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232519AbiBAB7z (ORCPT ); Mon, 31 Jan 2022 20:59:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232251AbiBAB7e (ORCPT ); Mon, 31 Jan 2022 20:59:34 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC488C061759 for ; Mon, 31 Jan 2022 17:59:28 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id o131-20020a25d789000000b00614957c60dfso30386017ybg.15 for ; Mon, 31 Jan 2022 17:59:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=m9P7l1wPw2IJBEBlP+3ErnRE6Ow+jCRnbk5gI4kbsxM=; b=O/bBcIU2NBVcpPPXLRHQUnb0uBcE1JdAAXASarOIIjhmN+o264qIgBtlcVN2FIhuOq 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iiDqa4b0DrE7R2bq+iHEK+MG/sHLcMAA X-Google-Smtp-Source: ABdhPJyv6k9FvzP8w9o3dvcnm/M3QHxUi/5l8dKb5ckMorMYAes5F/50iipqlGanWpwr4wsuvhI3u8zUYAE9 X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a81:1214:: with SMTP id 20mr1643yws.486.1643680766681; Mon, 31 Jan 2022 17:59:26 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:40 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-9-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 08/26] perf vendor events: Update metrics for IcelakeX From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 1.11: https://download.01.org/perfmon/ICX Json files generated by: https://github.com/intel/event-converter-for-linux-perf Tested: ... 6: Parse event definition strings : Ok 7: Simple expression parser : Ok ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... 68: Parse and process metrics : Ok ... 88: perf stat metrics (shadow stat) test : Ok 89: perf all metricgroups test : Ok 90: perf all metrics test : FAIL= ED! 91: perf all PMU test : Ok ... Test 90 failed due to MEM_PMM_Read_Latency as the test machine lacks optane memory, and the divide by 0 causes the metric not to print - which is intended behavior. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/icelakex/cache.json | 851 ++++++++----- .../arch/x86/icelakex/floating-point.json | 51 +- .../arch/x86/icelakex/frontend.json | 501 ++++---- .../arch/x86/icelakex/icx-metrics.json | 304 ++++- .../pmu-events/arch/x86/icelakex/memory.json | 601 ++++++--- .../pmu-events/arch/x86/icelakex/other.json | 794 +++++++++++- .../arch/x86/icelakex/pipeline.json | 1112 +++++++++-------- .../arch/x86/icelakex/uncore-other.json | 61 +- .../arch/x86/icelakex/virtual-memory.json | 150 ++- 9 files changed, 2994 insertions(+), 1431 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/per= f/pmu-events/arch/x86/icelakex/cache.json index 624762008aaa..104409fd8647 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -1,111 +1,126 @@ [ { - "BriefDescription": "Demand Data Read miss L2, no rejects", + "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x21" + "UMask": "0x1" }, { - "BriefDescription": "RFO requests that miss L2 cache", + "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_MISS", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x22" + "UMask": "0x2" }, { - "BriefDescription": "L2 cache misses when fetching instructions", + "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailablability.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts number of phases a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x24" + "UMask": "0x2" }, { - "BriefDescription": "Demand requests that miss L2 cache", + "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.L2_STALL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts demand requests that miss L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x27" + "UMask": "0x4" }, { - "BriefDescription": "SW prefetch requests that miss L2 cache.", + "BriefDescription": "Number of L1D misses that are outstanding", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_MISS", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instru= ctions.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x28" + "UMask": "0x1" }, { - "BriefDescription": "Demand Data Read requests that hit L2 cache", + "BriefDescription": "Cycles with L1D load Misses outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0xc1" + "UMask": "0x1" }, { - "BriefDescription": "RFO requests that hit L2 cache", + "BriefDescription": "L2 cache lines filling L2", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_HIT", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", + "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1f" + }, + { + "BriefDescription": "Cache lines that are evicted by L2 cache when= triggered by an L2 cache fill.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.NON_SILENT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of lines that are evicted = by the L2 cache due to L2 cache fills. Evicted lines are delivered to the = L3, which may or may not cache them, according to system load and prioritie= s.", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0xc2" + "UMask": "0x2" }, { - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.SILENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", + "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0xc4" + "UMask": "0x1" }, { - "BriefDescription": "SW prefetch requests that hit L2 cache.", + "BriefDescription": "L2 code requests", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_HIT", + "EventName": "L2_RQSTS.ALL_CODE_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instruc= tions.", + "PublicDescription": "Counts the total number of L2 code requests.= ", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0xc8" + "UMask": "0xe4" }, { "BriefDescription": "Demand Data Read requests", @@ -119,6 +134,18 @@ "Speculative": "1", "UMask": "0xe1" }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x27" + }, { "BriefDescription": "RFO requests to L2 cache", "CollectPEBSRecord": "2", @@ -132,204 +159,177 @@ "UMask": "0xe2" }, { - "BriefDescription": "L2 code requests", + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_CODE_RD", + "EventName": "L2_RQSTS.CODE_RD_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of L2 code requests.= ", + "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0xe4" + "UMask": "0xc4" }, { - "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "BriefDescription": "L2 cache misses when fetching instructions", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x2e", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches from L1 and L2. It does not include all misses to the L3.", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x24" }, { - "BriefDescription": "Number of L1D misses that are outstanding", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0xc1" }, { - "BriefDescription": "Cycles with L1D load Misses outstanding.", + "BriefDescription": "Demand Data Read miss L2, no rejects", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x21" }, { - "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "BriefDescription": "RFO requests that hit L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0xc2" }, { - "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailablability.", + "BriefDescription": "RFO requests that miss L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of phases a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x22" }, { - "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "BriefDescription": "SW prefetch requests that hit L2 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.L2_STALL", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0xc8" }, { - "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "BriefDescription": "SW prefetch requests that miss L2 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "L1D.REPLACEMENT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x28" }, { - "BriefDescription": "For every cycle where the core is waiting on = at least 1 outstanding Demand RFO request, increments by 1.", + "BriefDescription": "L2 writebacks that access L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", "PEBScounters": "0,1,2,3", - "PublicDescription": "For every cycle where the core is waiting on= at least 1 outstanding demand RFO request, increments by 1. RFOs are ini= tiated by a core as part of a data store operation. Demand RFO requests in= clude RFOs, locks, and ItoM transactions. Requests are considered outstand= ing from the time they miss the core's L2 cache until the transaction compl= etion message is sent to the requestor.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x40" }, { - "BriefDescription": "For every cycle, increments by the number of = outstanding data read requests the core is waiting on.", + "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "For every cycle, increments by the number of= outstanding data read requests the core is waiting on. Data read requests= include cacheable demand reads and L2 prefetches, but do not include RFOs,= code reads or prefetches to the L3. Reads due to page walks resulting fro= m any request type will also be counted. Requests are considered outstandi= ng from the time they miss the core's L2 cache until the transaction comple= tion message is sent to the requestor.", - "SampleAfterValue": "1000003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x41" }, { - "BriefDescription": "For every cycle where the core is waiting on = at least 1 outstanding demand data read request, increments by 1.", + "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "For every cycle where the core is waiting on= at least 1 outstanding data read request, increments by 1. Data read requ= ests include cacheable demand reads and L2 prefetches, but do not include R= FOs, code reads or prefetches to the L3. Reads due to page walks resulting= from any request type will also be counted. Requests are considered outst= anding from the time they miss the core's L2 cache until the transaction co= mpletion message is sent to the requestor.", - "SampleAfterValue": "1000003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x4f" }, { - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "All retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xb0", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand and prefetch data reads", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts memory transactions sent to the uncore= .", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts memory transactions sent to the uncor= e including requests initiated by the core, all L3 prefetches, reads result= ing from page walks, and snoop responses.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x80" + "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", + "SampleAfterValue": "1000003", + "UMask": "0x81" }, { - "BriefDescription": "Retired load instructions that miss the STLB.= ", + "BriefDescription": "All retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that true m= iss the STLB.", - "SampleAfterValue": "100003", - "UMask": "0x11" + "PublicDescription": "Counts all retired store instructions. This = event account for SW prefetch instructions and PREFETCHW instruction for st= ores.", + "SampleAfterValue": "1000003", + "UMask": "0x82" }, { - "BriefDescription": "Retired store instructions that miss the STLB= .", + "BriefDescription": "All retired memory instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "EventName": "MEM_INST_RETIRED.ANY", "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that true = miss the STLB.", - "SampleAfterValue": "100003", - "UMask": "0x12" + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" }, { "BriefDescription": "Retired load instructions with locked access.= ", @@ -372,325 +372,570 @@ "UMask": "0x42" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions that miss the STLB.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", - "SampleAfterValue": "1000003", - "UMask": "0x81" + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions that miss the STLB= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_STORES", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired store instructions. This = event account for SW prefetch instructions and PREFETCHW instruction for st= ores.", - "SampleAfterValue": "1000003", - "UMask": "0x82" + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", - "SampleAfterValue": "1000003", - "UMask": "0x1" + "PublicDescription": "Counts retired load instructions whose data = sources were HitM responses from shared L3.", + "SampleAfterValue": "20011", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "BriefDescription": "This event is deprecated. Refer to new event = MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with L2 cac= he hits as data sources.", - "SampleAfterValue": "200003", + "SampleAfterValue": "20011", "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "BriefDescription": "This event is deprecated. Refer to new event = MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", - "SampleAfterValue": "100021", + "SampleAfterValue": "20011", "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", - "SampleAfterValue": "200003", - "UMask": "0x8" + "PublicDescription": "Counts the retired load instructions whose d= ata sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions missed L2 c= ache as data sources.", - "SampleAfterValue": "100021", - "UMask": "0x10" + "PublicDescription": "Counts retired load instructions whose data = sources were hits in L3 without snoops required.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", - "SampleAfterValue": "50021", - "UMask": "0x20" + "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", + "PublicDescription": "Retired load instructions which data sources= missed L3 but serviced from local DRAM.", "SampleAfterValue": "100007", - "UMask": "0x40" + "UMask": "0x1" }, { - "BriefDescription": "Retired demand load instructions which missed= L3 but serviced from local IXP memory as data sources", + "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from remote dram", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "100003", - "UMask": "0x80" + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the retired load instructions whose d= ata sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "SampleAfterValue": "20011", - "UMask": "0x1" + "PublicDescription": "Retired load instructions whose data sources= was forwarded from a remote cache.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "BriefDescription": "This event is deprecated. Refer to new event = MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Retired load instructions whose data sources = was remote HITM", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "20011", - "UMask": "0x2" + "PublicDescription": "Retired load instructions whose data sources= was remote HITM.", + "SampleAfterValue": "100007", + "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "BriefDescription": "Retired load instructions with remote Intel O= ptane DC persistent memory as the data source where the data request missed= all caches.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", - "SampleAfterValue": "20011", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts retired load instructions with remote= Intel Optane DC persistent memory as the data source and the data request = missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", + "SampleAfterValue": "100007", + "UMask": "0x10" }, { - "BriefDescription": "This event is deprecated. Refer to new event = MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or Bus Lock.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "EventCode": "0xd4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", "PEBS": "1", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "20011", + "PublicDescription": "Retired instructions with at least one load = to uncacheable memory-type, or at least one cache-line split locked access = (Bus Lock).", + "SampleAfterValue": "100007", "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data = sources were HitM responses from shared L3.", - "SampleAfterValue": "20011", - "Speculative": "1", - "UMask": "0x4" + "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data = sources were hits in L3 without snoops required.", - "SampleAfterValue": "100003", - "UMask": "0x8" + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "BriefDescription": "Retired load instructions missed L1 cache as = data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd3", - "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Retired load instructions which data sources= missed L3 but serviced from local DRAM.", - "SampleAfterValue": "100007", - "UMask": "0x1" + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from remote dram", + "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd3", - "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "100007", + "PublicDescription": "Counts retired load instructions with L2 cac= he hits as data sources.", + "SampleAfterValue": "200003", "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions whose data sources = was remote HITM", + "BriefDescription": "Retired load instructions missed L2 cache as = data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd3", - "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Retired load instructions whose data sources= was remote HITM.", - "SampleAfterValue": "100007", + "PublicDescription": "Counts retired load instructions missed L2 c= ache as data sources.", + "SampleAfterValue": "100021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", + "SampleAfterValue": "100021", "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "BriefDescription": "Retired load instructions missed L3 cache as = data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd3", - "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Retired load instructions whose data sources= was forwarded from a remote cache.", - "SampleAfterValue": "100007", - "UMask": "0x8" + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x20" }, { - "BriefDescription": "Retired demand load instructions which missed= L3 but serviced from remote IXP memory as data sources", + "BriefDescription": "Retired load instructions with local Intel Op= tane DC persistent memory as the data source where the data request missed = all caches.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd3", - "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Retired load instructions which data source = was serviced from L4", - "SampleAfterValue": "100007", - "UMask": "0x10" + "PublicDescription": "Counts retired load instructions with local = Intel Optane DC persistent memory as the data source and the data request m= issed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", + "SampleAfterValue": "100003", + "UMask": "0x80" }, { - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a modified line in a distant L3 Cache or = were snooped from a distant core's L1/L2 caches on this socket when the sys= tem is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that either hit a non-modified line in a distant L= 3 Cache or were snooped from a distant core's L1/L2 caches on this socket w= hen the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit a modified line in another c= ore's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit in another core's caches whi= ch forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a modified = line in a distant L3 Cache or were snooped from a distant core's L1/L2 cach= es on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that either hit a no= n-modified line in a distant L3 Cache or were snooped from a distant core's= L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) m= ode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = modified line in a distant L3 Cache or were snooped from a distant core's L= 1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mod= e.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that either= hit a non-modified line in a distant L3 Cache or were snooped from a dista= nt core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA c= luster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by a cache on a remote socket where a snoop hit a modified line = in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by a cache on a remote socket where a snoop hit in another core'= s caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hit= a modified line in a distant L3 Cache or were snooped from a distant core'= s L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) = mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that eit= her hit a non-modified line in a distant L3 Cache or were snooped from a di= stant core's L1/L2 caches on this socket when the system is in SNC (sub-NUM= A cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand and prefetch data reads", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF0", - "EventName": "L2_TRANS.L2_WB", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x40" + "UMask": "0x8" }, { - "BriefDescription": "L2 cache lines filling L2", + "BriefDescription": "Counts memory transactions sent to the uncore= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF1", - "EventName": "L2_LINES_IN.ALL", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", + "PublicDescription": "Counts memory transactions sent to the uncor= e including requests initiated by the core, all L3 prefetches, reads result= ing from page walks, and snoop responses.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1f" + "UMask": "0x80" }, { - "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "Counts cacheable and non-cacheable code reads= to the core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.SILENT", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts both cacheable and non-cacheable code= reads to the core.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cache lines that are evicted by L2 cache when= triggered by an L2 cache fill.", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.NON_SILENT", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are evicted = by the L2 cache due to L2 cache fills. Evicted lines are delivered to the = L3, which may or may not cache them, according to system load and prioritie= s.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "For every cycle, increments by the number of = outstanding data read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of= outstanding data read requests pending. Data read requests include cachea= ble demand reads and L2 prefetches, but do not include RFOs, code reads or = prefetches to the L3. Reads due to page walks resulting from any request t= ype will also be counted. Requests are considered outstanding from the tim= e they miss the core's L2 cache until the transaction completion message is= sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles where at least 1 outstanding data read= request is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least 1 outstanding data rea= d request is pending. Data read requests include cacheable demand reads an= d L2 prefetches, but do not include RFOs, code reads or prefetches to the L= 3. Reads due to page walks resulting from any request type will also be co= unted. Requests are considered outstanding from the time they miss the cor= e's L2 cache until the transaction completion message is sent to the reques= tor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with outstanding code read requests pe= nding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles with outstanding code read requests p= ending. Code Read requests include both cacheable and non-cacheable Code R= eads. Requests are considered outstanding from the time they miss the core= 's L2 cache until the transaction completion message is sent to the request= or.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 outstanding Demand RF= O request is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least 1 outstanding Demand R= FO request is pending. RFOs are initiated by a core as part of a data sto= re operation. Demand RFO requests include RFOs, locks, and ItoM transactio= ns. Requests are considered outstanding from the time they miss the core's= L2 cache until the transaction completion message is sent to the requestor= .", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "For every cycle, increments by the number of = outstanding code read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of= outstanding code read requests pending. Code Read requests include both c= acheable and non-cacheable Code Reads. Requests are considered outstandin= g from the time they miss the core's L2 cache until the transaction complet= ion message is sent to the requestor.", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x2" }, + { + "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Cycles the queue waiting for offcore response= s is full.", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/icelakex/floating-point.json index bcedcd985e84..4347e2d0d090 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json @@ -11,26 +11,6 @@ "Speculative": "1", "UMask": "0x2" }, - { - "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", "CollectPEBSRecord": "2", @@ -38,6 +18,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x4" }, @@ -48,7 +29,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of SSE/AVX computational 128-b= it packed single precision floating-point instructions retired; some instru= ctions will count twice as noted below. Each count represents 4 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MI= N MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions c= ount twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x8" }, @@ -59,6 +40,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x10" }, @@ -69,6 +51,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x20" }, @@ -79,17 +62,41 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", "SampleAfterValue": "100003", "UMask": "0x40" }, { - "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed double= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x80" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/= perf/pmu-events/arch/x86/icelakex/frontend.json index cc59cee1cd57..f217c3211ba2 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json @@ -1,230 +1,83 @@ [ { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.MITE_UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles MITE is delivering any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. During these cycles uops are not being delivered from the Decod= e Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.DSB_UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_ANY", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delive= red to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) p= ath.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_SWITCHES", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.COUNT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "PublicDescription": "Counts the number of Decode Stream Buffer (D= SB a.k.a. Uop Cache)-to-MITE speculative transitions.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x30" + "UMask": "0x2" }, { - "BriefDescription": "Uops delivered to IDQ while MS is busy", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.MS_UOPS", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x30" - }, - { - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "ICACHE_16B.IFDATA_STALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", - "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_STALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x9c", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "BriefDescription": "Retired Instructions who experienced DSB miss= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "5", - "EventCode": "0x9c", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", + "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "Invert": "1", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "DSB-to-MITE switch true penalty cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of Decode Stream Buffer (D= SB a.k.a. Uop Cache)-to-MITE speculative transitions.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.DSB_MISS", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x11", + "MSRValue": "0x14", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" @@ -260,91 +113,91 @@ "UMask": "0x1" }, { - "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", - "MSRValue": "0x14", + "MSRValue": "0x500106", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", + "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.STLB_MISS", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", - "MSRValue": "0x15", + "MSRValue": "0x508006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 12= 8 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", - "MSRValue": "0x500206", + "MSRValue": "0x501006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", - "MSRValue": "0x500406", + "MSRValue": "0x500206", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 4 = cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 2 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", - "MSRValue": "0x500806", + "MSRValue": "0x510006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 25= 6 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", - "MSRValue": "0x501006", + "MSRValue": "0x100206", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" @@ -365,105 +218,267 @@ "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", - "MSRValue": "0x504006", + "MSRValue": "0x500406", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 64= cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 4 = cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", - "MSRValue": "0x508006", + "MSRValue": "0x520006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 12= 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 51= 2 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", - "MSRValue": "0x510006", + "MSRValue": "0x504006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 25= 6 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 64= cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", - "MSRValue": "0x520006", + "MSRValue": "0x500806", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 51= 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x100206", + "MSRValue": "0x15", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", + "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x500106", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE_16B.IFDATA_STALL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", + "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xe6", - "EventName": "BACLEARS.ANY", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", + "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_STALL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delive= red to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) p= ath.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. During these cycles uops are not being delivered from the Decod= e Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "SampleAfterValue": "100003", "Speculative": "1", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 14b9a8ab15b9..a737fa40feb0 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -1,26 +1,38 @@ [ + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED= .NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 *= BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_= STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHAL= TED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TO= PDOWN.SLOTS)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -30,27 +42,53 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", + "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on el= se 1", + "MetricGroup": "SMT", + "MetricName": "Slots_Utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -74,122 +112,237 @@ { "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.25= 6B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARI= TH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SI= NGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", - "MetricGroup": "LSD", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", + "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_B= RANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BR= ANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_= RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_= TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not indi= vidually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRE= D.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHE= S) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST= _RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.CON= D_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", + "MetricGroup": "Bad;Branches", + "MetricName": "Other_Branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIB= UTED )", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_R= EQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) = / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Offcore", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIB= UTED )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_Silent_PKI" }, { "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, { @@ -207,7 +360,7 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -216,6 +369,27 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." + }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_DISTRIBUTED if #SMT_on else 0", @@ -228,52 +402,64 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", "MetricExpr": "1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / = UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( cha_0@event\\=3D0x0@ / duration_time = )", - "MetricGroup": "MemoryLat;SoC", + "MetricGroup": "Mem;MemoryLat;SoC", "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@event\\=3D0= x36\\,umask\\=3D0xC817FE01\\,thresh\\=3D1@", - "MetricGroup": "MemoryBW;SoC", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Average latency of data read request to exter= nal 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2= data-read prefetches", "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_= PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha_0@event\\=3D0x0@ )", - "MetricGroup": "MemoryLat;SoC;Server", + "MetricGroup": "Mem;MemoryLat;SoC;Server", "MetricName": "MEM_PMM_Read_Latency" }, + { + "BriefDescription": "Average latency of data read request to exter= nal DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-= read prefetches", + "MetricExpr": " 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_D= DR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha_0@event\\=3D0x0@", + "MetricGroup": "Mem;MemoryLat;SoC;Server", + "MetricName": "MEM_DRAM_Read_Latency" + }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [= GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=3D0xe3@ / 1000000000 ) / durat= ion_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Read_BW" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes = [GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=3D0xe7@ / 1000000000 ) / durat= ion_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Writes [GB / sec]", "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 /= duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Reads [GB / sec]", "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INS= ERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_= INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Read_BW" }, { @@ -289,10 +475,10 @@ "MetricName": "IpFarBranch" }, { - "BriefDescription": "C1 residency percent per core", - "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", - "MetricName": "C1_Core_Residency" + "MetricName": "C3_Core_Residency" }, { "BriefDescription": "C6 residency percent per core", @@ -300,16 +486,34 @@ "MetricGroup": "Power", "MetricName": "C6_Core_Residency" }, + { + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency" + }, { "BriefDescription": "C2 residency percent per package", "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C2_Pkg_Residency" }, + { + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency" + }, { "BriefDescription": "C6 residency percent per package", "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" + }, + { + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/pe= rf/pmu-events/arch/x86/icelakex/memory.json index d319d448e2aa..9ebcd442e6d3 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json @@ -1,109 +1,420 @@ [ { - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x6" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_READ", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x80" + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC2", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "6", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x6" + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.START", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution successfully= committed", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.COMMIT", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM commit succee= ded.", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x2" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F8CC00004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches and the cacheline is homed lo= cally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F8CC00001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches and were supplied by= the local socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F0CC00002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were not supplied by the local so= cket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were not supplied by the local so= cket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F8CC00400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only tha= t missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94002380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84002380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cacheline writes (ItoM) that were= not supplied by the local socket's L1, L2, or L3 caches and the cacheline = is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ITOM.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that were not supplied by the local socket's L1, L2= , or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC08000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that were not supplied by the local socket's L1, L2= , or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F8CC08000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware and software prefetches to al= l cache levels that were not supplied by the local socket's L1, L2, or L3 c= aches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F8CC027F0", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the local socket's L1, L2, or L3 caches and were supplied= by the local socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F0CC00477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that missed the local= socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94000800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplie= d by the local socket's L1, L2, or L3 caches and the cacheline is homed loc= ally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where at least one demand data read re= quest known to have missed the L3 cache is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least one demand data read r= equest known to have missed the L3 cache is pending. Note that this does n= ot capture all elapsed cycles while requests are outstanding - only cycles = from when the requests were known to have missed the L3 cache.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "For every cycle, increments by the number of = demand data read requests pending that are known to have missed the L3 cach= e.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of= demand data read requests pending that are known to have missed the L3 cac= he. Note that this does not capture all elapsed cycles while requests are = outstanding - only cycles from when the requests were known to have missed = the L3 cache.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where the core is waiting on at least = 6 outstanding demand data read requests known to have missed the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where the core is waiting on at least= 6 outstanding demand data read requests known to have missed the L3 cache.= Note that this event does not capture all elapsed cycles while the reques= ts are outstanding - only cycles from when the requests were known to have = missed the L3 cache.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" }, { "BriefDescription": "Number of times an RTM execution aborted.", @@ -117,26 +428,26 @@ "UMask": "0x4" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEM", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", + "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", "SampleAfterValue": "100003", - "UMask": "0x8" + "UMask": "0x80" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "EventName": "RTM_RETIRED.ABORTED_MEM", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", + "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", "SampleAfterValue": "100003", - "UMask": "0x20" + "UMask": "0x8" }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", @@ -150,142 +461,96 @@ "UMask": "0x40" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", + "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", "SampleAfterValue": "100003", - "UMask": "0x80" + "UMask": "0x20" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "BriefDescription": "Number of times an RTM execution successfully= committed", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", + "PublicDescription": "Counts the number of times RTM commit succee= ded.", "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "BriefDescription": "Number of times an RTM execution started.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "20011", - "TakenAlone": "1", + "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", - "UMask": "0x1" + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "MSRValue": "0x200", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "101", - "TakenAlone": "1", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", + "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/per= f/pmu-events/arch/x86/icelakex/other.json index ef50d3a3392e..43524f274307 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json @@ -1,14 +1,15 @@ [ { - "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", "CollectPEBSRecord": "2", - "Counter": "35", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x7" }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", @@ -47,91 +48,199 @@ "UMask": "0x20" }, { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "BriefDescription": "Hit snoop reply with data, line invalidated.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated: removed from this core's cache, after the dat= a is forwarded back to the requestor and indicating the data was found unmo= dified in the (FE) Forward or Exclusive State in this cores caches cache. = A single snoop response from the core counts on all hyperthreads of the cor= e.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "BriefDescription": "HitM snoop reply with data, line invalidated.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.I_FWD_M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated: removed from this core's caches, after the da= ta is forwarded back to the requestor, and indicating the data was found mo= dified(M) in this cores caches cache (aka HitM response). A single snoop r= esponse from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x10" }, { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "BriefDescription": "Hit snoop reply without sending the data, lin= e invalidated.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated in this core's caches without being forwarded = back to the requestor. The line was in Forward, Shared or Exclusive (FSE) s= tate in this cores caches. A single snoop response from the core counts on= all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x2" }, { - "BriefDescription": "Number of PREFETCHW instructions executed.", + "BriefDescription": "Line not found snoop reply", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating that t= he data was not found (IHitI) in this core's caches. A single snoop respons= e from the core counts on all hyperthreads of the Core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "BriefDescription": "Hit snoop reply with data, line kept in Share= d state.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", - "SampleAfterValue": "10000003", + "Counter": "0,1,2,3", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts responses to snoops indicating the li= ne may be kept on this core in the (S)hared state, after the data is forwar= ded back to the requestor, initially the data was found in the cache in the= (FS) Forward or Shared state. A single snoop response from the core count= s on all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x40" }, { - "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "BriefDescription": "HitM snoop reply with data, line kept in Shar= ed state", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", - "SampleAfterValue": "10000003", + "Counter": "0,1,2,3", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.S_FWD_M", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts responses to snoops indicating the li= ne may be kept on this core in the (S)hared state, after the data is forwar= ded back to the requestor, initially the data was found in the cache in the= (M)odified state. A single snoop response from the core counts on all hyp= erthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "BriefDescription": "Hit snoop reply without sending the data, lin= e kept in Shared state.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc1", - "EventName": "ASSISTS.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts responses to snoops indicating the li= ne was kept on this core in the (S)hared state, and that the data was found= unmodified but not forwarded back to the requestor, initially the data was= found in the cache in the (FSE) Forward, Shared state or Exclusive state. = A single snoop response from the core counts on all hyperthreads of the co= re.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x7" + "UMask": "0x4" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit in the L3 or were snooped from another co= re's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that resulted in a snoop hit a modified line in an= other core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that the DRAM attached to this socket supplied the= request.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM on a distant memory con= troller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the L3 o= r were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches, data forwarding is re= quired as the data is modified.", + "BriefDescription": "Counts demand data reads that resulted in a s= noop hit a modified line in another core's caches which forwarded the data.= ", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", @@ -143,7 +252,19 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches which forwarded the un= modified data to the requesting core.", + "BriefDescription": "Counts demand data reads that resulted in a s= noop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another core's caches which forwarded the unmodified data to th= e requesting core.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -155,7 +276,127 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts writes that generate a demand reads fo= r ownership (RFO) request and software prefetches for exclusive ownership (= PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core= s caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand data reads that the DRAM attach= ed to this socket supplied the request.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y PMM attached to this socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y PMM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y DRAM on a distant memory controller of this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that (IC) were suppl= ied by PMM on a distant memory controller of this socket when the system is= in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit in= the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that result= ed in a snoop hit a modified line in another core's caches which forwarded = the data.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", @@ -167,15 +408,446 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that have any type of= response.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that the DR= AM attached to this socket supplied the request.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10800", + "MSRValue": "0x104000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM attached to this socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.REMOTE_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM on a distant memory controller of this socket when the syst= em is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that (IC) w= ere supplied by PMM on a distant memory controller of this socket when the = system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit in the L3 or were snooped fro= m another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that the DRAM attached to this socket = supplied the request.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only tha= t have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x12380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit in the L3 or were snooped from another core's caches on the same sock= et.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80082380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline was homed in a remote socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.REMOTE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90002380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cacheline writes (ItoM) that were= not supplied by the local socket's L1, L2, or L3 caches and the cacheline = was homed in a remote socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ITOM.REMOTE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware and software prefetches to al= l cache levels that hit in the L3 or were snooped from another core's cache= s on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PREFETCHES.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C27F0", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hit= in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that res= ulted in a snoop hit a modified line in another core's caches which forward= ed the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that res= ulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that res= ulted in a snoop hit in another core's caches which forwarded the unmodifie= d data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that the= DRAM attached to this socket supplied the request.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by PMM attached to this socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the local socket's L1, L2, or L3 caches and were supplied= by a remote socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F33000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM on a distant memory controller of this socket when the s= ystem is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that (IC= ) were supplied by PMM on a distant memory controller of this socket when t= he system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that hit in the L3 or= were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/icelakex/pipeline.json index 3cc71244e699..9a0b4907cb3a 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -1,206 +1,218 @@ [ { - "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.ANY", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when divide unit is busy execu= ting divide or square root operations. Accounts for integer and floating-po= int operations.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x9" + }, + { + "BriefDescription": "All branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all branch instructions retired.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", + "BriefDescription": "Conditional branch instructions retired.", "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.PREC_DIST", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts conditional branch instructions retir= ed.", + "SampleAfterValue": "400009", + "UMask": "0x11" }, { - "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "BriefDescription": "Not taken branch instructions retired.", "CollectPEBSRecord": "2", - "Counter": "33", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts not taken branch instructions retired= .", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "BriefDescription": "Reference cycles when the core is not in halt= state.", + "BriefDescription": "Taken conditional branch instructions retired= .", "CollectPEBSRecord": "2", - "Counter": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PEBScounters": "34", - "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x3" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts taken conditional branch instructions= retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "BriefDescription": "Far branch instructions retired.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts near indirect branch instructions ret= ired excluding returns. TSX abort is an indirect branch.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" + "UMask": "0x80" }, { - "BriefDescription": "False dependencies due to partial compare on = address.", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies due to partial compare on address.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts both direct and indirect near call in= structions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "BriefDescription": "Return instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "BriefDescription": "Taken branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0D", - "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles the Backend cluster is recover= ing after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x3" + "PublicDescription": "Counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "BriefDescription": "TMA slots where uops got dropped", + "BriefDescription": "All mispredicted branch instructions retired.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.UOP_DROPPING", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" + "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", + "SampleAfterValue": "50021" }, { - "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x80" + "PublicDescription": "Counts mispredicted conditional branch instr= uctions retired.", + "SampleAfterValue": "50021", + "UMask": "0x11" }, { - "BriefDescription": "Uops that RAT issues to RS", + "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.ANY", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts the number of conditional branch inst= ructions retired that were mispredicted and the branch direction was not ta= ken.", + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", + "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken. Non PEBS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "Invert": "1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", - "SampleAfterValue": "1000003", - "Speculative": "1", + "PublicDescription": "Counts taken conditional mispredicted branch= instructions retired.", + "SampleAfterValue": "50021", "UMask": "0x1" }, { - "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts all miss-predicted indirect branch in= structions retired (excluding RETs. TSX aborts is considered indirect branc= h).", + "SampleAfterValue": "50021", + "UMask": "0x80" }, { - "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x14", - "EventName": "ARITH.DIVIDER_ACTIVE", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when divide unit is busy execu= ting divide or square root operations. Accounts for integer and floating-po= int operations.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x9" + "PublicDescription": "Counts retired mispredicted indirect (near t= aken) calls, including both register and memory indirect.", + "SampleAfterValue": "50021", + "UMask": "0x2" }, { - "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", - "SampleAfterValue": "2000003", - "Speculative": "1" + "PublicDescription": "Counts number of near branch instructions re= tired that were mispredicted and taken.", + "SampleAfterValue": "50021", + "UMask": "0x20" }, { - "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", - "SampleAfterValue": "25003", + "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", @@ -227,317 +239,357 @@ "UMask": "0x8" }, { - "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", + "SampleAfterValue": "25003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "SampleAfterValue": "2000003", + "Speculative": "1" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x4c", - "EventName": "LOAD_HIT_PREFETCH.SWPF", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5e", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into stravation periods (e.g. branch mispredi= ctions or i-cache misses)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x5E", - "EventName": "RS_EVENTS.EMPTY_END", - "Invert": "1", + "CounterMask": "16", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to closely sample on front-end late= ncy issues (see the FRONTEND_RETIRED event of designated precise events)", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x10" }, { - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", - "SampleAfterValue": "500009", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0xc" }, { - "BriefDescription": "Number of uops executed on port 0", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_0", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", - "SampleAfterValue": "2000003", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x5" }, { - "BriefDescription": "Number of uops executed on port 1", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_1", + "CounterMask": "20", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", - "SampleAfterValue": "2000003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x14" }, { - "BriefDescription": "Number of uops executed on port 2 and 3", + "BriefDescription": "Total execution stalls.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_2_3", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", - "SampleAfterValue": "2000003", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x4" }, { - "BriefDescription": "Number of uops executed on port 4 and 9", + "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_4_9", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", + "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x2" }, { - "BriefDescription": "Number of uops executed on port 5", + "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_5", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", + "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x4" }, { - "BriefDescription": "Number of uops executed on port 6", + "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_6", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", + "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x40" + "UMask": "0x8" }, { - "BriefDescription": "Number of uops executed on port 7 and 8", + "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_7_8", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", + "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x10" }, { - "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SCOREBOARD", + "CounterMask": "2", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", + "PublicDescription": "Counts cycles where the Store Buffer was ful= l and no loads caused an execution stall.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x40" }, { - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SB", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "500009", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "BriefDescription": "Instruction decoders utilized in a cycle", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "EventCode": "0x55", + "EventName": "INST_DECODED.DECODERS", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Total execution stalls.", + "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x4" + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x5" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "BriefDescription": "Number of all retired NOP instructions.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0xc" + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "16", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts cycles the Backend cluster is recover= ing after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x3" }, { - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "20", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "EventCode": "0x0d", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", + "SampleAfterValue": "500009", "Speculative": "1", - "UMask": "0x14" + "UMask": "0x80" }, { - "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", + "SampleAfterValue": "500009", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "TMA slots where uops got dropped", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "EventCode": "0x0d", + "EventName": "INT_MISC.UOP_DROPPING", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", + "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x10" }, { - "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x8" }, { - "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x2" }, { - "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "BriefDescription": "False dependencies due to partial compare on = address.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles where the Store Buffer was ful= l and no loads caused an execution stall.", - "SampleAfterValue": "1000003", + "Counter": "0,1,2,3", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies due to partial compare on address.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x40" + "UMask": "0x1" }, { - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xa8", - "EventName": "LSD.UOPS", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, @@ -568,405 +620,425 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "BriefDescription": "Number of Uops delivered by the LSD.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.THREAD", - "PEBScounters": "0,1,2,3,4,5,6,7", + "Counter": "0,1,2,3", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of machine clears (nukes) = of any type.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "BriefDescription": "Self-modifying code (SMC) detected.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x4" }, { - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "BriefDescription": "Increments whenever there is an update to the= LBR array.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR to be enabled properly.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.PAUSE_INST", + "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SB", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 1 micro-op is ex= ecuted from any thread on physical core.", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "EventCode": "0x5e", + "EventName": "RS_EVENTS.EMPTY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 2 micro-ops are = executed from any thread on physical core.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into stravation periods (e.g. branch mispredi= ctions or i-cache misses)", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 3 micro-ops are = executed from any thread on physical core.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to closely sample on front-end late= ncy issues (see the FRONTEND_RETIRED event of designated precise events)", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 4 micro-ops are = executed from any thread on physical core.", - "SampleAfterValue": "2000003", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Counts the number of x87 uops dispatched.", + "BriefDescription": "Number of uops executed on port 0", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.X87", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_0", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of x87 uops executed.", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x1" }, { - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "BriefDescription": "Number of uops executed on port 1", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc0", - "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003" + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "BriefDescription": "Number of uops executed on port 2 and 3", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_2_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles using always tru= e condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "1000003", - "UMask": "0x2" + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Retirement slots used.", + "BriefDescription": "Number of uops executed on port 4 and 9", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.SLOTS", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_4_9", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the retirement slots used each cycle.= ", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "Speculative": "1", + "UMask": "0x10" }, { - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "BriefDescription": "Number of uops executed on port 5", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.COUNT", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_5", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of machine clears (nukes) = of any type.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Number of uops executed on port 6", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.SMC", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_6", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x40" }, { - "BriefDescription": "All branch instructions retired.", + "BriefDescription": "Number of uops executed on port 7 and 8", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_7_8", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all branch instructions retired.", - "SampleAfterValue": "400009" + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Taken conditional branch instructions retired= .", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional branch instructions= retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" + "PublicDescription": "Counts cycles when at least 1 micro-op is ex= ecuted from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Direct and indirect near call instructions re= tired.", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts both direct and indirect near call in= structions retired.", - "SampleAfterValue": "100007", + "PublicDescription": "Counts cycles when at least 2 micro-ops are = executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Return instructions retired.", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts return instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x8" + "PublicDescription": "Counts cycles when at least 3 micro-ops are = executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_NTAKEN", - "PEBS": "1", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts not taken branch instructions retired= .", - "SampleAfterValue": "400009", - "UMask": "0x10" + "PublicDescription": "Counts cycles when at least 4 micro-ops are = executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Conditional branch instructions retired.", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts conditional branch instructions retir= ed.", - "SampleAfterValue": "400009", - "UMask": "0x11" + "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Taken branch instructions retired.", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PEBS": "1", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x20" + "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts far branch instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x40" + "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "All indirect branch instructions retired (exc= luding RETs. TSX aborts are considered indirect branch).", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.INDIRECT", - "PEBS": "1", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions reti= red (excluding RETs. TSX aborts is considered indirect branch).", - "SampleAfterValue": "100003", - "UMask": "0x80" + "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "All mispredicted branch instructions retired.= ", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", - "SampleAfterValue": "50021" + "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken. Non PEBS", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional mispredicted branch= instructions retired.", - "SampleAfterValue": "50021", + "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "BriefDescription": "Counts the number of x87 uops dispatched.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", - "PEBS": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.X87", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of conditional branch inst= ructions retired that were mispredicted and the branch direction was not ta= ken.", - "SampleAfterValue": "50021", + "PublicDescription": "Counts the number of x87 uops executed.", + "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "BriefDescription": "Uops that RAT issues to RS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts mispredicted conditional branch instr= uctions retired.", - "SampleAfterValue": "50021", - "UMask": "0x11" + "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of near branch instructions re= tired that were mispredicted and taken.", - "SampleAfterValue": "50021", - "UMask": "0x20" + "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", + "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all miss-predicted indirect branch in= structions retired (excluding RETs. TSX aborts is considered indirect branc= h).", - "SampleAfterValue": "50021", - "UMask": "0x80" + "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", + "BriefDescription": "Retirement slots used.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.PAUSE_INST", - "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", - "SampleAfterValue": "100003", - "UMask": "0x40" + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the retirement slots used each cycle.= ", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "BriefDescription": "Cycles without actually retired uops.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xec", - "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", - "SampleAfterValue": "2000003", + "PublicDescription": "This event counts cycles without actually re= tired uops.", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "10", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles using always tru= e condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "1000003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/icelakex/uncore-other.json index 52f2301582bb..71e052667e50 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json @@ -60,7 +60,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the uncore caching &amp; ho= me agent (CHA)", + "BriefDescription": "Clockticks of the uncore caching and home age= nt (CHA)", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventName": "UNC_CHA_CLOCKTICKS", @@ -2472,5 +2472,64 @@ "PerPkg": "1", "UMask": "0x27", "Unit": "UPI LL" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices to locally HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices : Counts the number of entries succes= sfuly inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xCD42FF04", + "UMaskExt": "0xCD42FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices to remotely HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices : Counts the number of entries succes= sfuly inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xCD437F04", + "UMaskExt": "0xCD437F", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to l= ocally HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : C= ounts the number of entries successfuly inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", + "UMask": "0xCC42FF04", + "UMaskExt": "0xCC42FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to r= emotely HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : C= ounts the number of entries successfuly inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", + "UMask": "0xCC437F04", + "UMaskExt": "0xCC437F", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates : Fr= om/to any state. Note: event counts are incorrect in 2LM mode.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2e", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Multi-socket cacheline Directory Updates : F= rom/to any state. Note: event counts are incorrect in 2LM mode.", + "UMask": "0x01", + "Unit": "M2M" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json index 1b9d03039c53..bc43ea855840 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json @@ -1,27 +1,28 @@ [ { - "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x20" }, { - "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a demand load.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x10" }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", @@ -36,65 +37,77 @@ "UMask": "0xe" }, { - "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", + "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x8" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a demand load.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x4" }, { - "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", + "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x2" }, { - "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x20" }, { - "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a store.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x10" }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", @@ -109,65 +122,77 @@ "UMask": "0xe" }, { - "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", + "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x8" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a store.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x4" }, { - "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", + "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x2" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "EventName": "ITLB_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", + "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x20" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "EventName": "ITLB_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a code (instruction fetch) request= .", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x10" }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", @@ -182,41 +207,40 @@ "UMask": "0xe" }, { - "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_PENDING", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", + "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x4" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_ACTIVE", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a code (instruction fetch) request= .", + "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x2" }, { - "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x85", - "EventName": "ITLB_MISSES.STLB_HIT", + "EventName": "ITLB_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x10" }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B715AC433F5 for ; Tue, 1 Feb 2022 02:00:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232191AbiBACAS (ORCPT ); Mon, 31 Jan 2022 21:00:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232259AbiBAB7e (ORCPT ); Mon, 31 Jan 2022 20:59:34 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43310C06173B for ; Mon, 31 Jan 2022 17:59:31 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id i10-20020a25540a000000b0061391789216so30528907ybb.2 for ; Mon, 31 Jan 2022 17:59:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=IYSlycU9lIF6lm3LvLPYLGd5cIVLv8NNBJ+0Oesu4hQ=; b=JdFVGax+WE6ZdBhi3IcC43XSGTA7WzpQxLDkKx9ECouINN/2vno76kyBIE4whQMFs6 DxIeOX4yW25N8UB/QI8r4IYFQGG7GLEZE2er6CPTp3axbnGYhvGW16lc6dzmMY3hvh+v FG8o2FyS8vKtSjnDdCodHlImh02VgUpHN5CuOcjhBXTxCXvWJBwQ6ZcHd1BfVzY7Xu5d 8ScvVqi/+wRtekTgzp1iVjgXDmPxHtAwRBJkKbZ4t/6BI/moAsTTp8lFGmNDInAo79qr LujLWHCZPOnpPJ6477XnKoLyfqQwIx0fg+xDQjIZ7hjFwMFImE8Z1qvOaY1Kj/cqFdp4 2WuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=IYSlycU9lIF6lm3LvLPYLGd5cIVLv8NNBJ+0Oesu4hQ=; b=3gErlEBzVgtPUAxNgEhFz9fLtdBk3R93HrUjAOEkOZ9iWVHmTRX0AKkJoDWoQ0+47I mWxd+OrBu6QPtEUG8j28WYtEqWeFM7VNYFXyhttMyUTeJNEafBs6q3zjETwLvj1kbVIg 6BsQQREkObco8FPq0VerfZ0Tj5S+Bx4rOLOx3jC028nv8xAFSRd1vFAdNj4rkfg3M0L+ bQha368dKC5I1wlT12oVdgWgqwXt+sd9FYzhJMg/ySaV162g7eMxeR1yhBwmjOX4aVxT qlYJUOBfwkUjFMYVMKwkym0uVDIAZ4GOVvrZCWZxpswDSIP1VlkWXfpvb8LUh3f+Fg9X yktg== X-Gm-Message-State: AOAM533lVttaGcL9oG1wJME54rtgGl+JRUZrrJSME1Sgh7buZZpkwyyI lnd0T9GU17Lu8tDbhI0CmVlG+WCY2MYY X-Google-Smtp-Source: ABdhPJyV1agnwaGYs20HFQRLvkS7M3xOIjjJctqdUW7XZnHvkBYVumn0HciR7vQxTPzpiaCKgbuJihBK0T2t X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a05:6902:1022:: with SMTP id x2mr37023025ybt.124.1643680770397; Mon, 31 Jan 2022 17:59:30 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:41 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-10-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 09/26] perf vendor events: Update for Bonnell From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Events are still at version 4: https://download.01.org/perfmon/BNL Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Bonnell, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/bonnell/cache.json | 748 +++++++++--------- .../arch/x86/bonnell/floating-point.json | 274 +++---- .../pmu-events/arch/x86/bonnell/frontend.json | 96 +-- .../pmu-events/arch/x86/bonnell/memory.json | 152 ++-- .../pmu-events/arch/x86/bonnell/other.json | 452 +++++------ .../pmu-events/arch/x86/bonnell/pipeline.json | 402 +++++----- .../arch/x86/bonnell/virtual-memory.json | 126 +-- 7 files changed, 1125 insertions(+), 1125 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf= /pmu-events/arch/x86/bonnell/cache.json index ffab90c5891c..71653bfe7093 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json @@ -1,746 +1,746 @@ [ { - "EventCode": "0x21", + "BriefDescription": "L1 Data Cacheable reads and writes", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_ADS.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Cycles L2 address bus is in use." + "EventCode": "0x40", + "EventName": "L1D_CACHE.ALL_CACHE_REF", + "SampleAfterValue": "2000000", + "UMask": "0xa3" }, { - "EventCode": "0x22", + "BriefDescription": "L1 Data reads and writes", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_DBUS_BUSY.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Cycles the L2 cache data bus is busy." + "EventCode": "0x40", + "EventName": "L1D_CACHE.ALL_REF", + "SampleAfterValue": "2000000", + "UMask": "0x83" }, { - "EventCode": "0x23", + "BriefDescription": "Modified cache lines evicted from the L1 data= cache", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_DBUS_BUSY_RD.SELF", + "EventCode": "0x40", + "EventName": "L1D_CACHE.EVICT", "SampleAfterValue": "200000", - "BriefDescription": "Cycles the L2 transfers data to the core." + "UMask": "0x10" }, { - "EventCode": "0x24", + "BriefDescription": "L1 Cacheable Data Reads", "Counter": "0,1", - "UMask": "0x70", - "EventName": "L2_LINES_IN.SELF.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache misses." + "EventCode": "0x40", + "EventName": "L1D_CACHE.LD", + "SampleAfterValue": "2000000", + "UMask": "0xa1" }, { - "EventCode": "0x24", + "BriefDescription": "L1 Data line replacements", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_LINES_IN.SELF.DEMAND", + "EventCode": "0x40", + "EventName": "L1D_CACHE.REPL", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache misses." + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "Modified cache lines allocated in the L1 data= cache", "Counter": "0,1", - "UMask": "0x50", - "EventName": "L2_LINES_IN.SELF.PREFETCH", + "EventCode": "0x40", + "EventName": "L1D_CACHE.REPLM", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache misses." + "UMask": "0x48" }, { - "EventCode": "0x25", + "BriefDescription": "L1 Cacheable Data Writes", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_M_LINES_IN.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache line modifications." + "EventCode": "0x40", + "EventName": "L1D_CACHE.ST", + "SampleAfterValue": "2000000", + "UMask": "0xa2" }, { - "EventCode": "0x26", + "BriefDescription": "Cycles L2 address bus is in use.", "Counter": "0,1", - "UMask": "0x70", - "EventName": "L2_LINES_OUT.SELF.ANY", + "EventCode": "0x21", + "EventName": "L2_ADS.SELF", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache lines evicted." + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "All data requests from the L1 data cache", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_LINES_OUT.SELF.DEMAND", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache lines evicted." + "UMask": "0x44" }, { - "EventCode": "0x26", + "BriefDescription": "All data requests from the L1 data cache", "Counter": "0,1", - "UMask": "0x50", - "EventName": "L2_LINES_OUT.SELF.PREFETCH", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache lines evicted." + "UMask": "0x41" }, { - "EventCode": "0x27", + "BriefDescription": "All data requests from the L1 data cache", "Counter": "0,1", - "UMask": "0x70", - "EventName": "L2_M_LINES_OUT.SELF.ANY", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.MESI", "SampleAfterValue": "200000", - "BriefDescription": "Modified lines evicted from the L2 cache" + "UMask": "0x4f" }, { - "EventCode": "0x27", + "BriefDescription": "All data requests from the L1 data cache", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_M_LINES_OUT.SELF.DEMAND", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Modified lines evicted from the L2 cache" + "UMask": "0x48" }, { - "EventCode": "0x27", + "BriefDescription": "All data requests from the L1 data cache", "Counter": "0,1", - "UMask": "0x50", - "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Modified lines evicted from the L2 cache" + "UMask": "0x42" }, { - "EventCode": "0x28", + "BriefDescription": "Cycles the L2 cache data bus is busy.", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_IFETCH.SELF.E_STATE", + "EventCode": "0x22", + "EventName": "L2_DBUS_BUSY.SELF", "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" + "UMask": "0x40" }, { - "EventCode": "0x28", + "BriefDescription": "Cycles the L2 transfers data to the core.", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_IFETCH.SELF.I_STATE", + "EventCode": "0x23", + "EventName": "L2_DBUS_BUSY_RD.SELF", "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" + "UMask": "0x40" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cacheable instruction fetch requests", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_IFETCH.SELF.M_STATE", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" + "UMask": "0x44" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cacheable instruction fetch requests", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_IFETCH.SELF.S_STATE", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" + "UMask": "0x41" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cacheable instruction fetch requests", "Counter": "0,1", - "UMask": "0x4f", + "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" + "UMask": "0x4f" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cacheable instruction fetch requests", "Counter": "0,1", - "UMask": "0x74", - "EventName": "L2_LD.SELF.ANY.E_STATE", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x48" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cacheable instruction fetch requests", "Counter": "0,1", - "UMask": "0x71", - "EventName": "L2_LD.SELF.ANY.I_STATE", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x42" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x78", - "EventName": "L2_LD.SELF.ANY.M_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x74" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x72", - "EventName": "L2_LD.SELF.ANY.S_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x71" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x7f", + "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x7f" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_LD.SELF.DEMAND.E_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x78" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_LD.SELF.DEMAND.I_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x72" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_LD.SELF.DEMAND.M_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x44" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_LD.SELF.DEMAND.S_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x41" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x4f", + "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x4f" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x54", - "EventName": "L2_LD.SELF.PREFETCH.E_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x48" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x51", - "EventName": "L2_LD.SELF.PREFETCH.I_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x42" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x58", - "EventName": "L2_LD.SELF.PREFETCH.M_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x54" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x52", - "EventName": "L2_LD.SELF.PREFETCH.S_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x51" }, { - "EventCode": "0x29", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x5f", + "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" + "UMask": "0x5f" }, { - "EventCode": "0x2A", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_ST.SELF.E_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" + "UMask": "0x58" }, { - "EventCode": "0x2A", + "BriefDescription": "L2 cache reads", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_ST.SELF.I_STATE", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" + "UMask": "0x52" }, { - "EventCode": "0x2A", + "BriefDescription": "All read requests from L1 instruction and dat= a caches", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_ST.SELF.M_STATE", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" + "UMask": "0x44" }, { - "EventCode": "0x2A", + "BriefDescription": "All read requests from L1 instruction and dat= a caches", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_ST.SELF.S_STATE", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" + "UMask": "0x41" }, { - "EventCode": "0x2A", + "BriefDescription": "All read requests from L1 instruction and dat= a caches", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_ST.SELF.MESI", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" + "UMask": "0x4f" }, { - "EventCode": "0x2B", + "BriefDescription": "All read requests from L1 instruction and dat= a caches", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_LOCK.SELF.E_STATE", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" + "UMask": "0x48" }, { - "EventCode": "0x2B", + "BriefDescription": "All read requests from L1 instruction and dat= a caches", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_LOCK.SELF.I_STATE", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" + "UMask": "0x42" }, { - "EventCode": "0x2B", + "BriefDescription": "L2 cache misses.", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_LOCK.SELF.M_STATE", + "EventCode": "0x24", + "EventName": "L2_LINES_IN.SELF.ANY", "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" + "UMask": "0x70" }, { - "EventCode": "0x2B", + "BriefDescription": "L2 cache misses.", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_LOCK.SELF.S_STATE", + "EventCode": "0x24", + "EventName": "L2_LINES_IN.SELF.DEMAND", "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" + "UMask": "0x40" }, { - "EventCode": "0x2B", + "BriefDescription": "L2 cache misses.", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_LOCK.SELF.MESI", + "EventCode": "0x24", + "EventName": "L2_LINES_IN.SELF.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" + "UMask": "0x50" }, { - "EventCode": "0x2C", + "BriefDescription": "L2 cache lines evicted.", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_DATA_RQSTS.SELF.E_STATE", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SELF.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" + "UMask": "0x70" }, { - "EventCode": "0x2C", + "BriefDescription": "L2 cache lines evicted.", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_DATA_RQSTS.SELF.I_STATE", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SELF.DEMAND", "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" + "UMask": "0x40" }, { - "EventCode": "0x2C", + "BriefDescription": "L2 cache lines evicted.", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_DATA_RQSTS.SELF.M_STATE", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SELF.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" + "UMask": "0x50" }, { - "EventCode": "0x2C", + "BriefDescription": "L2 locked accesses", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_DATA_RQSTS.SELF.S_STATE", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" + "UMask": "0x44" }, { - "EventCode": "0x2C", + "BriefDescription": "L2 locked accesses", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_DATA_RQSTS.SELF.MESI", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" + "UMask": "0x41" }, { - "EventCode": "0x2D", + "BriefDescription": "L2 locked accesses", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_LD_IFETCH.SELF.E_STATE", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.MESI", "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and dat= a caches" + "UMask": "0x4f" }, { - "EventCode": "0x2D", + "BriefDescription": "L2 locked accesses", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_LD_IFETCH.SELF.I_STATE", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and dat= a caches" + "UMask": "0x48" }, { - "EventCode": "0x2D", + "BriefDescription": "L2 locked accesses", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_LD_IFETCH.SELF.M_STATE", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and dat= a caches" + "UMask": "0x42" }, { - "EventCode": "0x2D", + "BriefDescription": "L2 cache line modifications.", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_LD_IFETCH.SELF.S_STATE", + "EventCode": "0x25", + "EventName": "L2_M_LINES_IN.SELF", "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and dat= a caches" + "UMask": "0x40" }, { - "EventCode": "0x2D", + "BriefDescription": "Modified lines evicted from the L2 cache", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_LD_IFETCH.SELF.MESI", + "EventCode": "0x27", + "EventName": "L2_M_LINES_OUT.SELF.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and dat= a caches" + "UMask": "0x70" }, { - "EventCode": "0x2E", + "BriefDescription": "Modified lines evicted from the L2 cache", "Counter": "0,1", - "UMask": "0x74", - "EventName": "L2_RQSTS.SELF.ANY.E_STATE", + "EventCode": "0x27", + "EventName": "L2_M_LINES_OUT.SELF.DEMAND", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x40" }, { - "EventCode": "0x2E", + "BriefDescription": "Modified lines evicted from the L2 cache", "Counter": "0,1", - "UMask": "0x71", - "EventName": "L2_RQSTS.SELF.ANY.I_STATE", + "EventCode": "0x27", + "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x50" }, { - "EventCode": "0x2E", + "BriefDescription": "Cycles no L2 cache requests are pending", "Counter": "0,1", - "UMask": "0x78", - "EventName": "L2_RQSTS.SELF.ANY.M_STATE", + "EventCode": "0x32", + "EventName": "L2_NO_REQ.SELF", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x40" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x72", - "EventName": "L2_RQSTS.SELF.ANY.S_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x74" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x7f", - "EventName": "L2_RQSTS.SELF.ANY.MESI", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x71" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x7f" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x78" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x72" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x54", - "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x44" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x51", - "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x58", - "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x4f" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x52", - "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x48" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x5f", - "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" + "UMask": "0x42" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache demand requests from this core that = missed the L2" + "UMask": "0x54" }, { - "EventCode": "0x2E", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_RQSTS.SELF.DEMAND.MESI", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 cache demand requests from this core" + "UMask": "0x51" }, { - "EventCode": "0x30", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x74", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x5f" }, { - "EventCode": "0x30", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x71", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x58" }, { - "EventCode": "0x30", + "BriefDescription": "Rejected L2 cache requests", "Counter": "0,1", - "UMask": "0x78", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x52" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x72", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x74" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x7f", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x71" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.MESI", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x7f" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x78" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x72" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x44" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache demand requests from this core that = missed the L2", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x41" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache demand requests from this core", "Counter": "0,1", - "UMask": "0x54", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x4f" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x51", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x48" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x58", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x42" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x52", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x54" }, { - "EventCode": "0x30", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x5f", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" + "UMask": "0x51" }, { - "EventCode": "0x32", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_NO_REQ.SELF", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "Cycles no L2 cache requests are pending" + "UMask": "0x5f" }, { - "EventCode": "0x40", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0xa1", - "EventName": "L1D_CACHE.LD", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Cacheable Data Reads" + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x58" }, { - "EventCode": "0x40", + "BriefDescription": "L2 cache requests", "Counter": "0,1", - "UMask": "0xa2", - "EventName": "L1D_CACHE.ST", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Cacheable Data Writes" + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x52" }, { - "EventCode": "0x40", + "BriefDescription": "L2 store requests", "Counter": "0,1", - "UMask": "0x83", - "EventName": "L1D_CACHE.ALL_REF", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Data reads and writes" + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" }, { - "EventCode": "0x40", + "BriefDescription": "L2 store requests", "Counter": "0,1", - "UMask": "0xa3", - "EventName": "L1D_CACHE.ALL_CACHE_REF", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Data Cacheable reads and writes" + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" }, { - "EventCode": "0x40", + "BriefDescription": "L2 store requests", "Counter": "0,1", - "UMask": "0x8", - "EventName": "L1D_CACHE.REPL", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L1 Data line replacements" + "UMask": "0x4f" }, { - "EventCode": "0x40", + "BriefDescription": "L2 store requests", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L1D_CACHE.REPLM", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Modified cache lines allocated in the L1 data= cache" + "UMask": "0x48" }, { - "EventCode": "0x40", + "BriefDescription": "L2 store requests", "Counter": "0,1", - "UMask": "0x10", - "EventName": "L1D_CACHE.EVICT", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "Modified cache lines evicted from the L1 data= cache" + "UMask": "0x42" }, { - "EventCode": "0xCB", + "BriefDescription": "Retired loads that hit the L2 cache (precise = event).", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (precise = event)." + "UMask": "0x1" }, { - "EventCode": "0xCB", + "BriefDescription": "Retired loads that miss the L2 cache", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_MISS", "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the L2 cache" + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/t= ools/perf/pmu-events/arch/x86/bonnell/floating-point.json index f0e090cdb9f0..f8055ff47f19 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json @@ -1,261 +1,261 @@ [ { - "EventCode": "0x10", + "BriefDescription": "Floating point assists for retired operations= .", "Counter": "0,1", - "UMask": "0x1", - "EventName": "X87_COMP_OPS_EXE.ANY.S", - "SampleAfterValue": "2000000", - "BriefDescription": "Floating point computational micro-ops execut= ed." + "EventCode": "0x11", + "EventName": "FP_ASSIST.AR", + "SampleAfterValue": "10000", + "UMask": "0x81" }, { - "PEBS": "2", - "EventCode": "0x10", + "BriefDescription": "Floating point assists.", "Counter": "0,1", - "UMask": "0x81", - "EventName": "X87_COMP_OPS_EXE.ANY.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "Floating point computational micro-ops retire= d." + "EventCode": "0x11", + "EventName": "FP_ASSIST.S", + "SampleAfterValue": "10000", + "UMask": "0x1" }, { - "EventCode": "0x10", + "BriefDescription": "SIMD assists invoked.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "X87_COMP_OPS_EXE.FXCH.S", - "SampleAfterValue": "2000000", - "BriefDescription": "FXCH uops executed." + "EventCode": "0xCD", + "EventName": "SIMD_ASSIST", + "SampleAfterValue": "100000", + "UMask": "0x0" }, { - "PEBS": "2", - "EventCode": "0x10", + "BriefDescription": "Retired computational Streaming SIMD Extensio= ns (SSE) packed-single instructions.", "Counter": "0,1", - "UMask": "0x82", - "EventName": "X87_COMP_OPS_EXE.FXCH.AR", + "EventCode": "0xCA", + "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "SampleAfterValue": "2000000", - "BriefDescription": "FXCH uops retired." + "UMask": "0x1" }, { - "EventCode": "0x11", + "BriefDescription": "Retired computational Streaming SIMD Extensio= ns 2 (SSE2) scalar-double instructions.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "FP_ASSIST.S", - "SampleAfterValue": "10000", - "BriefDescription": "Floating point assists." + "EventCode": "0xCA", + "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000000", + "UMask": "0x8" }, { - "EventCode": "0x11", + "BriefDescription": "Retired computational Streaming SIMD Extensio= ns (SSE) scalar-single instructions.", "Counter": "0,1", - "UMask": "0x81", - "EventName": "FP_ASSIST.AR", - "SampleAfterValue": "10000", - "BriefDescription": "Floating point assists for retired operations= ." + "EventCode": "0xCA", + "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { - "EventCode": "0xB0", + "BriefDescription": "SIMD Instructions retired.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_UOPS_EXEC.S", + "EventCode": "0xCE", + "EventName": "SIMD_INSTR_RETIRED", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD micro-ops executed (excluding stores)." + "UMask": "0x0" }, { - "PEBS": "2", - "EventCode": "0xB0", + "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packe= d-single instructions.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "SIMD_UOPS_EXEC.AR", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD micro-ops retired (excluding stores)." + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) sc= alar-double instructions.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_SAT_UOP_EXEC.S", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD saturated arithmetic micro-ops executed." + "UMask": "0x8" }, { - "EventCode": "0xB1", + "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scala= r-single instructions.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "SIMD_SAT_UOP_EXEC.AR", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD saturated arithmetic micro-ops retired." + "UMask": "0x2" }, { - "EventCode": "0xB3", + "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) ve= ctor instructions.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.VECTOR", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed multiply micro-ops executed" + "UMask": "0x10" }, { - "EventCode": "0xB3", + "BriefDescription": "Saturated arithmetic instructions retired.", "Counter": "0,1", - "UMask": "0x81", - "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", + "EventCode": "0xCF", + "EventName": "SIMD_SAT_INSTR_RETIRED", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed multiply micro-ops retired" + "UMask": "0x0" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD saturated arithmetic micro-ops retired.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", + "EventCode": "0xB1", + "EventName": "SIMD_SAT_UOP_EXEC.AR", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed shift micro-ops executed" + "UMask": "0x80" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD saturated arithmetic micro-ops executed.= ", "Counter": "0,1", - "UMask": "0x82", - "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", + "EventCode": "0xB1", + "EventName": "SIMD_SAT_UOP_EXEC.S", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed shift micro-ops retired" + "UMask": "0x0" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD micro-ops retired (excluding stores).", "Counter": "0,1", - "UMask": "0x4", - "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", + "EventCode": "0xB0", + "EventName": "SIMD_UOPS_EXEC.AR", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed micro-ops executed" + "UMask": "0x80" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD micro-ops executed (excluding stores).", "Counter": "0,1", - "UMask": "0x84", - "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", + "EventCode": "0xB0", + "EventName": "SIMD_UOPS_EXEC.S", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed micro-ops retired" + "UMask": "0x0" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD packed arithmetic micro-ops retired", "Counter": "0,1", - "UMask": "0x8", - "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD unpacked micro-ops executed" + "UMask": "0xa0" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD packed arithmetic micro-ops executed", "Counter": "0,1", - "UMask": "0x88", - "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD unpacked micro-ops retired" + "UMask": "0x20" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD packed logical micro-ops retired", "Counter": "0,1", - "UMask": "0x10", - "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed logical micro-ops executed" + "UMask": "0x90" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD packed logical micro-ops executed", "Counter": "0,1", - "UMask": "0x90", - "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed logical micro-ops retired" + "UMask": "0x10" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD packed multiply micro-ops retired", "Counter": "0,1", - "UMask": "0x20", - "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed arithmetic micro-ops executed" + "UMask": "0x81" }, { - "EventCode": "0xB3", + "BriefDescription": "SIMD packed multiply micro-ops executed", "Counter": "0,1", - "UMask": "0xa0", - "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed arithmetic micro-ops retired" + "UMask": "0x1" }, { - "EventCode": "0xC7", + "BriefDescription": "SIMD packed micro-ops retired", "Counter": "0,1", - "UMask": "0x1", - "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packe= d-single instructions." + "UMask": "0x84" }, { - "EventCode": "0xC7", + "BriefDescription": "SIMD packed micro-ops executed", "Counter": "0,1", - "UMask": "0x2", - "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scala= r-single instructions." + "UMask": "0x4" }, { - "EventCode": "0xC7", + "BriefDescription": "SIMD packed shift micro-ops retired", "Counter": "0,1", - "UMask": "0x8", - "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) sc= alar-double instructions." + "UMask": "0x82" }, { - "EventCode": "0xC7", + "BriefDescription": "SIMD packed shift micro-ops executed", "Counter": "0,1", - "UMask": "0x10", - "EventName": "SIMD_INST_RETIRED.VECTOR", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) ve= ctor instructions." + "UMask": "0x2" }, { - "EventCode": "0xCA", + "BriefDescription": "SIMD unpacked micro-ops retired", "Counter": "0,1", - "UMask": "0x1", - "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", "SampleAfterValue": "2000000", - "BriefDescription": "Retired computational Streaming SIMD Extensio= ns (SSE) packed-single instructions." + "UMask": "0x88" }, { - "EventCode": "0xCA", + "BriefDescription": "SIMD unpacked micro-ops executed", "Counter": "0,1", - "UMask": "0x2", - "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", "SampleAfterValue": "2000000", - "BriefDescription": "Retired computational Streaming SIMD Extensio= ns (SSE) scalar-single instructions." + "UMask": "0x8" }, { - "EventCode": "0xCA", + "BriefDescription": "Floating point computational micro-ops retire= d.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.ANY.AR", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Retired computational Streaming SIMD Extensio= ns 2 (SSE2) scalar-double instructions." + "UMask": "0x81" }, { - "EventCode": "0xCD", + "BriefDescription": "Floating point computational micro-ops execut= ed.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_ASSIST", - "SampleAfterValue": "100000", - "BriefDescription": "SIMD assists invoked." + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.ANY.S", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xCE", + "BriefDescription": "FXCH uops retired.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_INSTR_RETIRED", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.FXCH.AR", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD Instructions retired." + "UMask": "0x82" }, { - "EventCode": "0xCF", + "BriefDescription": "FXCH uops executed.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_SAT_INSTR_RETIRED", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.FXCH.S", "SampleAfterValue": "2000000", - "BriefDescription": "Saturated arithmetic instructions retired." + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/p= erf/pmu-events/arch/x86/bonnell/frontend.json index ef69540ab61d..e852eb2cc878 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -1,83 +1,91 @@ [ { - "EventCode": "0x80", + "BriefDescription": "BACLEARS asserted.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", - "SampleAfterValue": "200000", - "BriefDescription": "Instruction fetches." + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Cycles during which instruction fetches are = stalled.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Icache hit" + "EventCode": "0x86", + "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Decode stall due to IQ full", "Counter": "0,1", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200000", - "BriefDescription": "Icache miss" + "EventCode": "0x87", + "EventName": "DECODE_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { - "EventCode": "0x86", + "BriefDescription": "Decode stall due to PFB empty", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", + "EventCode": "0x87", + "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which instruction fetches are = stalled." + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction fetches.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "DECODE_STALL.PFB_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Decode stall due to PFB empty" + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200000", + "UMask": "0x3" }, { - "EventCode": "0x87", + "BriefDescription": "Icache hit", "Counter": "0,1", - "UMask": "0x2", - "EventName": "DECODE_STALL.IQ_FULL", - "SampleAfterValue": "2000000", - "BriefDescription": "Decode stall due to IQ full" + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0xAA", + "BriefDescription": "Icache miss", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACRO_INSTS.NON_CISC_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Non-CISC nacro instructions decoded" + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200000", + "UMask": "0x2" }, { + "BriefDescription": "All Instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", + "EventName": "MACRO_INSTS.ALL_DECODED", + "SampleAfterValue": "2000000", + "UMask": "0x3" + }, + { + "BriefDescription": "CISC macro instructions decoded", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xAA", "EventName": "MACRO_INSTS.CISC_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "CISC macro instructions decoded" + "UMask": "0x2" }, { - "EventCode": "0xAA", + "BriefDescription": "Non-CISC nacro instructions decoded", "Counter": "0,1", - "UMask": "0x3", - "EventName": "MACRO_INSTS.ALL_DECODED", + "EventCode": "0xAA", + "EventName": "MACRO_INSTS.NON_CISC_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "All Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA9", + "BriefDescription": "This event counts the cycles where 1 or more = uops are issued by the micro-sequencer (MS), including microcode assists an= d inserted flows, and written to the IQ.", "Counter": "0,1", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA9", "EventName": "UOPS.MS_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "This event counts the cycles where 1 or more = uops are issued by the micro-sequencer (MS), including microcode assists an= d inserted flows, and written to the IQ.", - "CounterMask": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/per= f/pmu-events/arch/x86/bonnell/memory.json index 3ae843b20c8a..2aa4c41f528e 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json @@ -1,154 +1,154 @@ [ { - "EventCode": "0x5", + "BriefDescription": "Nonzero segbase 1 bubble", "Counter": "0,1", - "UMask": "0xf", - "EventName": "MISALIGN_MEM_REF.SPLIT", - "SampleAfterValue": "200000", - "BriefDescription": "Memory references that cross an 8-byte bounda= ry." - }, - { "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x9", - "EventName": "MISALIGN_MEM_REF.LD_SPLIT", + "EventName": "MISALIGN_MEM_REF.BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Load splits" + "UMask": "0x97" }, { - "EventCode": "0x5", + "BriefDescription": "Nonzero segbase load 1 bubble", "Counter": "0,1", - "UMask": "0xa", - "EventName": "MISALIGN_MEM_REF.ST_SPLIT", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.LD_BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Store splits" + "UMask": "0x91" }, { - "EventCode": "0x5", + "BriefDescription": "Load splits", "Counter": "0,1", - "UMask": "0x8f", - "EventName": "MISALIGN_MEM_REF.SPLIT.AR", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.LD_SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Memory references that cross an 8-byte bounda= ry (At Retirement)" + "UMask": "0x9" }, { - "EventCode": "0x5", + "BriefDescription": "Load splits (At Retirement)", "Counter": "0,1", - "UMask": "0x89", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", "SampleAfterValue": "200000", - "BriefDescription": "Load splits (At Retirement)" + "UMask": "0x89" }, { - "EventCode": "0x5", + "BriefDescription": "Nonzero segbase ld-op-st 1 bubble", "Counter": "0,1", - "UMask": "0x8a", - "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Store splits (Ar Retirement)" + "UMask": "0x94" }, { - "EventCode": "0x5", + "BriefDescription": "ld-op-st splits", "Counter": "0,1", - "UMask": "0x8c", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.RMW_SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "ld-op-st splits" + "UMask": "0x8c" }, { - "EventCode": "0x5", + "BriefDescription": "Memory references that cross an 8-byte bounda= ry.", "Counter": "0,1", - "UMask": "0x97", - "EventName": "MISALIGN_MEM_REF.BUBBLE", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase 1 bubble" + "UMask": "0xf" }, { - "EventCode": "0x5", + "BriefDescription": "Memory references that cross an 8-byte bounda= ry (At Retirement)", "Counter": "0,1", - "UMask": "0x91", - "EventName": "MISALIGN_MEM_REF.LD_BUBBLE", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.SPLIT.AR", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase load 1 bubble" + "UMask": "0x8f" }, { - "EventCode": "0x5", + "BriefDescription": "Nonzero segbase store 1 bubble", "Counter": "0,1", - "UMask": "0x92", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase store 1 bubble" + "UMask": "0x92" }, { - "EventCode": "0x5", + "BriefDescription": "Store splits", "Counter": "0,1", - "UMask": "0x94", - "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.ST_SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase ld-op-st 1 bubble" + "UMask": "0xa" }, { - "EventCode": "0x7", + "BriefDescription": "Store splits (Ar Retirement)", "Counter": "0,1", - "UMask": "0x81", - "EventName": "PREFETCH.PREFETCHT0", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 in= structions executed." + "UMask": "0x8a" }, { - "EventCode": "0x7", + "BriefDescription": "L1 hardware prefetch request", "Counter": "0,1", - "UMask": "0x82", - "EventName": "PREFETCH.PREFETCHT1", - "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 in= structions executed." + "EventCode": "0x7", + "EventName": "PREFETCH.HW_PREFETCH", + "SampleAfterValue": "2000000", + "UMask": "0x10" }, { - "EventCode": "0x7", + "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA = instructions executed", "Counter": "0,1", - "UMask": "0x84", - "EventName": "PREFETCH.PREFETCHT2", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHNTA", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 in= structions executed." + "UMask": "0x88" }, { - "EventCode": "0x7", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 in= structions executed.", "Counter": "0,1", - "UMask": "0x86", - "EventName": "PREFETCH.SW_L2", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHT0", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 an= d PrefetchT2 instructions executed" + "UMask": "0x81" }, { - "EventCode": "0x7", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 in= structions executed.", "Counter": "0,1", - "UMask": "0x88", - "EventName": "PREFETCH.PREFETCHNTA", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHT1", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA = instructions executed" + "UMask": "0x82" }, { - "EventCode": "0x7", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 in= structions executed.", "Counter": "0,1", - "UMask": "0x10", - "EventName": "PREFETCH.HW_PREFETCH", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 hardware prefetch request" + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHT2", + "SampleAfterValue": "200000", + "UMask": "0x84" }, { - "EventCode": "0x7", + "BriefDescription": "Any Software prefetch", "Counter": "0,1", - "UMask": "0xf", + "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "Any Software prefetch" + "UMask": "0xf" }, { - "EventCode": "0x7", + "BriefDescription": "Any Software prefetch", "Counter": "0,1", - "UMask": "0x8f", + "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", "SampleAfterValue": "200000", - "BriefDescription": "Any Software prefetch" + "UMask": "0x8f" + }, + { + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 an= d PrefetchT2 instructions executed", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "PREFETCH.SW_L2", + "SampleAfterValue": "200000", + "UMask": "0x86" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf= /pmu-events/arch/x86/bonnell/other.json index 4bc1c582d1cd..114c062e7e96 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/other.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json @@ -1,450 +1,450 @@ [ { - "EventCode": "0x6", + "BriefDescription": "Bus queue is empty.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "SEGMENT_REG_LOADS.ANY", + "EventCode": "0x7D", + "EventName": "BUSQ_EMPTY.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Number of segment register loads." + "UMask": "0x40" }, { - "EventCode": "0x9", + "BriefDescription": "Number of Bus Not Ready signals asserted.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "DISPATCH_BLOCKED.ANY", + "EventCode": "0x61", + "EventName": "BUS_BNR_DRV.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Memory cluster signals to block micro-op disp= atch for any reason" + "UMask": "0x20" }, { - "EventCode": "0x3A", + "BriefDescription": "Number of Bus Not Ready signals asserted.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "EIST_TRANS", + "EventCode": "0x61", + "EventName": "BUS_BNR_DRV.THIS_AGENT", "SampleAfterValue": "200000", - "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technol= ogy (EIST) transitions" + "UMask": "0x0" }, { - "EventCode": "0x3B", + "BriefDescription": "Bus cycles while processor receives data.", "Counter": "0,1", - "UMask": "0xc0", - "EventName": "THERMAL_TRIP", + "EventCode": "0x64", + "EventName": "BUS_DATA_RCV.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Number of thermal trips" + "UMask": "0x40" }, { - "EventCode": "0x60", + "BriefDescription": "Bus cycles when data is sent on the bus.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS", + "EventCode": "0x62", + "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Outstanding cacheable data read bus requests = duration." + "UMask": "0x20" }, { - "EventCode": "0x60", + "BriefDescription": "Bus cycles when data is sent on the bus.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_REQUEST_OUTSTANDING.SELF", + "EventCode": "0x62", + "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT", "SampleAfterValue": "200000", - "BriefDescription": "Outstanding cacheable data read bus requests = duration." + "UMask": "0x0" }, { - "EventCode": "0x61", + "BriefDescription": "HITM signal asserted.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_BNR_DRV.ALL_AGENTS", + "EventCode": "0x7B", + "EventName": "BUS_HITM_DRV.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Number of Bus Not Ready signals asserted." + "UMask": "0x20" }, { - "EventCode": "0x61", + "BriefDescription": "HITM signal asserted.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_BNR_DRV.THIS_AGENT", + "EventCode": "0x7B", + "EventName": "BUS_HITM_DRV.THIS_AGENT", "SampleAfterValue": "200000", - "BriefDescription": "Number of Bus Not Ready signals asserted." + "UMask": "0x0" }, { - "EventCode": "0x62", + "BriefDescription": "HIT signal asserted.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS", + "EventCode": "0x7A", + "EventName": "BUS_HIT_DRV.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when data is sent on the bus." + "UMask": "0x20" }, { - "EventCode": "0x62", + "BriefDescription": "HIT signal asserted.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT", + "EventCode": "0x7A", + "EventName": "BUS_HIT_DRV.THIS_AGENT", "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when data is sent on the bus." + "UMask": "0x0" }, { - "EventCode": "0x63", + "BriefDescription": "IO requests waiting in the bus queue.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS", + "EventCode": "0x7F", + "EventName": "BUS_IO_WAIT.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when a LOCK signal is asserted." + "UMask": "0x40" }, { - "EventCode": "0x63", + "BriefDescription": "Bus cycles when a LOCK signal is asserted.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_LOCK_CLOCKS.SELF", + "EventCode": "0x63", + "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when a LOCK signal is asserted." + "UMask": "0xe0" }, { - "EventCode": "0x64", + "BriefDescription": "Bus cycles when a LOCK signal is asserted.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_DATA_RCV.SELF", + "EventCode": "0x63", + "EventName": "BUS_LOCK_CLOCKS.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles while processor receives data." + "UMask": "0x40" }, { - "EventCode": "0x65", + "BriefDescription": "Outstanding cacheable data read bus requests = duration.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_BRD.ALL_AGENTS", + "EventCode": "0x60", + "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Burst read bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x65", + "BriefDescription": "Outstanding cacheable data read bus requests = duration.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_BRD.SELF", + "EventCode": "0x60", + "EventName": "BUS_REQUEST_OUTSTANDING.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Burst read bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x66", + "BriefDescription": "All bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_RFO.ALL_AGENTS", + "EventCode": "0x70", + "EventName": "BUS_TRANS_ANY.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "RFO bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x66", + "BriefDescription": "All bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_RFO.SELF", + "EventCode": "0x70", + "EventName": "BUS_TRANS_ANY.SELF", "SampleAfterValue": "200000", - "BriefDescription": "RFO bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x67", + "BriefDescription": "Burst read bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_WB.ALL_AGENTS", + "EventCode": "0x65", + "EventName": "BUS_TRANS_BRD.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Explicit writeback bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x67", + "BriefDescription": "Burst read bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_WB.SELF", + "EventCode": "0x65", + "EventName": "BUS_TRANS_BRD.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Explicit writeback bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x68", + "BriefDescription": "Burst (full cache-line) bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS", + "EventCode": "0x6E", + "EventName": "BUS_TRANS_BURST.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Instruction-fetch bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x68", + "BriefDescription": "Burst (full cache-line) bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_IFETCH.SELF", + "EventCode": "0x6E", + "EventName": "BUS_TRANS_BURST.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Instruction-fetch bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x69", + "BriefDescription": "Deferred bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_INVAL.ALL_AGENTS", + "EventCode": "0x6D", + "EventName": "BUS_TRANS_DEF.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Invalidate bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x69", + "BriefDescription": "Deferred bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_INVAL.SELF", + "EventCode": "0x6D", + "EventName": "BUS_TRANS_DEF.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Invalidate bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x6A", + "BriefDescription": "Instruction-fetch bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_PWR.ALL_AGENTS", + "EventCode": "0x68", + "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Partial write bus transaction." + "UMask": "0xe0" }, { - "EventCode": "0x6A", + "BriefDescription": "Instruction-fetch bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_PWR.SELF", + "EventCode": "0x68", + "EventName": "BUS_TRANS_IFETCH.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Partial write bus transaction." + "UMask": "0x40" }, { - "EventCode": "0x6B", + "BriefDescription": "Invalidate bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_P.ALL_AGENTS", + "EventCode": "0x69", + "EventName": "BUS_TRANS_INVAL.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Partial bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x6B", + "BriefDescription": "Invalidate bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_P.SELF", + "EventCode": "0x69", + "EventName": "BUS_TRANS_INVAL.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Partial bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x6C", + "BriefDescription": "IO bus transactions.", "Counter": "0,1", - "UMask": "0xe0", + "EventCode": "0x6C", "EventName": "BUS_TRANS_IO.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "IO bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x6C", + "BriefDescription": "IO bus transactions.", "Counter": "0,1", - "UMask": "0x40", + "EventCode": "0x6C", "EventName": "BUS_TRANS_IO.SELF", "SampleAfterValue": "200000", - "BriefDescription": "IO bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x6D", + "BriefDescription": "Memory bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_DEF.ALL_AGENTS", + "EventCode": "0x6F", + "EventName": "BUS_TRANS_MEM.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Deferred bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x6D", + "BriefDescription": "Memory bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_DEF.SELF", + "EventCode": "0x6F", + "EventName": "BUS_TRANS_MEM.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Deferred bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x6E", + "BriefDescription": "Partial bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_BURST.ALL_AGENTS", + "EventCode": "0x6B", + "EventName": "BUS_TRANS_P.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Burst (full cache-line) bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x6E", + "BriefDescription": "Partial bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_BURST.SELF", + "EventCode": "0x6B", + "EventName": "BUS_TRANS_P.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Burst (full cache-line) bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x6F", + "BriefDescription": "Partial write bus transaction.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_MEM.ALL_AGENTS", + "EventCode": "0x6A", + "EventName": "BUS_TRANS_PWR.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Memory bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x6F", + "BriefDescription": "Partial write bus transaction.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_MEM.SELF", + "EventCode": "0x6A", + "EventName": "BUS_TRANS_PWR.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Memory bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x70", + "BriefDescription": "RFO bus transactions.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_ANY.ALL_AGENTS", + "EventCode": "0x66", + "EventName": "BUS_TRANS_RFO.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "All bus transactions." + "UMask": "0xe0" }, { - "EventCode": "0x70", + "BriefDescription": "RFO bus transactions.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_ANY.SELF", + "EventCode": "0x66", + "EventName": "BUS_TRANS_RFO.SELF", "SampleAfterValue": "200000", - "BriefDescription": "All bus transactions." + "UMask": "0x40" }, { - "EventCode": "0x77", + "BriefDescription": "Explicit writeback bus transactions.", "Counter": "0,1", - "UMask": "0xb", - "EventName": "EXT_SNOOP.THIS_AGENT.ANY", + "EventCode": "0x67", + "EventName": "BUS_TRANS_WB.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "UMask": "0xe0" }, { - "EventCode": "0x77", + "BriefDescription": "Explicit writeback bus transactions.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN", + "EventCode": "0x67", + "EventName": "BUS_TRANS_WB.SELF", "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "UMask": "0x40" }, { - "EventCode": "0x77", + "BriefDescription": "Cycles during which interrupts are disabled.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "EXT_SNOOP.THIS_AGENT.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "EventCode": "0xC6", + "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x77", + "BriefDescription": "Cycles during which interrupts are pending an= d disabled.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "EXT_SNOOP.THIS_AGENT.HITM", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "EventCode": "0xC6", + "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { - "EventCode": "0x77", + "BriefDescription": "Memory cluster signals to block micro-op disp= atch for any reason", "Counter": "0,1", - "UMask": "0x2b", - "EventName": "EXT_SNOOP.ALL_AGENTS.ANY", + "EventCode": "0x9", + "EventName": "DISPATCH_BLOCKED.ANY", "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "UMask": "0x20" }, { - "EventCode": "0x77", + "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technol= ogy (EIST) transitions", "Counter": "0,1", - "UMask": "0x21", - "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN", + "EventCode": "0x3A", + "EventName": "EIST_TRANS", "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "UMask": "0x0" }, { - "EventCode": "0x77", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x22", - "EventName": "EXT_SNOOP.ALL_AGENTS.HIT", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "UMask": "0x2b" }, { - "EventCode": "0x77", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x28", - "EventName": "EXT_SNOOP.ALL_AGENTS.HITM", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN", "SampleAfterValue": "200000", - "BriefDescription": "External snoops." + "UMask": "0x21" }, { - "EventCode": "0x7A", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_HIT_DRV.ALL_AGENTS", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.HIT", "SampleAfterValue": "200000", - "BriefDescription": "HIT signal asserted." + "UMask": "0x22" }, { - "EventCode": "0x7A", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_HIT_DRV.THIS_AGENT", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.HITM", "SampleAfterValue": "200000", - "BriefDescription": "HIT signal asserted." + "UMask": "0x28" }, { - "EventCode": "0x7B", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_HITM_DRV.ALL_AGENTS", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.ANY", "SampleAfterValue": "200000", - "BriefDescription": "HITM signal asserted." + "UMask": "0xb" }, { - "EventCode": "0x7B", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_HITM_DRV.THIS_AGENT", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN", "SampleAfterValue": "200000", - "BriefDescription": "HITM signal asserted." + "UMask": "0x1" }, { - "EventCode": "0x7D", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUSQ_EMPTY.SELF", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Bus queue is empty." + "UMask": "0x2" }, { - "EventCode": "0x7E", + "BriefDescription": "External snoops.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "SNOOP_STALL_DRV.ALL_AGENTS", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.HITM", "SampleAfterValue": "200000", - "BriefDescription": "Bus stalled for snoops." + "UMask": "0x8" }, { - "EventCode": "0x7E", + "BriefDescription": "Hardware interrupts received.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "SNOOP_STALL_DRV.SELF", + "EventCode": "0xC8", + "EventName": "HW_INT_RCV", "SampleAfterValue": "200000", - "BriefDescription": "Bus stalled for snoops." + "UMask": "0x0" }, { - "EventCode": "0x7F", + "BriefDescription": "Number of segment register loads.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_IO_WAIT.SELF", + "EventCode": "0x6", + "EventName": "SEGMENT_REG_LOADS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "IO requests waiting in the bus queue." + "UMask": "0x80" }, { - "EventCode": "0xC6", + "BriefDescription": "Bus stalled for snoops.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which interrupts are disabled." + "EventCode": "0x7E", + "EventName": "SNOOP_STALL_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" }, { - "EventCode": "0xC6", + "BriefDescription": "Bus stalled for snoops.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which interrupts are pending an= d disabled." + "EventCode": "0x7E", + "EventName": "SNOOP_STALL_DRV.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" }, { - "EventCode": "0xC8", + "BriefDescription": "Number of thermal trips", "Counter": "0,1", - "UMask": "0x0", - "EventName": "HW_INT_RCV", + "EventCode": "0x3B", + "EventName": "THERMAL_TRIP", "SampleAfterValue": "200000", - "BriefDescription": "Hardware interrupts received." + "UMask": "0xc0" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/bonnell/pipeline.json index 09c6de13de20..896b738e59b6 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json @@ -1,364 +1,356 @@ [ { - "EventCode": "0x2", - "Counter": "0,1", - "UMask": "0x83", - "EventName": "STORE_FORWARDS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "All store forwards" - }, - { - "EventCode": "0x2", + "BriefDescription": "Bogus branches", "Counter": "0,1", - "UMask": "0x81", - "EventName": "STORE_FORWARDS.GOOD", - "SampleAfterValue": "200000", - "BriefDescription": "Good store forwards" - }, - { - "EventCode": "0x3", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "REISSUE.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues for any cause" + "EventCode": "0xE4", + "EventName": "BOGUS_BR", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1", - "UMask": "0xff", - "EventName": "REISSUE.ANY.AR", - "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues for any cause (At Retiremen= t)" + "EventCode": "0xE0", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "Retired branch instructions.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MUL.S", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed." + "UMask": "0x0" }, { - "EventCode": "0x12", + "BriefDescription": "Retired branch instructions.", "Counter": "0,1", - "UMask": "0x81", - "EventName": "MUL.AR", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ANY1", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations retired" + "UMask": "0xf" }, { - "EventCode": "0x13", + "BriefDescription": "Retired mispredicted branch instructions (pre= cise event).", "Counter": "0,1", - "UMask": "0x1", - "EventName": "DIV.S", - "SampleAfterValue": "2000000", - "BriefDescription": "Divide operations executed." + "EventCode": "0xC5", + "EventName": "BR_INST_RETIRED.MISPRED", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x0" }, { - "EventCode": "0x13", + "BriefDescription": "Retired branch instructions that were mispred= icted not-taken.", "Counter": "0,1", - "UMask": "0x81", - "EventName": "DIV.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "Divide operations retired" + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", + "SampleAfterValue": "200000", + "UMask": "0x2" }, { - "EventCode": "0x14", + "BriefDescription": "Retired branch instructions that were mispred= icted taken.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_DIV_BUSY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy." + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", + "SampleAfterValue": "200000", + "UMask": "0x8" }, { - "EventCode": "0x3C", + "BriefDescription": "Retired branch instructions that were predict= ed not-taken.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE_P", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", "SampleAfterValue": "2000000", - "BriefDescription": "Core cycles when core is not halted" + "UMask": "0x1" }, { - "EventCode": "0x3C", + "BriefDescription": "Retired branch instructions that were predict= ed taken.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.BUS", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when core is not halted" - }, - { - "EventCode": "0xA", - "Counter": "Fixed counter 2", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.PRED_TAKEN", "SampleAfterValue": "2000000", - "BriefDescription": "Core cycles when core is not halted" + "UMask": "0x4" }, { - "EventCode": "0xA", - "Counter": "Fixed counter 3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.REF", + "BriefDescription": "Retired taken branch instructions.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when core is not halted." + "UMask": "0xc" }, { - "EventCode": "0x88", + "BriefDescription": "All macro conditional branch instructions.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.COND", "SampleAfterValue": "2000000", - "BriefDescription": "All macro conditional branch instructions." + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Only taken macro conditional branch instructi= ons", "Counter": "0,1", - "UMask": "0x2", - "EventName": "BR_INST_TYPE_RETIRED.UNCOND", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", "SampleAfterValue": "2000000", - "BriefDescription": "All macro unconditional branch instructions, = excluding calls and indirects" + "UMask": "0x41" }, { - "EventCode": "0x88", + "BriefDescription": "All non-indirect calls", "Counter": "0,1", - "UMask": "0x4", - "EventName": "BR_INST_TYPE_RETIRED.IND", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", "SampleAfterValue": "2000000", - "BriefDescription": "All indirect branches that are not calls." + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "All indirect branches that are not calls.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "BR_INST_TYPE_RETIRED.RET", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.IND", "SampleAfterValue": "2000000", - "BriefDescription": "All indirect branches that have a return mnem= onic" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "All indirect calls, including both register a= nd memory indirect.", "Counter": "0,1", - "UMask": "0x10", - "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", "SampleAfterValue": "2000000", - "BriefDescription": "All non-indirect calls" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "All indirect branches that have a return mnem= onic", "Counter": "0,1", - "UMask": "0x20", - "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.RET", "SampleAfterValue": "2000000", - "BriefDescription": "All indirect calls, including both register a= nd memory indirect." + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "All macro unconditional branch instructions, = excluding calls and indirects", "Counter": "0,1", - "UMask": "0x41", - "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.UNCOND", "SampleAfterValue": "2000000", - "BriefDescription": "Only taken macro conditional branch instructi= ons" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted cond branch instructions retired= ", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.COND", "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted cond branch instructions retired" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted and taken cond branch instructio= ns retired", "Counter": "0,1", - "UMask": "0x2", - "EventName": "BR_MISSP_TYPE_RETIRED.IND", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted ind branches that are not calls" + "UMask": "0x11" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted ind branches that are not calls", "Counter": "0,1", - "UMask": "0x4", - "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.IND", "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted return branches" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect calls, including both r= egister and memory indirect.", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL", "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted indirect calls, including both r= egister and memory indirect." + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches", "Counter": "0,1", - "UMask": "0x11", - "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted and taken cond branch instructio= ns retired" + "UMask": "0x4" }, { - "PEBS": "2", - "EventCode": "0xC0", + "BriefDescription": "Bus cycles when core is not halted", "Counter": "0,1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (precise event)." + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.BUS", + "SampleAfterValue": "200000", + "UMask": "0x1" }, { + "BriefDescription": "Core cycles when core is not halted", + "Counter": "Fixed counter 2", "EventCode": "0xA", - "Counter": "Fixed counter 1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY", + "EventName": "CPU_CLK_UNHALTED.CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired." + "UMask": "0x0" }, { - "EventCode": "0xC2", + "BriefDescription": "Core cycles when core is not halted", "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.ANY", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000000", - "BriefDescription": "Micro-ops retired." + "UMask": "0x0" }, { - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.STALLED_CYCLES", + "BriefDescription": "Reference cycles when core is not halted.", + "Counter": "Fixed counter 3", + "EventCode": "0xA", + "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no micro-ops retired." + "UMask": "0x0" }, { - "EventCode": "0xC2", + "BriefDescription": "Cycles the divider is busy.", "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.STALLS", + "EventCode": "0x14", + "EventName": "CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Periods no micro-ops retired." + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Divide operations retired", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "200000", - "BriefDescription": "Self-Modifying Code detected." + "EventCode": "0x13", + "EventName": "DIV.AR", + "SampleAfterValue": "2000000", + "UMask": "0x81" }, { - "EventCode": "0xC4", + "BriefDescription": "Divide operations executed.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ANY", + "EventCode": "0x13", + "EventName": "DIV.S", "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions." + "UMask": "0x1" }, { - "EventCode": "0xC4", + "BriefDescription": "Instructions retired.", + "Counter": "Fixed counter 1", + "EventCode": "0xA", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Instructions retired (precise event).", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions that were predict= ed not-taken." + "UMask": "0x0" }, { - "EventCode": "0xC4", + "BriefDescription": "Self-Modifying Code detected.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions that were mispred= icted not-taken." + "UMask": "0x1" }, { - "EventCode": "0xC4", + "BriefDescription": "Multiply operations retired", "Counter": "0,1", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.PRED_TAKEN", + "EventCode": "0x12", + "EventName": "MUL.AR", "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions that were predict= ed taken." + "UMask": "0x81" }, { - "EventCode": "0xC4", + "BriefDescription": "Multiply operations executed.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", + "EventCode": "0x12", + "EventName": "MUL.S", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Micro-op reissues for any cause", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "REISSUE.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions that were mispred= icted taken." + "UMask": "0x7f" }, { - "EventCode": "0xC4", + "BriefDescription": "Micro-op reissues for any cause (At Retiremen= t)", "Counter": "0,1", - "UMask": "0xc", - "EventName": "BR_INST_RETIRED.TAKEN", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired taken branch instructions." + "EventCode": "0x3", + "EventName": "REISSUE.ANY.AR", + "SampleAfterValue": "200000", + "UMask": "0xff" }, { - "EventCode": "0xC4", + "BriefDescription": "Micro-op reissues on a store-load collision", "Counter": "0,1", - "UMask": "0xf", - "EventName": "BR_INST_RETIRED.ANY1", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions." + "EventCode": "0x3", + "EventName": "REISSUE.OVERLAP_STORE", + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Micro-op reissues on a store-load collision (= At Retirement)", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.MISPRED", + "EventCode": "0x3", + "EventName": "REISSUE.OVERLAP_STORE.AR", "SampleAfterValue": "200000", - "BriefDescription": "Retired mispredicted branch instructions (pre= cise event)." + "UMask": "0x81" }, { - "EventCode": "0xDC", + "BriefDescription": "Cycles issue is stalled due to div busy.", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xDC", "EventName": "RESOURCE_STALLS.DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles issue is stalled due to div busy." + "UMask": "0x2" }, { - "EventCode": "0xE0", + "BriefDescription": "All store forwards", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BR_INST_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "EventCode": "0x2", + "EventName": "STORE_FORWARDS.ANY", + "SampleAfterValue": "200000", + "UMask": "0x83" }, { - "EventCode": "0xE4", + "BriefDescription": "Good store forwards", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BOGUS_BR", - "SampleAfterValue": "2000000", - "BriefDescription": "Bogus branches" + "EventCode": "0x2", + "EventName": "STORE_FORWARDS.GOOD", + "SampleAfterValue": "200000", + "UMask": "0x81" }, { - "EventCode": "0xE6", + "BriefDescription": "Micro-ops retired.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BACLEARS.ANY", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEARS asserted." + "UMask": "0x10" }, { - "EventCode": "0x3", + "BriefDescription": "Cycles no micro-ops retired.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "REISSUE.OVERLAP_STORE", - "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues on a store-load collision" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALLED_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x10" }, { - "EventCode": "0x3", + "BriefDescription": "Periods no micro-ops retired.", "Counter": "0,1", - "UMask": "0x81", - "EventName": "REISSUE.OVERLAP_STORE.AR", - "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues on a store-load collision (= At Retirement)" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALLS", + "SampleAfterValue": "2000000", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json index 7bb817588721..c2363b8e61b4 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -1,124 +1,124 @@ [ { - "EventCode": "0x8", + "BriefDescription": "Memory accesses that missed the DTLB.", "Counter": "0,1", - "UMask": "0x7", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS", "SampleAfterValue": "200000", - "BriefDescription": "Memory accesses that missed the DTLB." + "UMask": "0x7" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB misses due to load operations.", "Counter": "0,1", - "UMask": "0x5", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses due to load operations." + "UMask": "0x5" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB misses due to store operations.", "Counter": "0,1", - "UMask": "0x9", - "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", + "EventCode": "0x8", + "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "SampleAfterValue": "200000", - "BriefDescription": "L0 DTLB misses due to load operations." + "UMask": "0x6" }, { - "EventCode": "0x8", + "BriefDescription": "L0 DTLB misses due to load operations.", "Counter": "0,1", - "UMask": "0x6", - "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", + "EventCode": "0x8", + "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses due to store operations." + "UMask": "0x9" }, { - "EventCode": "0x8", + "BriefDescription": "L0 DTLB misses due to store operations", "Counter": "0,1", - "UMask": "0xa", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "SampleAfterValue": "200000", - "BriefDescription": "L0 DTLB misses due to store operations" + "UMask": "0xa" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB flushes.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", + "EventCode": "0x82", + "EventName": "ITLB.FLUSH", "SampleAfterValue": "200000", - "BriefDescription": "Number of page-walks executed." + "UMask": "0x4" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB hits.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of page-walks in core cycles" + "EventCode": "0x82", + "EventName": "ITLB.HIT", + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB misses.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "EventCode": "0x82", + "EventName": "ITLB.MISSES", + "PEBS": "2", "SampleAfterValue": "200000", - "BriefDescription": "Number of D-side only page walks" + "UMask": "0x2" }, { - "EventCode": "0xC", + "BriefDescription": "Retired loads that miss the DTLB (precise eve= nt).", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of D-side only page walks" + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x4" }, { - "EventCode": "0xC", + "BriefDescription": "Duration of page-walks in core cycles", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of I-Side page walks" + "EventCode": "0xC", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x3" }, { - "EventCode": "0xC", + "BriefDescription": "Duration of D-side only page walks", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Duration of I-Side page walks" + "UMask": "0x1" }, { - "EventCode": "0x82", + "BriefDescription": "Number of D-side only page walks", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ITLB.HIT", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", "SampleAfterValue": "200000", - "BriefDescription": "ITLB hits." + "UMask": "0x1" }, { - "EventCode": "0x82", + "BriefDescription": "Duration of I-Side page walks", "Counter": "0,1", - "UMask": "0x4", - "EventName": "ITLB.FLUSH", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB flushes." + "EventCode": "0xC", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0x82", + "BriefDescription": "Number of I-Side page walks", "Counter": "0,1", - "UMask": "0x2", - "EventName": "ITLB.MISSES", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "200000", - "BriefDescription": "ITLB misses." + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xCB", + "BriefDescription": "Number of page-walks executed.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.WALKS", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (precise eve= nt)." + "UMask": "0x3" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 473ABC433EF for ; Tue, 1 Feb 2022 02:00:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232202AbiBACAV (ORCPT ); Mon, 31 Jan 2022 21:00:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232137AbiBAB7f (ORCPT ); Mon, 31 Jan 2022 20:59:35 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68134C06173D for ; Mon, 31 Jan 2022 17:59:34 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id g67-20020a25db46000000b0061437d5e4b3so29960969ybf.10 for ; Mon, 31 Jan 2022 17:59:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=0Qol0Q4x+XpSK+8Wcu2YAjs5NRKv0PnTFcyxa5VvRIo=; b=osiZ7/yQtPH0dB463jK7vovO0FQDqhZCh3LeQjy7DrDVLjTmXIoN6VM2ka3Zy14WPi y9zUGQJjcyRFlSOERHv33Y3IpsAm9AHM7gUB+WqTdnE/9IhZ3zw12GYTk1RW1L7DH3EC 48Iracf3D86DUVKEnY82cE1z5IBKKyyfq76QBXqfe9nmgwW0nR7R1PS/I0tcg7ifoqUp 6R+Et3JdJe86UXmh7xBdwnbrxSxxxPb2fvaouHdr+fHG7Iu6GdUT2bgI9tZgkwLE2xZd s5n4I2CSn4VJ3BnO7ohIP4FEXqq9PRgJ2cLnP98yqUDSk9pl75uEfwo4Yd3sUPEw1ERq KUVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=0Qol0Q4x+XpSK+8Wcu2YAjs5NRKv0PnTFcyxa5VvRIo=; b=X7HVVFAMnZDUgiyTtzokd1uC8+NH2RZIpjpIuuOdGg+eC8TEGOZpiANm0Lfad6uftK ljJc2OIS3SMexP7FPUyRXYcptxtUEbIxds9EulzkKKsFIT0gfcM1cufFXgDHbXmLZTS3 eOZVDCC/ploY2QPXW9iDrTFwzP1G8osKRzAiyBdeK0d8MlMc/s4xzlTUI5vmLXOeJSyL WWNBIDlizueXiFRyNkKWK4IZ6yj1YyIW+548r1nFgnBp10g74SqBKxogXpDNP/xbEuE3 G8UqJyjcanl0u1JFCgMmd7BOtOrB/bJX4iZtR4feN3dz0v8NsiRHve6SypKThylMq3la ijFQ== X-Gm-Message-State: AOAM5329Y/mz5mIEDeGxgqwDPPnuoJC+IbqLwOXtH8xXBoKQS4z93WcD uRL0Sthe35fUGkLPFSthK8cFqTc22/xD X-Google-Smtp-Source: ABdhPJwmihMrzsZtkrrQNTKx7I7K/ToP2EhWPijeZp33DbFFKZEF7V6hWLrEWfiSEM4v2KAxqaVazrbJk4/7 X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:b003:: with SMTP id q3mr30756802ybf.767.1643680773498; Mon, 31 Jan 2022 17:59:33 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:42 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-11-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 10/26] perf vendor events: Update metrics for Broadwell From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 26: https://download.01.org/perfmon/BDW Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Broadwell, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/broadwell/bdw-metrics.json | 353 +- .../pmu-events/arch/x86/broadwell/cache.json | 4713 +++++++++-------- .../arch/x86/broadwell/floating-point.json | 235 +- .../arch/x86/broadwell/frontend.json | 361 +- .../pmu-events/arch/x86/broadwell/memory.json | 4312 +++++++-------- .../pmu-events/arch/x86/broadwell/other.json | 42 +- .../arch/x86/broadwell/pipeline.json | 1903 ++++--- .../arch/x86/broadwell/virtual-memory.json | 412 +- 8 files changed, 6219 insertions(+), 6112 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/to= ols/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index 8cdc7c13dc2a..91d23341eabd 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -1,196 +1,170 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLO= TS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_A= RITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_D= OUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETI= RED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) = / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_A= RITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_D= OUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETI= RED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) = / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_AC= TIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIV= E / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDow= n slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_M= ISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) = / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * = (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDow= n slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOP= S_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP= _RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (= 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + C= PU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MI= SP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts_SMT", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", "MetricName": "Branch_Misprediction_Cost_SMT" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -200,87 +174,196 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cp= u@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WAL= K_DURATION\\,cmask\\=3D1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_L= OAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cp= u@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WAL= K_DURATION\\,cmask\\=3D1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_L= OAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / (( ( CPU_CLK_U= NHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_U= NHALTED.REF_XCLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B= _PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cp= u@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WAL= K_DURATION\\,cmask\\=3D1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_L= OAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALT= ED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cp= u@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=3D1@ + cpu@DTLB_STORE_MISSES.WAL= K_DURATION\\,cmask\\=3D1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_L= OAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP= _ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED= _DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RE= TIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )= ) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -291,22 +374,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external m= emory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/cache.json index 7938bf5689ab..890412f02e06 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -1,3399 +1,3410 @@ [ { - "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x27", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outst= anding in cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", - "EventCode": "0x24", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.L2_PF_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "EventCode": "0x24", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "UMask": "0x3f", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "All requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", - "EventCode": "0x24", + "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "L2_RQSTS.L2_PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x5" }, { - "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", - "EventCode": "0x24", + "BriefDescription": "L2 code requests", "Counter": "0,1,2,3", - "UMask": "0xe1", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 cod= e requests.", "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe4" }, { - "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", - "EventCode": "0x24", + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "UMask": "0xe2", - "EventName": "L2_RQSTS.ALL_RFO", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe1" }, { - "PublicDescription": "This event counts the total number of L2 cod= e requests.", - "EventCode": "0x24", + "BriefDescription": "Demand requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0xe4", - "EventName": "L2_RQSTS.ALL_CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x27" }, { - "EventCode": "0x24", + "BriefDescription": "Demand requests to L2 cache.", "Counter": "0,1,2,3", - "UMask": "0xe7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "SampleAfterValue": "200003", - "BriefDescription": "Demand requests to L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe7" }, { - "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", - "EventCode": "0x24", + "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", - "UMask": "0xf8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf8" }, { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", - "BriefDescription": "All L2 requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", - "EventCode": "0x27", + "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", - "UMask": "0x50", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", - "EventCode": "0x2E", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", - "EventCode": "0x2E", + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "This event counts duration of L1D miss outst= anding in cycles.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "EventCode": "0x48", + "BriefDescription": "All L2 requests.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", - "EventCode": "0x51", + "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "PublicDescription": "This event counts the number of offcore outs= tanding Demand Data Read transactions in the super queue (SQ) every cycle. = A transaction is considered to be in the Offcore outstanding state between = L2 miss and transaction completion sent to requestor. See the corresponding= Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is coun= ted from the promotion point.", - "EventCode": "0x60", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x22" }, { - "PublicDescription": "This event counts cycles when offcore outsta= nding Demand Data Read transactions are present in the super queue (SQ). A = transaction is considered to be in the Offcore outstanding state between L2= miss and transaction completion sent to requestor (SQ de-allocation).", - "EventCode": "0x60", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0x60", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "PublicDescription": "This event counts the number of offcore outs= tanding Code Reads transactions in the super queue every cycle. The Offcore= outstanding state of the transaction lasts from the L2 miss until the send= ing transaction completion to requestor (SQ deallocation). See the correspo= nding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of offcore outs= tanding RFO (store) transactions in the super queue (SQ) every cycle. A tra= nsaction is considered to be in the Offcore outstanding state between L2 mi= ss and transaction completion sent to requestor (SQ de-allocation). See cor= responding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of offcore outs= tanding demand rfo Reads transactions in the super queue every cycle. The O= ffcore outstanding state of the transaction lasts from the L2 miss until th= e sending transaction completion to requestor (SQ deallocation). See the co= rresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PublicDescription": "This event counts the number of offcore outs= tanding cacheable Core Data Read transactions in the super queue every cycl= e. A transaction is considered to be in the Offcore outstanding state betwe= en L2 miss and transaction completion sent to requestor (SQ de-allocation).= See corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "This event counts cycles when offcore outsta= nding cacheable Core Data Read transactions are present in the super queue.= A transaction is considered to be in the Offcore outstanding state between= L2 miss and transaction completion sent to requestor (SQ de-allocation). S= ee corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", - "EventCode": "0x63", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", - "EventCode": "0xB0", + "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", - "EventCode": "0xB0", + "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", - "EventCode": "0xB0", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", - "EventCode": "0xB0", + "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.= ", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", - "EventCode": "0xb2", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", + "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were L3 Hit and a cross-core snoop missed in the on-pkg core cac= he.", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with true STLB miss retired to the ar= chitected path. True STLB miss is an uop triggering page walk that gets com= pleted without blocks, and later gets retired. This page walk can end up wi= th or without a fault.", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops true STLB miss retired to the archit= ected path. True STLB miss is an uop triggering page walk that gets complet= ed without blocks, and later gets retired. This page walk can end up with o= r without a fault.", - "EventCode": "0xD0", + "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS)", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with locked access retired to the arc= hitected path.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "Errata": "BDM35", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PublicDescription": "Retired load uop whose Data Source was: loca= l DRAM either Snoop not needed or Snoop Miss (RspI).", "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted load uops retired to the architec= ted path. A line split is across 64B cache-line which includes a page split= (4K).", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.(Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were load uops missed L1 but hit a fill buffer due to a precedin= g miss to the same cache line with the data not ready.\nNote: Only two data= -sources of L1/FB are applicable for AVX-256bit even though the correspond= ing AVX load could be serviced by a deeper level in the memory hierarchy. D= ata source is reported for the Low-half load.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted store uops retired to the archite= cted path. A line split is across 64B cache-line which includes a page spli= t (4K).", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops retired to the architected path with = a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/= store double-pump memory uops as a single uop at retirement. This event als= o counts SW prefetches.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the nearest-level (L1) cache.\nNote: Only two data-= sources of L1/FB are applicable for AVX-256bit even though the correspondi= ng AVX load could be serviced by a deeper level in the memory hierarchy. Da= ta source is reported for the Low-half load. This event also counts SW pref= etches independent of the actual data source.", "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event - PEBS)= ", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops retired to the architected path with= a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load= /store double-pump memory uops as a single uop at retirement.", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data source were hits i= n the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are a= pplicable for AVX-256bit even though the corresponding AVX load could be s= erviced by a deeper level in the memory hierarchy. Data source is reported = for the Low-half load. This event also counts SW prefetches independent of = the actual data source.", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the nearest-level (L1) cache. Counting excludes u= nknown and UC data source.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the mid-level (L2) cache.", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM35", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the mid-level (L2) cache.", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were data = hits in the last-level (L3) cache without snoops required.", - "EventCode": "0xD1", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknow= n data-source. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the mid-level (L2) cache. Counting excludes unkno= wn and UC data source.", + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the nearest-level (L1) cache. Counting excludes unknown and UC data so= urce.", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops misses in L1 cache as data = sources. Uses PEBS.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the mid-level (L2) cache. Counting excludes unknown and UC data source= .", + "Data_LA": "1", + "Errata": "BDM100", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were data hits in the last-level (L3) cache without snoops requi= red.", "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources. Uses PEBS.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM100, BDE70", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x20" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were load = uops missed L1 but hit a fill buffer due to a preceding miss to the same ca= che line with the data not ready.\nNote: Only two data-sources of L1/FB are= applicable for AVX-256bit even though the corresponding AVX load could be= serviced by a deeper level in the memory hierarchy. Data source is reporte= d for the Low-half load.", - "EventCode": "0xD1", + "BriefDescription": "All retired load uops.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops retired to the a= rchitected path with a filter on bits 0 and 1 applied.\nNote: This event co= unts AVX-256bit load/store double-pump memory uops as a single uop at retir= ement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 Hi= t and a cross-core snoop missed in the on-pkg core cache.", - "EventCode": "0xD2", + "BriefDescription": "All retired store uops.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS= )", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts store uops retired to the = architected path with a filter on bits 0 and 1 applied.\nNote: This event c= ounts AVX-256bit load/store double-pump memory uops as a single uop at reti= rement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 hi= t and a cross-core snoop hit in the on-pkg core cache.", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops with locked access.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops with locked acce= ss retired to the architected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were HitM = responses from a core on same socket (shared L3).", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the last-level (L3) cache without snoops required.", - "EventCode": "0xD2", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches. Thi= s is a precise event.", - "EventCode": "0xD3", + "PublicDescription": "This event counts load uops with true STLB m= iss retired to the architected path. True STLB miss is an uop triggering pa= ge walk that gets completed without blocks, and later gets retired. This pa= ge walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDE70, BDM100", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100007", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts store uops with true STLB = miss retired to the architected path. True STLB miss is an uop triggering p= age walk that gets completed without blocks, and later gets retired. This p= age walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", - "EventCode": "0xF0", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Any memory transaction that reached the SQ.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reache= d the super queue including requests initiated by the core, all L3 prefetch= es, page walks, and so on.", + "SampleAfterValue": "100003", + "UMask": "0x80" }, { - "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", - "EventCode": "0xF0", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", - "EventCode": "0xF0", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding cacheable Core Data Read transactions in the super queue every cycl= e. A transaction is considered to be in the Offcore outstanding state betwe= en L2 miss and transaction completion sent to requestor (SQ de-allocation).= See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", - "EventCode": "0xF0", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outsta= nding cacheable Core Data Read transactions are present in the super queue.= A transaction is considered to be in the Offcore outstanding state between= L2 miss and transaction completion sent to requestor (SQ de-allocation). S= ee corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", - "EventCode": "0xF1", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "PublicDescription": "This event counts cycles when offcore outsta= nding Demand Data Read transactions are present in the super queue (SQ). A = transaction is considered to be in the Offcore outstanding state between L2= miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outs= tanding demand rfo Reads transactions in the super queue every cycle. The O= ffcore outstanding state of the transaction lasts from the L2 miss until th= e sending transaction completion to requestor (SQ deallocation). See the co= rresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding Code Reads transactions in the super queue every cycle. The Offcore= outstanding state of the transaction lasts from the L2 miss until the send= ing transaction completion to requestor (SQ deallocation). See the correspo= nding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding Demand Data Read transactions in the super queue (SQ) every cycle. = A transaction is considered to be in the Offcore outstanding state between = L2 miss and transaction completion sent to requestor. See the corresponding= Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is coun= ted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of split locks = in the super queue.", - "EventCode": "0xf4", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outs= tanding RFO (store) transactions in the super queue (SQ) every cycle. A tra= nsaction is considered to be in the Offcore outstanding state between L2 mi= ss and transaction completion sent to requestor (SQ de-allocation). See cor= responding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts demand data reads have any response t= ype.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010001", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads have any response ty= pe.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020001", + "BriefDescription": "Counts all demand & prefetch data reads have = any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads have= any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0001", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= _NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020091", "Offcore": "1", - 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"EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEED= ED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_F= WD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0008", + "BriefDescription": "Counts all prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020090", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0008", + "BriefDescription": "Counts prefetch RFOs have any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs have any response type.= ", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0008", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0008", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0008", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts writebacks (modified to exclusive)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0008", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads have any response type.", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads have any response type.", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", - "MSRIndex": "0x1a6, 0x1a7", + "PublicDescription": "Counts prefetch RFOs", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= ITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0010", + "BriefDescription": "Counts prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020120", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0010", + "BriefDescription": "Counts all demand & prefetch RFOs have any re= sponse type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs have any r= esponse type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0010", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs have any response type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_= FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0020", + "BriefDescription": "Counts all demand & prefetch RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEE= DED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0020", + "BriefDescription": "Counts writebacks (modified to exclusive) hav= e any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive) ha= ve any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0020", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads have any response type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_H= ITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020008", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts writebacks (modified to exclusive)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020040", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNO= OP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020008", "Offcore": "1", - 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"EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0080", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs have any response type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0100", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0100", + "BriefDescription": "Counts all demand data writes (RFOs) have any= response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs) have an= y response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0100", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0100", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0100", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010200", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads have any response type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020200", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020200", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020200", + "BriefDescription": "Counts any other requests have any response t= ype.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018000", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts any other requests have any response = type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020200", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C8000", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts any other requests", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020200", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= ITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C8000", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts any other requests", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020200", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNO= OP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C8000", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts any other requests", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", - 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"PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads have any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= ITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0090", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs have any response type.= ", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010120", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs have any response type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020120", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs have any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0120", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads have any resp= onse type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010240", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads have any respo= nse type.", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads have any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_F= WD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEED= ED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNO= OP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= ITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0240", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads have= any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010091", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads have = any response type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads have any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= E", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT= _NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MIS= S", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= _NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= M", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP= ", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_H= ITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs have any r= esponse type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs have any response type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs have any re= sponse type.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEE= DED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_= FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0122", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0122", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "This event counts the number of split locks = in the super queue.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b= /tools/perf/pmu-events/arch/x86/broadwell/floating-point.json index 15291239c128..9ad37dddb354 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -1,172 +1,193 @@ [ { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of transitions from AVX-256 to legac= y SSE when penalty is applicable.", - "EventCode": "0xC1", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM30", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of transitions from legacy SSE to AV= X-256 when penalty is applicable.", - "EventCode": "0xC1", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x10", - "Errata": "BDM30", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from legacy SSE to AVX-= 256 when penalty applicable (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar double precision floating-point = instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB inst= ructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar single precision floating-point = instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)AD= D/SUB instructions count twice as they perform multiple calculations per el= ement.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed double precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired. Applies to SSE* and AVX* scalar, double and = single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(= N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element. (RSQRT for single precision?)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* packed double and single precision floating= -point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RC= P DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired. Each count represe= nts 2 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM= (N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform = multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "UMask": "0x3c" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM= (N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform = multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x15", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP = FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perfor= m multiple calculations per element.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xc7", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired. Each count represe= nts 8 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed single precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x2a", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", - "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT= SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as t= hey perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2a" }, { - "EventCode": "0xC7", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "FP_ARITH_INST_RETIRED.PACKED", - "SampleAfterValue": "2000004", - "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired. Applies to SSE* and AVX*, packed, double and= single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX = SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as th= ey perform multiple calculations per element. (RSQRT for single-precision?)= ", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and = output SSE or x87 FP assist. If an input and output assist are detected on = the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of x87 floating point (FP) micro-cod= e assist (numeric overflow/underflow, inexact result) when the output value= (destination register) is invalid.", - "EventCode": "0xCA", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", "SampleAfterValue": "100003", - "BriefDescription": "output - Numeric Overflow, Numeric Underflow,= Inexact Result (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts x87 floating point (FP) micro-code assist (inva= lid operation, denormal operand, SNaN operand) when the input value (one of= the source operands to an FP instruction) is invalid.", + "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "This event counts x87 floating point (FP) mi= cro-code assist (invalid operation, denormal operand, SNaN operand) when th= e input value (one of the source operands to an FP instruction) is invalid.= ", "SampleAfterValue": "100003", - "BriefDescription": "input - Invalid Operation, Denormal Operand, = SNaN Operand (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of SSE* floating point (FP) micro-co= de assist (numeric overflow/underflow) when the output value (destination r= egister) is invalid. Counting covers only cases involving penalties that re= quire micro-code assist intervention.", - "EventCode": "0xCA", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", "SampleAfterValue": "100003", - "BriefDescription": "SSE* FP micro-code assist when output value i= s invalid. (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts any input SSE* floating-point (FP) assist - inv= alid operation, denormal operand, dividing by zero, SNaN operand. Counting = includes only cases involving penalties that required micro-code assist int= ervention.", - "EventCode": "0xCA", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions = from AVX-256 to legacy SSE when penalty is applicable.", "SampleAfterValue": "100003", - "BriefDescription": "Any input SSE* FP Assist - (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "This event counts cycles with any input and = output SSE or x87 FP assist. If an input and output assist are detected on = the same cycle the event increments by 1. Uses PEBS.", - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions = from legacy SSE to AVX-256 when penalty is applicable.", "SampleAfterValue": "100003", - "BriefDescription": "Counts any FP_ASSIST umask was incrementing = (Precise Event)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools= /perf/pmu-events/arch/x86/broadwell/frontend.json index aa4a5d762f21..f0bcb945ff76 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -1,286 +1,295 @@ [ { - "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "PublicDescription": "This event counts cycles during which uops i= nitiated by Decode Stream Buffer (DSB) are being delivered to Instruction D= ecode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting incl= udes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the Decode Stream B= uffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" }, { - "PublicDescription": "This event counts the number of deliveries t= o Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) wh= ile the Microcode Sequencer (MS) is busy. Counting includes uops that may b= ypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the MITE path. Count= ing includes uops that may bypass the IDQ. This also means that uops are no= t being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the Decode Stream B= uffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the MITE path. Count= ing includes uops that may bypass the IDQ. This also means that uops are no= t being delivered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops i= nitiated by Decode Stream Buffer (DSB) are being delivered to Instruction D= ecode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting incl= udes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", "Counter": "0,1,2,3", - "UMask": "0x30", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries t= o Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) wh= ile the Microcode Sequencer (MS) is busy. Counting includes uops that may b= ypass the IDQ.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", - "EventCode": "0x80", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", - "EventCode": "0x80", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", - "EventCode": "0x80", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFDATA_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding \u201c4 \u2013 = x\u201d when Resource Allocation Table (RAT) is not stalled and Instruction= Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (whe= re x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Re= source Allocation Table (RAT) pipe serves the other thread;\n b. Resource A= llocation Table (RAT) is stalled for the thread (including uop drops and cl= ear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops= .", - "EventCode": "0x9C", + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding 4 x when Resou= rce Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ= ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0= ,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation = Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (R= AT) is stalled for the thread (including uop drops and clear BE conditions)= ; \n c. Instruction Decode Queue (IDQ) delivers four uops.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_U= ops_Not_Delivered.core =3D4.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, = cycles when less than 1 uop is delivered to Resource Allocation Table (RAT= ). IDQ_Uops_Not_Delivered.core >=3D3.", "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, = cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_U= ops_Not_Delivered.core =3D4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, = cycles when less than 1 uop is delivered to Resource Allocation Table (RAT= ). IDQ_Uops_Not_Delivered.core >=3D3.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "Invert": "1", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0\u20132 c= ycles.", - "EventCode": "0xAB", + "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/p= erf/pmu-events/arch/x86/broadwell/memory.json index b6b5247d3d5a..f4eebecf371f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -1,3045 +1,3053 @@ [ { - "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", - "EventCode": "0x05", + "BriefDescription": "Number of times HLE abort was triggered", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Number of times a TSX line had a cache confl= ict.", - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX line had a cache confli= ct", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", - "EventCode": "0x54", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of times we could not allocate Lock B= uffer.", - "EventCode": "0x54", + "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5d", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 128", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 128.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 16", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "RTM region detected inside HLE.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 256", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 256.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 32", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Randomly selected loads with latency value be= ing above 4", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above four.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 512", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 512.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "Number of times HLE commit succeeded.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE commit succeeded", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 64", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered (PEB= S).", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "HLE_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE abort was triggered (PEBS= )", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 8", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above eight.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", - "EventCode": "0xc8", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "HLE_RETIRED.ABORTED_MISC1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", - "EventCode": "0xc8", + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "HLE_RETIRED.ABORTED_MISC2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", - "EventCode": "0xc8", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "HLE_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times HLE caused a fault.", - "EventCode": "0xc8", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "HLE_RETIRED.ABORTED_MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FW= D", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x043C000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", - "EventCode": "0xc8", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x023C000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RTM_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00BC000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times RTM commit succeeded.", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RTM_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times RTM commit succeeded", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDE= D", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x013C000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered (PEB= S).", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RTM_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times RTM abort was triggered (PEBS= )", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_= SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0404000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0204000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times a RTM caused a fault.", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0084000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above four.", - "EventCode": "0xCD", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value be= ing above 4", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above eight.", - "EventCode": "0xCD", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Randomly selected loads with latency value be= ing above 8", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Randomly selected loads with latency value be= ing above 16", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100007", - "BriefDescription": "Randomly selected loads with latency value be= ing above 32", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Randomly selected loads with latency value be= ing above 64", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0104000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Randomly selected loads with latency value be= ing above 128", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= _DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Randomly selected loads with latency value be= ing above 256", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20003C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency = value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Randomly selected loads with latency value be= ing above 512", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x043C000240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2000020001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x023C000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20003C0001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRA= M", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00BC000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0084000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x013C000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0104000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0204000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0404000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0404000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0204000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0084000240", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F84000001", + "BriefDescription": "Counts all prefetch code reads", "Counter": "0,1,2,3", - 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"CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x043C000240", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SN= OOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2000020091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= _DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20003C0091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0404000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0084000091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0204000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0104000091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0084000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0204000091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0104000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0404000091", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_D= RAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004000091", + "BriefDescription": "Number of times RTM abort was triggered", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004000091", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F84000091", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_= SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00BC000091", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x013C000091", + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDE= D", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x023C000091", + "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x043C000091", + "BriefDescription": "Number of times RTM commit succeeded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FW= D", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2000020122", + "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRA= M", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20003C0122", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0084000122", + "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= NE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0104000122", + "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= T_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0204000122", + "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0404000122", + "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HI= T_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004000122", + "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HI= TM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004000122", + "BriefDescription": "Number of times a TSX line had a cache confli= ct", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= N_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache confl= ict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F84000122", + "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOO= P", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00BC000122", + "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x013C000122", + "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x023C000122", + "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x043C000122", + "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock B= uffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/other.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/other.json index 4f829c5febbe..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/other.json @@ -1,44 +1,44 @@ [ { - "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts when there is a transition= from ring 1,2 or 3 to ring0.", - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", + "PublicDescription": "This event counts when there is a transition= from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools= /perf/pmu-events/arch/x86/broadwell/pipeline.json index bb25574b8d21..18d21b94a4b9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -1,1429 +1,1380 @@ [ { - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Cycles when divider is busy executing divide = operations", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "CounterHTOff": "Fixed counter 2" + "UMask": "0x1" }, { - "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", - "EventCode": "0x03", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x03", + "BriefDescription": "Speculative and retired macro-conditional bra= nches", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", - "EventCode": "0x07", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial comp= are", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "PublicDescription": "Cycles checkpoints in Resource Allocation Ta= ble (RAT) are recovering from JEClear or machine clear.", - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", - "EventCode": "0x0E", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "This event counts cycles during which the Re= source Allocation Table (RAT) does not issue any Uops to the reservation st= ation (RS) for the current thread.", - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Taken speculative and retired macro-condition= al branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired direct near cal= ls", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", - "EventCode": "0x14", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide = operations", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", + "SampleAfterValue": "400009" }, { - "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instruc= tions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", - "EventCode": "0x3C", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions re= tired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect n= ear call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3c", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect m= acro near call instructions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This event counts return instructions retire= d.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", - "EventCode": "0x4c", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This event counts taken branch instructions = retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", - "EventCode": "0x4C", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructi= ons retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x58", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x58", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x58", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x58", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", - "EventCode": "0x5E", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x5E", - "Invert": "1", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", - "EventCode": "0x88", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", + "SampleAfterValue": "400009" }, { - "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", - "EventCode": "0x88", + "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", - "EventCode": "0x88", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional b= ranch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", - "EventCode": "0x88", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", - "EventCode": "0x88", + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near cal= ls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted return instru= ctions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional bra= nches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", - "EventCode": "0x89", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", - "EventCode": "0x89", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", - "EventCode": "0xA0", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request (that is cycles with non-completed load w= aiting for its data from memory subsystem).", "SampleAfterValue": "2000003", - "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", - "EventCode": "0xA1", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest missing the L1 data cache.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand* load re= quest missing the L2 cache.(as a footprint) * includes also L1 HW prefetch = requests that may or may not be required by demands.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "UMask": "0x4", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", - "EventCode": "0xA1", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", - "EventCode": "0xA1", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", - "EventCode": "0xA1", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions= (EOMs) retired. Counting covers macro-fused instructions individually (tha= t is, increments by two).", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts instructions retired.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", "Counter": "0,1,2,3", - "UMask": "0x10", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", - "EventCode": "0xA1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", - "EventCode": "0xA1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Ta= ble (RAT) are recovering from JEClear or machine clear.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", - "EventCode": "0xA1", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", - "EventCode": "0xA1", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "False dependencies in MOB due to partial comp= are", "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", - "EventCode": "0xA1", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts resource-related stall cyc= les.", - "EventCode": "0xa2", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", - "EventCode": "0xA2", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", - "EventCode": "0xA2", + "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", - "EventCode": "0xA2", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand* load request missing the L2 cache.", - "EventCode": "0xA3", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request (that is cycles with non-completed load w= aiting for its data from memory subsystem).", - "EventCode": "0xA3", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port.", - "EventCode": "0xA3", + "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cyc= les.", "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", "SampleAfterValue": "2000003", - "BriefDescription": "Total execution stalls.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand* load re= quest missing the L2 cache.(as a footprint) * includes also L1 HW prefetch = requests that may or may not be required by demands.", - "EventCode": "0xA3", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xA3", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest.", - "EventCode": "0xA3", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xA3", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request missing the L1 data cache.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "CounterMask": "8", - "CounterHTOff": "2" + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "CounterMask": "8", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest missing the L1 data cache.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x2" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x4" }, { - "PublicDescription": "Number of Uops delivered by the LSD.", - "EventCode": "0xA8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.THREAD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "This event counts cycles during which no uop= s were dispatched from the Reservation Station (RS) per thread.", - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xB1", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PublicDescription": "Number of uops executed from any thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "Invert": "1", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of instructions= (EOMs) retired. Counting covers macro-fused instructions individually (tha= t is, increments by two).", - "EventCode": "0xC0", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", - "UMask": "0x0", - "Errata": "BDM61", - "EventName": "INST_RETIRED.ANY_P", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uop= s were dispatched from the Reservation Station (RS) per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts instructions retired.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "Errata": "BDM11, BDM55", - "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts FP operations retired. For X87 FP operations th= at have no exceptions counting also includes flows that have several X87, o= r flows that use X87 uops in the exception handling.", - "EventCode": "0xC0", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts all actually retired uops. Counting increments = by two for micro-fused uops, and by one for macro-fused and other uops. Max= imal increment value for one cycle is eight.", - "EventCode": "0xC2", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= ", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Data_LA": "1" + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts cycles without actually retired uops.", - "EventCode": "0xC2", - "Invert": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired (Precise Ev= ent)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to PEBS uops retired event.", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles using always true condition = applied to PEBS uops retired event.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of retirement slots used.", - "EventCode": "0xC2", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", - "EventCode": "0xC3", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xC3", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", - "EventCode": "0xC3", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", - "EventCode": "0xC3", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts conditional branch instructions retired.", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect near call instructions= retired.", - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect macro near call instru= ctions retired (captured in ring 3).", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "2", - "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDW98", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts return instructions retired.", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired. (Precise Event -= PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts not taken branch instructions retired.", - "EventCode": "0xC4", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Counts all not taken macro branch instruction= s retired. (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts taken branch instructions retired.", - "EventCode": "0xC4", + "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts far branch instructions retired.", - "EventCode": "0xC4", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "BDW98", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of far branch instructions = retired.(Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", - "EventCode": "0xC5", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted conditional branch instructions re= tired.", - "EventCode": "0xC5", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Re= source Allocation Table (RAT) does not issue any Uops to the reservation st= ation (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", - "EventCode": "0xC5", + "BriefDescription": "Actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted return instructions retired.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_MISP_RETIRED.RET", - "SampleAfterValue": "100007", - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired.(Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "PublicDescription": "This event counts all actually retired uops.= Counting increments by two for micro-fused uops, and by one for macro-fuse= d and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken. (Precise Event - PEBS).", - "EventCode": "0xC5", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement s= lots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", - "EventCode": "0xCC", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually re= tired uops.", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xe6", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json index 2a015e4c7e21..818a8b132c08 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause page walks of any page size (4K/2M/4M/1G).", - "EventCode": "0x08", + "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (4K page size). The page walk can end= with or without a fault.", - "EventCode": "0x08", + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (2M and 4M page sizes). The page walk= can end with or without a fault.", - "EventCode": "0x08", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (1G page size). The page walk can en= d with or without a fault.", - "EventCode": "0x08", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", - "EventCode": "0x08", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (1G page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (2M and 4M page sizes). The page walk= can end with or without a fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (4K page size). The page walk can end= with or without a fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x08", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", "SampleAfterValue": "2000003", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", - "EventCode": "0x49", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", - "EventCode": "0x49", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", - "EventCode": "0x4F", + "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", + "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", - "EventCode": "0x85", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", - "EventCode": "0x85", + "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", - "EventCode": "0x85", + "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x85", + "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", - "EventCode": "0x85", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x85", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "ITLB_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x85", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", - "EventCode": "0xAE", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", "Counter": "0,1,2,3", - "UMask": "0x11", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "UMask": "0x12", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", "Counter": "0,1,2,3", - "UMask": "0x14", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "UMask": "0x18", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in Memory.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", "Counter": "0,1,2,3", - "UMask": "0x21", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "UMask": "0x22", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", - "EventCode": "0xBD", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEE46C433EF for ; Tue, 1 Feb 2022 02:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232462AbiBACAX (ORCPT ); Mon, 31 Jan 2022 21:00:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232212AbiBAB7h (ORCPT ); Mon, 31 Jan 2022 20:59:37 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51344C061749 for ; Mon, 31 Jan 2022 17:59:37 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id d65-20020a256844000000b00614359972a6so29895785ybc.16 for ; Mon, 31 Jan 2022 17:59:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=uwLDiyD2qKlTAqyGBALnEJ6Ij0bVYOJ+GSfW0u5/tEI=; b=EhSbGYk3Gv+u74PkoBhGIclg4VTX17iYs5rPbD/HdnbLU/aSgAU6kVlUfuvVXTBJ7s BDCact1AOtOpeMTdCq58d5iPQvAfcjlRr5BstWUlwLcvgMvDwnids0q6Ugubwbnwtp6u Rbx/dqP9FLxXU0ogOEBCHWkzeMBJOh+8t5Q+euuGESon6Ilnfh8ctk0KBO4+BdU4QKpQ NeZgZz+WzBB4JUChmQ4G/R/Jb4z70cS1t0TskO8LBk2AtJe8yLUbYy35NeIeNR/H+Mtc m5L/kLCXhww0RwjlfbB3Vv4QNu8Wgru4ThAq5/AEWvCJG7JetSy/HtthlTNDXigbVZmt PmOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=uwLDiyD2qKlTAqyGBALnEJ6Ij0bVYOJ+GSfW0u5/tEI=; b=x4mE+RZwL7+nrfnF+KOj/P4kUwvNDgMeiUzPFV5x8FaAtHbBwQR4tjBFp73AJBuOfY O4Zyq9Tu2tksMrepFgZqiC7ay0h+8K6cWzgCN1pKXamI0n+q5WKQ41r3qTdZFcz9C4qt XBO/dj1xj6+VqYLJ3jtRDKKDTryKbcnnMxeakILTaU7I2GYD5nlPOfi4NnDAyrjVT8SU KakBXaznBBaYkjbBhRSwst30kfZkP2yMITBMCMNkcVwwVUGFuVkpi+aeYETurVS9h323 IKqKGvzI7gKomrtvPlcXk4H8fTOjiZK2NZQj5TKEiFClBf+QSHrzx3ChtEF+AETCqIKe c0aw== X-Gm-Message-State: AOAM5337qWuqEUujc3oodlNwjwjJeW39vRXHpK7P3Fm4FuaAaVJssDua Fi53dDqty7ZBVcQgfs8aeYP1TtVWRHye X-Google-Smtp-Source: ABdhPJylhw5AOO2aujUi4vXdKmeIrcc013LukCkyPKaoVHuE/FYzsu13RB5EjXT7tLTVrlkLKWbxlzh7f0Lw X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a05:6902:1104:: with SMTP id o4mr31717010ybu.309.1643680776428; Mon, 31 Jan 2022 17:59:36 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:43 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-12-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 11/26] perf vendor events: Update metrics for BroadwellX From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 17: https://download.01.org/perfmon/BDX Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a BroadwellX, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/broadwellx/bdx-metrics.json | 351 +-- .../pmu-events/arch/x86/broadwellx/cache.json | 1300 +++++------ .../arch/x86/broadwellx/floating-point.json | 224 +- .../arch/x86/broadwellx/frontend.json | 335 +-- .../arch/x86/broadwellx/memory.json | 974 ++++----- .../pmu-events/arch/x86/broadwellx/other.json | 28 +- .../arch/x86/broadwellx/pipeline.json | 1891 ++++++++--------- .../arch/x86/broadwellx/virtual-memory.json | 394 ++-- 8 files changed, 2802 insertions(+), 2695 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/t= ools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 1eb0415fa11a..b055947c0afe 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -1,196 +1,170 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLO= TS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_A= RITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_D= OUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETI= RED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) = / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_A= RITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_D= OUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETI= RED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) = / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_AC= TIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIV= E / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDow= n slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_M= ISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) = / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * = (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDow= n slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOP= S_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP= _RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (= 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + C= PU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MI= SP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts_SMT", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", "MetricName": "Branch_Misprediction_Cost_SMT" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -200,87 +174,196 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_= COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) = ) / ( 2 * cycles )", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_= COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) = ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_T= HREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) )", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B= _PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_= COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) = ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_= COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) = ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_TH= READ_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP= _ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED= _DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RE= TIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )= ) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -291,40 +374,52 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", "MetricExpr": "1000000000 * ( cbox@event\\=3D0x36\\,umask\\=3D0x3\= \,filter_opc\\=3D0x182@ / cbox@event\\=3D0x35\\,umask\\=3D0x3\\,filter_opc\= \=3D0x182@ ) / ( cbox_0@event\\=3D0x0@ / duration_time )", - "MetricGroup": "Memory_Lat", - "MetricName": "DRAM_Read_Latency" + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cbox@event\\=3D0x36\\,umask\\=3D0x3\\,filter_opc\\= =3D0x182@ / cbox@event\\=3D0x36\\,umask\\=3D0x3\\,filter_opc\\=3D0x182\\,th= resh\\=3D1@", - "MetricGroup": "Memory_BW", - "MetricName": "DRAM_Parallel_Reads" + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Socket actual clocks when any core is active = on that socket", "MetricExpr": "cbox_0@event\\=3D0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/p= erf/pmu-events/arch/x86/broadwellx/cache.json index 75a3098d5775..127abe08362f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -1,966 +1,976 @@ [ { + "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outst= anding in cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x50" + }, + { + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x7" + }, + { + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x5" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 cod= e requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe1" }, { + "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache.", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe2" }, { + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache.", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x21" }, { + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0x30", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { "BriefDescription": "L2 prefetch requests that miss L2 cache", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x24", - "UMask": "0x3f", "BriefDescription": "All requests that miss L2 cache.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3f" }, { - "EventCode": "0x24", - "UMask": "0xc1", - "BriefDescription": "Demand Data Read requests that hit L2 cache", + "BriefDescription": "All L2 requests.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x24", - "UMask": "0xc2", "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x24", - "UMask": "0xc4", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x22" }, { - "EventCode": "0x24", - "UMask": "0xd0", - "BriefDescription": "L2 prefetch requests that hit L2 cache", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x24", - "UMask": "0xe1", - "BriefDescription": "Demand Data Read requests", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "This event counts the total number of L2 cod= e requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0xe7", - "BriefDescription": "Demand requests to L2 cache.", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x24", - "UMask": "0xf8", - "BriefDescription": "Requests from L2 hardware prefetchers", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests.", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x2E", - "UMask": "0x41", "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x2E", - "UMask": "0x4f", "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts duration of L1D miss outst= anding in cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", - "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "UMask": "0x1", - "BriefDescription": "L1D data line replacements", - "Counter": "0,1,2,3", - "EventName": "L1D.REPLACEMENT", - "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding Demand Data Read transactions in the super queue (SQ) every cycle. = A transaction is considered to be in the Offcore outstanding state between = L2 miss and transaction completion sent to requestor. See the corresponding= Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is coun= ted from the promotion point.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outsta= nding Demand Data Read transactions are present in the super queue (SQ). A = transaction is considered to be in the Offcore outstanding state between L2= miss and transaction completion sent to requestor (SQ de-allocation).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "BDM76", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding Code Reads transactions in the super queue every cycle. The Offcore= outstanding state of the transaction lasts from the L2 miss until the send= ing transaction completion to requestor (SQ deallocation). See the correspo= nding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding RFO (store) transactions in the super queue (SQ) every cycle. A tra= nsaction is considered to be in the Offcore outstanding state between L2 mi= ss and transaction completion sent to requestor (SQ de-allocation). See cor= responding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding demand rfo Reads transactions in the super queue every cycle. The O= ffcore outstanding state of the transaction lasts from the L2 miss until th= e sending transaction completion to requestor (SQ deallocation). See the co= rresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outs= tanding cacheable Core Data Read transactions in the super queue every cycl= e. A transaction is considered to be in the Offcore outstanding state betwe= en L2 miss and transaction completion sent to requestor (SQ de-allocation).= See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outsta= nding cacheable Core Data Read transactions are present in the super queue.= A transaction is considered to be in the Offcore outstanding state between= L2 miss and transaction completion sent to requestor (SQ de-allocation). S= ee corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x63", - "UMask": "0x2", - "BriefDescription": "Cycles when L1D is locked", - "Counter": "0,1,2,3", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.= ", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were L3 Hit and a cross-core snoop missed in the on-pkg core cac= he.", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", + "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "PublicDescription": "This event counts load uops with true STLB m= iss retired to the architected path. True STLB miss is an uop triggering pa= ge walk that gets completed without blocks, and later gets retired. This pa= ge walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Retired load uop whose Data Source was: loca= l DRAM either Snoop not needed or Snoop Miss (RspI).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB.", + "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "PublicDescription": "This event counts store uops with true STLB = miss retired to the architected path. True STLB miss is an uop triggering p= age walk that gets completed without blocks, and later gets retired. This p= age walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x4" }, { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access.", + "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "BDM35", - "PublicDescription": "This event counts load uops with locked acce= ss retired to the architected path.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x10" }, { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K).", + "PublicDescription": "This event counts retired load uops which da= ta sources were load uops missed L1 but hit a fill buffer due to a precedin= g miss to the same cache line with the data not ready.\nNote: Only two data= -sources of L1/FB are applicable for AVX-256bit even though the correspond= ing AVX load could be serviced by a deeper level in the memory hierarchy. D= ata source is reported for the Low-half load.", "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PublicDescription": "This event counts load uops retired to the a= rchitected path with a filter on bits 0 and 1 applied.\nNote: This event co= unts AVX-256bit load/store double-pump memory uops as a single uop at retir= ement. This event also counts SW prefetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "This event counts store uops retired to the = architected path with a filter on bits 0 and 1 applied.\nNote: This event c= ounts AVX-256bit load/store double-pump memory uops as a single uop at reti= rement.", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the nearest-level (L1) cache.\nNote: Only two data-= sources of L1/FB are applicable for AVX-256bit even though the correspondi= ng AVX load could be serviced by a deeper level in the memory hierarchy. Da= ta source is reported for the Low-half load. This event also counts SW pref= etches independent of the actual data source.", "SampleAfterValue": "2000003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xD1", - "UMask": "0x1", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the nearest-level (L1) cache.\nNote: Only two data-= sources of L1/FB are applicable for AVX-256bit even though the correspondi= ng AVX load could be serviced by a deeper level in the memory hierarchy. Da= ta source is reported for the Low-half load. This event also counts SW pref= etches independent of the actual data source.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the nearest-level (L1) cache. Counting excludes u= nknown and UC data source.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xD1", - "UMask": "0x2", "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM35", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the mid-level (L2) cache.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which da= ta sources were data hits in the last-level (L3) cache without snoops requi= red.", + "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the mid-level (L2) cache. Counting excludes unkno= wn and UC data source.", "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xD1", - "UMask": "0x8", - "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the nearest-level (L1) cache. Counting excludes u= nknown and UC data source.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x10", - "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the mid-level (L2) cache. Counting excludes unkno= wn and UC data source.", + "PublicDescription": "This event counts retired load uops which da= ta sources were data hits in the last-level (L3) cache without snoops requi= red.", "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xD1", - "UMask": "0x20", "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM100, BDE70", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "PublicDescription": "This event counts retired load uops which da= ta sources were load uops missed L1 but hit a fill buffer due to a precedin= g miss to the same cache line with the data not ready.\nNote: Only two data= -sources of L1/FB are applicable for AVX-256bit even though the correspond= ing AVX load could be serviced by a deeper level in the memory hierarchy. D= ata source is reported for the Low-half load.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts load uops retired to the a= rchitected path with a filter on bits 0 and 1 applied.\nNote: This event co= unts AVX-256bit load/store double-pump memory uops as a single uop at retir= ement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which da= ta sources were L3 Hit and a cross-core snoop missed in the on-pkg core cac= he.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts store uops retired to the = architected path with a filter on bits 0 and 1 applied.\nNote: This event c= ounts AVX-256bit load/store double-pump memory uops as a single uop at reti= rement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which da= ta sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.= ", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts load uops with locked acce= ss retired to the architected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which da= ta sources were HitM responses from a core on same socket (shared L3).", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the last-level (L3) cache without snoops required.", + "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "EventCode": "0xD3", - "UMask": "0x1", - "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "BDE70, BDM100", - "PublicDescription": "Retired load uop whose Data Source was: loca= l DRAM either Snoop not needed or Snoop Miss (RspI).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts load uops with true STLB m= iss retired to the architected path. True STLB miss is an uop triggering pa= ge walk that gets completed without blocks, and later gets retired. This pa= ge walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", + "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "This event counts store uops with true STLB = miss retired to the architected path. True STLB miss is an uop triggering p= age walk that gets completed without blocks, and later gets retired. This p= age walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Any memory transaction that reached the SQ.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reache= d the super queue including requests initiated by the core, all L3 prefetch= es, page walks, and so on.", + "SampleAfterValue": "100003", + "UMask": "0x80" }, { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xF0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", + "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding cacheable Core Data Read transactions in the super queue every cycl= e. A transaction is considered to be in the Offcore outstanding state betwe= en L2 miss and transaction completion sent to requestor (SQ de-allocation).= See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outsta= nding cacheable Core Data Read transactions are present in the super queue.= A transaction is considered to be in the Offcore outstanding state between= L2 miss and transaction completion sent to requestor (SQ de-allocation). S= ee corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "PublicDescription": "This event counts cycles when offcore outsta= nding Demand Data Read transactions are present in the super queue (SQ). A = transaction is considered to be in the Offcore outstanding state between L2= miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outs= tanding demand rfo Reads transactions in the super queue every cycle. The O= ffcore outstanding state of the transaction lasts from the L2 miss until th= e sending transaction completion to requestor (SQ deallocation). See the co= rresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding Code Reads transactions in the super queue every cycle. The Offcore= outstanding state of the transaction lasts from the L2 miss until the send= ing transaction completion to requestor (SQ deallocation). See the correspo= nding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outs= tanding Demand Data Read transactions in the super queue (SQ) every cycle. = A transaction is considered to be in the Offcore outstanding state between = L2 miss and transaction completion sent to requestor. See the corresponding= Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is coun= ted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outs= tanding RFO (store) transactions in the super queue (SQ) every cycle. A tra= nsaction is considered to be in the Offcore outstanding state between L2 mi= ss and transaction completion sent to requestor (SQ de-allocation). See cor= responding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF1", - "UMask": "0x7", - "BriefDescription": "L2 cache lines filling L2", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.ALL", - "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF2", - "UMask": "0x5", - "BriefDescription": "Clean L2 cache lines evicted by demand.", + "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "Counter": "0,1,2,3", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xf4", - "UMask": "0x10", - "BriefDescription": "Split locks in SQ", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", "Counter": "0,1,2,3", - "EventName": "SQ_MISC.SPLIT_LOCK", - "PublicDescription": "This event counts the number of split locks = in the super queue.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests hit in the L3", - "MSRValue": "0x3F803C8FFF", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests hit in the L3", + "MSRValue": "0x04003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded", - "MSRValue": "0x10003C07F7", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C07F7", + "Offcore": "1", "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) hit in the L3 and the snoop to one of the sibling cores hits the lin= e in M state and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoops to sibling cores hit in either E/S state= and the line is not forwarded", - "MSRValue": "0x04003C07F7", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C07F7", + "Offcore": "1", "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) hit in the L3 and the snoops to sibling cores hit in either E/S stat= e and the line is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", - "MSRValue": "0x04003C0244", + "BriefDescription": "Counts all requests hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", + "MSRValue": "0x3F803C8FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", - "MSRValue": "0x10003C0122", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", + "Offcore": "1", "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoop to one of the sibling cores hits the line in M state and = the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", - "MSRValue": "0x04003C0122", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0122", + "Offcore": "1", "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", - "MSRValue": "0x10003C0091", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", - "MSRValue": "0x04003C0091", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", - "MSRValue": "0x3F803C0200", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0200", + "Offcore": "1", "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", - "MSRValue": "0x3F803C0100", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { + "MSRValue": "0x3F803C0100", "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", - "MSRValue": "0x10003C0002", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3", - "MSRValue": "0x3F803C0002", + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "This event counts the number of split locks = in the super queue.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json = b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json index ba0e0c4e74eb..9ad37dddb354 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json @@ -1,165 +1,193 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions = from AVX-256 to legacy SSE when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions = from legacy SSE to AVX-256 when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC7", - "UMask": "0x1", - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar double precision floating-point = instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB inst= ructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", - "UMask": "0x2", - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar single precision floating-point = instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)AD= D/SUB instructions count twice as they perform multiple calculations per el= ement.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", - "UMask": "0x3", - "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired. Applies to SSE* and AVX* scalar, double and = single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(= N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element. (RSQRT for single precision?)", + "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed double precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", - "UMask": "0x4", - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired. Each count represe= nts 2 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM= (N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform = multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* packed double and single precision floating= -point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RC= P DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "UMask": "0x3c" }, { - "EventCode": "0xC7", - "UMask": "0x8", - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xC7", - "UMask": "0x10", - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM= (N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform = multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xC7", - "UMask": "0x15", - "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP = FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perfor= m multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xc7", - "UMask": "0x20", - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired. Each count represe= nts 8 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC7", - "UMask": "0x2a", - "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT= SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as t= hey perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed single precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2a" }, { - "EventCode": "0xC7", - "UMask": "0x3c", - "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired. Applies to SSE* and AVX*, packed, double and= single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX = SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as th= ey perform multiple calculations per element. (RSQRT for single-precision?)= ", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.PACKED", - "SampleAfterValue": "2000004", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and = output SSE or x87 FP assist. If an input and output assist are detected on = the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { + "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCA", - "UMask": "0x4", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "This event counts x87 floating point (FP) mi= cro-code assist (invalid operation, denormal operand, SNaN operand) when th= e input value (one of the source operands to an FP instruction) is invalid.= ", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCA", - "UMask": "0x10", - "BriefDescription": "Number of SIMD FP assists due to input values= ", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_INPUT", - "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions = from AVX-256 to legacy SSE when penalty is applicable.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "This event counts cycles with any input and = output SSE or x87 FP assist. If an input and output assist are detected on = the same cycle the event increments by 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions = from legacy SSE to AVX-256 when penalty is applicable.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tool= s/perf/pmu-events/arch/x86/broadwellx/frontend.json index 72781e1e3362..f0bcb945ff76 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -1,286 +1,295 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops i= nitiated by Decode Stream Buffer (DSB) are being delivered to Instruction D= ecode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting incl= udes uops that may bypass the IDQ.", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the Decode Stream B= uffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", - "CounterMask": "1", - "PublicDescription": "This event counts the number of deliveries t= o Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) wh= ile the Microcode Sequencer (MS) is busy. Counting includes uops that may b= ypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the MITE path. Count= ing includes uops that may bypass the IDQ. This also means that uops are no= t being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the Decode Stream B= uffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the Decode Stream= Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uo= ps were delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops= were delivered to Instruction Decode Queue (IDQ) from the MITE path. Count= ing includes uops that may bypass the IDQ. This also means that uops are no= t being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) from the MITE path. Co= unting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops i= nitiated by Decode Stream Buffer (DSB) are being delivered to Instruction D= ecode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting incl= udes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries t= o Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) wh= ile the Microcode Sequencer (MS) is busy. Counting includes uops that may b= ypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x80", - "UMask": "0x1", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.HIT", - "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x80", - "UMask": "0x2", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "EventName": "ICACHE.MISSES", - "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", - "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding 4 x when Resou= rce Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ= ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0= ,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation = Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (R= AT) is stalled for the thread (including uop drops and clear BE conditions)= ; \n c. Instruction Decode Queue (IDQ) delivers four uops.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "PublicDescription": "This event counts, on the per-thread basis, = cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_U= ops_Not_Delivered.core =3D4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x9C", - "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "PublicDescription": "This event counts, on the per-thread basis, = cycles when less than 1 uop is delivered to Resource Allocation Table (RAT= ). IDQ_Uops_Not_Delivered.core >=3D3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xAB", - "UMask": "0x2", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "Counter": "0,1,2,3", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/= perf/pmu-events/arch/x86/broadwellx/memory.json index ecb413bb67ca..cce993b197e3 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json @@ -1,679 +1,687 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a TSX line had a cache confli= ct", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache confl= ict.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock B= uffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times HLE commit succeeded", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x4", "BriefDescription": "Number of times HLE abort was triggered", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x8", "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x10", "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x20", "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x40", "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc8", - "UMask": "0x80", "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc9", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x2", - "BriefDescription": "Number of times RTM commit succeeded", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x4", - "BriefDescription": "Number of times RTM abort was triggered", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED", - "PublicDescription": "Number of times RTM abort was triggered .", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x8", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x10", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xc9", - "UMask": "0x20", - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x40", - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "PublicDescription": "Number of times a RTM caused a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x80", - "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 4", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above four.", - "TakenAlone": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", "SampleAfterValue": "100003", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 8", - "PEBS": "2", - "MSRValue": "0x8", + "BriefDescription": "Randomly selected loads with latency value be= ing above 128", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above eight.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 128.", + "SampleAfterValue": "1009", "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", "BriefDescription": "Randomly selected loads with latency value be= ing above 16", - "PEBS": "2", - "MSRValue": "0x10", "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", + "MSRValue": "0x10", + "PEBS": "2", "PublicDescription": "Counts randomly selected loads with latency = value being above 16.", - "TakenAlone": "1", "SampleAfterValue": "20011", - "CounterHTOff": "3" + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 32", - "PEBS": "2", - "MSRValue": "0x20", + "BriefDescription": "Randomly selected loads with latency value be= ing above 256", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above 32.", - "TakenAlone": "1", - "SampleAfterValue": "100007", - "CounterHTOff": "3" + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 256.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 64", - "PEBS": "2", - "MSRValue": "0x40", + "BriefDescription": "Randomly selected loads with latency value be= ing above 32", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above 64.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 32.", + "SampleAfterValue": "100007", "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 128", - "PEBS": "2", - "MSRValue": "0x80", + "BriefDescription": "Randomly selected loads with latency value be= ing above 4", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above 128.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above four.", + "SampleAfterValue": "100003", "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 256", - "PEBS": "2", - "MSRValue": "0x100", + "BriefDescription": "Randomly selected loads with latency value be= ing above 512", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above 256.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value be= ing above 512", - "PEBS": "2", - "MSRValue": "0x200", + "BriefDescription": "Randomly selected loads with latency value be= ing above 64", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value be= ing above 8", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency = value being above 512.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency = value being above eight.", + "SampleAfterValue": "50021", "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests miss in the L3", - "MSRValue": "0x3FBFC08FFF", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests miss in the L3", + "MSRValue": "0x3FBFC00244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and clean or shared data is transferred from remote cache= ", - "MSRValue": "0x087FC007F7", + "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and clean or shared data is transferred from remote cach= e", + "MSRValue": "0x0604000244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC007F7", + "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x3FBFC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063BC007F7", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from remote dram", + "MSRValue": "0x0604000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from local dram", - "MSRValue": "0x06040007F7", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from remote dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from local dram", + "MSRValue": "0x063BC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from remote dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00091", "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x087FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and clean or shared data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss in the L3", - "MSRValue": "0x3FBFC007F7", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC007F7", + "Offcore": "1", "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", - "MSRValue": "0x0604000244", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch)miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", + "MSRValue": "0x06040007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch)miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", - "MSRValue": "0x3FBFC00244", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from remote dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", + "MSRValue": "0x063BC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the data is returned from remote dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", - "MSRValue": "0x0604000122", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the modified data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", + "MSRValue": "0x103FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and the modified data is transferred from remote cache", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", - "MSRValue": "0x3FBFC00122", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and clean or shared data is transferred from remote cache= ", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", + "MSRValue": "0x087FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & pre= fetch) miss the L3 and clean or shared data is transferred from remote cach= e", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x087FC00091", + "BriefDescription": "Counts all requests miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x3FBFC08FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00091", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x3FBFC00122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from remote dram", - "MSRValue": "0x063BC00091", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from remote dram", + "MSRValue": "0x0604000122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", - "MSRValue": "0x0604000091", + "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", + "MSRValue": "0x3FBFC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss in= the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", - "MSRValue": "0x3FBFC00091", + "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the modified data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", + "MSRValue": "0x103FC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the modified data is transferred from remote cache", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", - "MSRValue": "0x3FBFC00200", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00200", + "Offcore": "1", "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", - "MSRValue": "0x3FBFC00100", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00100", + "Offcore": "1", "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs miss in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00002", + "BriefDescription": "Number of times RTM abort was triggered", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", - "MSRValue": "0x3FBFC00002", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss in= the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a TSX line had a cache confli= ct", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache confl= ict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock B= uffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/p= erf/pmu-events/arch/x86/broadwellx/other.json index 4475249ea9da..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json @@ -1,44 +1,44 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "PublicDescription": "This event counts when there is a transition= from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tool= s/perf/pmu-events/arch/x86/broadwellx/pipeline.json index c2f6932a5817..18d21b94a4b9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -1,1423 +1,1380 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial comp= are", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "Cycles checkpoints in Resource Allocation Ta= ble (RAT) are recovering from JEClear or machine clear.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "BriefDescription": "Cycles when divider is busy executing divide = operations", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x0D", - "UMask": "0x8", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "BriefDescription": "Speculative and retired macro-conditional bra= nches", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which the Re= source Allocation Table (RAT) does not issue any Uops to the reservation st= ation (RS) for the current thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "EventCode": "0x14", - "UMask": "0x1", - "BriefDescription": "Cycles when divider is busy executing divide = operations", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "BriefDescription": "Taken speculative and retired macro-condition= al branches", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired direct near cal= ls", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instruc= tions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x4C", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions re= tired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect n= ear call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect m= acro near call instructions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This event counts return instructions retire= d.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This event counts taken branch instructions = retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructi= ons retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near cal= ls", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional b= ranch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branc= hes.", + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted return instru= ctions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "UMask": "0xff", - "BriefDescription": "Speculative and retired branches", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xA0", - "UMask": "0x3", - "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", - "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request (that is cycles with non-completed load w= aiting for its data from memory subsystem).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest missing the L1 data cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand* load re= quest missing the L2 cache.(as a footprint) * includes also L1 HW prefetch = requests that may or may not be required by demands.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions= (EOMs) retired. Counting covers macro-fused instructions individually (tha= t is, increments by two).", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts instructions retired.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Ta= ble (RAT) are recovering from JEClear or machine clear.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "BriefDescription": "False dependencies in MOB due to partial comp= are", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xa2", - "UMask": "0x1", - "BriefDescription": "Resource-related stall cycles", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cyc= les.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x4", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.RS", - "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x8", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", - "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand* load request missing the L2 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request (that is cycles with non-completed load w= aiting for its data from memory subsystem).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cyc= les.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "Total execution stalls.", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand* load re= quest missing the L2 cache.(as a footprint) * includes also L1 HW prefetch = requests that may or may not be required by demands.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "CounterMask": "5", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "CounterMask": "6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Counts number of cycles the CPU has at least= one pending demand load request missing the L1 data cache.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "CounterMask": "8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x2" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Counts number of cycles nothing is executed = on any execution port, while there was at least one pending demand load req= uest missing the L1 data cache.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "CounterMask": "12", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x8" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which no uop= s were dispatched from the Reservation Station (RS) per thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x2", - "BriefDescription": "Number of uops executed on the core.", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE", - "PublicDescription": "Number of uops executed from any thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uop= s were dispatched from the Reservation Station (RS) per thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "BDM61", - "PublicDescription": "This event counts the number of instructions= (EOMs) retired. Counting covers macro-fused instructions individually (tha= t is, increments by two).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "BDM11, BDM55", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", "SampleAfterValue": "2000003", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "This event counts all actually retired uops.= Counting increments by two for micro-fused uops, and by one for macro-fuse= d and other uops. Maximal increment value for one cycle is eight.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles without actually re= tired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", - "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This event counts the number of retirement s= lots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", - "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x0", - "BriefDescription": "All (macro) branch instructions retired.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PublicDescription": "This event counts conditional branch instruc= tions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions re= tired.", - "PEBS": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PublicDescription": "This event counts both direct and indirect n= ear call instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "PublicDescription": "This event counts both direct and indirect m= acro near call instructions retired (captured in ring 3).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x4", - "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", - "PEBS": "2", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "Errata": "BDW98", - "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PublicDescription": "This event counts return instructions retire= d.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC4", - "UMask": "0x10", - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "This event counts not taken branch instructi= ons retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired.", - "PEBS": "1", + "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "This event counts taken branch instructions = retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x40", - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "Errata": "BDW98", - "PublicDescription": "This event counts far branch instructions re= tired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC5", - "UMask": "0x0", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "PEBS": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PublicDescription": "This event counts mispredicted conditional b= ranch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Re= source Allocation Table (RAT) does not issue any Uops to the reservation st= ation (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x4", - "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", - "PEBS": "2", + "BriefDescription": "Actually retired uops.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC5", - "UMask": "0x8", - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This event counts mispredicted return instru= ctions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "PublicDescription": "This event counts all actually retired uops.= Counting increments by two for micro-fused uops, and by one for macro-fuse= d and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x20", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", - "PEBS": "1", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement s= lots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCC", - "UMask": "0x20", - "BriefDescription": "Count cases of saving new LBR", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually re= tired uops.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json index 7d79c707c6d1..818a8b132c08 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts load misses in all DTLB le= vels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (4K page size). The page walk can end= with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (2M and 4M page sizes). The page walk= can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (1G page size). The page walk can en= d with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x08", - "UMask": "0xe", "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (1G page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (2M and 4M page sizes). The page walk= can end with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB le= vels that cause a completed page walk (4K page size). The page walk can end= with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x08", - "UMask": "0x60", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x1", "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x49", - "UMask": "0xe", "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x49", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x49", - "UMask": "0x60", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x4F", - "UMask": "0x10", "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x1", "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts store misses in all DTLB l= evels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x85", - "UMask": "0xe", "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x85", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (1G page size). The page walk can e= nd with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (2M and 4M page sizes). The page wal= k can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB l= evels that cause a completed page walk (4K page size). The page walk can en= d with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xAE", - "UMask": "0x1", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "ITLB.ITLB_FLUSH", - "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while= PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", - "UMask": "0x21", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", - "UMask": "0x22", "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", - "UMask": "0x24", "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B878C433FE for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=H70K4kIW2kMmz+S6yPyBXFiclZwUN5AbFQ2Ah8qRrNA=; b=QdYgOd5yN9nYYNGVESyf+hKROPMrXfKldtePSRD+4q1C+Ew3+olOhHEHmX1OVd0HQK MF5YBw1DSY1tPwuimRfu8B+mLd4sK+DmPIXUpvJ8xNToyl5UP12BTl1MVXhgelaeo77h MQFxG2e0d6DAEDcjqOoGXNvqWy7V6AxmA5MqatRh+TTSr861NtC1maeY+caHRUDtECNL Y9LvqhtkCcDuNQwNQhnzvGFu3vWUV4mOA/1EE4RKdN0jE0P75rhppZDX78CXlqZOblTO YDEW760qWD/2UnjomZHZT9g7OEtz77iX3ioh1nOkw23TZFT/K/fD3aUzvVov+dPkr/VS hj4A== X-Gm-Message-State: AOAM530gnEtJvaJpBg++eWCgtCWjxsJUgASSu8NNNcwv64cNLJN380Gq dVp8VO/ZuyBb6vOuzdO3afgRt5OYvGpx X-Google-Smtp-Source: ABdhPJz/3AALBjw1hK+phkOU4wwJAo5z77sAhc11mB5WUdHdsFDrsuAi4aChBfZ13V7AR7llVxd4phIvxpiY X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:55d5:: with SMTP id j204mr32085054ybb.264.1643680779394; Mon, 31 Jan 2022 17:59:39 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:44 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-13-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 12/26] perf vendor events: Update for Goldmont From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Events are still at version 13: https://download.01.org/perfmon/GLM Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf The addition of a floating-point.json is due to events having their topic better identified by the converter script. Tested: Not tested on a Goldmont, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/goldmont/cache.json | 1466 ++++++++--------- .../arch/x86/goldmont/floating-point.json | 33 + .../arch/x86/goldmont/frontend.json | 78 +- .../pmu-events/arch/x86/goldmont/memory.json | 38 +- .../pmu-events/arch/x86/goldmont/other.json | 92 +- .../arch/x86/goldmont/pipeline.json | 538 +++--- .../arch/x86/goldmont/virtual-memory.json | 94 +- 7 files changed, 1164 insertions(+), 1175 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/goldmont/floating-point.= json diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/per= f/pmu-events/arch/x86/goldmont/cache.json index 52a105666afc..0b887d73b7f3 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json @@ -1,1305 +1,1303 @@ [ { + "BriefDescription": "Requests rejected by the L2Q", "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", - "EventCode": "0x2E", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ALL", + "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to ensure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L1 Cache evictions for dirty data", "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", - "EventCode": "0x2E", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "EventCode": "0x51", + "EventName": "DL1.DIRTY_EVICTION", + "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", - "EventCode": "0x30", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "L2_REJECT_XQ.ALL", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the XQ" + "UMask": "0x2" }, { + "BriefDescription": "Requests rejected by the XQ", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to ensure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", - "EventCode": "0x31", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CORE_REJECT_L2Q.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the L2Q" + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L2 cache request misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", - "EventCode": "0x51", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DL1.DIRTY_EVICTION", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "L1 Cache evictions for dirty data" + "UMask": "0x41" }, { + "BriefDescription": "L2 cache requests", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss." - }, - { - "CollectPEBSRecord": "1", - "EventCode": "0xB7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100007", - "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)" + "UMask": "0x4f" }, { - "PEBS": "2", + "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts locked memory uops retired. This inc= ludes regular locks and bus locks. (To specifically count bus locks only, s= ee the Offcore response event.) A locked access is one with a lock prefix,= or an exchange to memory. See the SDM for a complete description of which= memory load accesses are locks.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "2", + "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from DRAM. Event is counted at retirement, so the speculat= ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (= or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.= ", "SampleAfterValue": "200003", - "BriefDescription": "Locked load uops retired (Precise event capab= le)", - "Data_LA": "1" + "UMask": "0x80" }, { - "PEBS": "2", + "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the data requ= ested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "2", + "PublicDescription": "Counts load uops retired where the cache lin= e containing the data was in the modified state of another core or modules = cache (HITM). More specifically, this means that when the load address was= checked by other caching agents (typically another processor) in the syste= m, one of those caching agents indicated that they had a dirty copy of the = data. Loads that obtain a HITM response incur greater latency than most is= typical for a load. In addition, since HITM indicates that some other pro= cessor had this data in its cache, it implies that the data was shared betw= een processors, or potentially was a lock or semaphore value. This event i= s useful for locating sharing, false sharing, and contended locks.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", - "Data_LA": "1" + "UMask": "0x20" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired where the data req= uested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that hit the L1 dat= a cache.", "SampleAfterValue": "200003", - "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory uops retired where the data re= quested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x43", - "EventName": "MEM_UOPS_RETIRED.SPLIT", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that miss the L1 da= ta cache.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x8" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that hit in the L2 = cache.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that miss in the L2= cache.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x10" }, { - "PEBS": "2", + "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of memory uops retired tha= t is either a loads or a store or both.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x83", - "EventName": "MEM_UOPS_RETIRED.ALL", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PEBS": "2", + "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from the WCB (or fill buffer), indicating that the load fou= nd its data while that data was in the process of being brought into the L1= cache. Typically a load will receive this indication when some other load= or prefetch missed the L1 cache and was in the process of retrieving the c= ache line containing the data, but that process had not yet finished (and w= ritten the data back to the cache). For example, consider load X and Y, bot= h referencing the same cache line that is not in the L1 cache. If load X m= isses cache first, it obtains and WCB (or fill buffer) and begins the proce= ss of requesting the data. When load Y requests the data, it will either h= it the WCB, or the L1 cache, depending on exactly what time the request to = Y occurs.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x40" }, { - "PEBS": "2", + "BriefDescription": "Memory uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit the L1 dat= a cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "2", + "PublicDescription": "Counts the number of memory uops retired tha= t is either a loads or a store or both.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", - "Data_LA": "1" + "UMask": "0x83" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit in the L2 = cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "2", + "PublicDescription": "Counts the number of load uops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", - "Data_LA": "1" + "UMask": "0x81" }, { - "PEBS": "2", + "BriefDescription": "Store uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss the L1 da= ta cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "2", + "PublicDescription": "Counts the number of store uops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x82" }, { - "PEBS": "2", + "BriefDescription": "Locked load uops retired (Precise event capab= le)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss in the L2= cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "2", + "PublicDescription": "Counts locked memory uops retired. This inc= ludes regular locks and bus locks. (To specifically count bus locks only, s= ee the Offcore response event.) A locked access is one with a lock prefix,= or an exchange to memory. See the SDM for a complete description of which= memory load accesses are locks.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", - "Data_LA": "1" + "UMask": "0x21" }, { - "PEBS": "2", + "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the cache lin= e containing the data was in the modified state of another core or modules = cache (HITM). More specifically, this means that when the load address was= checked by other caching agents (typically another processor) in the syste= m, one of those caching agents indicated that they had a dirty copy of the = data. Loads that obtain a HITM response incur greater latency than most is= typical for a load. In addition, since HITM indicates that some other pro= cessor had this data in its cache, it implies that the data was shared betw= een processors, or potentially was a lock or semaphore value. This event i= s useful for locating sharing, false sharing, and contended locks.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "2", + "PublicDescription": "Counts memory uops retired where the data re= quested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", - "Data_LA": "1" + "UMask": "0x43" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from the WCB (or fill buffer), indicating that the load fou= nd its data while that data was in the process of being brought into the L1= cache. Typically a load will receive this indication when some other load= or prefetch missed the L1 cache and was in the process of retrieving the c= ache line containing the data, but that process had not yet finished (and w= ritten the data back to the cache). For example, consider load X and Y, bot= h referencing the same cache line that is not in the L1 cache. If load X m= isses cache first, it obtains and WCB (or fill buffer) and begins the proce= ss of requesting the data. When load Y requests the data, it will either h= it the WCB, or the L1 cache, depending on exactly what time the request to = Y occurs.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired where the data requ= ested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", - "Data_LA": "1" + "UMask": "0x41" }, { - "PEBS": "2", + "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from DRAM. Event is counted at retirement, so the speculat= ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (= or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.= ", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "2", + "PublicDescription": "Counts store uops retired where the data req= uested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", - "Data_LA": "1" + "UMask": "0x42" }, { + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires= MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated fo= r both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x36000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that hi= t the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that miss the L2 cache with a sn= oop hit in the other processor module, data forwarding is required. Require= s MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated f= or both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x10000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000043091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that h= it the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and= response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache with a sno= op hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that miss the L2 cache with a sn= oop hit in the other processor module, no data forwarding is required. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x04000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_= FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that m= iss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache with a sno= op hit in the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache with a snoop hit in the other processor module, data forwar= ding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that true miss for the L2 cache = with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x02000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that m= iss the L2 cache with a snoop hit in the other processor module, data forwa= rding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type a= nd response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that true miss for the L2 cache w= ith a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache with a snoop hit in the other processor module, no data for= warding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000432b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that m= iss the L2 cache with a snoop hit in the other processor module, no data fo= rwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request typ= e and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that tr= ue miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to= specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that t= rue miss for the L2 cache with a snoop miss in the other processor module. = Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that miss the L2 cache with a snoop hit in the other proc= essor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000043010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that miss the L2 cache with a snoop hit in the other proc= essor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", + "Counter": "0,1,2,3", "EventCode": "0xB7", - "MSRValue": "0x0400000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_F= WD", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache with a snoop hit in the other proce= ssor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache with a snoop hit in the other processor modul= e, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that true miss for the L2 cache with a snoop miss in the = other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that true miss for the L2 cache with a snoop miss in the o= ther processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to = specify request type and response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x0000040022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that miss the L2 cache with a snoop hit in the other processor modu= le, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache with a snoop hit in the other processor modul= e, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that m= iss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that m= iss the L2 cache with a snoop hit in the other processor module, data forwa= rding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type a= nd response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x1000003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that miss the L2 cache with a snoop hit in the other processor modu= le, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache with a snoop hit in the other processor module, data forwar= ding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that true miss for the L2 cache with a snoop miss in the other proce= ssor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that m= iss the L2 cache with a snoop hit in the other processor module, no data fo= rwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request typ= e and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that true miss for the L2 cache with a snoop miss in the other proc= essor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache with a snoop hit in the other processor module, no data for= warding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that t= rue miss for the L2 cache with a snoop miss in the other processor module. = Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00000432b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that tr= ue miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that h= it the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and= response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043091", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x36000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires= MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated fo= r both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that hi= t the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache with a sno= op hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that miss the L2 cache with a sn= oop hit in the other processor module, data forwarding is required. Require= s MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated f= or both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache with a sno= op hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that miss the L2 cache with a snoop hit in the other processor modu= le, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that miss the L2 cache with a sn= oop hit in the other processor module, no data forwarding is required. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache with a snoop hit in the other processor modul= e, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that true miss for the L2 cache w= ith a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that miss the L2 cache with a snoop hit in the other processor modu= le, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) that true miss for the L2 cache = with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache with a snoop hit in the other processor modul= e, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that = have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that true miss for the L2 cache with a snoop miss in the other proc= essor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that= have any transaction responses from the uncore subsystem. Requires MSR_OFF= CORE_RESP[0,1] to specify request type and response. (duplicated for both M= SRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that true miss for the L2 cache with a snoop miss in the other proce= ssor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that = hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000048000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that= hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type a= nd response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that = miss the L2 cache with a snoop hit in the other processor module, data forw= arding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that= miss the L2 cache with a snoop hit in the other processor module, data for= warding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type= and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000008000", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000008000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that= miss the L2 cache with a snoop hit in the other processor module, data for= warding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type= and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that = miss the L2 cache with a snoop hit in the other processor module, data forw= arding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that = miss the L2 cache with a snoop hit in the other processor module, no data f= orwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that= miss the L2 cache with a snoop hit in the other processor module, no data = forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request t= ype and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400008000", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400008000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that= miss the L2 cache with a snoop hit in the other processor module, no data = forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request t= ype and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that = miss the L2 cache with a snoop hit in the other processor module, no data f= orwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that = true miss for the L2 cache with a snoop miss in the other processor module.= ", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that= true miss for the L2 cache with a snoop miss in the other processor module= . Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (du= plicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200008000", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200008000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that= true miss for the L2 cache with a snoop miss in the other processor module= . Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (du= plicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that = true miss for the L2 cache with a snoop miss in the other processor module.= ", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that= hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type a= nd response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000048000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to = specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that = hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that= have any transaction responses from the uncore subsystem. Requires MSR_OFF= CORE_RESP[0,1] to specify request type and response. (duplicated for both M= SRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000018000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to= specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that = have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCOR= E_RESP[0,1] to specify request type and response. (duplicated for both MSRs= )", - "EventCode": "0xB7", - "MSRValue": "0x3600004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that miss the L2 cache with a snoop hit in the other proc= essor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache with a snoop hit in the other proce= ssor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x0000044800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that miss the L2 cache with a snoop hit in the other proc= essor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that true miss for the L2 cache with a snoop miss in the o= ther processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that miss the L2 cache. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.AN= Y", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) that true miss for the L2 cache with a snoop miss in the = other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests that = have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required. Req= uires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicat= ed for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HI= TM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", + "PublicDescription": "Counts bus lock and split lock requests that= have any transaction responses from the uncore subsystem. Requires MSR_OFF= CORE_RESP[0,1] to specify request type and response. (duplicated for both M= SRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache with a= snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that miss the L2 cache with = a snoop hit in the other processor module, no data forwarding is required. = Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupli= cated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HI= T_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", + "MSRIndex": "0x1a6", + "MSRValue": "0x0000040008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFC= ORE_RESP[0,1] to specify request type and response. (duplicated for both MS= Rs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache with a= snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that true miss for the L2 ca= che with a snoop miss in the other processor module. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SN= OOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", + "MSRIndex": "0x1a6", + "MSRValue": "0x3600000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFF= CORE_RESP[0,1] to specify request type and response. (duplicated for both M= SRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that true miss for the L2 cac= he with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit i= n the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that hit the L2 cache. Requi= res MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated= for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000044000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6", + "MSRValue": "0x1000000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit = in the other processor module, data forwarding is required. Requires MSR_OF= FCORE_RESP[0,1] to specify request type and response. (duplicated for both = MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit i= n the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCOR= E_RESP[0,1] to specify request type and response. (duplicated for both MSRs= )", - "EventCode": "0xB7", - "MSRValue": "0x3600002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FW= D", + "MSRIndex": "0x1a6", + "MSRValue": "0x0400000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit = in the other processor module, no data forwarding is required. Requires MSR= _OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bo= th MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that true miss for the L2 cache with a sn= oop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that miss the L2 cache with a snoop hit in = the other processor module, data forwarding is required. Requires MSR_OFFCO= RE_RESP[0,1] to specify request type and response. (duplicated for both MSR= s)", - "EventCode": "0xB7", - "MSRValue": "0x1000002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", + "MSRIndex": "0x1a6", + "MSRValue": "0x0200000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that true miss for the L2 cache with a s= noop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to= specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache with a snoop hit in t= he other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that miss the L2 cache with a snoop hit in = the other processor module, no data forwarding is required. Requires MSR_OF= FCORE_RESP[0,1] to specify request type and response. (duplicated for both = MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that hit the L2 cache.= Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache with a snoop hit in t= he other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that miss the L2 cache.= ", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that true miss for the L2 cache with a snoo= p miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to sp= ecify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that miss the L2 cache= . Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dup= licated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that true miss for the L2 cache with a snoop= miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that miss the L2 cache = with a snoop hit in the other processor module, no data forwarding is requi= red.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x0000042000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that miss the L2 cache= with a snoop hit in the other processor module, no data forwarding is requ= ired. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that true miss for the = L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,= 1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that true miss for the= L2 cache with a snoop miss in the other processor module. Requires MSR_OF= FCORE_RESP[0,1] to specify request type and response. (duplicated for both = MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that are outstanding, p= er cycle, from the time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that miss the L2 cache with a snoop hit in the other= processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0= ,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that are outstanding, = per cycle, from the time of the L2 miss to when any response is received. R= equires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplic= ated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache with a snoop hit in the other = processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that miss the L2 cache with a snoop hit in the other= processor module, no data forwarding is required. Requires MSR_OFFCORE_RES= P[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_= NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache with a snoop hit in the other = processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that true miss for the L2 cache with a snoop miss in= the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specif= y request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that true miss for the L2 cache with a snoop miss in = the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache with a snoop hit in the other processor mo= dule, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000041000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that miss the L2 cache with a snoop hit in the other processor m= odule, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache with a snoop hit in the other processor mo= dule, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that miss the L2 cache with a snoop hit in the other processor m= odule, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to sp= ecify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that true miss for the L2 cache with a snoop miss in the other pr= ocessor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that miss the L2 cache with a snoop hit in the other processor modu= le, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that true miss for the L2 cache with a snoop miss in the other p= rocessor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache with a snoop hit in the other processor modul= e, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that are outstanding, per cycle, from the time of the L2 miss to = when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that miss the L2 cache with a snoop hit in the other processor modu= le, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_O= THER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that are outstanding, per cycle, from the time of the L2 miss to= when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache with a snoop hit in the other processor modul= e, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that true miss for the L2 cache with a snoop miss in the other proc= essor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that hit the L2 cache. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that true miss for the L2 cache with a snoop miss in the other proce= ssor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that miss the L2 cache. R= equires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplic= ated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache wit= h a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests that= have any transaction responses from the uncore subsystem. Requires MSR_OFF= CORE_RESP[0,1] to specify request type and response. (duplicated for both M= SRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010400", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that miss the L2 cache wi= th a snoop hit in the other processor module, data forwarding is required. = Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupli= cated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests that = have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache wit= h a snoop hit in the other processor module, no data forwarding is required= .", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand write requests (= RFO) generated by a write to partial data cache line, including the writes = to uncacheable (UC) and write through (WT), and write protected (WP) types = of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000100", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that miss the L2 cache wi= th a snoop hit in the other processor module, no data forwarding is require= d. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (du= plicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of demand write requests (R= FO) generated by a write to partial data cache line, including the writes t= o uncacheable (UC) and write through (WT), and write protected (WP) types o= f memory that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that true miss for the L2 = cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand data partial reads, including = data in uncacheable (UC) or uncacheable write combining (USWC) memory types= that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000080", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that true miss for the L2= cache with a snoop miss in the other processor module. Requires MSR_OFFCO= RE_RESP[0,1] to specify request type and response. (duplicated for both MSR= s)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand data partial reads, including d= ata in uncacheable (UC) or uncacheable write combining (USWC) memory types = that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that are outstanding, per = cycle, from the time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[= 0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that are outstanding, per= cycle, from the time of the L2 miss to when any response is received. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, data forwarding is required. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache with a snoop hit in the othe= r processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, no data forwarding is required. Requires MSR_OFFCORE_R= ESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO= _FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache with a snoop hit in the othe= r processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache with a snoop hit in the other processor modul= e, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that true miss for the L2 cache with a snoop miss = in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that miss the L2 cache with a snoop hit in the other processor modu= le, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that true miss for the L2 cache with a snoop miss i= n the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache with a snoop hit in the other processor modul= e, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0= ,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040020", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_O= THER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that miss the L2 cache with a snoop hit in the other processor modu= le, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that true miss for the L2 cache with a snoop miss in the other proce= ssor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes that true miss for the L2 cache with a snoop miss in the other proc= essor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand data partial reads, including d= ata in uncacheable (UC) or uncacheable write combining (USWC) memory types = that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required. Requires MSR_OFFCORE_RES= P[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000080", + "Offcore": "1", + "PublicDescription": "Counts demand data partial reads, including = data in uncacheable (UC) or uncacheable write combining (USWC) memory types= that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that miss the L2 cache with a snoop hit in the ot= her processor module, no data forwarding is required. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000044000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that hit the L2 cache. Requi= res MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated= for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that true miss for the L2 cache with a snoop miss= in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.AN= Y", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that miss the L2 cache. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that true miss for the L2 cache with a snoop miss = in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache with a= snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[= 0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HI= TM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required. Req= uires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicat= ed for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache with a= snoop hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFF= CORE_RESP[0,1] to specify request type and response. (duplicated for both M= SRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HI= T_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that miss the L2 cache with = a snoop hit in the other processor module, no data forwarding is required. = Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupli= cated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that true miss for the L2 cac= he with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit = in the other processor module, data forwarding is required. Requires MSR_OF= FCORE_RESP[0,1] to specify request type and response. (duplicated for both = MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SN= OOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to unc= acheable write combining (USWC) memory region that true miss for the L2 ca= che with a snoop miss in the other processor module. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit i= n the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of demand write requests (R= FO) generated by a write to partial data cache line, including the writes t= o uncacheable (UC) and write through (WT), and write protected (WP) types o= f memory that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit = in the other processor module, no data forwarding is required. Requires MSR= _OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bo= th MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FW= D", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000100", + "Offcore": "1", + "PublicDescription": "Counts the number of demand write requests (= RFO) generated by a write to partial data cache line, including the writes = to uncacheable (UC) and write through (WT), and write protected (WP) types = of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit i= n the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that true miss for the L2 cache with a s= noop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to= specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000042000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that true miss for the L2 cache with a sn= oop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFC= ORE_RESP[0,1] to specify request type and response. (duplicated for both MS= Rs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040008", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCOR= E_RESP[0,1] to specify request type and response. (duplicated for both MSRs= )", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache with a snoop hit in t= he other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that are outstanding, = per cycle, from the time of the L2 miss to when any response is received. R= equires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplic= ated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that miss the L2 cache with a snoop hit in = the other processor module, data forwarding is required. Requires MSR_OFFCO= RE_RESP[0,1] to specify request type and response. (duplicated for both MSR= s)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that are outstanding, p= er cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache with a snoop hit in t= he other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that miss the L2 cache= . Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dup= licated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that miss the L2 cache with a snoop hit in = the other processor module, no data forwarding is required. Requires MSR_OF= FCORE_RESP[0,1] to specify request type and response. (duplicated for both = MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that miss the L2 cache.= ", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that true miss for the L2 cache with a snoop= miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that miss the L2 cache= with a snoop hit in the other processor module, no data forwarding is requ= ired. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher that true miss for the L2 cache with a snoo= p miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to sp= ecify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that miss the L2 cache = with a snoop hit in the other processor module, no data forwarding is requi= red.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that true miss for the= L2 cache with a snoop miss in the other processor module. Requires MSR_OF= FCORE_RESP[0,1] to specify request type and response. (duplicated for both = MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[= 0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that true miss for the = L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache that hit the L2 cache.= Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that are outstanding, per= cycle, from the time of the L2 miss to when any response is received. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required. Requires MSR_OFFCORE_RES= P[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that are outstanding, per = cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that miss the L2 cache. R= equires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplic= ated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that miss the L2 cache with a snoop hit in the ot= her processor module, no data forwarding is required. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that true miss for the L2 cache with a snoop miss = in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that miss the L2 cache wi= th a snoop hit in the other processor module, data forwarding is required. = Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupli= cated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher that true miss for the L2 cache with a snoop miss= in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache wit= h a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that miss the L2 cache wi= th a snoop hit in the other processor module, no data forwarding is require= d. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (du= plicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_N= O_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0= ,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache wit= h a snoop hit in the other processor module, no data forwarding is required= .", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that true miss for the L2= cache with a snoop miss in the other processor module. Requires MSR_OFFCO= RE_RESP[0,1] to specify request type and response. (duplicated for both MSR= s)", - "EventCode": "0xB7", - "MSRValue": "0x0200000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[= 0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that true miss for the L2 = cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache with a snoop hit in the othe= r processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line that hit the L2 cache. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, data forwarding is required. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache with a snoop hit in the othe= r processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that are outstanding, per cycle, from the time of the L2 miss to= when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO= _FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, no data forwarding is required. Requires MSR_OFFCORE_R= ESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that are outstanding, per cycle, from the time of the L2 miss to = when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that true miss for the L2 cache with a snoop miss i= n the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specif= y request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher that true miss for the L2 cache with a snoop miss = in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify r= equest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that miss the L2 cache with a snoop hit in the other processor m= odule, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000044800", + "Offcore": "1", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache with a snoop hit in the other processor mo= dule, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that miss the L2 cache with a snoop hit in the other processor m= odule, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to sp= ecify request type and response. (duplicated for both MSRs)", + "Counter": "0,1,2,3", "EventCode": "0xB7", - "MSRValue": "0x0400000001", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600004800", + "Offcore": "1", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCOR= E_RESP[0,1] to specify request type and response. (duplicated for both MSRs= )", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that hit the L2 cache.", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000041000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache with a snoop hit in the other processor mo= dule, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that true miss for the L2 cache with a snoop miss in the other p= rocessor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", + "Counter": "0,1,2,3", "EventCode": "0xB7", - "MSRValue": "0x0200000001", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,= 1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache with a snoop hit in the other = processor module, data forwarding is required.", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that miss the L2 cache with a snoop hit in the other= processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0= ,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that true miss for the L2 cache with a snoop miss in the other pr= ocessor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache with a snoop hit in the other = processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", + "Counter": "0,1,2,3", "EventCode": "0xB7", - "MSRValue": "0x0000040001", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_= NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that miss the L2 cache with a snoop hit in the other= processor module, no data forwarding is required. Requires MSR_OFFCORE_RES= P[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that true miss for the L2 cache with a snoop miss in = the other processor module.", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions that true miss for the L2 cache with a snoop miss in= the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/= tools/perf/pmu-events/arch/x86/goldmont/floating-point.json new file mode 100644 index 000000000000..bb364a04a75f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json @@ -0,0 +1,33 @@ +[ + { + "BriefDescription": "Cycles the FP divide unit is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Machine clears due to FP assists", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Floating point divide uops retired. (Precise = Event Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "2", + "PublicDescription": "Counts the number of floating point divide u= ops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/= perf/pmu-events/arch/x86/goldmont/frontend.json index 9ba08518649e..120ff65897c0 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json @@ -1,52 +1,82 @@ [ { + "BriefDescription": "BACLEARs asserted for any branch type", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", + "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture" + "UMask": "0x1" }, { + "BriefDescription": "BACLEARs asserted for conditional branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture" + "UMask": "0x10" }, { + "BriefDescription": "BACLEARs asserted for return branch", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", + "PublicDescription": "Counts BACLEARS on return instructions.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xE9", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x3" }, { + "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", - "EventCode": "0xE7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MS_DECODED.MS_ENTRY", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", "SampleAfterValue": "200003", - "BriefDescription": "MS decode starts" + "UMask": "0x1" }, { + "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", - "EventCode": "0xE9", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "MS decode starts", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", + "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", "SampleAfterValue": "200003", - "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/pe= rf/pmu-events/arch/x86/goldmont/memory.json index 197dc76d49dd..6252503f68a1 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json @@ -1,34 +1,34 @@ [ { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory load of a uop spans a p= age boundary (a split) is retired.", - "EventCode": "0x13", + "BriefDescription": "Machine clears due to memory ordering issue", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved as another core is in the process= of modifying the data.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split a page (Precise event ca= pable)" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Load uops that split a page (Precise event ca= pable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory store of a uop spans a = page boundary (a split) is retired.", - "EventCode": "0x13", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "2", + "PublicDescription": "Counts when a memory load of a uop spans a p= age boundary (a split) is retired.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split a page (Precise event c= apable)" + "UMask": "0x2" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved as another core is in the process= of modifying the data.", - "EventCode": "0xC3", + "BriefDescription": "Store uops that split a page (Precise event c= apable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "2", + "PublicDescription": "Counts when a memory store of a uop spans a = page boundary (a split) is retired.", "SampleAfterValue": "200003", - "BriefDescription": "Machine clears due to memory ordering issue" + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/per= f/pmu-events/arch/x86/goldmont/other.json index 959cadd7cb0e..e4605e636447 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json @@ -1,82 +1,80 @@ [ { + "BriefDescription": "Cycles code-fetch stalled due to any reason.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ITLB miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ITLB miss." - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", - "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle" + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", - "EventCode": "0xCA", + "BriefDescription": "Cycles hardware interrupts are masked", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.MASKED", + "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend" + "UMask": "0x2" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", - "EventCode": "0xCA", + "BriefDescription": "Cycles pending interrupts are masked", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle to recover" + "UMask": "0x4" }, { + "BriefDescription": "Hardware interrupts received", "CollectPEBSRecord": "2", - "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", + "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", "SampleAfterValue": "203", - "BriefDescription": "Hardware interrupts received" + "UMask": "0x1" }, { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", - "EventCode": "0xCB", + "BriefDescription": "Unfilled issue slots per cycle", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HW_INTERRUPTS.MASKED", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Unfilled issue slots per cycle to recover", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles hardware interrupts are masked" + "UMask": "0x2" }, { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", - "EventCode": "0xCB", + "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles pending interrupts are masked" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/= perf/pmu-events/arch/x86/goldmont/pipeline.json index 6342368accf8..cb9155c3836d 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -1,452 +1,382 @@ [ { - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Fixed event)" + "BriefDescription": "Retired branch instructions (Precise event ca= pable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "2", + "PublicDescription": "Counts branch instructions retired for all b= ranch types. This is an architectural performance event.", + "SampleAfterValue": "200003" }, { - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)" + "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", + "PublicDescription": "Counts the number of taken branch instructio= ns retired.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)" + "BriefDescription": "Retired near call instructions (Precise event= capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "2", + "PublicDescription": "Counts near CALL branch instructions retired= .", + "SampleAfterValue": "200003", + "UMask": "0xf9" }, { - "PEBS": "2", + "BriefDescription": "Retired far branch instructions (Precise even= t capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store for= ward, but did not occur because the store data was not available at the rig= ht time. The forward might occur subsequently when the data is available.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "2", + "PublicDescription": "Counts far branch instructions retired. Thi= s includes far jump, far call and return, and Interrupt call and return.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)" + "UMask": "0xbf" }, { - "PEBS": "2", + "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store for= ward because of an address/size mismatch, only one of the loads blocked fro= m each store will be counted.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "2", + "PublicDescription": "Counts near indirect CALL branch instruction= s retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)" + "UMask": "0xfb" }, { - "PEBS": "2", + "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads that block because their addres= s modulo 4K matches a pending store.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "LD_BLOCKS.4K_ALIAS", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "2", + "PublicDescription": "Counts retired Jcc (Jump on Conditional Code= /Jump if Condition is Met) branch instructions retired, including both when= the branch was taken and when it was not taken.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)" + "UMask": "0x7e" }, { - "PEBS": "2", + "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads blocked because they are unable= to find their physical address in the micro TLB (UTLB).", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.UTLB_MISS", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "2", + "PublicDescription": "Counts near indirect call or near indirect j= mp branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)" + "UMask": "0xeb" }, { - "PEBS": "2", + "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts anytime a load that retires is blocke= d for any reason.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "LD_BLOCKS.ALL_BLOCK", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "2", + "PublicDescription": "Counts near relative CALL branch instruction= s retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked (Precise event capable)" + "UMask": "0xfd" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", - "EventCode": "0x0E", + "BriefDescription": "Retired near return instructions (Precise eve= nt capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "UOPS_ISSUED.ANY", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "2", + "PublicDescription": "Counts near return branch instructions retir= ed.", "SampleAfterValue": "200003", - "BriefDescription": "Uops issued to the back end per cycle" + "UMask": "0xf7" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", + "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "2", + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if= Condition is Met) branch instructions retired that were taken and does not= count when the Jcc branch instruction were not taken.", + "SampleAfterValue": "200003", + "UMask": "0xfe" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Reference cycles when core is not halted. T= his event uses a programmable general purpose performance counter.", - "EventCode": "0x3C", + "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "2", + "PublicDescription": "Counts mispredicted branch instructions reti= red including all branch types.", + "SampleAfterValue": "200003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", - "EventCode": "0x9C", + "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "UOPS_NOT_DELIVERED.ANY", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "2", + "PublicDescription": "Counts mispredicted near indirect CALL branc= h instructions retired, where the target address taken was not what the pro= cessor predicted.", "SampleAfterValue": "200003", - "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle" + "UMask": "0xfb" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", - "EventCode": "0xC0", + "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Precise event capable)" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "2", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired, includ= ing both when the branch was supposed to be taken and when it was not suppo= sed to be taken (but the processor predicted the opposite condition).", + "SampleAfterValue": "200003", + "UMask": "0x7e" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call. (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops which retired.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "UOPS_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops retired (Precise event capable)" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "2", + "PublicDescription": "Counts mispredicted branch instructions reti= red that were near indirect call or near indirect jmp, where the target add= ress taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xeb" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that are from the comple= x flows issued by the micro-sequencer (MS). Counts both the uops from a mi= cro-coded instruction, and the uops that might be generated from a micro-co= ded assist.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.MS", - "SampleAfterValue": "2000003", - "BriefDescription": "MS uops retired (Precise event capable)" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "2", + "PublicDescription": "Counts mispredicted near RET branch instruct= ions retired, where the return address taken was not what the processor pre= dicted.", + "SampleAfterValue": "200003", + "UMask": "0xf7" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of floating point divide u= ops retired.", - "EventCode": "0xC2", + "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_RETIRED.FPDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Floating point divide uops retired. (Precise = Event Capable)" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "2", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired that we= re supposed to be taken but the processor predicted that it would not be ta= ken.", + "SampleAfterValue": "200003", + "UMask": "0xfe" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of integer divide uops ret= ired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.IDIV", + "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", "SampleAfterValue": "2000003", - "BriefDescription": "Integer divide uops retired. (Precise Event C= apable)" + "UMask": "0x2" }, { + "BriefDescription": "Core cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears for any reason.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "MACHINE_CLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "All machine clears" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Reference cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel\u00ae architecture processors.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "200003", - "BriefDescription": "Self-Modifying Code detected" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", + "PublicDescription": "Reference cycles when core is not halted. T= his event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.FP_ASSIST", - "SampleAfterValue": "200003", - "BriefDescription": "Machine clears due to FP assists" + "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { + "BriefDescription": "Cycles a divider is busy", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MACHINE_CLEARS.DISAMBIGUATION", - "SampleAfterValue": "200003", - "BriefDescription": "Machine clears due to memory disambiguation" + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", + "PublicDescription": "Counts core cycles if either divide unit is = busy.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all b= ranch types. This is an architectural performance event.", - "EventCode": "0xC4", + "BriefDescription": "Cycles the integer divide unit is busy", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.IDIV", + "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", "SampleAfterValue": "200003", - "BriefDescription": "Retired branch instructions (Precise event ca= pable)" + "UMask": "0x1" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts retired Jcc (Jump on Conditional Code= /Jump if Condition is Met) branch instructions retired, including both when= the branch was taken and when it was not taken.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x7e", - "EventName": "BR_INST_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)" + "BriefDescription": "Instructions retired (Fixed event)", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Instructions retired (Precise event capable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of taken branch instructio= ns retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)" - }, - { + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts far branch instructions retired. Thi= s includes far jump, far call and return, and Interrupt call and return.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xbf", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "200003", - "BriefDescription": "Retired far branch instructions (Precise even= t capable)" + "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect call or near indirect j= mp branch instructions retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xeb", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near return branch instructions retir= ed.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf7", - "EventName": "BR_INST_RETIRED.RETURN", + "PublicDescription": "Counts loads that block because their addres= s modulo 4K matches a pending store.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near return instructions (Precise eve= nt capable)" + "UMask": "0x4" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near CALL branch instructions retired= .", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xf9", - "EventName": "BR_INST_RETIRED.CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near call instructions (Precise event= capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect CALL branch instruction= s retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfb", - "EventName": "BR_INST_RETIRED.IND_CALL", + "PublicDescription": "Counts anytime a load that retires is blocke= d for any reason.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)" + "UMask": "0x10" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near relative CALL branch instruction= s retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfd", - "EventName": "BR_INST_RETIRED.REL_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if= Condition is Met) branch instructions retired that were taken and does not= count when the Jcc branch instruction were not taken.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfe", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PublicDescription": "Counts a load blocked from using a store for= ward, but did not occur because the store data was not available at the rig= ht time. The forward might occur subsequently when the data is available.", "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)" + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red including all branch types.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired, includ= ing both when the branch was supposed to be taken and when it was not suppo= sed to be taken (but the processor predicted the opposite condition).", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x7e", - "EventName": "BR_MISP_RETIRED.JCC", + "PublicDescription": "Counts a load blocked from using a store for= ward because of an address/size mismatch, only one of the loads blocked fro= m each store will be counted.", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red that were near indirect call or near indirect jmp, where the target add= ress taken was not what the processor predicted.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0xeb", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call. (Precise event capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.UTLB_MISS", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near RET branch instruct= ions retired, where the return address taken was not what the processor pre= dicted.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xf7", - "EventName": "BR_MISP_RETIRED.RETURN", + "PublicDescription": "Counts loads blocked because they are unable= to find their physical address in the micro TLB (UTLB).", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)" + "UMask": "0x8" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near indirect CALL branc= h instructions retired, where the target address taken was not what the pro= cessor predicted.", - "EventCode": "0xC5", + "BriefDescription": "All machine clears", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xfb", - "EventName": "BR_MISP_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)" + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "PublicDescription": "Counts machine clears for any reason.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired that we= re supposed to be taken but the processor predicted that it would not be ta= ken.", - "EventCode": "0xC5", + "BriefDescription": "Machine clears due to memory disambiguation", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xfe", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)" + "UMask": "0x8" }, { + "BriefDescription": "Self-Modifying Code detected", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles if either divide unit is = busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CYCLES_DIV_BUSY.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a divider is busy" + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel architecture processors.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { + "BriefDescription": "Uops issued to the back end per cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLES_DIV_BUSY.IDIV", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the integer divide unit is busy" + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLES_DIV_BUSY.FPDIV", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the FP divide unit is busy" + "EventCode": "0x9C", + "EventName": "UOPS_NOT_DELIVERED.ANY", + "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", + "SampleAfterValue": "200003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", - "EventCode": "0xE6", + "BriefDescription": "Uops retired (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BACLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for any branch type" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", + "PEBS": "2", + "PublicDescription": "Counts uops which retired.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Integer divide uops retired. (Precise Event C= apable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on return instructions.", - "EventCode": "0xE6", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BACLEARS.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for return branch" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "2", + "PublicDescription": "Counts the number of integer divide uops ret= ired.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", - "EventCode": "0xE6", + "BriefDescription": "MS uops retired (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BACLEARS.COND", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for conditional branch" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PEBS": "2", + "PublicDescription": "Counts uops retired that are from the comple= x flows issued by the micro-sequencer (MS). Counts both the uops from a mi= cro-coded instruction, and the uops that might be generated from a micro-co= ded assist.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json index 343d66bbd777..d5e89c74a9be 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json @@ -1,78 +1,78 @@ [ { + "BriefDescription": "ITLB misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts every core cycle when a Data-side (wa= lks due to a data operation) page walk is in progress.", - "EventCode": "0x05", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "EventCode": "0x81", + "EventName": "ITLB.MISS", + "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "Duration of D-side page-walks in cycles" + "UMask": "0x4" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts every core cycle when a Instruction-s= ide (walks due to an instruction fetch) page walk is in progress.", - "EventCode": "0x05", + "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "2", + "PublicDescription": "Counts uops retired that had a DTLB miss on = load, store or either. Note that when two distinct memory operations to th= e same page miss the DTLB, only one of them will be recorded as a DTLB miss= .", "SampleAfterValue": "200003", - "BriefDescription": "Duration of I-side pagewalks in cycles" + "UMask": "0x13" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts every core cycle a page-walk is in pr= ogress due to either a data memory operation or an instruction fetch.", - "EventCode": "0x05", + "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that caused a DTLB = miss.", "SampleAfterValue": "200003", - "BriefDescription": "Duration of page-walks in cycles" + "UMask": "0x11" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", - "EventCode": "0x81", + "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB.MISS", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "2", + "PublicDescription": "Counts store uops retired that caused a DTLB= miss.", "SampleAfterValue": "200003", - "BriefDescription": "ITLB misses" + "UMask": "0x12" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that caused a DTLB = miss.", - "EventCode": "0xD0", + "BriefDescription": "Duration of page-walks in cycles", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "Counts every core cycle a page-walk is in pr= ogress due to either a data memory operation or an instruction fetch.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", - "Data_LA": "1" + "UMask": "0x3" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired that caused a DTLB= miss.", - "EventCode": "0xD0", + "BriefDescription": "Duration of D-side page-walks in cycles", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "PublicDescription": "Counts every core cycle when a Data-side (wa= lks due to a data operation) page walk is in progress.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that had a DTLB miss on = load, store or either. Note that when two distinct memory operations to th= e same page miss the DTLB, only one of them will be recorded as a DTLB miss= .", - "EventCode": "0xD0", + "BriefDescription": "Duration of I-side pagewalks in cycles", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x13", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "Counts every core cycle when a Instruction-s= ide (walks due to an instruction fetch) page walk is in progress.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", - "Data_LA": "1" + "UMask": "0x2" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81E5DC4332F for ; Tue, 1 Feb 2022 02:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232832AbiBACAe (ORCPT ); Mon, 31 Jan 2022 21:00:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232356AbiBAB7n (ORCPT ); Mon, 31 Jan 2022 20:59:43 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2F0DC061755 for ; Mon, 31 Jan 2022 17:59:42 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id b2-20020a252e42000000b00619593ff8ddso18999045ybn.6 for ; Mon, 31 Jan 2022 17:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=RQSsiXVj404EMJ1vKlTzVnd+hcmHRgpEfx8XBgBCiT4=; b=mV+e1gfnXjDWWQDwwx/yrj8Jz0I5EbYO0rlAgt50IisgFBd9N1sxWjumeZAGEdmoxF zrePIdtGIwD9G/qw+66+FLdrdCtCtuEIbbVyE4gqse1OMnm2rzvPvApChfY4VjlEHzZ9 howXy4zShQmsn1gk7cd2UY1jhgVsnx+FrYt83fhn6f3PXb0pZjefkAxnQbHe1v9LIKNP 3o9Hlsg9DgpirSRPg2G/pfAzV4IJrq9EMaelH+t7iDFxF7Pg/uXnwZ8k8xeTcayoOjH9 wIZYE0C6RIgX3COYRykBCv0SpTjwgEQhbeGYHB8/DZUFVsL0jOOCO5jZRjwhVyXCBj9c uSJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=RQSsiXVj404EMJ1vKlTzVnd+hcmHRgpEfx8XBgBCiT4=; b=aUXHom7Qo6S/a1YjfdwEo2H2dOE3dgliBi5xYJTxyGEMukyv+pJ+eyxaoQE9GXd0Qy dGPR52YgBfDVGiS6wlrJ6xr/BJarLDskWPn74UYmgeUNMKdExMbmBDc9AmXwbFOXFv1k 8eU2X1Cw0XPwFIq13OuSx6sZEI19H6yplE+Ypd6OsNNPA8ld76xwZ/bBaA5MscJOHX24 aMo30Z7/mbrL4zA3rygQ4MWwFKMVlCQHfAWnXq1a9aHE0rZqKWErfGZrmcttG9Ij9MQH XpSKgFsnbBA3JvDN8pLnPGOU1H5jt4wDbGRV+cRW4PMihbfExPBBvRD0xeqk+rxDmoUr rdkg== X-Gm-Message-State: AOAM531Fk2s+H3B96c90stPuAKAX8llccXAveeTufr8gsN9iUlzdMOS8 Om6J822B9ZF0tQjvwpx1OQ3XxjmOVVnu X-Google-Smtp-Source: ABdhPJzJs6hvHTPYcaCHT+eW6zVExnyxZScAOfYgEKJyOjgC4AMJ6Qk9Zw1KCOmg2ODjyl0NzkVmUzPzoER6 X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:557:: with SMTP id 84mr33574640ybf.637.1643680782167; Mon, 31 Jan 2022 17:59:42 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:45 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-14-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 13/26] perf vendor events: Update for GoldmontPlus From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Events are still at version 1.01: https://download.01.org/perfmon/GLP Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf The addition of a floating-point.json is due to events having their topic better identified by the converter script. Tested: Not tested on a GoldmontPlus, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/goldmontplus/cache.json | 1730 ++++++++--------- .../arch/x86/goldmontplus/floating-point.json | 38 + .../arch/x86/goldmontplus/frontend.json | 88 +- .../arch/x86/goldmontplus/memory.json | 44 +- .../arch/x86/goldmontplus/other.json | 106 +- .../arch/x86/goldmontplus/pipeline.json | 616 +++--- .../arch/x86/goldmontplus/virtual-memory.json | 214 +- 7 files changed, 1412 insertions(+), 1424 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/floating-po= int.json diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/cache.json index 5a6ac8285ad4..59c039169eb8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json @@ -1,1467 +1,1465 @@ [ { + "BriefDescription": "Requests rejected by the L2Q", "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", - "EventCode": "0x2E", "Counter": "0,1,2,3", - "UMask": "0x41", - "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests" + "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to insure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L1 Cache evictions for dirty data", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", - "EventCode": "0x30", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "L2_REJECT_XQ.ALL", + "EventCode": "0x51", + "EventName": "DL1.REPLACEMENT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the XQ" + "UMask": "0x1" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to insure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", - "EventCode": "0x31", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "CORE_REJECT_L2Q.ALL", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the L2Q" + "UMask": "0x2" }, { + "BriefDescription": "Requests rejected by the XQ", "CollectPEBSRecord": "1", - "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", - "EventCode": "0x51", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "DL1.REPLACEMENT", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L1 Cache evictions for dirty data" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L2 cache request misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss." + "UMask": "0x41" }, { + "BriefDescription": "L2 cache requests", "CollectPEBSRecord": "1", - "EventCode": "0xB7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PDIR_COUNTER": "na", - "SampleAfterValue": "100007", - "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4f" }, { - "PEBS": "2", + "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts locked memory uops retired. This inc= ludes regular locks and bus locks. (To specifically count bus locks only, s= ee the Offcore response event.) A locked access is one with a lock prefix,= or an exchange to memory. See the SDM for a complete description of which= memory load accesses are locks.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x21", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from DRAM. Event is counted at retirement, so the speculat= ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (= or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.= ", "SampleAfterValue": "200003", - "BriefDescription": "Locked load uops retired (Precise event capab= le)", - "Data_LA": "1" + "UMask": "0x80" }, { - "PEBS": "2", + "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the data requ= ested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x41", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PublicDescription": "Counts load uops retired where the cache lin= e containing the data was in the modified state of another core or modules = cache (HITM). More specifically, this means that when the load address was= checked by other caching agents (typically another processor) in the syste= m, one of those caching agents indicated that they had a dirty copy of the = data. Loads that obtain a HITM response incur greater latency than most is= typical for a load. In addition, since HITM indicates that some other pro= cessor had this data in its cache, it implies that the data was shared betw= een processors, or potentially was a lock or semaphore value. This event i= s useful for locating sharing, false sharing, and contended locks.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", - "Data_LA": "1" + "UMask": "0x20" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired where the data req= uested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x42", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PublicDescription": "Counts load uops retired that hit the L1 dat= a cache.", "SampleAfterValue": "200003", - "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory uops retired where the data re= quested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x43", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PublicDescription": "Counts load uops retired that miss the L1 da= ta cache.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x8" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x81", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "Counts load uops retired that hit in the L2 = cache.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x82", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "Counts load uops retired that miss in the L2= cache.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x10" }, { - "PEBS": "2", + "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of memory uops retired tha= t is either a loads or a store or both.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x83", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL", + "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from the WCB (or fill buffer), indicating that the load fou= nd its data while that data was in the process of being brought into the L1= cache. Typically a load will receive this indication when some other load= or prefetch missed the L1 cache and was in the process of retrieving the c= ache line containing the data, but that process had not yet finished (and w= ritten the data back to the cache). For example, consider load X and Y, bot= h referencing the same cache line that is not in the L1 cache. If load X m= isses cache first, it obtains and WCB (or fill buffer) and begins the proce= ss of requesting the data. When load Y requests the data, it will either h= it the WCB, or the L1 cache, depending on exactly what time the request to = Y occurs.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x40" }, { - "PEBS": "2", + "BriefDescription": "Memory uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit the L1 dat= a cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x1", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PublicDescription": "Counts the number of memory uops retired tha= t is either a loads or a store or both.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", - "Data_LA": "1" + "UMask": "0x83" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit in the L2 = cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x2", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PublicDescription": "Counts the number of load uops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", - "Data_LA": "1" + "UMask": "0x81" }, { - "PEBS": "2", + "BriefDescription": "Store uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss the L1 da= ta cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x8", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PublicDescription": "Counts the number of store uops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x82" }, { - "PEBS": "2", + "BriefDescription": "Locked load uops retired (Precise event capab= le)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss in the L2= cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x10", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PublicDescription": "Counts locked memory uops retired. This inc= ludes regular locks and bus locks. (To specifically count bus locks only, s= ee the Offcore response event.) A locked access is one with a lock prefix,= or an exchange to memory. See the SDM for a complete description of which= memory load accesses are locks.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", - "Data_LA": "1" + "UMask": "0x21" }, { - "PEBS": "2", + "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the cache lin= e containing the data was in the modified state of another core or modules = cache (HITM). More specifically, this means that when the load address was= checked by other caching agents (typically another processor) in the syste= m, one of those caching agents indicated that they had a dirty copy of the = data. Loads that obtain a HITM response incur greater latency than most is= typical for a load. In addition, since HITM indicates that some other pro= cessor had this data in its cache, it implies that the data was shared betw= een processors, or potentially was a lock or semaphore value. This event i= s useful for locating sharing, false sharing, and contended locks.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x20", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PublicDescription": "Counts memory uops retired where the data re= quested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", - "Data_LA": "1" + "UMask": "0x43" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from the WCB (or fill buffer), indicating that the load fou= nd its data while that data was in the process of being brought into the L1= cache. Typically a load will receive this indication when some other load= or prefetch missed the L1 cache and was in the process of retrieving the c= ache line containing the data, but that process had not yet finished (and w= ritten the data back to the cache). For example, consider load X and Y, bot= h referencing the same cache line that is not in the L1 cache. If load X m= isses cache first, it obtains and WCB (or fill buffer) and begins the proce= ss of requesting the data. When load Y requests the data, it will either h= it the WCB, or the L1 cache, depending on exactly what time the request to = Y occurs.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x40", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PublicDescription": "Counts load uops retired where the data requ= ested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", - "Data_LA": "1" + "UMask": "0x41" }, { - "PEBS": "2", + "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from DRAM. Event is counted at retirement, so the speculat= ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (= or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.= ", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x80", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PublicDescription": "Counts store uops retired where the data req= uested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", - "Data_LA": "1" + "UMask": "0x42" }, { + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines have any transaction responses from the uncore subsystem. Requir= es MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated = for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) have an= y transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify requ= est type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) have a= ny transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) hit the= L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines true miss for the L2 cache with a snoop miss in the other proces= sor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and res= ponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000043091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) hit th= e L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and resp= onse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines true miss for the L2 cache with a snoop miss in the other process= or module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) miss th= e L2 cache with a snoop hit in the other processor module, data forwarding = is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines miss the L2 cache with a snoop hit in the other processor module= , data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) miss t= he L2 cache with a snoop hit in the other processor module, data forwarding= is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines miss the L2 cache with a snoop hit in the other processor module,= data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) true mi= ss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines outstanding, per cycle, from the time of the L2 miss to when any= response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request ty= pe and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) true m= iss for the L2 cache with a snoop miss in the other processor module. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines outstanding, per cycle, from the time of the L2 miss to when any = response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) outstan= ding, per cycle, from the time of the L2 miss to when any response is recei= ved.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line have any transaction resp= onses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000003091", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) outsta= nding, per cycle, from the time of the L2 miss to when any response is rece= ived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line have any transaction respo= nses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line hit the L2 cache. Require= s MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated f= or both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000013010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line true miss for the L2 cach= e with a snoop miss in the other processor module. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000043010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line true miss for the L2 cache= with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line miss the L2 cache with a = snoop hit in the other processor module, data forwarding is required. Requi= res MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated= for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000003010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line miss the L2 cache with a s= noop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers true miss for the L2 cache with a snoop miss in the other processor = module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line outstanding, per cycle, f= rom the time of the L2 miss to when any response is received. Requires MSR_= OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bot= h MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200003010", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line outstanding, per cycle, fr= om the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache have any transaction r= esponses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000003010", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache have any transaction re= sponses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) have any transaction responses fr= om the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache hit the L2 cache. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x00000132b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) have any transaction responses f= rom the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache true miss for the L2 c= ache with a snoop miss in the other processor module. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x0200000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x00000432b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_O= FFCORE_RESP[0,1] to specify request type and response. (duplicated for both= MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache true miss for the L2 ca= che with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hi= t in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache miss the L2 cache with= a snoop hit in the other processor module, data forwarding is required. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_C= ORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x10000032b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h= it in the other processor module, data forwarding is required. Requires MSR= _OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bo= th MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) true miss for the L2 cache with a= snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache outstanding, per cycle= , from the time of the L2 miss to when any response is received. Requires M= SR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for = both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x02000032b7", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) true miss for the L2 cache with = a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache outstanding, per cycle,= from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) outstanding, per cycle, from the = time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions have any transaction responses from the = uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x40000032b7", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) outstanding, per cycle, from the= time of the L2 miss to when any response is received. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions have any transaction responses from the u= ncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem have = any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_R= ESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem hit t= he L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop = miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000048000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions true miss for the L2 cache with a snoop m= iss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in th= e other processor module, data forwarding is required. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x1000000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000008000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the= other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem true = miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions outstanding, per cycle, from the time of= the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,= 1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200008000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions outstanding, per cycle, from the time of = the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher have any transaction responses from the uncore su= bsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respons= e. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000008000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher have any transaction responses from the uncore sub= system.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) have any transaction responses from the uncore subsystem.= Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher true miss for the L2 cache with a snoop miss in t= he other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) miss the L2 cache with a snoop hit in the other processor = module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher miss the L2 cache with a snoop hit in the other p= rocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) miss the L2 cache with a snoop hit in the other processor= module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) true miss for the L2 cache with a snoop miss in the other = processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher outstanding, per cycle, from the time of the L2 m= iss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) true miss for the L2 cache with a snoop miss in the other= processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) outstanding, per cycle, from the time of the L2 miss to wh= en any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher have any transaction responses from the uncore sub= system. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000022", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) outstanding, per cycle, from the time of the L2 miss to w= hen any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher have any transaction responses from the uncore subs= ystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests have = any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests hit t= he L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reques= t type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher true miss for the L2 cache with a snoop miss in the= other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher miss the L2 cache with a snoop hit in the other pro= cessor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests true = miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000400", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher outstanding, per cycle, from the time of the L2 mis= s to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000400", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests have = any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions have any transaction responses from the u= ncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions have any transaction responses from the = uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests hit t= he L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_R= ESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests true = miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the= other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in th= e other processor module, data forwarding is required. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions true miss for the L2 cache with a snoop m= iss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000008", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop = miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions outstanding, per cycle, from the time of = the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000008", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions outstanding, per cycle, from the time of= the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,= 1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache have any transaction re= sponses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache have any transaction r= esponses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache hit the L2 cache. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes true miss for the L2 cache with a snoop miss in the other processor = module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache miss the L2 cache with= a snoop hit in the other processor module, data forwarding is required. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache true miss for the L2 ca= che with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache true miss for the L2 c= ache with a snoop miss in the other processor module. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache outstanding, per cycle,= from the time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions have any transaction responses from the uncore subsy= stem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000011000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache outstanding, per cycle= , from the time of the L2 miss to when any response is received. Requires M= SR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for = both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions have any transaction responses from the uncore subsys= tem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to = specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000041000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines have any transaction responses from the uncore subsystem. Requir= es MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated = for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions true miss for the L2 cache with a snoop miss in the = other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify requ= est type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions true miss for the L2 cache with a snoop miss in the o= ther processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines miss the L2 cache with a snoop hit in the other processor module,= data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions miss the L2 cache with a snoop hit in the other proc= essor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines miss the L2 cache with a snoop hit in the other processor module= , data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines true miss for the L2 cache with a snoop miss in the other process= or module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions outstanding, per cycle, from the time of the L2 miss= to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specif= y request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines true miss for the L2 cache with a snoop miss in the other proces= sor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and res= ponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions outstanding, per cycle, from the time of the L2 miss = to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines outstanding, per cycle, from the time of the L2 miss to when any = response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000012000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines outstanding, per cycle, from the time of the L2 miss to when any= response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request ty= pe and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher have any transaction responses from the unco= re subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line have any transaction respo= nses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000042000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line have any transaction resp= onses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line hit the L2 cache. Require= s MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated f= or both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher true miss for the L2 cache with a snoop miss= in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line miss the L2 cache with a s= noop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line miss the L2 cache with a = snoop hit in the other processor module, data forwarding is required. Requi= res MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated= for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line true miss for the L2 cache= with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line true miss for the L2 cach= e with a snoop miss in the other processor module. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher outstanding, per cycle, from the time of the= L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line outstanding, per cycle, fr= om the time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000014800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line outstanding, per cycle, f= rom the time of the L2 miss to when any response is received. Requires MSR_= OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bot= h MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region have any transaction responses from the unco= re subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000044800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS= _OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region true miss for the L2 cache with a snoop miss= in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER= _CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes true miss for the L2 cache with a snoop miss in the other processor = module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000800", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region outstanding, per cycle, from the time of the= L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000018000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000800", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem have = any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher have any transaction responses from the unco= re subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000048000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem hit t= he L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000042000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem true = miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher true miss for the L2 cache with a snoop miss= in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher outstanding, per cycle, from the time of the= L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000013010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000002000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher have any transaction responses from the uncore sub= system.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043010", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010010", + "Offcore": "1", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher have any transaction responses from the uncore su= bsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respons= e. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040010", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher miss the L2 cache with a snoop hit in the other p= rocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers true miss for the L2 cache with a snoop miss in the other processor = module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher true miss for the L2 cache with a snoop miss in t= he other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher outstanding, per cycle, from the time of the L2 m= iss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher have any transaction responses from the uncore subs= ystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) have a= ny transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000013091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher have any transaction responses from the uncore sub= system. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) have an= y transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) hit th= e L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and resp= onse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) hit the= L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher miss the L2 cache with a snoop hit in the other pro= cessor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) true m= iss for the L2 cache with a snoop miss in the other processor module. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) true mi= ss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher true miss for the L2 cache with a snoop miss in the= other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) miss t= he L2 cache with a snoop hit in the other processor module, data forwarding= is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reques= t type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) miss th= e L2 cache with a snoop hit in the other processor module, data forwarding = is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher outstanding, per cycle, from the time of the L2 mis= s to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) outsta= nding, per cycle, from the time of the L2 miss to when any response is rece= ived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) outstan= ding, per cycle, from the time of the L2 miss to when any response is recei= ved.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region have any transaction responses from the unco= re subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) have any transaction responses from the uncore subsystem.= Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000014800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000044800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) true miss for the L2 cache with a snoop miss in the other= processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER= _CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) true miss for the L2 cache with a snoop miss in the other = processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region true miss for the L2 cache with a snoop miss= in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) miss the L2 cache with a snoop hit in the other processor= module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS= _OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) miss the L2 cache with a snoop hit in the other processor = module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region outstanding, per cycle, from the time of the= L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) outstanding, per cycle, from the time of the L2 miss to w= hen any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) outstanding, per cycle, from the time of the L2 miss to wh= en any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions have any transaction responses from the uncore subsys= tem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) have any transaction responses f= rom the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000132b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000011000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions have any transaction responses from the uncore subsy= stem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) have any transaction responses fr= om the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_O= FFCORE_RESP[0,1] to specify request type and response. (duplicated for both= MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000432b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000041000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to = specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) true miss for the L2 cache with = a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x02000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions miss the L2 cache with a snoop hit in the other proc= essor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) true miss for the L2 cache with a= snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions true miss for the L2 cache with a snoop miss in the o= ther processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h= it in the other processor module, data forwarding is required. Requires MSR= _OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bo= th MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x10000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions true miss for the L2 cache with a snoop miss in the = other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hi= t in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions outstanding, per cycle, from the time of the L2 miss = to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) outstanding, per cycle, from the= time of the L2 miss to when any response is received. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x40000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions outstanding, per cycle, from the time of the L2 miss= to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specif= y request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) outstanding, per cycle, from the = time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json new file mode 100644 index 000000000000..c1f00c9470f4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json @@ -0,0 +1,38 @@ +[ + { + "BriefDescription": "Cycles the FP divide unit is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Machine clears due to FP assists", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", + "SampleAfterValue": "20003", + "UMask": "0x4" + }, + { + "BriefDescription": "Floating point divide uops retired (Precise E= vent Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of floating point divide u= ops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/frontend.json index a7878965ceab..3fdc788a2b20 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json @@ -1,62 +1,98 @@ [ { + "BriefDescription": "BACLEARs asserted for any branch type", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture" + "UMask": "0x1" }, { + "BriefDescription": "BACLEARs asserted for conditional branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.MISSES", + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "BACLEARs asserted for return branch", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts BACLEARS on return instructions.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture" + "UMask": "0x8" }, { + "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xE9", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x3" }, { + "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", - "EventCode": "0xE7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MS_DECODED.MS_ENTRY", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", "SampleAfterValue": "200003", - "BriefDescription": "MS decode starts" + "UMask": "0x1" }, { + "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", - "EventCode": "0xE9", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "MS decode starts", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", "SampleAfterValue": "200003", - "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tool= s/perf/pmu-events/arch/x86/goldmontplus/memory.json index 91e0815f3ffb..e26763d16d52 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json @@ -1,38 +1,38 @@ [ { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory load of a uop spans a p= age boundary (a split) is retired.", - "EventCode": "0x13", + "BriefDescription": "Machine clears due to memory ordering issue", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split a page (Precise event ca= pable)" + "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved - as another core is in the proce= ss of modifying the data.", + "SampleAfterValue": "20003", + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Load uops that split a page (Precise event ca= pable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory store of a uop spans a = page boundary (a split) is retired.", - "EventCode": "0x13", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PublicDescription": "Counts when a memory load of a uop spans a p= age boundary (a split) is retired.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split a page (Precise event c= apable)" + "UMask": "0x2" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved - as another core is in the proce= ss of modifying the data.", - "EventCode": "0xC3", + "BriefDescription": "Store uops that split a page (Precise event c= apable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to memory ordering issue" + "PublicDescription": "Counts when a memory store of a uop spans a = page boundary (a split) is retired.", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/other.json index b860374418ab..3378f48cb818 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json @@ -1,98 +1,96 @@ [ { + "BriefDescription": "Cycles code-fetch stalled due to any reason.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss= is outstanding.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss= is outstanding." - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x0", "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle" + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", - "EventCode": "0xCA", + "BriefDescription": "Cycles hardware interrupts are masked", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.MASKED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend" + "UMask": "0x2" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", - "EventCode": "0xCA", + "BriefDescription": "Cycles pending interrupts are masked", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle to recover" + "UMask": "0x4" }, { + "BriefDescription": "Hardware interrupts received", "CollectPEBSRecord": "2", - "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", "SampleAfterValue": "203", - "BriefDescription": "Hardware interrupts received" + "UMask": "0x1" }, { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", - "EventCode": "0xCB", + "BriefDescription": "Unfilled issue slots per cycle", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "HW_INTERRUPTS.MASKED", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Unfilled issue slots per cycle to recover", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles hardware interrupts are masked" + "UMask": "0x2" }, { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", - "EventCode": "0xCB", + "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles pending interrupts are masked" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/pipeline.json index e3fa1a0ba71b..8305e2ecf617 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json @@ -1,541 +1,459 @@ [ { + "BriefDescription": "Retired branch instructions (Precise event ca= pable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "PEBScounters": "32", - "EventName": "INST_RETIRED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Fixed event)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "PEBScounters": "33", - "EventName": "CPU_CLK_UNHALTED.CORE", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "PEBScounters": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts branch instructions retired for all b= ranch types. This is an architectural performance event.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", + "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store for= ward, but did not occur because the store data was not available at the rig= ht time. The forward might occur subsequently when the data is available.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PublicDescription": "Counts the number of taken branch instructio= ns retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)" + "UMask": "0x80" }, { - "PEBS": "2", + "BriefDescription": "Retired near call instructions (Precise event= capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store for= ward because of an address/size mismatch, only one of the loads blocked fro= m each store will be counted.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Counts near CALL branch instructions retired= .", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)" + "UMask": "0xf9" }, { - "PEBS": "2", + "BriefDescription": "Retired far branch instructions (Precise even= t capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads that block because their addres= s modulo 4K matches a pending store.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.4K_ALIAS", + "PublicDescription": "Counts far branch instructions retired. Thi= s includes far jump, far call and return, and Interrupt call and return.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)" + "UMask": "0xbf" }, { - "PEBS": "2", + "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads blocked because they are unable= to find their physical address in the micro TLB (UTLB).", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.UTLB_MISS", + "PublicDescription": "Counts near indirect CALL branch instruction= s retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)" + "UMask": "0xfb" }, { - "PEBS": "2", + "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts anytime a load that retires is blocke= d for any reason.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.ALL_BLOCK", + "PublicDescription": "Counts retired Jcc (Jump on Conditional Code= /Jump if Condition is Met) branch instructions retired, including both when= the branch was taken and when it was not taken.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked (Precise event capable)" + "UMask": "0x7e" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", - "EventCode": "0x0E", + "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts near indirect call or near indirect j= mp branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Uops issued to the back end per cycle" + "UMask": "0xeb" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", + "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" + "PublicDescription": "Counts near relative CALL branch instruction= s retired.", + "SampleAfterValue": "200003", + "UMask": "0xfd" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Reference cycles when core is not halted. T= his event uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", + "BriefDescription": "Retired near return instructions (Precise eve= nt capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" + "PublicDescription": "Counts near return branch instructions retir= ed.", + "SampleAfterValue": "200003", + "UMask": "0xf7" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", - "EventCode": "0x9C", + "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_NOT_DELIVERED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if= Condition is Met) branch instructions retired that were taken and does not= count when the Jcc branch instruction were not taken.", "SampleAfterValue": "200003", - "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle" + "UMask": "0xfe" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", - "EventCode": "0xC0", + "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Precise event capable)" + "PublicDescription": "Counts mispredicted branch instructions reti= red including all branch types.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Sk= id PEBS feature that reduces the shadow in which events aren't counted allo= wing for a more unbiased distribution of samples across instructions retire= d.", - "EventCode": "0xC0", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired - using Reduced Skid PEB= S feature" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted near indirect CALL branc= h instructions retired, where the target address taken was not what the pro= cessor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xfb" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops which retired.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops retired (Precise event capable)" + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired, includ= ing both when the branch was supposed to be taken and when it was not suppo= sed to be taken (but the processor predicted the opposite condition).", + "SampleAfterValue": "200003", + "UMask": "0x7e" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that are from the comple= x flows issued by the micro-sequencer (MS). Counts both the uops from a mi= cro-coded instruction, and the uops that might be generated from a micro-co= ded assist.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.MS", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "MS uops retired (Precise event capable)" + "PublicDescription": "Counts mispredicted branch instructions reti= red that were near indirect call or near indirect jmp, where the target add= ress taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xeb" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of floating point divide u= ops retired.", - "EventCode": "0xC2", + "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.FPDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Floating point divide uops retired (Precise E= vent Capable)" + "PublicDescription": "Counts mispredicted near RET branch instruct= ions retired, where the return address taken was not what the processor pre= dicted.", + "SampleAfterValue": "200003", + "UMask": "0xf7" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of integer divide uops ret= ired.", - "EventCode": "0xC2", + "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.IDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Integer divide uops retired (Precise Event Ca= pable)" + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired that we= re supposed to be taken but the processor predicted that it would not be ta= ken.", + "SampleAfterValue": "200003", + "UMask": "0xfe" }, { + "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears for any reason.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.ALL", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.CORE", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "All machine clears" + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { + "BriefDescription": "Core cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel\u00ae architecture processors.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Self-Modifying Code detected" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Reference cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.FP_ASSIST", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to FP assists" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Reference cycles when core is not halted. T= his event uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { + "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to memory disambiguation" + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { + "BriefDescription": "Cycles a divider is busy", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the machines= clears due to a page fault. Covers both I-side and D-side(Loads/Stores) pa= ge faults. A page fault occurs when either page is not present, or an acces= s violation", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x20", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machines clear due to a page fault" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all b= ranch types. This is an architectural performance event.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired branch instructions (Precise event ca= pable)" + "PublicDescription": "Counts core cycles if either divide unit is = busy.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts retired Jcc (Jump on Conditional Code= /Jump if Condition is Met) branch instructions retired, including both when= the branch was taken and when it was not taken.", - "EventCode": "0xC4", + "BriefDescription": "Cycles the integer divide unit is busy", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x7e", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.IDIV", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.JCC", + "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)" + "UMask": "0x1" }, { + "BriefDescription": "Instructions retired (Fixed event)", + "CollectPEBSRecord": "1", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PDIR_COUNTER": "na", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of taken branch instructio= ns retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x80", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)" + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts far branch instructions retired. Thi= s includes far jump, far call and return, and Interrupt call and return.", - "EventCode": "0xC4", + "BriefDescription": "Instructions retired (Precise event capable)", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xbf", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "200003", - "BriefDescription": "Retired far branch instructions (Precise even= t capable)" - }, - { + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect call or near indirect j= mp branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xeb", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)" + "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", + "BriefDescription": "Instructions retired - using Reduced Skid PEB= S feature", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near return branch instructions retir= ed.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xf7", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near return instructions (Precise eve= nt capable)" - }, - { + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near CALL branch instructions retired= .", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf9", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near call instructions (Precise event= capable)" + "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Sk= id PEBS feature that reduces the shadow in which events aren't counted allo= wing for a more unbiased distribution of samples across instructions retire= d.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect CALL branch instruction= s retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfb", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near relative CALL branch instruction= s retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfd", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.REL_CALL", + "PublicDescription": "Counts loads that block because their addres= s modulo 4K matches a pending store.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)" + "UMask": "0x4" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if= Condition is Met) branch instructions retired that were taken and does not= count when the Jcc branch instruction were not taken.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfe", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PublicDescription": "Counts anytime a load that retires is blocke= d for any reason.", "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)" + "UMask": "0x10" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red including all branch types.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Counts a load blocked from using a store for= ward, but did not occur because the store data was not available at the rig= ht time. The forward might occur subsequently when the data is available.", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)" + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired, includ= ing both when the branch was supposed to be taken and when it was not suppo= sed to be taken (but the processor predicted the opposite condition).", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x7e", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.JCC", + "PublicDescription": "Counts a load blocked from using a store for= ward because of an address/size mismatch, only one of the loads blocked fro= m each store will be counted.", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red that were near indirect call or near indirect jmp, where the target add= ress taken was not what the processor predicted.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0xeb", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.UTLB_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PublicDescription": "Counts loads blocked because they are unable= to find their physical address in the micro TLB (UTLB).", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call (Precise event capable)" + "UMask": "0x8" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near RET branch instruct= ions retired, where the return address taken was not what the processor pre= dicted.", - "EventCode": "0xC5", + "BriefDescription": "All machine clears", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xf7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)" + "PublicDescription": "Counts machine clears for any reason.", + "SampleAfterValue": "20003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near indirect CALL branc= h instructions retired, where the target address taken was not what the pro= cessor predicted.", - "EventCode": "0xC5", + "BriefDescription": "Machine clears due to memory disambiguation", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xfb", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)" + "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", + "SampleAfterValue": "20003", + "UMask": "0x8" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired that we= re supposed to be taken but the processor predicted that it would not be ta= ken.", - "EventCode": "0xC5", + "BriefDescription": "Machines clear due to a page fault", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xfe", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)" + "PublicDescription": "Counts the number of times that the machines= clears due to a page fault. Covers both I-side and D-side(Loads/Stores) pa= ge faults. A page fault occurs when either page is not present, or an acces= s violation", + "SampleAfterValue": "20003", + "UMask": "0x20" }, { + "BriefDescription": "Self-Modifying Code detected", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles if either divide unit is = busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.ALL", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a divider is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel architecture processors.", + "SampleAfterValue": "20003", + "UMask": "0x1" }, { + "BriefDescription": "Uops issued to the back end per cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.IDIV", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the integer divide unit is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.FPDIV", + "EventCode": "0x9C", + "EventName": "UOPS_NOT_DELIVERED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the FP divide unit is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", + "SampleAfterValue": "200003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", - "EventCode": "0xE6", + "BriefDescription": "Uops retired (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.ALL", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for any branch type" + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops which retired.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Integer divide uops retired (Precise Event Ca= pable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on return instructions.", - "EventCode": "0xE6", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.RETURN", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for return branch" + "PublicDescription": "Counts the number of integer divide uops ret= ired.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", - "EventCode": "0xE6", + "BriefDescription": "MS uops retired (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.COND", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for conditional branch" + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops retired that are from the comple= x flows issued by the micro-sequencer (MS). Counts both the uops from a mi= cro-coded instruction, and the uops that might be generated from a micro-co= ded assist.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json index 0d32fd26ded1..36eaec87eead 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json @@ -1,221 +1,221 @@ [ { + "BriefDescription": "Page walk completed due to a demand load to a= 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 4K pages. The page walks can end with or wi= thout a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 1GB pages. The page walks can end with or w= ithout a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 4K page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to a demand load to a= 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 2M or 4M pages. The page walks can end with= or without a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 2M or 4M pages. The page walks can end with= or without a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 2M or 4M page" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to a demand load to a= 4K page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 1GB pages. The page walks can end with or w= ithout a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 4K pages. The page walks can end with or wi= thout a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 1GB page" + "UMask": "0x2" }, { + "BriefDescription": "Page walks outstanding due to a demand load e= very cycle.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a load (demand data loads or SW prefetches). Includes cycles = spent traversing the Extended Page Table (EPT). Average cycles per walk can= be calculated by dividing by the number of walks.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a load (demand data loads or SW prefetches). Includes cycles = spent traversing the Extended Page Table (EPT). Average cycles per walk can= be calculated by dividing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to a demand load e= very cycle." + "UMask": "0x10" }, { + "BriefDescription": "Page walk completed due to a demand data stor= e to a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 1= GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M or 4M pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M or 4M page" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 1= GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 1GB page" + "UMask": "0x2" }, { + "BriefDescription": "Page walks outstanding due to a demand data s= tore every cycle.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a demand data store. Includes cycles spent traversing the Ext= ended Page Table (EPT). Average cycles per walk can be calculated by dividi= ng by the number of walks.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a demand data store. Includes cycles spent traversing the Ext= ended Page Table (EPT). Average cycles per walk can be calculated by dividi= ng by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to a demand data s= tore every cycle." + "UMask": "0x10" }, { + "BriefDescription": "Page walks outstanding due to walking the EPT= every cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk onl= y while traversing the Extended Page Table (EPT), and does not count during= the rest of the translation. The EPT is used for translating Guest-Physic= al Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Av= erage cycles per walk can be calculated by dividing the count by number of = walks.", - "EventCode": "0x4F", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x4F", "EventName": "EPT.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk onl= y while traversing the Extended Page Table (EPT), and does not count during= the rest of the translation. The EPT is used for translating Guest-Physic= al Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Av= erage cycles per walk can be calculated by dividing the count by number of = walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to walking the EPT= every cycle" + "UMask": "0x10" }, { + "BriefDescription": "ITLB misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", - "EventCode": "0x81", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x81", "EventName": "ITLB.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "ITLB misses" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to an instruction fet= ch in a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 1GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 4K page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to an instruction fet= ch in a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 2M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 2M or 4M pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 2M or 4M page" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to an instruction fet= ch in a 4K page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 1GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 4K pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 1GB page" + "UMask": "0x2" }, { + "BriefDescription": "Page walks outstanding due to an instruction = fetch every cycle.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occ= urring due to an instruction fetch. Includes cycles spent traversing the Ex= tended Page Table (EPT). Average cycles per walk can be calculated by divid= ing by the number of walks.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occ= urring due to an instruction fetch. Includes cycles spent traversing the Ex= tended Page Table (EPT). Average cycles per walk can be calculated by divid= ing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to an instruction = fetch every cycle." + "UMask": "0x10" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts STLB flushes. The TLBs are flushed o= n instructions like INVLPG and MOV to CR3.", - "EventCode": "0xBD", + "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x20", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "TLB_FLUSHES.STLB_ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "STLB flushes" + "PublicDescription": "Counts uops retired that had a DTLB miss on = load, store or either. Note that when two distinct memory operations to th= e same page miss the DTLB, only one of them will be recorded as a DTLB miss= .", + "SampleAfterValue": "200003", + "UMask": "0x13" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that caused a DTLB = miss.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x11", - "PEBScounters": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that caused a DTLB = miss.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", - "Data_LA": "1" + "UMask": "0x11" }, { - "PEBS": "2", + "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired that caused a DTLB= miss.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x12", - "PEBScounters": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts store uops retired that caused a DTLB= miss.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", - "Data_LA": "1" + "UMask": "0x12" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that had a DTLB miss on = load, store or either. Note that when two distinct memory operations to th= e same page miss the DTLB, only one of them will be recorded as a DTLB miss= .", - "EventCode": "0xD0", + "BriefDescription": "STLB flushes", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x13", + "EventCode": "0xBD", + "EventName": "TLB_FLUSHES.STLB_ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", - "Data_LA": "1" + "PublicDescription": "Counts STLB flushes. The TLBs are flushed o= n instructions like INVLPG and MOV to CR3.", + "SampleAfterValue": "20003", + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F9A6C43219 for ; Tue, 1 Feb 2022 02:01:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232739AbiBACBD (ORCPT ); Mon, 31 Jan 2022 21:01:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232693AbiBACAP (ORCPT ); Mon, 31 Jan 2022 21:00:15 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A4F5C06175E for ; Mon, 31 Jan 2022 17:59:46 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id n198-20020a2540cf000000b00614c2ee23b7so30231285yba.9 for ; Mon, 31 Jan 2022 17:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=l2Ld2UA2/uGat3mJ52ZgiEtJiHoP/HFjDSn+ZoyLRnQ=; b=h19jWI5VaY08zZLjKKSE2Xlx9GPWBP+5lhM1FONN5IbYdVSvbORwTTFXpj4BTzUa+N 9yACYwuDlzlxF9rNQCjMd8fdjM0dkp5glG3zxHrCo4tdHuAQLYtbZT1JLzIns2uoo1ou RQak9e/kANSbaPqtrt+roLH7uEYSjtoV5NakFB6tSGrmpXjWsEK9TxsCEwy4Lu1zdA28 0/A5Z8RD1yrslTfVk9HbnxMOJIon4x9aqtpimC6Ku5NlWSRdT4rPQZ+hZA63qQWN2Od0 zwsjqaAgsdWlF0wpDZPdkaqZ31A7Q4rdZJqnN0N9fSKxynfP2yd5Hsz0uhqDVtlKnPVZ kcVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=l2Ld2UA2/uGat3mJ52ZgiEtJiHoP/HFjDSn+ZoyLRnQ=; b=2G6Bl2pprj4GJ/ZpcvjDiGrFTlVf+x5L9zDz9iTZ991flpXTrEsKvFZ87RKMF38bmy DP2cwPb6xdZfGtAyKhg6XP9hcC8so1Ow41xTWkcfDzXllClO5XSHH5GrRRCM44yRKy9C ztVB9layRKvM9ou1YgJH7KKoCeW32qhNQyMJdLnxMw6f+bnmHAS7sDfMeskrRAjjrBnq TZ0bsGxewiLDLIt5P+5VItFcu+f/Yn8aJaB//BC8EMIGYueLlBfWHOruCJ5AAJRpc+Kf mEFYB99aiLL/0UwUBJo/ZmjJyADqIJguNosDt16wC9JnVr2ZZ+VgUnBiJZU7PV4szVKX Zvvg== X-Gm-Message-State: AOAM531SEt/ZdBMUwttKKNgkBenYP0FMOzyZy8OWuRG3kDvkO6slWS8j OS/Dg/orlQK28irWlFRCBCTCvq35wMiU X-Google-Smtp-Source: ABdhPJz2fcUi7GSolygAtV5OcKG6H2bshwmQGKzKBsCjC71p35A0y+3+LTN99bHpuzQ6WAAtm++5/AOFqGp+ X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:9cc2:: with SMTP id z2mr33569055ybo.194.1643680785121; Mon, 31 Jan 2022 17:59:45 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:46 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-15-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 14/26] perf vendor events: Update metrics for Haswell From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 30: https://download.01.org/perfmon/HSW Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Haswell, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/haswell/cache.json | 1446 +++++++------ .../arch/x86/haswell/floating-point.json | 129 +- .../pmu-events/arch/x86/haswell/frontend.json | 362 ++-- .../arch/x86/haswell/hsw-metrics.json | 265 +-- .../pmu-events/arch/x86/haswell/memory.json | 1004 ++++----- .../pmu-events/arch/x86/haswell/other.json | 40 +- .../pmu-events/arch/x86/haswell/pipeline.json | 1796 ++++++++--------- .../arch/x86/haswell/uncore-cache.json | 252 +++ .../arch/x86/haswell/uncore-other.json | 69 + .../pmu-events/arch/x86/haswell/uncore.json | 374 ---- .../arch/x86/haswell/virtual-memory.json | 552 ++--- 11 files changed, 3123 insertions(+), 3166 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/haswell/uncore-other.json delete mode 100644 tools/perf/pmu-events/arch/x86/haswell/uncore.json diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf= /pmu-events/arch/x86/haswell/cache.json index 7fb0ad8d8ca1..91464cfb9615 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -1,1063 +1,1061 @@ [ { - "PublicDescription": "Demand data read requests that missed L2, no= rejects.", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x21", - "Errata": "HSD78", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts when new data lines are br= ought into the L1 Data cache, which cause other lines to be evicted from th= e cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", - "EventCode": "0x24", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Demand requests that miss L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x27", - "Errata": "HSD78", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", - "EventCode": "0x24", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch. HWP are e.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.L2_PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "All requests that missed L2.", - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x3f", - "Errata": "HSD78", - "EventName": "L2_RQSTS.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "Not rejected writebacks that hit L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "All requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "UMask": "0xc1", - "Errata": "HSD78", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "PublicDescription": "Counts the number of store RFO requests that= hit the L2 cache.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "L2_RQSTS.L2_PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", - "EventCode": "0x24", + "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0xe1", - "Errata": "HSD78", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x5" }, { - "PublicDescription": "Counts all L2 store RFO requests.", - "EventCode": "0x24", + "BriefDescription": "Dirty L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0xe2", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x6" }, { - "PublicDescription": "Counts all L2 code requests.", - "EventCode": "0x24", + "BriefDescription": "L2 code requests", "Counter": "0,1,2,3", - "UMask": "0xe4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe4" }, { - "PublicDescription": "Demand requests to L2 cache.", - "EventCode": "0x24", + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "UMask": "0xe7", - "Errata": "HSD78", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", "SampleAfterValue": "200003", - "BriefDescription": "Demand requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe1" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "EventCode": "0x24", + "BriefDescription": "Demand requests that miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0xf8", - "EventName": "L2_RQSTS.ALL_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Demand requests that miss L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x27" }, { - "PublicDescription": "All requests to L2 cache.", - "EventCode": "0x24", + "BriefDescription": "Demand requests to L2 cache", "Counter": "0,1,2,3", - "UMask": "0xff", - "Errata": "HSD78", - "EventName": "L2_RQSTS.REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PublicDescription": "Demand requests to L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "All L2 requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe7" }, { - "PublicDescription": "Not rejected writebacks that hit L2 cache.", - "EventCode": "0x27", + "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", - "UMask": "0x50", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf8" }, { - "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", - "EventCode": "0x2E", + "BriefDescription": "RFO requests to L2 cache", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xe2" }, { - "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", - "EventCode": "0x2E", + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x24" }, { - "EventCode": "0x48", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch. HWP are e.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x48", + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Demand data read requests that missed L2, no= rejects.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "PublicDescription": "This event counts when new data lines are br= ought into the L1 Data cache, which cause other lines to be evicted from th= e cache.", - "EventCode": "0x51", + "BriefDescription": "L2 prefetch requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Offcore outstanding demand data read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 prefetch requests that miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78, HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "EventCode": "0x60", + "BriefDescription": "All requests that miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78, HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "All requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "EventCode": "0x60", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78, HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "All requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PublicDescription": "Offcore outstanding Demand code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "RFO requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the number of store RFO requests that= hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "RFO requests that miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" }, { - "EventCode": "0x60", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, incl= uding rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0x60", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions= .", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles in which the L1D is locked.", - "EventCode": "0x63", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests that access L2 cac= he.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Demand data read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PublicDescription": "Demand code read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", - "EventCode": "0xB0", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", - "EventCode": "0xB0", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0xb2", + "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", "SampleAfterValue": "2000003", - "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", + "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", "Counter": "0,1,2,3", - "UMask": "0x11", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (precis= e Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x12", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (preci= se Event)", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "L1_Hit_Indication": "1" + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", "Counter": "0,1,2,3", - "UMask": "0x21", - "Errata": "HSD76, HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with locked access. (precis= e Event)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This event counts load uops retired which ha= d memory addresses spilt across 2 cache lines. A line split is across 64B c= ache-lines which may include a page split (4K). This is a precise event.", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x41", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (precise Event)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts store uops retired which h= ad memory addresses spilt across 2 cache lines. A line split is across 64B = cache-lines which may include a page split (4K). This is a precise event.", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x42", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (precise Event)", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "L1_Hit_Indication": "1" + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "UMask": "0x81", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (precise Event)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts all store uops retired. Th= is is a precise event.", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Counter": "0,1,2,3", - "UMask": "0x82", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (precise Event)", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "L1_Hit_Indication": "1" + "Errata": "HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "HSD29, HSM30", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L1 cache as data so= urces.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops in which= data sources were data hits in the L3 cache without snoops required. This = does not include hardware prefetches. This is a precise event.", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L2. Unknown data so= urce excluded.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "Retired load uops with L3 cache hits as data= sources.", "SampleAfterValue": "50021", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops in which= data sources missed in the L1 cache. This does not include hardware prefet= ches. This is a precise event.", - "EventCode": "0xD1", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L3. Excludes unknow= n data source .", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "All retired load uops.", "Counter": "0,1,2,3", - "UMask": "0x10", - "Errata": "HSD29, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "All retired store uops.", "Counter": "0,1,2,3", - "UMask": "0x20", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with locked access.", "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x21" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit= in the L3 cache, but required a cross-core snoop which resulted in a HIT i= n an on-pkg core cache. This does not include hardware prefetches. This is = a precise event.", - "EventCode": "0xD2", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit= in the L3 cache, but required a cross-core snoop which resulted in a HITM = (hit modified) in an on-pkg core cache. This does not include hardware pref= etches. This is a precise event.", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired store uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches. Thi= s is a precise event.", - "EventCode": "0xD3", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD74, HSD29, HSD25, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x8" }, { - "PublicDescription": "Demand data read requests that access L2 cac= he.", - "EventCode": "0xf0", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "RFO requests that access L2 cache.", - "EventCode": "0xf0", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "L2 cache accesses when fetching instructions= .", - "EventCode": "0xf0", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, incl= uding rejects.", - "EventCode": "0xf0", + "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "L1D writebacks that access L2 cache.", - "EventCode": "0xf0", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "L2 fill requests that access L2 cache.", - "EventCode": "0xf0", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "L2 writebacks that access L2 cache.", - "EventCode": "0xf0", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Transactions accessing L2 pipe.", - "EventCode": "0xf0", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "L2 cache lines in I state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "L2 cache lines in S state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding demand data read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "L2 cache lines in E state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Dirty L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xf4", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Counts all requests hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C8FFF", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all requests hit in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "hit in the L3 and the snoop to one of the si= bling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C07F7", + "BriefDescription": "hit in the L3 and the snoop to one of the sib= ling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "hit in the L3 and the snoop to one of the sib= ling cores hits the line in M state and the line is forwarded", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C07F7", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "hit in the L3 and the snoop to one of the si= bling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "hit in the L3 and the snoops to sibling core= s hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C07F7", + "BriefDescription": "hit in the L3 and the snoops to sibling cores= hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_= FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "hit in the L3 and the snoops to sibling cores= hit in either E/S state and the line is not forwarded", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C07F7", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "hit in the L3 and the snoops to sibling core= s hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0244", + "BriefDescription": "Counts all requests hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C8FFF", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all requests hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoop to one of the sibling cores hits the line in M state and = the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0122", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoop to one of the sibling cores hits the line in M state and = the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0122", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0091", + "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0091", + "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0004", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoops to sibling cores hit in either E/S state and the line is not = forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0200", + "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0100", + "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoops to sibling cores hit in either E/S state and the line is not forw= arded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0080", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0040", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0002", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoops to sibling cores hit in either E/S state and the line= is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0020", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0040", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0010", "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", - "MSRIndex": "0x1a6, 0x1a7", + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads hit in the L3", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoops to sibling cores hit in either E/S state and the line is not = forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0004", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0020", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0002", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoops to sibling cores hit in either E/S state and the line= is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0002", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0001", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoops to sibling cores hit in either E/S state and the line is not forw= arded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0001", + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/t= ools/perf/pmu-events/arch/x86/haswell/floating-point.json index f5a3beaa19fc..55cf5b96464e 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json @@ -1,92 +1,103 @@ [ { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", + "BriefDescription": "Approximate counts of AVX & AVX2 256-bit inst= ructions, including non-arithmetic instructions, loads, and stores. May co= unt non-AVX instructions that employ 256-bit operations, including (but not= necessarily limited to) rep string instructions that use 256-bit loads and= stores for optimized performance, XSAVE* and XRSTOR*, and operations that = transition the x87 FPU data registers between x87 and MMX.", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD56, HSM57", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC6", + "EventName": "AVX_INSTS.ALL", + "PublicDescription": "Note that a whole rep string only counts AVX= _INST.ALL once.", + "SampleAfterValue": "2000003", + "UMask": "0x7" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "UMask": "0x10", - "Errata": "HSD56, HSM57", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from legacy SSE to AVX-= 256 when penalty applicable", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1e" }, { - "PublicDescription": "Note that a whole rep string only counts AVX= _INST.ALL once.", - "EventCode": "0xC6", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "AVX_INSTS.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Approximate counts of AVX & AVX2 256-bit inst= ructions, including non-arithmetic instructions, loads, and stores. May co= unt non-AVX instructions that employ 256-bit operations, including (but not= necessarily limited to) rep string instructions that use 256-bit loads and= stores for optimized performance, XSAVE* and XRSTOR*, and operations that = transition the x87 FPU data registers between x87 and MMX.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input value= s.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", + "BriefDescription": "Number of SIMD FP assists due to Output value= s", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output valu= es.", "SampleAfterValue": "100003", - "BriefDescription": "output - Numeric Overflow, Numeric Underflow,= Inexact Result", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", + "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values= .", "SampleAfterValue": "100003", - "BriefDescription": "input - Invalid Operation, Denormal Operand, = SNaN Operand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output value= s.", "SampleAfterValue": "100003", - "BriefDescription": "SSE* FP micro-code assist when output value i= s invalid.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD56, HSM57", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Any input SSE* FP Assist", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD56, HSM57", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Counts any FP_ASSIST umask was incrementing", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/p= erf/pmu-events/arch/x86/haswell/frontend.json index c0a5bedcc15c..0c8d5ccf1276 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json @@ -1,294 +1,304 @@ [ { - "PublicDescription": "Counts cycles the IDQ is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD135", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts Instruction Cache (ICACHE)= misses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", + "SampleAfterValue": "2000003", + "UMask": "0x18" }, { - "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", + "SampleAfterValue": "2000003", + "UMask": "0x24" }, { - "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one= uop. Set Cmask =3D 1.", + "SampleAfterValue": "2000003", + "UMask": "0x24" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Counts cycles MITE is delivered at least one= uop. Set Cmask =3D 1.", - "EventCode": "0x79", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD135", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts uops delivered by the Fron= t-end with the assistance of the microcode sequencer. Microcode assists ar= e used for complex instructions or scenarios that can't be handled by the s= tandard decoder. Using other instructions, if possible, will usually impro= ve performance.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the Front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance.", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the Front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", - "EventCode": "0x79", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x80", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts Instruction Cache (ICACHE)= misses.", - "EventCode": "0x80", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0x80", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFETCH_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x80", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFDATA_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts uops delivered by the Fron= t-end with the assistance of the microcode sequencer. Microcode assists ar= e used for complex instructions or scenarios that can't be handled by the s= tandard decoder. Using other instructions, if possible, will usually impro= ve performance.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "This event count the number of undelivered (= unallocated) uops from the Front-end to the Resource Allocation Table (RAT)= while the Back-end of the processor is not stalled. The Front-end can allo= cate up to 4 uops per cycle so this event can increment 0-4 times per cycle= depending on the number of unallocated uops. This event is counted on a pe= r-core basis.", - "EventCode": "0x9C", + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", "Errata": "HSD135", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event count the number of undelivered (= unallocated) uops from the Front-end to the Resource Allocation Table (RAT)= while the Back-end of the processor is not stalled. The Front-end can allo= cate up to 4 uops per cycle so this event can increment 0-4 times per cycle= depending on the number of unallocated uops. This event is counted on a pe= r-core basis.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number cycles during w= hich the Front-end allocated exactly zero uops to the Resource Allocation T= able (RAT) while the Back-end of the processor is not stalled. This event = is counted on a per-core basis.", - "EventCode": "0x9C", + "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", "Errata": "HSD135", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "This event counts the number cycles during w= hich the Front-end allocated exactly zero uops to the Resource Allocation T= able (RAT) while the Back-end of the processor is not stalled. This event = is counted on a per-core basis.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" - }, - { "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "Invert": "1", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xAB", + "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tool= s/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index f57c5f3506c2..3ade2c19533e 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -1,172 +1,125 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLO= TS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1= @) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask= \\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -176,83 +129,127 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREA= D / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_X= CLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L3MPKI" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", @@ -261,22 +258,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external m= emory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/per= f/pmu-events/arch/x86/haswell/memory.json index ef13ed88e2ea..8b69493e3726 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -1,676 +1,684 @@ [ { - "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative cache-line split store-address u= ops dispatched to L1D.", - "EventCode": "0x05", + "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional writes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD65", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an HLE execution aborted due= to none of the previous 4 categories (e.g. interrupts).", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution successfully= committed.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x54", + "BriefDescription": "Number of times an HLE execution started.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5d", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing machine clears detected. Memory ordering machine clears can result from= memory address aliasing or snoops from another hardware thread or core to = data inflight in the pipeline. Machine clears can have a significant perfo= rmance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 128.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 16.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 256.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 32.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of memory order= ing machine clears detected. Memory ordering machine clears can result from= memory address aliasing or snoops from another hardware thread or core to = data inflight in the pipeline. Machine clears can have a significant perfo= rmance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Randomly selected loads with latency value be= ing above 4.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution started.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 512.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution successfully= committed.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 64.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "HLE_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Randomly selected loads with latency value be= ing above 8.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "HLE_RETIRED.ABORTED_MISC1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xc8", + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "HLE_RETIRED.ABORTED_MISC2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split store-address u= ops dispatched to L1D.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xc8", + "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "HLE_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc8", + "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "HSD65", - "EventName": "HLE_RETIRED.ABORTED_MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times an HLE execution aborted due= to none of the previous 4 categories (e.g. interrupts).", - "EventCode": "0xc8", + "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RTM_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution started.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", + "BriefDescription": "miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RTM_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution successfully= committed.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC007F7", + "Offcore": "1", + "PublicDescription": "miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xc9", + "BriefDescription": "miss the L3 and the data is returned from loc= al dram", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RTM_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01004007F7", + "Offcore": "1", + "PublicDescription": "miss the L3 and the data is returned from lo= cal dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", - "EventCode": "0xc9", + "BriefDescription": "Counts all requests miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC08FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", + "BriefDescription": "Counts all demand code reads miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "HSD65", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", - "EventCode": "0xc9", + "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads miss the L3 and= the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "BriefDescription": "Counts demand data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads miss in the L3", "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value be= ing above 4.", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Randomly selected loads with latency value be= ing above 8.", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads miss the L3 and the= data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Randomly selected loads with latency value be= ing above 16.", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss in= the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", + "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the data is returned from local dram", "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value be= ing above 32.", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Randomly selected loads with latency value be= ing above 64.", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Randomly selected loads with latency value be= ing above 128.", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data= reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Randomly selected loads with latency value be= ing above 256.", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Randomly selected loads with latency value be= ing above 512.", - "TakenAlone": "1", - "CounterHTOff": "3" + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all requests miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC08FFF", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all requests miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "miss the L3 and the data is returned from lo= cal dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01004007F7", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "miss the L3 and the data is returned from loc= al dram", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC007F7", + "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400244", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00244", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400122", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00122", + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Errata": "HSD65", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400091", + "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00091", + "BriefDescription": "Number of times an RTM execution successfully= committed.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00200", + "BriefDescription": "Number of times an RTM execution started.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00100", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00080", + "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00040", + "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00020", + "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00010", + "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts all demand code reads miss the L3 and= the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400004", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional writes.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all demand code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00004", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400002", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts all demand data writes (RFOs) miss in= the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00002", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts demand data reads miss the L3 and the= data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400001", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Counts demand data reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00001", + "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE= ", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf= /pmu-events/arch/x86/haswell/other.json index 8a4d898d76c1..4c6b9d34325a 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/other.json @@ -1,43 +1,43 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100003", - "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/haswell/pipeline.json index 734d3873729e..a53f28ec9270 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -1,1343 +1,1305 @@ [ { - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leav= ing the programmable counters available for other events. Faulting executio= ns of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.= ", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "Errata": "HSD140, HSD143", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "PublicDescription": "This event counts the number of thread cycle= s while the thread is not in a halt state. The thread enters the halt state= when it is running the HLT instruction. The core frequency may change from= time to time due to power or thermal throttling.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. The penalty for blocked store forwarding is t= hat the load must wait for the store to write its value to the cache before= it can be issued.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "loads blocked by overlapping with store buffe= r that cannot be forwarded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline which can have a performance impact.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles spent= waiting for a recovery after an event such as a processor nuke, JEClear, a= ssist, hle/rtm abort etc.", - "EventCode": "0x0D", + "BriefDescription": "Any uop executed by the Divider. (This includ= es all divide uops, sqrt, ...)", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Core cycles the allocator was stalled due to= recovery from earlier clear event for any thread running on the physical c= ore (e.g. misprediction or memory nuke).", - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PublicDescription": "This event counts the number of uops issued = by the Front-end of the pipeline to the Back-end. This event is counted at = the allocation stage and will count both retired and non-retired uops.", - "EventCode": "0x0E", + "BriefDescription": "Speculative and retired macro-conditional bra= nches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Speculative and retired direct near calls.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Number of flags-merge uops allocated. Such u= ops add delay.", - "EventCode": "0x0E", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (for example, 2 sources + immediate) regardless of= whether it is a result of LEA instruction or not.", - "EventCode": "0x0E", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", - "EventCode": "0x0E", + "BriefDescription": "Not taken macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x14", + "BriefDescription": "Taken speculative and retired macro-condition= al branches.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ARITH.DIVIDER_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Any uop executed by the Divider. (This includ= es all divide uops, sqrt, ...)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired direct near cal= ls.", "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired indirect calls.= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x3c", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch inst= ructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", - "EventCode": "0x4c", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", - "EventCode": "0x4c", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of integer move elimination candidate= uops that were eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of integer move elimination candidate= uops that were not eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were not eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when the Reservatio= n Station ( RS ) is empty for the thread. The RS is a structure that buffer= s allocated micro-ops from the Front-end. If there are many cycles when the= RS is empty, it may represent an underflow of instructions delivered from = the Front-end.", - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x5E", - "Invert": "1", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles where the decoder i= s stalled on an instruction with a length changing prefix (LCP).", - "EventCode": "0x87", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "Counts the number of near return instruction= s retired.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x88", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x88", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near cal= ls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional bra= nches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retireme= nt.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", + "BriefDescription": "Mispredicted macro branch instructions retire= d.", "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This event counts all mispredicted branch in= structions retired. This is a precise event.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "EventCode": "0x88", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired t= hat were taken but mispredicted.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of thread cycle= s while the thread is not in a halt state. The thread enters the halt state= when it is running the HLT instruction. The core frequency may change from= time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "EventCode": "0x89", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 0 i= n this thread.", - "EventCode": "0xA1", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 data cache miss loads= . Set Cmask=3D8 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with pending L2 cache miss loads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask= =3D2 to count cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 0.", - "EventCode": "0xA1", + "BriefDescription": "Cycles with pending memory loads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set Cmask= =3D2 to count cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in por= t 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 1 i= n this thread.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls due to L2 cache misses.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "Errata": "HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 1.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls due to memory subsystem.", "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline and there we= re memory instructions pending (waiting for data).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in por= t 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", + "BriefDescription": "Stall cycles because IQ is full", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 2 i= n this thread.", - "EventCode": "0xA1", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts cycles where the decoder i= s stalled on an instruction with a length changing prefix (LCP).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "Errata": "HSD140, HSD143", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leav= ing the programmable counters available for other events. Faulting executio= ns of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.= ", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD11, HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 3 i= n this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "FP operations retired. X87 FP operations that= have no exceptions: Counts also flows that have several X87 or flows that = use X87 uops in the exception handling.", "Counter": "0,1,2,3", - "UMask": "0x8", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts FP operations retired. For X87 FP o= perations that have no exceptions counting also includes flows that have se= veral X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "This event counts the number of cycles spent= waiting for a recovery after an event such as a processor nuke, JEClear, a= ssist, hle/rtm abort etc.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 4 i= n this thread.", - "EventCode": "0xA1", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "PublicDescription": "Core cycles the allocator was stalled due to= recovery from earlier clear event for any thread running on the physical c= ore (e.g. misprediction or memory nuke).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 4.", - "EventCode": "0xA1", + "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", "Counter": "0,1,2,3", - "UMask": "0x10", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in por= t 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", + "BriefDescription": "loads blocked by overlapping with store buffe= r that cannot be forwarded", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. The penalty for blocked store forwarding is t= hat the load must wait for the store to write its value to the cache before= it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 5 i= n this thread.", - "EventCode": "0xA1", + "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline which can have a performance impact.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 5.", - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "UMask": "0x20", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in por= t 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 6 i= n this thread.", - "EventCode": "0xA1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 6.", - "EventCode": "0xA1", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in por= t 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered by the LSD.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 7 i= n this thread.", - "EventCode": "0xA1", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "PublicDescription": "Cycles allocation is stalled due to resource= related reason.", - "EventCode": "0xA2", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate= uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts cycles during which no ins= tructions were allocated because no Store Buffers (SB) were available.", - "EventCode": "0xA2", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate= uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "PublicDescription": "Number of microcode assists invoked by HW up= on uop writeback.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask= =3D2 to count cycle.", - "EventCode": "0xA3", + "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD135", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles allocation is stalled due to resource= related reason.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles with pending memory loads. Set Cmask= =3D2 to count cycle.", - "EventCode": "0xA3", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline.", - "EventCode": "0xA3", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts cycles during which no ins= tructions were allocated because no Store Buffers (SB) were available.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "This event counts cycles during which no ins= tructions were executed in the execution stage of the pipeline and there we= re memory instructions pending (waiting for data).", - "EventCode": "0xA3", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by har= dware.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "PublicDescription": "Cycles with pending L1 data cache miss loads= . Set Cmask=3D8 to count cycle.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles when the Reservatio= n Station ( RS ) is empty for the thread. The RS is a structure that buffer= s allocated micro-ops from the Front-end. If there are many cycles when the= RS is empty, it may represent an underflow of instructions delivered from = the Front-end.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "CounterMask": "8", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Number of uops delivered by the LSD.", - "EventCode": "0xa8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "This events counts the cycles where at least= one uop was executed. It is counted per thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "PublicDescription": "This events counts the cycles where at least= two uop were executed. It is counted per thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "PublicDescription": "This events counts the cycles where at least= three uop were executed. It is counted per thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", - "EventCode": "0xB1", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD30, HSM31", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "Invert": "1", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", "Counter": "0,1,2,3", - "UMask": "0x0", - "Errata": "HSD11, HSD140", - "EventName": "INST_RETIRED.ANY_P", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "This events counts the cycles where at least= one uop was executed. It is counted per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "Errata": "HSD140", - "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least= two uop were executed. It is counted per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts FP operations retired. For X87 FP operations th= at have no exceptions counting also includes flows that have several X87, o= r flows that use X87 uops in the exception handling.", - "EventCode": "0xC0", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least= three uop were executed. It is counted per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "FP operations retired. X87 FP operations that= have no exceptions: Counts also flows that have several X87 or flows that = use X87 uops in the exception handling.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "Cycles which a uop is dispatched on port 0 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "Cycles which a uop is dispatched on port 1 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 1.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops.", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Data_LA": "1" + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "Cycles which a uop is dispatched on port 2 i= n this thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles using always true condition = applied to PEBS uops retired event.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "Cycles which a uop is dispatched on port 3 i= n this thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired on core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC2", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "Cycles which a uop is dispatched on port 4 i= n this thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC3", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 4.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "Cycles which a uop is dispatched on port 5 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC3", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 5.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "Cycles which a uop is dispatched on port 6 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in por= t 6.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in p= ort 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100003", - "BriefDescription": "Direct and indirect near call instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "Cycles which a uop is dispatched on port 7 i= n this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100003", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "2", - "EventCode": "0xC4", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of uops issued = by the Front-end of the pipeline to the Back-end. This event is counted at = the allocation stage and will count both retired and non-retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100003", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC4", + "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Counts all not taken macro branch instruction= s retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such u= ops add delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC4", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of far branch instructions = retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (for example, 2 sources + immediate) regardless of= whether it is a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Mispredicted branch instructions at retireme= nt.", - "EventCode": "0xC5", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired. Use = Cmask=3D1 and invert to count active cycles or stalled cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "This event counts all mispredicted branch in= structions retired. This is a precise event.", - "EventCode": "0xC5", + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Count cases of saving new LBR records by har= dware.", - "EventCode": "0xCC", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", - "EventCode": "0xe6", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/haswell/uncore-cache.json new file mode 100644 index 000000000000..6b0639944d78 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json @@ -0,0 +1,252 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in E or S-state.", + "UMask": "0x46", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in I-state.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in M-state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in MESI-state.", + "UMask": "0x4f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in I-state.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which hits a modified line in some processor core.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a modified line in som= e processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a modified line in so= me processor core.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a modified line in some proce= ssor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which hits a non-modified line in some processor core.", + "UMask": "0x84", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a non-modified line in= some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a non-modified line i= n some processor core.", + "UMask": "0x24", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a non-modified line in some p= rocessor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop misses in some processor co= re.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop misses in some processor c= ore.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/haswell/uncore-other.json new file mode 100644 index 000000000000..8f2ae2891042 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json @@ -0,0 +1,69 @@ +[ + { + "BriefDescription": "Each cycle count number of valid entries in C= oherency Tracker queue from allocation till deallocation. Aperture requests= (snoops) appear as NC decoded internally and become coherent (snoop L3, ac= cess memory)", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of valid entries in = Coherency Tracker queue from allocation till deallocation. Aperture request= s (snoops) appear as NC decoded internally and become coherent (snoop L3, a= ccess memory).", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of entries allocated. Account for Any= type: e.g. Snoop, Core aperture, etc.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of all Core outgoing = valid entries. Such entry is defined as valid from it's allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of all Core outgoing= valid entries. Such entry is defined as valid from it's allocation till fi= rst of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coh= erent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0,", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of Core outgoing entries allocat= ed. Accounts for Coherent and non-coherent traffic.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Total number of Core outgoing entries alloca= ted. Accounts for Coherent and non-coherent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Number of Writes allocated - any write trans= actions: full/partials writes and evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "Unit": "NCU" + } +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore.json b/tools/per= f/pmu-events/arch/x86/haswell/uncore.json deleted file mode 100644 index 3ef5c21fef56..000000000000 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore.json +++ /dev/null @@ -1,374 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x21", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", - "BriefDescription": "An external snoop misses in some processor core.", - "PublicDescription": "An external snoop misses in some processor core.= ", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x41", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which misses in some processor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x81", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction whic= h misses in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction whi= ch misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x24", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", - "BriefDescription": "An external snoop hits a non-modified line in som= e processor core.", - "PublicDescription": "An external snoop hits a non-modified line in so= me processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x44", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which hits a non-modified line in some proces= sor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which hits a non-modified line in some proce= ssor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x84", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction whic= h hits a non-modified line in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction whi= ch hits a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x28", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", - "BriefDescription": "An external snoop hits a modified line in some pr= ocessor core.", - "PublicDescription": "An external snoop hits a modified line in some p= rocessor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x48", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which hits a modified line in some processor = core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which hits a modified line in some processor= core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x88", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction whic= h hits a modified line in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction whi= ch hits a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x11", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in M-state.", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x21", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in M-state.", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x41", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", - "BriefDescription": "L3 Lookup external snoop request that access cach= e and found line in M-state.", - "PublicDescription": "L3 Lookup external snoop request that access cac= he and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x81", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", - "BriefDescription": "L3 Lookup any request that access cache and found= line in M-state.", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x18", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in I-state.", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x28", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in I-state.", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x48", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", - "BriefDescription": "L3 Lookup external snoop request that access cach= e and found line in I-state.", - "PublicDescription": "L3 Lookup external snoop request that access cac= he and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x88", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", - "BriefDescription": "L3 Lookup any request that access cache and found= line in I-state.", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x1f", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in any MESI-state.", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in any MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x2f", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in MESI-state.", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x4f", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", - "BriefDescription": "L3 Lookup external snoop request that access cach= e and found line in MESI-state.", - "PublicDescription": "L3 Lookup external snoop request that access cac= he and found line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x8f", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", - "BriefDescription": "L3 Lookup any request that access cache and found= line in MESI-state.", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x86", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", - "BriefDescription": "L3 Lookup any request that access cache and found= line in E or S-state.", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x46", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", - "BriefDescription": "L3 Lookup external snoop request that access cach= e and found line in E or S-state.", - "PublicDescription": "L3 Lookup external snoop request that access cac= he and found line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x16", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in E or S-state.", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x26", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in E or S-state.", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Each cycle count number of all Core outgoing vali= d entries. Such entry is defined as valid from it's allocation till first o= f IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent= traffic.", - "PublicDescription": "Each cycle count number of all Core outgoing val= id entries. Such entry is defined as valid from it's allocation till first = of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coheren= t traffic.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Total number of Core outgoing entries allocated. = Accounts for Coherent and non-coherent traffic.", - "PublicDescription": "Total number of Core outgoing entries allocated.= Accounts for Coherent and non-coherent traffic.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Number of Writes allocated - any write transactio= ns: full/partials writes and evictions.", - "PublicDescription": "Number of Writes allocated - any write transacti= ons: full/partials writes and evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x83", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", - "BriefDescription": "Each cycle count number of valid entries in Coher= ency Tracker queue from allocation till deallocation. Aperture requests (sn= oops) appear as NC decoded internally and become coherent (snoop L3, access= memory)", - "PublicDescription": "Each cycle count number of valid entries in Cohe= rency Tracker queue from allocation till deallocation. Aperture requests (s= noops) appear as NC decoded internally and become coherent (snoop L3, acces= s memory).", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of entries allocated. Account for Any type= : e.g. Snoop, Core aperture, etc.", - "PublicDescription": "Number of entries allocated. Account for Any typ= e: e.g. Snoop, Core aperture, etc.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "NCU", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.= ", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles= .", - "Counter": "FIXED", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/haswell/virtual-memory.json index 777b500a5c9f..ba3e77a9f9a0 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json @@ -1,484 +1,484 @@ [ { - "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size.", - "EventCode": "0x08", + "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size.", "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to demand load miss= es that caused 4K page walks in any TLB levels.", + "BriefDescription": "DTLB demand load misses with low part of line= ar-to-physical address translation missed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB demand load misses with low part of lin= ear-to-physical address translation missed.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk= .", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "Completed page walks due to demand load miss= es that caused 2M/4M page walks in any TLB levels.", - "EventCode": "0x08", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M)", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts load operations from a 2M = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x08", + "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts load operations from a 4K = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", "SampleAfterValue": "2000003", - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Completed page walks in any TLB of any page = size due to demand load misses.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in any TLB of any page = size due to demand load misses.", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", - "EventCode": "0x08", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts load operations from a 4K = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to demand load miss= es that caused 2M/4M page walks in any TLB levels.", "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts load operations from a 2M = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to demand load miss= es that caused 4K page walks in any TLB levels.", "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of cache load STLB hits. No page walk= .", - "EventCode": "0x08", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", "SampleAfterValue": "2000003", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "DTLB demand load misses with low part of lin= ear-to-physical address translation missed.", - "EventCode": "0x08", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "DTLB demand load misses with low part of line= ar-to-physical address translation missed", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 4K page structure.", - "EventCode": "0x49", + "BriefDescription": "DTLB store misses with low part of linear-to-= physical address translation missed", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB store misses with low part of linear-to= -physical address translation missed.", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 2M/4M page structure.", - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts store operations from a 2M= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Completed page walks due to store miss in an= y TLB levels of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K)", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts store operations from a 4K= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB store misses.", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks due to store miss in an= y TLB levels of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "This event counts store operations from a 4K= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks. (1G)", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts store operations from a 2M= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 2M/4M page structure.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", - "EventCode": "0x49", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 4K page structure.", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "DTLB store misses with low part of linear-to= -physical address translation missed.", - "EventCode": "0x49", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB store misses.", "SampleAfterValue": "100003", - "BriefDescription": "DTLB store misses with low part of linear-to-= physical address translation missed", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x4f", + "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4f", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Misses in ITLB that causes a page walk of an= y page size.", - "EventCode": "0x85", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xae", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to misses in ITLB 4= K page entries.", - "EventCode": "0x85", + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in ITLB that causes a page walk of an= y page size.", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to misses in ITLB 2= M/4M page entries.", - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "ITLB misses that hit STLB. No page walk.", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", + "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "PublicDescription": "ITLB misses that hit STLB (2M).", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Completed page walks in ITLB of any page siz= e.", - "EventCode": "0x85", + "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K)", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "PublicDescription": "ITLB misses that hit STLB (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", + "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB of any page siz= e.", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "ITLB misses that hit STLB (4K).", - "EventCode": "0x85", + "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "ITLB misses that hit STLB (2M).", - "EventCode": "0x85", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "ITLB_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to misses in ITLB 2= M/4M page entries.", "SampleAfterValue": "100003", - "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "ITLB misses that hit STLB. No page walk.", - "EventCode": "0x85", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to misses in ITLB 4= K page entries.", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", - "EventCode": "0xae", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by ITLB misses.", "SampleAfterValue": "100003", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Number of DTLB page walker loads that hit in= the L1+FB.", - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB", "Counter": "0,1,2,3", - "UMask": "0x11", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "PublicDescription": "Number of DTLB page walker loads that hit in= the L1+FB.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L1+FB", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "PublicDescription": "Number of DTLB page walker loads that hit in= the L2.", - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L2", "Counter": "0,1,2,3", - "UMask": "0x12", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "PublicDescription": "Number of DTLB page walker loads that hit in= the L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "PublicDescription": "Number of DTLB page walker loads that hit in= the L3.", - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP", "Counter": "0,1,2,3", - "UMask": "0x14", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "PublicDescription": "Number of DTLB page walker loads that hit in= the L3.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "PublicDescription": "Number of DTLB page walker loads from memory= .", - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in Memory", "Counter": "0,1,2,3", - "UMask": "0x18", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "PublicDescription": "Number of DTLB page walker loads from memory= .", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in Memory", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "PublicDescription": "Number of ITLB page walker loads that hit in= the L1+FB.", - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L1 and FB.", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L1+FB", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PublicDescription": "Number of ITLB page walker loads that hit in= the L2.", - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L2.", "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "PublicDescription": "Number of ITLB page walker loads that hit in= the L3.", - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L3.", "Counter": "0,1,2,3", - "UMask": "0x24", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP", - "CounterHTOff": "0,1,2,3" + "UMask": "0x44" }, { - "PublicDescription": "Number of ITLB page walker loads from memory= .", - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in memory.", "Counter": "0,1,2,3", - "UMask": "0x28", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in Memory", - "CounterHTOff": "0,1,2,3" + "UMask": "0x48" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L1 and FB.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L1 and FB.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x81" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x82" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", "Counter": "0,1,2,3", - "UMask": "0x44", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L3.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x84" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in memory.", "Counter": "0,1,2,3", - "UMask": "0x48", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in memory.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x88" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "PublicDescription": "Number of ITLB page walker loads that hit in= the L1+FB.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L1 and FB.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L2", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "PublicDescription": "Number of ITLB page walker loads that hit in= the L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "PublicDescription": "Number of ITLB page walker loads that hit in= the L3.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in Memory", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "PublicDescription": "Number of ITLB page walker loads from memory= .", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in memory.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x28" }, { - "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", - "EventCode": "0xBD", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", "SampleAfterValue": "100003", - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", "SampleAfterValue": "100003", - "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C096DC433FE for ; Tue, 1 Feb 2022 02:01:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232689AbiBACBA (ORCPT ); Mon, 31 Jan 2022 21:01:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232695AbiBACAP (ORCPT ); Mon, 31 Jan 2022 21:00:15 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA156C06175F for ; Mon, 31 Jan 2022 17:59:48 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id o131-20020a25d789000000b00614957c60dfso30387742ybg.15 for ; Mon, 31 Jan 2022 17:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=HuNHJdwhmSl41bbCb1U0GMn7q9zJ4u4gg4A9+QA5fzk=; b=kz+CQh7ub+DjJTK7zDNq9KtMgdbSD+uQjTNPlUDX7rRV5skpuQO1nzTXBMlZL2ueuN tfMWDTIOSRAOlhdmDzATDxQN5EOr/LThxy9bmMcRoF3X0rzrKqKvok/96llWfdsD4iiD v1NOSyhK4TwnvMW8V49AEOgIhx8SxhJorQ2DftO0DG0co6wCDtcmG9edR2D6iquJwdtS qk9X3DOqANtqHO014nAvTB7alsZwAUjKia+40Eg5yX89pu4B8BZ2yVGzuRIvAWSsiNq/ ggOCHy+GOAfWhkBGMQr8DfHvbWeSHsbNvlHOyjvSxJzOyyw/rhdD36xwpqExN4t3aTIN ZZXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=HuNHJdwhmSl41bbCb1U0GMn7q9zJ4u4gg4A9+QA5fzk=; b=31mOGKGbnYjCeOsULi08kMlOC6kNXEDQU6FLbCoia/ALYRhg3pVdNIA5ZHA61kQ2n6 0KbV4B24qGQL8vvVJiAFNt250qY/0P2lbH69yZFwst/B6aUTPVaOprJAjnZzm9U5SKfI rPofd3xvzwCRcjt3DGsOTeB7a8Z2LTMU9Lyayc7wo13qzEbwvbmGShzQ6EL34uAvT1bC Q2GL3D7Ucy/bElfhlorrEI7zVbhZxskFbjUT954O9Wua0yDxlf1LP3aDBEUquxWDu5D/ IuaSQfIc36uFALrJzeVO/TlU0iCRhLQeLactGXv89HlO8g67yW0O5/N2gUbzzvhLS/om 5gAA== X-Gm-Message-State: AOAM530/5zJ3wdbi+CLg/ezOGcmfHv1NWs7HY/6L4tamWKOCF9HIFHAb 2LQ9KUaObMJZTDxp7+8h3lG/evaFdY6Q X-Google-Smtp-Source: ABdhPJxQyR5jkb0Ye6/bCkTl9Nu2pamDBHWDmRv7l4qz0ks7I2vWOw4rfniWmDLKBbMcJD2b33blsRRvIP6z X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a05:6902:110b:: with SMTP id o11mr32566998ybu.331.1643680788025; Mon, 31 Jan 2022 17:59:48 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:47 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-16-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 15/26] perf vendor events: Update metrics for Icelake From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are updated to version 1.12: https://download.01.org/perfmon/ICL Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on an Icelake, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/icelake/cache.json | 658 +++++----- .../arch/x86/icelake/floating-point.json | 69 +- .../pmu-events/arch/x86/icelake/frontend.json | 449 +++---- .../arch/x86/icelake/icl-metrics.json | 338 ++++-- .../pmu-events/arch/x86/icelake/memory.json | 591 +++++---- .../pmu-events/arch/x86/icelake/other.json | 630 +++++----- .../pmu-events/arch/x86/icelake/pipeline.json | 1081 +++++++++-------- .../arch/x86/icelake/virtual-memory.json | 178 +-- 8 files changed, 2116 insertions(+), 1878 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf= /pmu-events/arch/x86/icelake/cache.json index 49fe78fb6538..96dcd387c70e 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -1,89 +1,78 @@ [ { - "BriefDescription": "L2 code requests", + "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_CODE_RD", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of L2 code requests.= ", - "SampleAfterValue": "200003", + "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xe4" - }, - { - "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the retired load instructions whose d= ata sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Demand requests that miss L2 cache", + "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts demand requests that miss L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x27" + "UMask": "0x2" }, { - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailablability.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xb0", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts number of phases a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x2" }, { - "BriefDescription": "RFO requests that hit L2 cache", + "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_HIT", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.L2_STALL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0xc2" + "UMask": "0x4" }, { - "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "BriefDescription": "Number of L1D misses that are outstanding", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.FB_HIT", - "PEBS": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", - "SampleAfterValue": "100007", - "UMask": "0x40" + "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "BriefDescription": "Cycles with L1D load Misses outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", + "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1" }, { "BriefDescription": "L2 cache lines filling L2", @@ -98,127 +87,124 @@ "UMask": "0x1f" }, { - "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", - "PEBS": "1", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.NON_SILENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that split = across a cacheline boundary.", - "SampleAfterValue": "100003", - "UMask": "0x41" + "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_HIT", - "PEBS": "1", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.SILENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", - "SampleAfterValue": "100021", - "UMask": "0x4" + "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Demand Data Read miss L2, no rejects", + "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "EventCode": "0xf2", + "EventName": "L2_LINES_OUT.USELESS_HWPF", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", + "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x21" + "UMask": "0x4" }, { - "BriefDescription": "L2 cache misses when fetching instructions", + "BriefDescription": "L2 code requests", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", + "EventName": "L2_RQSTS.ALL_CODE_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", + "PublicDescription": "Counts the total number of L2 code requests.= ", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x24" + "UMask": "0xe4" }, { - "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "BriefDescription": "Demand Data Read requests", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0xe1" }, { - "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "BriefDescription": "Demand requests that miss L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "L1D.REPLACEMENT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x27" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Demand requests to L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "PEBS": "1", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", - "SampleAfterValue": "1000003", - "UMask": "0x81" + "PublicDescription": "Counts demand requests to L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe7" }, { - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "RFO requests to L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF0", - "EventName": "L2_TRANS.L2_WB", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x40" + "UMask": "0xe2" }, { - "BriefDescription": "Demand Data Read requests", + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "EventName": "L2_RQSTS.CODE_RD_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", + "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0xe1" + "UMask": "0xc4" }, { - "BriefDescription": "Demand Data Read transactions pending for off= -core. Highly correlated.", + "BriefDescription": "L2 cache misses when fetching instructions", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of off-core outstanding De= mand Data Read transactions every cycle. A transaction is considered to be = in the Off-core outstanding state between L2 cache miss and data-return to = the core.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x24" }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", @@ -233,131 +219,101 @@ "UMask": "0xc1" }, { - "BriefDescription": "Cycles the superQ cannot take any more entrie= s.", + "BriefDescription": "Demand Data Read miss L2, no rejects", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xf4", - "EventName": "SQ_MISC.SQ_FULL", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles for which the thread is ac= tive and the superQ cannot take any more entries.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x21" }, { - "BriefDescription": "Cycles with L1D load Misses outstanding.", + "BriefDescription": "RFO requests that hit L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0xc2" }, { - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "RFO requests that miss L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xb0", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x22" }, { - "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "BriefDescription": "SW prefetch requests that hit L2 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_HIT", - "PEBS": "1", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", - "SampleAfterValue": "1000003", - "UMask": "0x1" + "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc8" }, { - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "BriefDescription": "SW prefetch requests that miss L2 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when offcore outstanding cache= able Core Data Read transactions are present in the super queue. A transact= ion is considered to be in the Offcore outstanding state between L2 miss an= d transaction completion sent to requestor (SQ de-allocation). See correspo= nding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x28" }, { - "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "BriefDescription": "L2 writebacks that access L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of offcore outstanding dem= and rfo Reads transactions in the super queue every cycle. The 'Offcore out= standing' state of the transaction lasts from the L2 miss until the sending= transaction completion to requestor (SQ deallocation). See the correspondi= ng Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x40" }, { - "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.L2_STALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", - "SampleAfterValue": "1000003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with L2 cac= he hits as data sources.", - "SampleAfterValue": "200003", - "UMask": "0x2" + "UMask": "0x41" }, { - "BriefDescription": "Retired load instructions with locked access.= ", + "BriefDescription": "All retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.LOCK_LOADS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with locked= access.", - "SampleAfterValue": "100007", - "UMask": "0x21" - }, - { - "BriefDescription": "Retired load instructions missed L3 cache as = data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", - "SampleAfterValue": "50021", - "UMask": "0x20" + "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", + "SampleAfterValue": "1000003", + "UMask": "0x81" }, { "BriefDescription": "All retired store instructions.", @@ -374,102 +330,97 @@ "UMask": "0x82" }, { - "BriefDescription": "Demand requests to L2 cache", + "BriefDescription": "All retired memory instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts demand requests to L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe7" + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" }, { - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "BriefDescription": "Retired load instructions with locked access.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc4" + "PublicDescription": "Counts retired load instructions with locked= access.", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "BriefDescription": "Demand and prefetch data reads", + "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x2e", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches from L1 and L2. It does not include all misses to the L3.", + "PublicDescription": "Counts retired load instructions that split = across a cacheline boundary.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "UMask": "0x41" }, { - "BriefDescription": "SW prefetch requests that miss L2 cache.", + "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_MISS", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instru= ctions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x28" + "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { - "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "BriefDescription": "Retired load instructions that miss the STLB.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", - "SampleAfterValue": "200003", - "UMask": "0x8" + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "BriefDescription": "Number of L1D misses that are outstanding", + "BriefDescription": "Retired store instructions that miss the STLB= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailablability.", + "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of phases a demand request has= waited due to L1D Fill Buffer (FB) unavailablability. Demand requests incl= ude cacheable/uncacheable demand load, store, lock or SW prefetch accesses.= ", - "SampleAfterValue": "1000003", - "Speculative": "1", + "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", "UMask": "0x2" }, { @@ -486,17 +437,17 @@ "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose d= ata sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "SampleAfterValue": "20011", - "UMask": "0x2" + "UMask": "0x1" }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", @@ -512,30 +463,56 @@ "UMask": "0x8" }, { - "BriefDescription": "Retired store instructions that miss the STLB= .", + "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "L1_Hit_Indication": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that true = miss the STLB.", - "SampleAfterValue": "100003", - "UMask": "0x12" + "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "BriefDescription": "RFO requests to L2 cache", + "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_RFO", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe2" + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with L2 cac= he hits as data sources.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", @@ -551,113 +528,150 @@ "UMask": "0x10" }, { - "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", - "SampleAfterValue": "1000003", - "Speculative": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", + "SampleAfterValue": "100021", "UMask": "0x4" }, { - "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "Retired load instructions missed L3 cache as = data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.SILENT", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "BriefDescription": "Counts memory transactions sent to the uncore= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", + "PublicDescription": "Counts memory transactions sent to the uncor= e including requests initiated by the core, all L3 prefetches, reads result= ing from page walks, and snoop responses.", "SampleAfterValue": "100003", - "UMask": "0x42" + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "SW prefetch requests that hit L2 cache.", + "BriefDescription": "Demand Data Read requests sent to uncore", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_HIT", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instruc= tions.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xc8" + "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions that miss the STLB.= ", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", - "PEBS": "1", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that true m= iss the STLB.", + "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", "SampleAfterValue": "100003", - "UMask": "0x11" + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "RFO requests that miss L2 cache", + "BriefDescription": "For every cycle, increments by the number of = outstanding data read requests pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_MISS", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", - "SampleAfterValue": "200003", + "PublicDescription": "For every cycle, increments by the number of= outstanding data read requests pending. Data read requests include cachea= ble demand reads and L2 prefetches, but do not include RFOs, code reads or = prefetches to the L3. Reads due to page walks resulting from any request t= ype will also be counted. Requests are considered outstanding from the tim= e they miss the core's L2 cache until the transaction completion message is= sent to the requestor.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x22" + "UMask": "0x8" }, { - "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "BriefDescription": "Cycles where at least 1 outstanding data read= request is pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.NON_SILENT", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", - "SampleAfterValue": "200003", + "PublicDescription": "Cycles where at least 1 outstanding data rea= d request is pending. Data read requests include cacheable demand reads an= d L2 prefetches, but do not include RFOs, code reads or prefetches to the L= 3. Reads due to page walks resulting from any request type will also be co= unted. Requests are considered outstanding from the time they miss the cor= e's L2 cache until the transaction completion message is sent to the reques= tor.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Any memory transaction that reached the SQ.", + "BriefDescription": "Cycles where at least 1 outstanding Demand RF= O request is pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", - "SampleAfterValue": "100003", + "PublicDescription": "Cycles where at least 1 outstanding Demand R= FO request is pending. RFOs are initiated by a core as part of a data sto= re operation. Demand RFO requests include RFOs, locks, and ItoM transactio= ns. Requests are considered outstanding from the time they miss the core's= L2 cache until the transaction completion message is sent to the requestor= .", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x4" }, { - "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xf2", - "EventName": "L2_LINES_OUT.USELESS_HWPF", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", - "SampleAfterValue": "200003", + "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles the queue waiting for offcore response= s is full.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SQ_FULL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles for which the thread is ac= tive and the queue waiting for responses from the uncore cannot take any mo= re entries.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" } diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/icelake/floating-point.json index 5391c4f6eca3..4347e2d0d090 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json @@ -1,95 +1,102 @@ [ { - "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "BriefDescription": "Counts all microcode FP assists.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "EventCode": "0xc1", + "EventName": "ASSISTS.FP", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all microcode Floating Point assists.= ", "SampleAfterValue": "100003", - "UMask": "0x40" + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of SSE/AVX computational 128-b= it packed single precision floating-point instructions retired; some instru= ctions will count twice as noted below. Each count represents 4 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MI= N MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions c= ount twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x8" + "UMask": "0x4" }, { - "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed double= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x80" + "UMask": "0x8" }, { - "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x10" }, { - "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x4" + "UMask": "0x20" }, { - "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x20" + "UMask": "0x40" }, { - "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x2" + "UMask": "0x80" }, { - "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", - "UMask": "0x10" + "UMask": "0x1" }, { - "BriefDescription": "Counts all microcode FP assists.", + "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc1", - "EventName": "ASSISTS.FP", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all microcode Floating Point assists.= ", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", - "Speculative": "1", "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/frontend.json b/tools/p= erf/pmu-events/arch/x86/icelake/frontend.json index 4fa2a4186ee3..b510dd5d80da 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelake/frontend.json @@ -11,14 +11,40 @@ "Speculative": "1", "UMask": "0x1" }, + { + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of Decode Stream Buffer (D= SB a.k.a. Uop Cache)-to-MITE speculative transitions.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.DSB_MISS", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x11", + "MSRValue": "0x1", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", @@ -27,17 +53,19 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", @@ -55,155 +83,80 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "5", - "EventCode": "0x9c", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "ICACHE_16B.IFDATA_STALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x510006", + "MSRValue": "0x12", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 25= 6 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired Instructions who experienced = Instruction L1 Cache true miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delive= red to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) p= ath.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x100206", + "MSRValue": "0x13", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", + "PublicDescription": "Counts retired Instructions who experienced = Instruction L2 Cache true miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "DSB-to-MITE switch true penalty cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.STLB_MISS", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", - "MSRValue": "0x15", + "MSRValue": "0x500106", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", + "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.MITE_UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", - "MSRValue": "0x504006", + "MSRValue": "0x508006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 64= cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 12= 8 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", - "MSRValue": "0x502006", + "MSRValue": "0x501006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, - { - "BriefDescription": "Cycles MITE is delivering any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. During these cycles uops are not being delivered from the Decod= e Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", "CollectPEBSRecord": "2", @@ -220,113 +173,91 @@ "UMask": "0x1" }, { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of Decode Stream Buffer (D= SB a.k.a. Uop Cache)-to-MITE speculative transitions.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.DSB_UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.L2_MISS", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", - "MSRValue": "0x13", + "MSRValue": "0x510006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions who experienced = Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 25= 6 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", - "Speculative": "1", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", - "MSRValue": "0x520006", + "MSRValue": "0x502006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 51= 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "Invert": "1", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "MSRIndex": "0x3F7", + "MSRValue": "0x500406", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 4 = cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", - "MSRValue": "0x501006", + "MSRValue": "0x520006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 51= 2 cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", - "MSRValue": "0x508006", + "MSRValue": "0x504006", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 12= 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 64= cycles which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" @@ -347,48 +278,55 @@ "UMask": "0x1" }, { - "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x500106", + "MSRValue": "0x15", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", - "MSRIndex": "0x3F7", - "MSRValue": "0x500406", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 4 = cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE_16B.IFDATA_STALL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", + "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_SWITCHES", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x30" + "UMask": "0x2" }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", @@ -403,28 +341,80 @@ "UMask": "0x4" }, { - "BriefDescription": "Uops delivered to IDQ while MS is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x79", - "EventName": "IDQ.MS_UOPS", + "EventName": "IDQ.DSB_CYCLES_ANY", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts the number of cycles uops were delive= red to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) p= ath.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x30" + "UMask": "0x8" }, { - "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_MISS", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_OK", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. During these cycles uops are not being delivered from the Decod= e Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", @@ -440,32 +430,30 @@ "UMask": "0x30" }, { - "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "BriefDescription": "Number of switches from DSB or MITE to the MS= ", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.L1I_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x12", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions who experienced = Instruction L1 Cache true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x30" }, { - "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "BriefDescription": "Uops delivered to IDQ while MS is busy", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "5", "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_OK", + "EventName": "IDQ.MS_UOPS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x30" }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", @@ -478,5 +466,32 @@ "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index 432e45ac6814..4af23c04dc18 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -1,272 +1,452 @@ [ { - "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED= .NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 *= BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_= STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHAL= TED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TO= PDOWN.SLOTS)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", - "MetricGroup": "Summary", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { - "MetricExpr": "UOPS_RETIRED.SLOTS / INST_RETIRED.ANY", "BriefDescription": "Uops Per Instruction", - "MetricGroup": "Pipeline;Retire", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Instruction per taken branch", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricGroup": "Pipeline", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", + "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on el= se 1", + "MetricGroup": "SMT", + "MetricName": "Slots_Utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", "BriefDescription": "Floating Point Operations Per Cycle", - "MetricGroup": "Flops", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { - "MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_= GE_1 / 2 )", + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricGroup": "BrMispredicts", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", "MetricGroup": "InsType", "MetricName": "IpLoad" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", "MetricGroup": "InsType", "MetricName": "IpStore" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", - "MetricGroup": "Branches;InsType", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", - "MetricGroup": "Branches", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, { - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { "BriefDescription": "Branch instructions per taken branch. ", - "MetricGroup": "Branches;PGO", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.25= 6B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARI= TH_INST_RETIRED.512B_PACKED_SINGLE )", "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricGroup": "Flops;FpArith;InsType", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.25= 6B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARI= TH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SI= NGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", - "BriefDescription": "Total number of retired Instructions", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, { - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, + { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", - "MetricGroup": "LSD", + "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricGroup": "DSB;FetchBW", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { + "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_B= RANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BR= ANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_= RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_= TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not indi= vidually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRE= D.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHE= S) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST= _RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.CON= D_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", + "MetricGroup": "Bad;Branches", + "MetricName": "Other_Branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, { - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIB= UTED )", - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricGroup": "MemoryBW", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricGroup": "MemoryBW", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricGroup": "MemoryBW", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricGroup": "MemoryBW;Offcore", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricGroup": "CacheMisses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, + { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricGroup": "CacheMisses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_R= EQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) = / INST_RETIRED.ANY", "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", - "MetricGroup": "CacheMisses;Offcore", + "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_R= EQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) = / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricGroup": "CacheMisses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIB= UTED )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, { - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", "MetricGroup": "Summary;Power", "MetricName": "Average_Frequency" }, { - "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricGroup": "Flops;HPC", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, { - "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_DISTRIBUTED", + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." + }, + { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_DISTRIBUTED if #SMT_on else 0", "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, { - "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "Branches;OS", "MetricName": "IpFarBranch" }, { - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Core_Residency" }, { - "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per core", + "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Core_Residency" }, { - "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Core_Residency" }, { - "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C2_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per package", + "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" } diff --git a/tools/perf/pmu-events/arch/x86/icelake/memory.json b/tools/per= f/pmu-events/arch/x86/icelake/memory.json index 3701bd93a462..f045e1f6a868 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/memory.json @@ -1,15 +1,27 @@ [ { - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x6" }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", @@ -23,50 +35,15 @@ "UMask": "0x4" }, { - "BriefDescription": "Counts demand data reads that was not supplie= d by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", - "PEBS": "2", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "20011", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that was not supplied by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "PublicDescription": "Counts the number of times an HLE execution = aborted due to unfriendly events (such as interrupts).", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "UMask": "0x80" }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", @@ -80,185 +57,231 @@ "UMask": "0x8" }, { - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to attempting an unsupported alignment from Lock Buffer.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an HLE execution = aborted due to HLE-unfriendly instructions and certain unfriendly events (s= uch as AD assists etc.).", "SampleAfterValue": "100003", - "Speculative": "1", "UMask": "0x20" }, { - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "BriefDescription": "Number of times an HLE execution successfully= committed", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to commit but Lock Buffer not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times HLE commit succee= ded.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" + "UMask": "0x2" }, { - "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", + "BriefDescription": "Number of times an HLE execution started.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC3", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", + "PublicDescription": "Counts the number of times we entered an HLE= region. Does not count nested transactions.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", + "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC2", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", + "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles where data return is pending for a Dem= and Data Read request who miss L3 cache.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Cycles with at least 1 Demand Data Read requ= ests who miss L3 cache in the superQ.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that was no= t supplied by the L3 cache.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "MSRValue": "0x200", + "MSRValue": "0x100", "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "101", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "503", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution successfully= committed", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.COMMIT", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM commit succee= ded.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution = aborted due to unfriendly events (such as interrupts).", - "SampleAfterValue": "100003", - "UMask": "0x80" + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution successfully= committed", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.COMMIT", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times HLE commit succee= ded.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x40" + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "BriefDescription": "Counts demand data reads that was not supplie= d by the L3 cache.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that was no= t supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00002", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to release/commit but data and address mismatch.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that was not supplied= by the L3 cache.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that was not supplied by the L3 cache.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_MISS", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00800", + "MSRValue": "0x3FFFC00400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -267,16 +290,34 @@ "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00020", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x1" }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that was not supplied by the L3 cache.", @@ -294,13 +335,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that was not supplied by the L3 cache.", + "BriefDescription": "Counts streaming stores that was not supplied= by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00020", + "MSRValue": "0x3FFFC00800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -309,39 +350,39 @@ "UMask": "0x1" }, { - "BriefDescription": "Demand Data Read requests who miss L3 cache", + "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "BriefDescription": "Cycles where at least one demand data read re= quest known to have missed the L3 cache is pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "2", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least one demand data read r= equest known to have missed the L3 cache is pending. Note that this does n= ot capture all elapsed cycles while requests are outstanding - only cycles = from when the requests were known to have missed the L3 cache.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x10" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "BriefDescription": "Number of times an RTM execution aborted.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "EventName": "RTM_RETIRED.ABORTED", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", + "PublicDescription": "Counts the number of times RTM abort was tri= ggered.", "SampleAfterValue": "100003", - "UMask": "0x20" + "UMask": "0x4" }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", @@ -355,208 +396,154 @@ "UMask": "0x80" }, { - "BriefDescription": "Number of times an HLE execution started.", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.START", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEM", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an HLE= region. Does not count nested transactions.", + "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", + "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" + "UMask": "0x40" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times we could not allo= cate Lock Buffer.", + "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x40" + "UMask": "0x20" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "BriefDescription": "Number of times an RTM execution successfully= committed", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts the number of times RTM commit succee= ded.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "BriefDescription": "Number of times an RTM execution started.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", + "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "6", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEM", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", "SampleAfterValue": "100003", - "UMask": "0x8" + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that was not supplied by the L3 cache.= ", + "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00400", - "Offcore": "1", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that was not supplied by the L3 cache.", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00004", - "Offcore": "1", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted.", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM abort was tri= ggered.", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to release/commit but data and address mismatch.", "SampleAfterValue": "100003", - "UMask": "0x4" + "Speculative": "1", + "UMask": "0x10" }, { - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.START", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to commit but Lock Buffer not empty.", "SampleAfterValue": "100003", - "UMask": "0x1" + "Speculative": "1", + "UMask": "0x8" }, { - "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution = aborted due to HLE-unfriendly instructions and certain unfriendly events (s= uch as AD assists etc.).", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to attempting an unsupported alignment from Lock Buffer.", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x20" }, { @@ -570,5 +557,17 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times we could not allo= cate Lock Buffer.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf= /pmu-events/arch/x86/icelake/other.json index a806b00f8616..10e8582774ce 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json @@ -1,27 +1,60 @@ [ { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was no= t needed to satisfy the request.", + "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", - "Offcore": "1", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for baseline license level 0. This includes non-AVX = codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x7" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", + "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for license level 1. This includes high current AVX = 256-bit instructions as well as low current AVX 512-bit instructions.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x18" + }, + { + "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarcht= ecture). This includes high current AVX 512-bit instructions.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.DRAM", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000020", + "MSRValue": "0x10004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -30,13 +63,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.LOCAL_DRAM", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184008000", + "MSRValue": "0x184000004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -45,13 +78,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000010", + "MSRValue": "0x3FC03C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -60,13 +93,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another cores caches, data forward= ing is required as the data is modified.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another cores caches, data forwarding is required as the data is modified= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", + "MSRValue": "0x10003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -75,25 +108,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent but no other cores had the data.= ", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x2003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -102,13 +138,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was n= ot needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x1003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -117,13 +153,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent or not.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0400", + "MSRValue": "0x1E003C0004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -132,13 +168,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.DRAM", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184008000", + "MSRValue": "0x184000004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -147,13 +183,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "BriefDescription": "Counts demand data reads that have any type o= f response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -162,13 +198,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt but no other cores had the data.", + "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x184000001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -177,13 +213,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x3FC03C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -192,25 +228,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by branch mispredictions. This event estimates number= of operations that were issued but not retired from the specualtive path a= s well as the out-of-order engine recovery past a branch misprediction.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was not neede= d to satisfy the request.", + "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches, data forwarding is re= quired as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x10003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -219,13 +243,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that have any type of= response.", + "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another core, data forwarding is not requir= ed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010800", + "MSRValue": "0x4003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -234,13 +258,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", + "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.DRAM", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000800", + "MSRValue": "0x2003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -249,13 +273,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that have any type of response.", + "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x1003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -264,13 +288,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches, data forwarding is re= quired as the data is modified.", + "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", + "MSRValue": "0x1E003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -279,13 +303,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", + "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000010", + "MSRValue": "0x184000001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -294,13 +318,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C8000", + "MSRValue": "0x10002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -309,13 +333,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that have any type of response.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x184000002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -324,13 +348,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent or n= ot.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0010", + "MSRValue": "0x3FC03C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -339,25 +363,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another cores caches, data forward= ing is required as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for license level 1. This includes high current AVX = 256-bit instructions as well as low current AVX 512-bit instructions.", - "SampleAfterValue": "200003", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x18" + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another core, data forwarding is n= ot required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x4003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -366,13 +393,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent but no other cores had the data.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0001", + "MSRValue": "0x2003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -381,13 +408,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0010", + "MSRValue": "0x1003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -396,13 +423,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000001", + "MSRValue": "0x1E003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -411,13 +438,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000800", + "MSRValue": "0x184000002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -426,13 +453,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000004", + "MSRValue": "0x10400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -441,13 +468,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was n= ot needed to satisfy the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x184000400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -456,13 +483,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000020", + "MSRValue": "0x3FC03C0400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -471,13 +498,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000004", + "MSRValue": "0x2003C0400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -486,13 +513,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another core, data forwarding is n= ot required.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was not needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x1003C0400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -501,13 +528,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent but no other cores had the data.", + "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", + "MSRValue": "0x184000400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -516,13 +543,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0020", + "MSRValue": "0x10010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -531,13 +558,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r core, data forwarding is not required.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x184000010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -546,13 +573,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another core, data forwarding is not requir= ed.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent or n= ot.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x3FC03C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -561,13 +588,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r cores caches, data forwarding is required as the data is modified.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0020", + "MSRValue": "0x10003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -576,13 +603,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x4003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -591,13 +618,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in= another core, data forwarding is not required.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent but = no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x2003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -606,36 +633,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "35", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was not neede= d to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0001", + "MSRValue": "0x1003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -644,13 +648,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000400", + "MSRValue": "0x1E003C0010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -659,25 +663,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was not needed to sa= tisfy the request.", + "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x184000010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -686,25 +678,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another cores caches, data forwarding is required as the data is modified= .", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", + "MSRValue": "0x10020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -713,13 +693,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that have any type o= f response.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x184000020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -728,13 +708,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another core, data forwarding is not required.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x3FC03C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -758,13 +738,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that have any type of response.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop hit in another core,= data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.ANY_RESPONSE", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x4003C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -773,25 +753,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHW instructions executed.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent but no othe= r cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was not needed to sa= tisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0010", + "MSRValue": "0x1003C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -800,13 +783,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000400", + "MSRValue": "0x1E003C0020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -815,13 +798,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", + "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.DRAM", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000002", + "MSRValue": "0x184000020", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -830,25 +813,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc1", - "EventName": "ASSISTS.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x7" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent but = no other cores had the data.", + "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit a cacheline in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x3FC03C2380", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -857,13 +828,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent or not.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", + "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0004", + "MSRValue": "0x18000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -872,25 +843,28 @@ "UMask": "0x1" }, { - "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184008000", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarcht= ecture). This includes high current AVX 512-bit instructions.", - "SampleAfterValue": "200003", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that hit a cacheline = in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in= another core, data forwarding is not required.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0800", + "MSRValue": "0x4003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -899,13 +873,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent but no othe= r cores had the data.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt but no other cores had the data.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -914,13 +888,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was no= t needed to satisfy the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000001", + "MSRValue": "0x1003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -929,13 +903,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0004", + "MSRValue": "0x1E003C8000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -944,13 +918,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", + "EventName": "OCR.OTHER.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0002", + "MSRValue": "0x184008000", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -959,13 +933,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts streaming stores that have any type of= response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L3.L3_HIT.ANY", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C2380", + "MSRValue": "0x10800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -974,25 +948,13 @@ "UMask": "0x1" }, { - "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was not needed to satisfy the request.", + "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.STREAMING_WR.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x184000800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -1001,13 +963,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts streaming stores that hit a cacheline = in the L3 where a snoop was sent or not.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0002", + "MSRValue": "0x3FC03C0800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -1016,13 +978,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that have any type of response.", + "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x184000800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -1031,60 +993,98 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000002", - "Offcore": "1", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "BriefDescription": "Number of PREFETCHW instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for baseline license level 0. This includes non-AVX = codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x7" + "UMask": "0x8" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop hit in another core,= data forwarding is not required.", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", - "Offcore": "1", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent but no other cores had the data.", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", - "Offcore": "1", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", "SampleAfterValue": "100003", "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by branch mispredictions. This event estimates number= of operations that were issued but not retired from the specualtive path a= s well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/p= erf/pmu-events/arch/x86/icelake/pipeline.json index 4f4ce309c2f8..2b305bdc8cfc 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json @@ -1,50 +1,39 @@ [ { - "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired mispredicted indirect (near t= aken) CALL instructions, including both register and memory indirect.", - "SampleAfterValue": "50021", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of uops executed on the core.", + "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE", + "CounterMask": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops executed from any = thread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts cycles when divide unit is busy execu= ting divide or square root operations. Accounts for integer and floating-po= int operations.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x9" }, { - "BriefDescription": "Number of uops executed on port 4 and 9", + "BriefDescription": "All branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_4_9", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" + "PublicDescription": "Counts all branch instructions retired.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "BriefDescription": "Conditional branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.THREAD", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts conditional branch instructions retir= ed.", + "SampleAfterValue": "400009", + "UMask": "0x11" }, { "BriefDescription": "Not taken branch instructions retired.", @@ -59,66 +48,64 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "BriefDescription": "Taken conditional branch instructions retired= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts taken conditional branch instructions= retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "BriefDescription": "Far branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "BriefDescription": "All indirect branch instructions retired (exc= luding RETs. TSX aborts are considered indirect branch).", + "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions reti= red (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts near indirect branch instructions ret= ired excluding returns. TSX abort is an indirect branch.", "SampleAfterValue": "100003", "UMask": "0x80" }, { - "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" + "PublicDescription": "Counts both direct and indirect near call in= structions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "BriefDescription": "Number of uops executed on port 2 and 3", + "BriefDescription": "Return instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_2_3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" + "PublicDescription": "Counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { "BriefDescription": "Taken branch instructions retired.", @@ -133,188 +120,192 @@ "UMask": "0x20" }, { - "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "BriefDescription": "All mispredicted branch instructions retired.= ", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x4c", - "EventName": "LOAD_HIT_PREFETCH.SWPF", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", + "SampleAfterValue": "50021" }, { - "BriefDescription": "Number of uops executed on port 1", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts mispredicted conditional branch instr= uctions retired.", + "SampleAfterValue": "50021", + "UMask": "0x11" }, { - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xa8", - "EventName": "LSD.UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of conditional branch inst= ructions retired that were mispredicted and the branch direction was not ta= ken.", + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "BriefDescription": "Number of uops executed on port 5", + "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken. Non PEBS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x20" + "PublicDescription": "Counts taken conditional mispredicted branch= instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x1" }, { - "BriefDescription": "Number of uops executed on port 6", + "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_6", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x40" + "PublicDescription": "Counts all miss-predicted indirect branch in= structions retired (excluding RETs. TSX aborts is considered indirect branc= h).", + "SampleAfterValue": "50021", + "UMask": "0x80" }, { - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_ACTIVE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when at least one uop is d= elivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired mispredicted indirect (near t= aken) CALL instructions, including both register and memory indirect.", + "SampleAfterValue": "50021", + "UMask": "0x2" }, { - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts number of near branch instructions re= tired that were mispredicted and taken.", + "SampleAfterValue": "50021", + "UMask": "0x20" }, { - "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles where the Store Buffer was ful= l and no loads caused an execution stall.", - "SampleAfterValue": "1000003", + "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x40" + "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", + "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", "SampleAfterValue": "25003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", - "SampleAfterValue": "500009", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "BriefDescription": "Reference cycles when the core is not in halt= state.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", - "SampleAfterValue": "100003", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x3" }, { - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5e", - "EventName": "RS_EVENTS.EMPTY_CYCLES", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into stravation periods (e.g. branch mispredi= ctions or i-cache misses)", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", + "SampleAfterValue": "25003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "BriefDescription": "Core cycles when the thread is not in halt st= ate", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", - "SampleAfterValue": "100003", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "Invert": "1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event counts cycles without actually re= tired uops.", + "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "SampleAfterValue": "2000003", + "Speculative": "1" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts far branch instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x40" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", @@ -329,160 +320,169 @@ "UMask": "0x10" }, { - "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.ANY", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "Counter": "0,1,2,3", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xc" }, { - "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SCOREBOARD", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x5" }, { - "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.LBR_INSERTS", + "CounterMask": "20", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", - "SampleAfterValue": "100003", - "UMask": "0x20" + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x14" }, { - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "BriefDescription": "Total execution stalls.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc0", - "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003" + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Counts the number of x87 uops dispatched.", + "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.X87", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of x87 uops executed.", + "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x2" }, { - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 2 micro-ops are = executed from any thread on physical core.", + "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x4" }, { - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SB", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", - "SampleAfterValue": "100003", + "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x8" }, { - "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x10" }, { - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.COUNT", + "CounterMask": "2", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of machine clears (nukes) = of any type.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts cycles where the Store Buffer was ful= l and no loads caused an execution stall.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "500009", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of near branch instructions re= tired that were mispredicted and taken.", - "SampleAfterValue": "50021", - "UMask": "0x20" + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Return instructions retired.", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts return instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x8" + "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "BriefDescription": "Number of all retired NOP instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x14", - "EventName": "ARITH.DIVIDER_ACTIVE", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when divide unit is busy execu= ting divide or square root operations. Accounts for integer and floating-po= int operations.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x9" + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { "BriefDescription": "Cycles without actually retired instructions.= ", @@ -499,241 +499,221 @@ "UMask": "0x1" }, { - "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of conditional branch inst= ructions retired that were mispredicted and the branch direction was not ta= ken.", - "SampleAfterValue": "50021", - "UMask": "0x10" - }, - { - "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "CollectPEBSRecord": "2", - "Counter": "33", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles the Backend cluster is recover= ing after a miss-speculation or a Store Buffer or Load Buffer drain stall.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x3" }, { - "BriefDescription": "Taken conditional branch instructions retired= .", + "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", + "EventCode": "0x0d", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional branch instructions= retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" + "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Direct and indirect near call instructions re= tired.", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts both direct and indirect near call in= structions retired.", - "SampleAfterValue": "100007", - "UMask": "0x2" + "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "TMA slots where uops got dropped", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "EventCode": "0x0d", + "EventName": "INT_MISC.UOP_DROPPING", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 4 micro-ops are = executed from any thread on physical core.", - "SampleAfterValue": "2000003", + "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", - "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.PREC_DIST", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x10" }, { - "BriefDescription": "Total execution stalls.", + "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x8" }, { - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xc" + "UMask": "0x2" }, { - "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", + "BriefDescription": "False dependencies due to partial compare on = address.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.PAUSE_INST", - "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies due to partial compare on address.", "SampleAfterValue": "100003", - "UMask": "0x40" + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.SMC", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", + "Counter": "0,1,2,3", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Uops that RAT issues to RS", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles when at least one uop is d= elivered by the LSD (Loop-stream detector).", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "5", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_OK", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the cycles when optimal number of uop= s is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x5" + "UMask": "0x1" }, { - "BriefDescription": "Reference cycles when the core is not in halt= state.", + "BriefDescription": "Number of Uops delivered by the LSD.", "CollectPEBSRecord": "2", - "Counter": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PEBScounters": "34", - "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", + "Counter": "0,1,2,3", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x3" + "UMask": "0x1" }, { - "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x0D", - "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles the Backend cluster is recover= ing after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of machine clears (nukes) = of any type.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x3" + "UMask": "0x1" }, { - "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "Self-modifying code (SMC) detected.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" }, { - "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "Increments whenever there is an update to the= LBR array.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR to be enabled properly.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.PAUSE_INST", + "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SB", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", - "SampleAfterValue": "500009", + "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x8" }, { - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles using always tru= e condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "All branch instructions retired.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "EventCode": "0x5e", + "EventName": "RS_EVENTS.EMPTY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all branch instructions retired.", - "SampleAfterValue": "400009" + "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into stravation periods (e.g. branch mispredi= ctions or i-cache misses)", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", @@ -745,127 +725,180 @@ "EventName": "RS_EVENTS.EMPTY_END", "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to closely sample on front-end late= ncy issues (see the FRONTEND_RETIRED event of designated precise events)", - "SampleAfterValue": "100003", + "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to closely sample on front-end late= ncy issues (see the FRONTEND_RETIRED event of designated precise events)", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops executed on port 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_0", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops executed on port 1", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of uops executed on port 2 and 3", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_2_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x4" }, { - "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "BriefDescription": "Number of uops executed on port 4 and 9", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xec", - "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_4_9", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x10" }, { - "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "BriefDescription": "Number of uops executed on port 5", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_5", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", - "SampleAfterValue": "25003", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x20" }, { - "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "BriefDescription": "Number of uops executed on port 6", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_6", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", "SampleAfterValue": "2000003", - "Speculative": "1" + "Speculative": "1", + "UMask": "0x40" }, { - "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "BriefDescription": "Number of uops executed on port 7 and 8", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_7_8", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts mispredicted conditional branch instr= uctions retired.", - "SampleAfterValue": "50021", - "UMask": "0x11" + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Number of uops executed on port 0", + "BriefDescription": "Number of uops executed on the core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_0", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", + "PublicDescription": "Counts the number of uops executed from any = thread.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Conditional branch instructions retired.", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts conditional branch instructions retir= ed.", - "SampleAfterValue": "400009", - "UMask": "0x11" + "PublicDescription": "Counts cycles when at least 1 micro-op is ex= ecuted from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Retirement slots used.", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.SLOTS", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the retirement slots used each cycle.= ", + "PublicDescription": "Counts cycles when at least 2 micro-ops are = executed from any thread on physical core.", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0xa8", - "EventName": "LSD.CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when optimal number of uop= s is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 3 micro-ops are = executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3c", - "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are = executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x2" }, { - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", + "CounterMask": "1", "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", + "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" @@ -884,14 +917,14 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", + "CounterMask": "3", "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", + "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" @@ -910,126 +943,116 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 3 micro-ops are = executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Counts the number of x87 uops dispatched.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "EventName": "UOPS_EXECUTED.X87", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 1 micro-op is ex= ecuted from any thread on physical core.", + "PublicDescription": "Counts the number of x87 uops executed.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x10" }, { - "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", + "BriefDescription": "Uops that RAT issues to RS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all miss-predicted indirect branch in= structions retired (excluding RETs. TSX aborts is considered indirect branc= h).", - "SampleAfterValue": "50021", - "UMask": "0x80" + "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "TMA slots where uops got dropped", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.UOP_DROPPING", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", + "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "20", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x14" + "UMask": "0x2" }, { - "BriefDescription": "Number of uops executed on port 7 and 8", + "BriefDescription": "Retirement slots used.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_7_8", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", + "PublicDescription": "Counts the retirement slots used each cycle.= ", "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x80" + "UMask": "0x2" }, { - "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken. Non PEBS", + "BriefDescription": "Cycles without actually retired uops.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional mispredicted branch= instructions retired.", - "SampleAfterValue": "50021", - "UMask": "0x1" + "PublicDescription": "This event counts cycles without actually re= tired uops.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "All mispredicted branch instructions retired.= ", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "CounterMask": "10", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", - "SampleAfterValue": "50021" + "PublicDescription": "Counts the number of cycles using always tru= e condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "1000003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/icelake/virtual-memory.json index f485f4664ea6..a006fd7f7b18 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json @@ -1,38 +1,14 @@ [ { - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", - "SampleAfterValue": "100007", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xe" - }, - { - "BriefDescription": "STLB flush attempts", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.STLB_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", - "SampleAfterValue": "100007", - "Speculative": "1", "UMask": "0x20" }, { @@ -49,77 +25,77 @@ "UMask": "0x10" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", + "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0xe" }, { - "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x4" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", + "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x2" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a store.", + "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x20" }, { - "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a store.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x10" }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", @@ -134,16 +110,16 @@ "UMask": "0xe" }, { - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xe" + "UMask": "0x4" }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", @@ -157,6 +133,18 @@ "Speculative": "1", "UMask": "0x2" }, + { + "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", "CollectPEBSRecord": "2", @@ -170,76 +158,88 @@ "UMask": "0x20" }, { - "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "CounterMask": "1", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a code (instruction fetch) request= .", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x10" }, { - "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_PENDING", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", + "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0xe" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_ACTIVE", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a code (instruction fetch) request= .", + "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x4" }, { - "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", + "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x20" + "UMask": "0x2" }, { - "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", + "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", + "SampleAfterValue": "100007", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x1" + }, + { + "BriefDescription": "STLB flush attempts", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "SampleAfterValue": "100007", + "Speculative": "1", + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DD31C433EF for ; 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charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are still at version 20: https://download.01.org/perfmon/IVT Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on an Ivytown, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/ivytown/cache.json | 1594 +++++++-------- .../arch/x86/ivytown/floating-point.json | 212 +- .../pmu-events/arch/x86/ivytown/frontend.json | 386 ++-- .../arch/x86/ivytown/ivt-metrics.json | 277 +-- .../pmu-events/arch/x86/ivytown/memory.json | 562 +++--- .../pmu-events/arch/x86/ivytown/other.json | 42 +- .../pmu-events/arch/x86/ivytown/pipeline.json | 1769 ++++++++--------- .../arch/x86/ivytown/virtual-memory.json | 232 +-- 8 files changed, 2546 insertions(+), 2528 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf= /pmu-events/arch/x86/ivytown/cache.json index 6dad3ad6b102..9bbf2bc59859 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json @@ -1,1260 +1,1260 @@ [ { - "PublicDescription": "Demand Data Read requests that hit L2 cache.= ", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "Counts the number of lines brought into the = L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", - "EventCode": "0x24", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Cycles a demand request was blocked due to F= ill Buffers inavailability.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "RFO requests that hit L2 cache.", - "EventCode": "0x24", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "PublicDescription": "Cycles with L1D load Misses outstanding from= any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in E state.", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Counts all L2 store RFO requests.", - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in M state.", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", - "EventCode": "0x24", + "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "PublicDescription": "Not rejected writebacks that missed LLC.", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "L2 cache lines filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "PublicDescription": "Counts all L2 code requests.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", - "EventCode": "0x24", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "EventCode": "0x24", + "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "RFOs that miss cache lines.", - "EventCode": "0x27", + "BriefDescription": "Dirty L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "RFOs that hit cache lines in M state.", - "EventCode": "0x27", + "BriefDescription": "Dirty L2 cache lines filling the L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "PublicDescription": "Dirty L2 cache lines filling the L2.", + "SampleAfterValue": "100003", + "UMask": "0xa" + }, + { + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by the MLC pref= etcher.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by the MLC pref= etcher.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "RFOs that access cache lines in any state.", - "EventCode": "0x27", + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "Not rejected writebacks that missed LLC.", - "EventCode": "0x28", + "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc0" }, { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in E state.", - "EventCode": "0x28", + "BriefDescription": "RFO requests to L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in M state.", - "EventCode": "0x28", + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cache misses when fetching instructions", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", - "EventCode": "0x2E", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Demand Data Read requests that hit L2 cache.= ", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", - "EventCode": "0x2E", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "RFO requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles with L1D load Misses outstanding from= any thread on physical core.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Cycles a demand request was blocked due to F= ill Buffers inavailability.", - "EventCode": "0x48", + "BriefDescription": "RFOs that access cache lines in any state", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "PublicDescription": "RFOs that access cache lines in any state.", + "SampleAfterValue": "200003", + "UMask": "0xf" }, { - "PublicDescription": "Counts the number of lines brought into the = L1 data cache.", - "EventCode": "0x51", + "BriefDescription": "RFOs that hit cache lines in M state", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "PublicDescription": "RFOs that hit cache lines in M state.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Offcore outstanding Demand Data Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "RFOs that miss cache lines", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "PublicDescription": "RFOs that miss cache lines.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles when offcore outstanding Demand Data = Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, inc= luding rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Cycles with at least 6 offcore outstanding D= emand Data Read transactions in uncore queue.", - "EventCode": "0x60", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "PublicDescription": "Offcore outstanding Demand Code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions= .", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Offcore outstanding code reads transactions = in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", + "BriefDescription": "Demand Data Read requests that access L2 cach= e", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests that access L2 cac= he.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PublicDescription": "Offcore outstanding demand rfo reads transac= tions in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "Cycles when offcore outstanding cacheable Co= re Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D is locked.", - "EventCode": "0x63", + "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Demand data read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "PublicDescription": "Demand code read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", - "EventCode": "0xB0", + "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", - "EventCode": "0xB0", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "PublicDescription": "Cases when offcore requests buffer cannot ta= ke more entries for core.", - "EventCode": "0xB2", + "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event)", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops whose data source was local= DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precis= e Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops whose data source was remot= e DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "100007", + "UMask": "0xc" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Data forwarded from remote cache.", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", + "SampleAfterValue": "100007", + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Remote cache HITM.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", + "SampleAfterValue": "100007", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", + "CounterHTOff": "0,1,2,3", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3" - }, - { + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops which data sources followin= g L1 data-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources followin= g L1 data-cache miss.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", + "CounterHTOff": "0,1,2,3", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", - "CounterHTOff": "0,1,2,3" - }, - { + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "50021", + "UMask": "0x4" }, { - "EventCode": "0xD3", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "PEBS": "1", "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops whose data source was local= DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xD3", + "BriefDescription": "All retired load uops. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops whose data source was remot= e DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "EventCode": "0xD3", + "BriefDescription": "All retired store uops. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", - "SampleAfterValue": "100007", - "BriefDescription": "Remote cache HITM.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xD3", + "BriefDescription": "Retired load uops with locked access. (Precis= e Event)", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", "SampleAfterValue": "100007", - "BriefDescription": "Data forwarded from remote cache.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "PublicDescription": "Demand Data Read requests that access L2 cac= he.", - "EventCode": "0xF0", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cach= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "PublicDescription": "RFO requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { - "PublicDescription": "L2 cache accesses when fetching instructions= .", - "EventCode": "0xF0", + "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event)", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, inc= luding rejects.", - "EventCode": "0xF0", + "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "PublicDescription": "L1D writebacks that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "L2 fill requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Cacheable and noncachaeble code read requests= ", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "L2 writebacks that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Transactions accessing L2 pipe.", - "EventCode": "0xF0", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "L2 cache lines in I state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "Cases when offcore requests buffer cannot ta= ke more entries for core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "L2 cache lines in S state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "L2 cache lines in E state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Cycles when offcore outstanding cacheable Co= re Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "L2 cache lines filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Offcore outstanding code reads transactions = in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "PublicDescription": "Cycles when offcore outstanding Demand Data = Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Dirty L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Offcore outstanding demand rfo reads transac= tions in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Clean L2 cache lines evicted by the MLC pref= etcher.", - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand Code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Dirty L2 cache lines evicted by the MLC pref= etcher.", - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding Demand Data Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Dirty L2 cache lines filling the L2.", - "EventCode": "0xF2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "PublicDescription": "Cycles with at least 6 offcore outstanding D= emand Data Read transactions in uncore queue.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF4", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090", + "BriefDescription": "Counts all prefetch data reads that hit the L= LC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit the L= LC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", + "BriefDescription": "Counts all writebacks from the core to the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all writebacks from the core to the LL= C", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", + "BriefDescription": "Counts all demand code reads that hit in the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the = LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", + "BriefDescription": "Counts all demand data reads that hit in the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the = LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803c8000", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803c8000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x23ffc08000", + "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23ffc08000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040", + "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", + "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", + "BriefDescription": "Counts non-temporal stores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/t= ools/perf/pmu-events/arch/x86/ivytown/floating-point.json index 950b62c0908e..db8b1c4fceb0 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json @@ -1,151 +1,169 @@ [ { - "PublicDescription": "Counts number of X87 uops executed.", - "EventCode": "0x10", + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked double-precision uops issued this cycle.", - "EventCode": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values= ", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input value= s.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational s= calar single-precision uops issued this cycle.", - "EventCode": "0x10", + "BriefDescription": "Number of SIMD FP assists due to Output value= s", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output valu= es.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked single-precision uops issued this cycle.", - "EventCode": "0x10", + "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values= .", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Counts number of SSE* or AVX-128 double prec= ision FP scalar uops executed.", + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output value= s.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked double-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked single-precision uops issued this cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Counts 256-bit packed single-precision float= ing-point instructions.", - "EventCode": "0x11", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "PublicDescription": "Counts number of SSE* or AVX-128 double prec= ision FP scalar uops executed.", "SampleAfterValue": "2000003", - "BriefDescription": "number of GSSE-256 Computational FP single pr= ecision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PublicDescription": "Counts 256-bit packed double-precision float= ing-point instructions.", - "EventCode": "0x11", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational s= calar single-precision uops issued this cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "number of AVX-256 Computational FP double pre= cision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of assists associated with 256-bit AV= X store operations.", - "EventCode": "0xC1", + "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "PublicDescription": "Counts number of X87 uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" }, { - "PublicDescription": "Number of X87 FP assists due to output value= s.", - "EventCode": "0xCA", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "PublicDescription": "Number of assists associated with 256-bit AV= X store operations.", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of X87 FP assists due to input values= .", - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Number of SIMD FP assists due to output valu= es.", - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output value= s", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of SIMD FP assists due to input value= s.", - "EventCode": "0xCA", + "BriefDescription": "number of AVX-256 Computational FP double pre= cision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "PublicDescription": "Counts 256-bit packed double-precision float= ing-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles with any input/output SSE* or FP assi= sts.", - "EventCode": "0xCA", + "BriefDescription": "number of GSSE-256 Computational FP single pr= ecision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist= ", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "PublicDescription": "Counts 256-bit packed single-precision float= ing-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/p= erf/pmu-events/arch/x86/ivytown/frontend.json index efaa949ead31..c956a0a51312 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json @@ -1,305 +1,315 @@ [ { - "PublicDescription": "Counts cycles the IDQ is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PublicDescription": "Number of DSB to MITE switches.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from MITE path.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Cycles DSB to MITE switches caused delay.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Reads. both cacheable and noncacheable, including UC fet= ches.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", - "EventCode": "0x79", + "BriefDescription": "Cycles where a code-fetch stalled due to L1 i= nstruction-cache miss or an iTLB miss", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", + "PublicDescription": "Cycles where a code-fetch stalled due to L1 = instruction-cache miss or an iTLB miss.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles when uops initiated by Decode Stream = Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mi= crocode Sequenser (MS) is busy.", - "EventCode": "0x79", + "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Misses. Includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ)= initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is = busy.", - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Se= t Cmask =3D 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one = uops. Set Cmask =3D 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. S= et Cmask =3D 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "Counts cycles MITE is delivered at least one= uops. Set Cmask =3D 1.", - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one= uops. Set Cmask =3D 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MS by either DSB or MITE. Set Cmask =3D 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "EventCode": "0x79", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x3c", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Reads. both cacheable and noncacheable, including UC fet= ches.", - "EventCode": "0x80", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) from MITE path.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Misses. Includes UC accesses.", - "EventCode": "0x80", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles where a code-fetch stalled due to L1 = instruction-cache miss or an iTLB miss.", - "EventCode": "0x80", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFETCH_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Inst= ruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code-fetch stalled due to L1 i= nstruction-cache miss or an iTLB miss", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "Count issue pipeline slots where no uop was = delivered from the front end to the back end when there is no back-end stal= l.", - "EventCode": "0x9C", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "Cycles when uops initiated by Decode Stream = Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mi= crocode Sequenser (MS) is busy.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ)= initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is = busy.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0x9C", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MS by either DSB or MITE. Set Cmask =3D 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0x9C", - "Invert": "1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Count issue pipeline slots where no uop was = delivered from the front end to the back end when there is no back-end stal= l.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Number of DSB to MITE switches.", - "EventCode": "0xAB", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DSB2MITE_SWITCHES.COUNT", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles DSB to MITE switches caused delay.", - "EventCode": "0xAB", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "DSB Fill encountered > 3 DSB lines.", - "EventCode": "0xAC", + "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tool= s/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index db23db2e98be..8d0ddcbd6c7c 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -1,184 +1,144 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_S= LOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -188,87 +148,138 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREA= D / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_X= CLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "1 / ( ((FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD) + ((FP_COMP_OPS_EXE.SSE= _PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SIN= GLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRE= D.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED= .ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRE= D.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L3MPKI" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK= _DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_C= OMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4= * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * = SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -279,28 +290,40 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Socket actual clocks when any core is active = on that socket", "MetricExpr": "cbox_0@event\\=3D0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/per= f/pmu-events/arch/x86/ivytown/memory.json index 3a7b86af8816..f904140203fe 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json @@ -1,503 +1,503 @@ [ { - "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative cache-line split Store-address u= ops dispatched to L1D.", - "EventCode": "0x05", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 4.", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", + "SampleAfterValue": "1009", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 8.", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 16", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "SampleAfterValue": "20011", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", + "BriefDescription": "Loads with latency value being above 256", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", + "SampleAfterValue": "503", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", + "BriefDescription": "Loads with latency value being above 32", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", + "BriefDescription": "Loads with latency value being above 4", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "SampleAfterValue": "100003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", + "BriefDescription": "Loads with latency value being above 512", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 64", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "SampleAfterValue": "2003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 8", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "SampleAfterValue": "50021", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", + "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only.", "Counter": "3", - "UMask": "0x2", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only.", + "PEBS": "2", "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc00244", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split Store-address u= ops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc00244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800244", + "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f800244", + "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f800244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20091", + "BriefDescription": "Counts all demand & prefetch data reads that = hits the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that = hits the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc203f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc203f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f8203f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC the data is found in M state in remote cache and f= orwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f8203f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC the data is found in M state in remote cache and f= orwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20004", + "BriefDescription": "Counts all demand code reads that miss the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400004", + "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800004", + "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820004", + "BriefDescription": "Counts all demand code reads that miss the LL= C the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_= FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00004", + "BriefDescription": "Counts all demand code reads that miss the LL= C and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20001", + "BriefDescription": "Counts demand data reads that miss in the LLC= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss in the LLC= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820001", + "BriefDescription": "Counts demand data reads that miss the LLC t= he data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_= FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC t= he data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc20002", + "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the LLC and the data is found in M state in remote cache and forwarded fr= om there.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc20002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the LLC and the data is found in M state in remote cache and forwarded fr= om there.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20040", + "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from remote & local dram= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from remote & local dram= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC the data is found in M state in remote cache and f= orwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_F= ORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC the data is found in M state in remote cache and f= orwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20200", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf= /pmu-events/arch/x86/ivytown/other.json index 4eb83ee40412..83fe8f79adc6 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/other.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json @@ -1,44 +1,44 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of intervals between processor halts = while thread is in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", + "PublicDescription": "Number of intervals between processor halts = while thread is in ring 0.", "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/p= erf/pmu-events/arch/x86/ivytown/pipeline.json index 2a0aad91d83d..2de31c56c2a5 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json @@ -1,1305 +1,1272 @@ [ { - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "Loads blocked by overlapping with store buff= er that cannot be forwarded.", - "EventCode": "0x03", + "BriefDescription": "Divide operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "Divide operations executed.", "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", - "EventCode": "0x03", + "BriefDescription": "Cycles when divider is busy executing divide = operations", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "Cycles that the divider is active, includes = INT and FP. Set 'edge =3D1, cmask=3D1' to count the number of divides.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "False dependencies in MOB due to partial com= pare on address.", - "EventCode": "0x07", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial comp= are on address", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired macro-conditional bra= nches", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired macro-conditional br= anches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "Speculative and retired macro-unconditional = branches excluding calls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0D", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "Speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Increments each cycle the # of Uops issued b= y the RAT to RS. Set Cmask =3D 1, Inv =3D 1, Any=3D 1to count stalled cycle= s of this core.", - "EventCode": "0x0E", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Speculative and retired indirect branches ex= cluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for the thread.", - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for all threads.", - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken macro-conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "Number of flags-merge uops allocated. Such u= ops adds delay.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired macro-condition= al branches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired macro-conditio= nal branches.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a re= sult of LEA instruction or not.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "Taken speculative and retired macro-conditio= nal branch instructions excluding calls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired direct near cal= ls", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired direct near ca= lls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "PublicDescription": "Cycles that the divider is active, includes = INT and FP. Set 'edge =3D1, cmask=3D1' to count the number of divides.", - "EventCode": "0x14", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide = operations", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired indirect branc= hes excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "PublicDescription": "Divide operations executed.", - "EventCode": "0x14", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "UMask": "0x4", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", - "BriefDescription": "Divide operations executed", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired indirect calls= .", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt stat= e", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "Taken speculative and retired indirect branc= hes with return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" }, { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", - "EventCode": "0x3C", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", - "EventCode": "0x3C", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", - "EventCode": "0x4C", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", - "EventCode": "0x4C", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x58", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x58", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired mispredicted macro c= onditional branches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x58", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Mispredicted indirect branches excluding cal= ls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x58", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken speculative and retired mispredict= ed macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "Cycles the RS is empty for the thread.", - "EventCode": "0x5E", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired mispredicted m= acro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x5E", - "Invert": "1", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired mispredicted i= ndirect calls.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches with return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "PublicDescription": "Not taken macro-conditional branches.", - "EventCode": "0x88", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retireme= nt.", + "SampleAfterValue": "400009" }, { - "PublicDescription": "Taken speculative and retired macro-conditio= nal branches.", - "EventCode": "0x88", + "BriefDescription": "Mispredicted macro branch instructions retire= d.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "PublicDescription": "Taken speculative and retired macro-conditio= nal branch instructions excluding calls and indirects.", - "EventCode": "0x88", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Taken speculative and retired indirect branc= hes excluding calls and returns.", - "EventCode": "0x88", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "Taken speculative and retired indirect branc= hes with return mnemonic.", - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Taken speculative and retired direct near ca= lls.", - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near cal= ls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Taken speculative and retired indirect calls= .", - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Speculative and retired macro-conditional br= anches.", - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional bra= nches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Speculative and retired macro-unconditional = branches excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PublicDescription": "Speculative and retired indirect branches ex= cluding calls and returns.", - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Speculative and retired direct near calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Not taken speculative and retired mispredict= ed macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Taken speculative and retired mispredicted m= acro conditional branches.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches excluding calls and returns.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches with return mnemonic.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 cache miss loads. Set= AnyThread to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Taken speculative and retired mispredicted i= ndirect calls.", - "EventCode": "0x89", + "BriefDescription": "Cycles while L2 cache miss load* is outstandi= ng.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Speculative and retired mispredicted macro c= onditional branches.", - "EventCode": "0x89", + "BriefDescription": "Cycles with pending L2 cache miss loads.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyTh= read to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Mispredicted indirect branches excluding cal= ls and returns.", - "EventCode": "0x89", + "BriefDescription": "Cycles with pending memory loads.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set AnyThr= ead to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", - "EventCode": "0x89", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 0.", - "EventCode": "0xA1", + "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Total execution stalls.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 1.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while L2 cache miss load* is= outstanding.", "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 2.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls due to L2 cache misses.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", + "BriefDescription": "Execution stalls due to memory subsystem.", "Counter": "0,1,2,3", - "UMask": "0xc", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched to port 2, loads and stores p= er core (speculative and retired).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 3.", - "EventCode": "0xA1", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "PublicDescription": "Cycles per core when load or STA uops are di= spatched to port 3.", - "EventCode": "0xA1", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", - "UMask": "0x30", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 4.", - "EventCode": "0xA1", + "BriefDescription": "Stall cycles because IQ is full", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 4.", - "EventCode": "0xA1", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles per core when uops are dispatched to = port 5.", - "EventCode": "0xA1", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles Allocation is stalled due to Resource= Related reason.", - "EventCode": "0xA2", + "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA2", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "Cycles stalled due to no store buffers avail= able (not including draining form sync).", - "EventCode": "0xA2", + "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA2", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Cycles with pending L2 miss loads. Set AnyTh= read to count per core.", - "EventCode": "0xA3", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Loads blocked by overlapping with store buff= er that cannot be forwarded.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA3", + "BriefDescription": "False dependencies in MOB due to partial comp= are on address", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss load* is outstandi= ng.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "False dependencies in MOB due to partial com= pare on address.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles with pending memory loads. Set AnyThr= ead to count per core.", - "EventCode": "0xA3", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn= 't come from the decoder.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Total execution stalls.", - "EventCode": "0xA3", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't= come from the decoder.", "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Total execution stalls.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss load* is= outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Counts the number of executed AVX masked loa= d operations that refer to an illegal address range with the mask bits set = to 0.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA3", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Number of self-modifying-code machine clears= detected.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles with pending L1 cache miss loads. Set= AnyThread to count per core.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "CounterMask": "8", - "CounterHTOff": "2" + "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "CounterMask": "8", - "CounterHTOff": "2" + "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x80" }, { - "PublicDescription": "Execution stalls due to L1 data cache miss l= oads. Set Cmask=3D0CH.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles Allocation is stalled due to Resource= Related reason.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x10" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles Uops delivered by the LSD, but didn't= come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "Cycles stalled due to no store buffers avail= able (not including draining form sync).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn= 't come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by har= dware.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Counts total number of uops to be executed p= er-thread each cycle. Set Cmask =3D 1, INV =3D1 to count stall cycles.", - "EventCode": "0xB1", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.THREAD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "Cycles the RS is empty for the thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 0", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles at least 1 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Uops dispatched to port 2, loads and stores p= er core (speculative and retired).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "Cycles at least 2 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "Cycles at least 3 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "PublicDescription": "Cycles per core when load or STA uops are di= spatched to port 3.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "Cycles at least 4 micro-op is executed from = any thread on physical core.", - "EventCode": "0xB1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 4", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Cycles with no micro-ops executed from any t= hread on physical core.", - "EventCode": "0xB1", - "Invert": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 5", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PEBS": "2", - "PublicDescription": "Precise instruction retired event with HW to= reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to = port 5.", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x80" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PublicDescription": "Cycles at least 1 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PublicDescription": "Cycles at least 2 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PublicDescription": "Cycles at least 3 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PublicDescription": "Cycles at least 4 micro-op is executed from = any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "PublicDescription": "Cycles with no micro-ops executed from any t= hread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Number of self-modifying-code machine clears= detected.", - "EventCode": "0xC3", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of executed AVX masked loa= d operations that refer to an illegal address range with the mask bits set = to 0.", - "EventCode": "0xC3", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Counts total number of uops to be executed p= er-thread each cycle. Set Cmask =3D 1, INV =3D1 to count stall cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Increments each cycle the # of Uops issued b= y the RAT to RS. Set Cmask =3D 1, Inv =3D 1, Any=3D 1to count stalled cycle= s of this core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for all threads.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Number of flags-merge uops being allocated.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such u= ops adds delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", - "EventCode": "0xC4", + "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a re= sult of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "Number of far branches retired.", - "EventCode": "0xC4", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) = does not issue Uops to Reservation Station (RS) for the thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Mispredicted branch instructions at retireme= nt.", - "EventCode": "0xC5", + "BriefDescription": "Retired uops.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC5", + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Count cases of saving new LBR records by har= dware.", - "EventCode": "0xCC", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", - "EventCode": "0xE6", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json index 4645e9d3f460..da6a3e09a782 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json @@ -1,198 +1,198 @@ [ { - "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size from demand loads.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes an page walk of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { + "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x84" + }, + { + "BriefDescription": "Page walk for a large page completed for Dema= nd load.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "PublicDescription": "Misses in all TLB levels that caused page wa= lk completed of any size by demand loads.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes an page walk of any page size.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size from demand loads.", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x08", + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5F", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Counts load operations that missed 1st level= DTLB but hit the 2nd level.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Cycle PMH is busy with a walk due to demand = loads.", + "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all TLB levels that caused page wa= lk completed of any size by demand loads.", + "SampleAfterValue": "100003", + "UMask": "0x82" + }, + { + "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", "Counter": "0,1,2,3", - "UMask": "0x84", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk due to demand = loads.", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x08", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Page walk for a large page completed for Dema= nd load.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk th= at completes of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Miss in all TLB levels causes a page walk th= at completes of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles PMH is busy with this walk.", - "EventCode": "0x49", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "Cycles PMH is busy with this walk.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", - "EventCode": "0x49", + "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4F", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Counts load operations that missed 1st level= DTLB but hit the 2nd level.", - "EventCode": "0x5F", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Misses in all ITLB levels that cause page wa= lks.", - "EventCode": "0x85", + "BriefDescription": "Completed page walks in ITLB due to STLB load= misses for large pages", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB due to STLB loa= d misses for large pages.", "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "PublicDescription": "Misses in all ITLB levels that cause complet= ed page walks.", - "EventCode": "0x85", + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all ITLB levels that cause page wa= lks.", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycle PMH is busy with a walk.", - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of cache load STLB hits. No page walk= .", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk= .", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Completed page walks in ITLB due to STLB loa= d misses for large pages.", - "EventCode": "0x85", + "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all ITLB levels that cause complet= ed page walks.", "SampleAfterValue": "100003", - "BriefDescription": "Completed page walks in ITLB due to STLB load= misses for large pages", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", - "EventCode": "0xAE", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", - "EventCode": "0xBD", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CEADC433F5 for ; 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charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are still at version 20: https://download.01.org/perfmon/JKT Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Jaketown, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/jaketown/cache.json | 1582 ++++++++--------- .../arch/x86/jaketown/floating-point.json | 160 +- .../arch/x86/jaketown/frontend.json | 363 ++-- .../arch/x86/jaketown/jkt-metrics.json | 140 +- .../pmu-events/arch/x86/jaketown/memory.json | 478 ++--- .../pmu-events/arch/x86/jaketown/other.json | 58 +- .../arch/x86/jaketown/pipeline.json | 1556 ++++++++-------- .../arch/x86/jaketown/virtual-memory.json | 178 +- 8 files changed, 2253 insertions(+), 2262 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/per= f/pmu-events/arch/x86/jaketown/cache.json index 52dc6ef40e63..97c7e0ceed18 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json @@ -1,1290 +1,1266 @@ [ { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Allocated L1D data cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.ALLOCATED_IN_M", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Cache lines in M state evicted out of L1D due= to Snoop HitM or dirty line replacement.", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.ALL_M_REPLACEMENT", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "L1D data cache lines in M state evicted due t= o replacement.", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.EVICTION", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K).", - "EventCode": "0xD0", + "BriefDescription": "L1D data line replacements.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements= . Replacements occur when a new line is brought into the cache, causing ev= iction of a line loaded earlier.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K).", - "EventCode": "0xD0", + "BriefDescription": "Cycles when dispatched loads are cancelled du= e to L1D bank conflicts with other load ports.", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xBF", + "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x5" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of load uops re= tired", - "EventCode": "0xD0", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of store uops r= etired.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "L1D miss oustandings duration in cycles.", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", - "CounterHTOff": "0,1,2,3" + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts retired load uops that hit= in the last-level (L3) cache without snoops required.", - "EventCode": "0xD1", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "UMask": "0xf" }, { - "EventCode": "0xD1", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0xD2", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in S state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_S", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a non-modified state.", - "EventCode": "0xD2", + "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a modified state, so the line ha= d to be invalidated in that L2 cache and transferred to the requesting L2.", - "EventCode": "0xD2", + "BriefDescription": "L2 cache lines filling L2.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "EventCode": "0xD2", + "BriefDescription": "L2 cache lines in E state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xD3", + "BriefDescription": "L2 cache lines in I state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xD3", + "BriefDescription": "L2 cache lines in S state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Data from remote DRAM either Snoop not needed= or Snoop Miss (RspI)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts L1D data line replacements= . Replacements occur when a new line is brought into the cache, causing ev= iction of a line loaded earlier.", - "EventCode": "0x51", + "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "Dirty L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D.ALLOCATED_IN_M", - "SampleAfterValue": "2000003", - "BriefDescription": "Allocated L1D data cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "Dirty L2 cache lines filling the L2.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L1D.EVICTION", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data cache lines in M state evicted due t= o replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "SampleAfterValue": "100003", + "UMask": "0xa" }, { - "EventCode": "0x51", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D.ALL_M_REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "Cache lines in M state evicted out of L1D due= to Snoop HitM or dirty line replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles.", - "CounterHTOff": "2" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0x63", + "BriefDescription": "L2 code requests.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "EventCode": "0x60", + "BriefDescription": "Demand Data Read requests.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "EventCode": "0x60", + "BriefDescription": "Requests from L2 hardware prefetchers.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0xc0" }, { - "EventCode": "0x60", + "BriefDescription": "RFO requests to L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "UMask": "0xc" }, { - "EventCode": "0x60", + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "EventCode": "0x60", + "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "EventCode": "0xB0", + "BriefDescription": "Demand Data Read requests that hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xB0", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "EventCode": "0xB0", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0xB0", + "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0xB2", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "RFOs that access cache lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "EventCode": "0x24", + "BriefDescription": "RFOs that hit cache lines in E state.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "RFOs that hit cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "RFOs that miss cache lines.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.= ", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "Transactions accessing L2 pipe.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x24", + "BriefDescription": "L2 cache accesses when fetching instructions.= ", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x27", + "BriefDescription": "Demand Data Read requests that access L2 cach= e.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "L1D writebacks that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "L2 fill requests that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "L2 writebacks that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x28", + "BriefDescription": "RFO requests that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x28", + "BriefDescription": "Cycles when L1D is locked.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_L1D_WB_RQSTS.HIT_S", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in S state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x28", + "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "EventCode": "0x28", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "UMask": "0x4f" }, { - "EventCode": "0x28", + "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a non-modified state.", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cach= e.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a modified state, so the line ha= d to be invalidated in that L2 cache and transferred to the requesting L2.", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "Data from remote DRAM either Snoop not needed= or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "100007", + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF1", + "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "PublicDescription": "This event counts retired load uops that hit= in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "All retired load uops.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load uops re= tired", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", - "EventCode": "0xF1", + "BriefDescription": "All retired store uops.", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PublicDescription": "This event counts the number of store uops r= etired.", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xF2", + "BriefDescription": "Retired load uops with locked access.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "EventCode": "0xF2", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0xF2", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x42" }, { - "EventCode": "0xF2", + "BriefDescription": "Retired load uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x11" }, { - "EventCode": "0xF2", + "BriefDescription": "Retired store uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x12" }, { - "EventCode": "0x2E", + "BriefDescription": "Demand and prefetch data reads.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x2E", + "BriefDescription": "Cacheable and noncachaeble code read requests= .", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xF4", + "BriefDescription": "Demand Data Read requests sent to uncore.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xBF", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles when dispatched loads are cancelled du= e to L1D bank conflicts with other load ports.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x60", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x60", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0x48", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000105B3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090", + "BriefDescription": "Counts all prefetch data reads that hit the L= LC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit the L= LC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c03f7", + "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch)", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000107F7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c03f7", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts all writebacks from the core to the LL= C", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10008", - "Counter": "0,1,2,3", - "UMask": "0x1", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all writebacks from the core to the LL= C", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts all demand code reads that hit in the = LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", + "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3f803c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010001", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads that hit in the = LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the = LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the = LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0001", + "BriefDescription": "Counts all demand rfo's", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803c8000", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803c8000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x23ffc08000", + "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23ffc08000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040", + "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x3f803c0080", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x10003c0080", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x4003c0080", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010008", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010002", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x1003c0080", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand rfo's", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010004", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000105B3", + "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010122", + "BriefDescription": "Counts non-temporal stores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch prefetch RFOs", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000107F7", + "BriefDescription": "Split locks in SQ.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/= tools/perf/pmu-events/arch/x86/jaketown/floating-point.json index 982eda48785e..713878fd062b 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json @@ -1,138 +1,138 @@ [ { - "EventCode": "0xC1", + "BriefDescription": "Cycles with any input/output SSE or FP assist= .", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1e" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD FP assists due to input values= .", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD FP assists due to Output value= s.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", + "EventName": "FP_ASSIST.SIMD_OUTPUT", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output value= s.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x10", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x10", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x10", + "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x10", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0x11", + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of GSSE-256 Computational FP single pr= ecision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0x11", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of AVX-256 Computational FP double pre= cision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of AVX-256 Computational FP double pre= cision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of GSSE-256 Computational FP single pr= ecision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist= .", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/= perf/pmu-events/arch/x86/jaketown/frontend.json index 1b7b1dd36c68..4bc0954448d2 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json @@ -1,305 +1,314 @@ [ { - "EventCode": "0x80", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes unchache= able accesses.", - "EventCode": "0x80", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts the cycles attributed to a= switch from the Decoded Stream Buffer (DSB), which holds decoded instructi= ons, to the legacy decode pipeline. It excludes cycles when the back-end c= annot accept new micro-ops. The penalty for these switches is potentially= several cycles of instruction starvation, where no micro-ops are delivered= to the back-end.", "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Cases of cancelling valid Decode Stream Buffe= r (DSB) fill not because of exceeding way limit.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.ALL_CANCEL", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", + "BriefDescription": "Cases of cancelling valid DSB fill not becaus= e of exceeding way limit.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.OTHER_CANCEL", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes unchache= able accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance. See the Intel? 64 and IA-32 Architectures Optimizat= ion Reference Manual for more information.", - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "PublicDescription": "This event counts the number of uops not del= ivered to the back-end per cycle, per thread, when the back-end was not sta= lled. In the ideal case 4 uops can be delivered each cycle. The event cou= nts the undelivered uops - so if 3 were delivered in one cycle, the counter= would be incremented by 1 for that cycle (4 - 3). If the back-end is stall= ed, the count for this event is not incremented even when uops were not del= ivered, because the back-end would not have been able to accept them. This= event is used in determining the front-end bound category of the top-down = pipeline slots characterization.", - "EventCode": "0x9C", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles MITE is delivering 4 Uops.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x24" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles MITE is delivering any Uop.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xAB", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DSB2MITE_SWITCHES.COUNT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts the cycles attributed to a= switch from the Decoded Stream Buffer (DSB), which holds decoded instructi= ons, to the legacy decode pipeline. It excludes cycles when the back-end c= annot accept new micro-ops. The penalty for these switches is potentially= several cycles of instruction starvation, where no micro-ops are delivered= to the back-end.", - "EventCode": "0xAB", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xAC", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB_FILL.OTHER_CANCEL", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid DSB fill not becaus= e of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xAC", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance. See the Intel? 64 and IA-32 Architectures Optimizat= ion Reference Manual for more information.", "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x79", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x79", "EventName": "IDQ.MS_DSB_OCCUR", "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0x9C", - "Invert": "1", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when 1 or more uops were delivered to = the by the front end.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x30" }, { - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x79", + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled .", "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not del= ivered to the back-end per cycle, per thread, when the back-end was not sta= lled. In the ideal case 4 uops can be delivered each cycle. The event cou= nts the undelivered uops - so if 3 were delivered in one cycle, the counter= would be incremented by 1 for that cycle (4 - 3). If the back-end is stall= ed, the count for this event is not incremented even when uops were not del= ivered, because the back-end would not have been able to accept them. This= event is used in determining the front-end bound category of the top-down = pipeline slots characterization.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop.", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xAC", + "BriefDescription": "Cycles when 1 or more uops were delivered to = the by the front end.", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "DSB_FILL.ALL_CANCEL", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid Decode Stream Buffe= r (DSB) fill not because of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "Invert": "1", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/too= ls/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index dbb33e00b72a..2800264c12aa 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -1,142 +1,132 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_S= LOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" - }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\= =3D1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { @@ -145,16 +135,34 @@ "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_C= OMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4= * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * = SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -165,28 +173,40 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@ca= s_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Socket actual clocks when any core is active = on that socket", "MetricExpr": "cbox_0@event\\=3D0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/pe= rf/pmu-events/arch/x86/jaketown/memory.json index 27e636428f4f..29b70f21a44b 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -1,422 +1,422 @@ [ { - "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stor= es) hitting load buffers. Machine clears can have a significant performanc= e impact if they are happening frequently.", - "EventCode": "0xC3", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stor= es) hitting load buffers. Machine clears can have a significant performanc= e impact if they are happening frequently.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4 .", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1009", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 16.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8.", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x10", + "BriefDescription": "Loads with latency value being above 256.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16.", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "503", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", + "BriefDescription": "Loads with latency value being above 32.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", + "BriefDescription": "Loads with latency value being above 4 .", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64.", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", + "BriefDescription": "Loads with latency value being above 512.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128.", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 64.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256.", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 8.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512.", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", + "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only. (Precise Event - PEBS).", "Counter": "3", - "UMask": "0x2", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only. (Precise Event - PEBS).", + "PEBS": "2", "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "EventCode": "0x05", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x05", + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20004", + "BriefDescription": "This event counts all LLC misses for all dema= nd and L2 prefetches. LLC prefetches are excluded.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC20077", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all local dram accesses for all demand= and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400077", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "This event counts all remote cache-to-cache t= ransfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. = LLC prefetches are excluded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400004", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= REMOTE_HITM_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x187FC20077", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20004", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800004", + "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820004", + "BriefDescription": "Counts all demand code reads that miss the LL= C the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_= FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00004", + "BriefDescription": "Counts all demand code reads that miss the LL= C and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LL= C the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20001", + "BriefDescription": "Counts demand data reads that miss in the LLC= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss in the LLC= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820001", + "BriefDescription": "Counts demand data reads that miss the LLC t= he data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_= FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00001", + "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC t= he data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20040", + "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from remote & local dram= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from remote & local dram= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820010", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x67f800010", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_F= ORWARD", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC the data is found in M state in remote cache and f= orwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC the data is found in M state in remote cache and f= orwarded from there", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20200", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x107fc00010", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20080", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= LOCAL_DRAM", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all local dram accesses for all demand= and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC20077", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "This event counts all LLC misses for all dema= nd and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x187FC20077", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= REMOTE_HITM_HIT_FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "This event counts all remote cache-to-cache t= ransfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. = LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/per= f/pmu-events/arch/x86/jaketown/other.json index 64b195b82c50..e251f535ec09 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/other.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json @@ -1,58 +1,58 @@ [ { - "EventCode": "0x17", + "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Valid instructions written to IQ per cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "Hardware Prefetch requests that miss the L1D = cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers= . A request is being counted each time it access the cache & miss it, inclu= ding if a block is applicable or if hit the Fill Buffer for .", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4E", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Hardware Prefetch requests that miss the L1D = cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers= . A request is being counted each time it access the cache & miss it, inclu= ding if a block is applicable or if hit the Fill Buffer for .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Valid instructions written to IQ per cycle.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x17", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/= perf/pmu-events/arch/x86/jaketown/pipeline.json index 783a5b4a67b1..87737c92c067 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -1,1216 +1,1202 @@ [ { - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", - "Counter": "Fixed counter 1", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 1" + "BriefDescription": "This event counts executed load operations wi= th all the following traits: 1. addressing of the format [base + offset], 2= . the offset is between 1 and 2047, 3. the address specified in the base re= gister is in one page and the address [base+offset] is in an.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB6", + "EventName": "AGU_BYPASS_CANCEL.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", - "Counter": "Fixed counter 2", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "CounterHTOff": "Fixed counter 2" + "BriefDescription": "Divide operations executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "This event counts the number of the divide o= perations executed.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", - "Counter": "Fixed counter 3", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Cycles when divider is busy executing divide = operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "CounterHTOff": "Fixed counter 3" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired branches.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired macro-conditional bra= nches.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "Speculative and retired direct near calls.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xd0" }, { + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { + "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired macro-condition= al branches.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Taken speculative and retired direct near cal= ls.", "Counter": "0,1,2,3", - "UMask": "0x90", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near cal= ls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x90" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired indirect calls.= ", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional bra= nches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", + "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x89", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted di= rect near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x89", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", "Counter": "0,1,2,3", - "UMask": "0xc1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { + "BriefDescription": "Speculative and retired mispredicted direct n= ear calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", "Counter": "0,1,2,3", - "UMask": "0xc4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x89", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted direct n= ear calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x3C", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt stat= e.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0xA8", + "BriefDescription": "Taken speculative and retired mispredicted di= rect near calls.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0xA8", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x87", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x0D", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" }, { - "EventCode": "0x59", + "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Increments the number of flags-merge uops in = flight each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "Mispredicted macro branch instructions retir= ed. (Precise Event - PEBS)", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Op= timization Reference Manual for more details about slow LEA instructions.", - "EventCode": "0x59", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least one slow LEA uop being a= llocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x59", + "BriefDescription": "Direct and indirect mispredicted near call in= structions retired.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Multiply packed/scalar single precision uops = allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "Mispredicted not taken branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Mispredicted taken branch instructions retire= d.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RESOURCE_STALLS.LB", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the cycles of stall due to lack of loa= d buffers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5B", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RESOURCE_STALLS2.BOB_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Allocator is stalled if BOB is fu= ll and new branch needs it.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of Uops issued = by the front-end of the pipeilne to the back-end.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 3", + "CounterHTOff": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate)", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", + "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", + "BriefDescription": "Thread cycles when thread is not in halt stat= e.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", - "EventCode": "0xC3", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread, increment by 1. Note this is in DCU and connected to Umask = 1. Miss Pending demand load should be deduced by OR-ing increment bits of D= CACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of micro-ops re= tired.", - "EventCode": "0xC2", + "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load this thread (i.e. Non-completed valid SQ entry allocated for demand = load and waiting for Uncore), increment by 1. Note this is in MLC and conne= cted to Umask 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. Th= is event is used in determining the 'Retiring' category of the Top-Down pip= eline slots characterization.", - "EventCode": "0xC2", + "BriefDescription": "Each cycle there was no dispatch for this thr= ead, increment by 1. Note this is connect to Umask 2. No dispatch can be de= duced from the UOPS_EXECUTED event.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread and no uops dispatched, increment by 1. Note this is in DCU = and connected to Umask 1 and 2. Miss Pending demand load should be deduced = by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x6" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load and no uops dispatched on this thread (i.e. Non-completed valid SQ e= ntry allocated for demand load and waiting for Uncore), increment by 1. Not= e this is in MLC and connected to Umask 0 and 2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Stall cycles because IQ is full.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xC4", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC4", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Instructions retired. (Precise Event - PEBS).= ", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect mispredicted near call in= structions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC5", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc...).", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_MISP_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted not taken branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PEBS": "1", - "EventCode": "0xC5", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted taken branch instructions retire= d.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PEBS": "2", - "PublicDescription": "Mispredicted macro branch instructions retir= ed. (Precise Event - PEBS)", - "EventCode": "0xC5", + "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc...).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of cases where any load ends up with a= valid block-code written to the load buffer (including blocks due to Memor= y Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)= .", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", "SampleAfterValue": "100003", - "BriefDescription": "Retired instructions experiencing ITLB misses= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x14", + "BriefDescription": "Loads delayed due to SB blocks, preceding sto= re operations with known addresses but unknown data.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide = operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of the divide o= perations executed.", - "EventCode": "0x14", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", "SampleAfterValue": "100003", - "BriefDescription": "Divide operations executed.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xB1", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched per thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a preceed= ing smaller uncompleted store. See the table of not supported store forwar= ds in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. = The penalty for blocked store forwarding is that the load must wait for th= e store to complete before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xB1", + "BriefDescription": "False dependencies in MOB due to partial comp= are.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched from any thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline. The enhanced address check typically ha= s a performance penalty of 5 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "This event counts the number of times that lo= ad operations are temporarily blocked because of older stores, with address= es that are not yet known. A load operation may incur more than one block o= f this type.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was no dispatch for this thr= ead, increment by 1. Note this is connect to Umask 2. No dispatch can be de= duced from the UOPS_EXECUTED event.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread, increment by 1. Note this is in DCU and connected to Umask = 1. Miss Pending demand load should be deduced by OR-ing increment bits of D= CACHE_MISS_PEND.PENDING.", - "CounterMask": "2", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load this thread (i.e. Non-completed valid SQ entry allocated for demand = load and waiting for Uncore), increment by 1. Note this is in MLC and conne= cted to Umask 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread and no uops dispatched, increment by 1. Note this is in DCU = and connected to Umask 1 and 2. Miss Pending demand load should be deduced = by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", - "CounterMask": "6", - "CounterHTOff": "2" + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA3", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load and no uops dispatched on this thread (i.e. Non-completed valid SQ e= ntry allocated for demand load and waiting for Uncore), increment by 1. Not= e this is in MLC and connected to Umask 0 and 2.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x4C", + "BriefDescription": "Retired instructions experiencing ITLB misses= .", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x4C", + "BriefDescription": "Increments the number of flags-merge uops in = flight each cycle.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0x03", + "BriefDescription": "Performance sensitive flags-merging uops adde= d by Sandy Bridge u-arch.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "SampleAfterValue": "100003", - "BriefDescription": "Loads delayed due to SB blocks, preceding sto= re operations with known addresses but unknown data.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "PublicDescription": "This event counts the number of cycles spent= executing performance-sensitive flags-merging uops. For example, shift CL = (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architec= tures Optimization Reference Manual.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a preceed= ing smaller uncompleted store. See the table of not supported store forwar= ds in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. = The penalty for blocked store forwarding is that the load must wait for th= e store to complete before it can be issued.", - "EventCode": "0x03", + "BriefDescription": "Multiply packed/scalar single precision uops = allocated.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0x03", + "BriefDescription": "Cycles with at least one slow LEA uop being a= llocated.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", + "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Op= timization Reference Manual for more details about slow LEA instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0x03", + "BriefDescription": "Resource-related stall cycles.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "LD_BLOCKS.ALL_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Number of cases where any load ends up with a= valid block-code written to the load buffer (including blocks due to Memor= y Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline. The enhanced address check typically ha= s a performance penalty of 5 cycles.", - "EventCode": "0x07", + "BriefDescription": "Counts the cycles of stall due to lack of loa= d buffers.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial comp= are.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x07", + "BriefDescription": "Resource stalls due to load or store buffers = all being in use.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that lo= ad operations are temporarily blocked because of older stores, with address= es that are not yet known. A load operation may incur more than one block o= f this type.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB_SB", + "SampleAfterValue": "2000003", + "UMask": "0xa" }, { - "EventCode": "0xB6", + "BriefDescription": "Resource stalls due to memory buffers or Rese= rvation Station (RS) being fully utilized.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "AGU_BYPASS_CANCEL.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts executed load operations wi= th all the following traits: 1. addressing of the format [base + offset], 2= . the offset is between 1 and 2047, 3. the address specified in the base re= gister is in one page and the address [base+offset] is in an.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.MEM_RS", + "SampleAfterValue": "2000003", + "UMask": "0xe" }, { - "EventCode": "0x3C", + "BriefDescription": "Resource stalls due to Rob being full, FCSW, = MXCSR and OTHER.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.OOO_RSRC", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles with either free list is empty.", "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", + "BriefDescription": "Resource stalls2 control structures full for = physical registers.", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles when Allocator is stalled if BOB is fu= ll and new branch needs it.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.BOB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xA1", + "BriefDescription": "Resource stalls out of order resources full.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.OOO_RSRC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "EventCode": "0xA1", + "BriefDescription": "Count cases of saving new LBR.", "Counter": "0,1,2,3", - "UMask": "0xc", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", "Counter": "0,1,2,3", - "UMask": "0x30", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired. (Precise Event - PEBS).= ", - "TakenAlone": "1", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0x5B", + "BriefDescription": "Uops dispatched from any thread.", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls2 control structures full for = physical registers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x5B", + "BriefDescription": "Uops dispatched per thread.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.THREAD", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with either free list is empty.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 0.", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "RESOURCE_STALLS.MEM_RS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to memory buffers or Rese= rvation Station (RS) being fully utilized.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0.", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "RESOURCE_STALLS.OOO_RSRC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to Rob being full, FCSW, = MXCSR and OTHER.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5B", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 1.", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "RESOURCE_STALLS2.OOO_RSRC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls out of order resources full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1.", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "RESOURCE_STALLS.LB_SB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to load or store buffers = all being in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x0D", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "PublicDescription": "This event counts the number of cycles spent= executing performance-sensitive flags-merging uops. For example, shift CL = (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architec= tures Optimization Reference Manual.", - "EventCode": "0x59", + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 2.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Performance sensitive flags-merging uops adde= d by Sandy Bridge u-arch.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0x0D", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0xE6", + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 4.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0x89", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 5.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xA8", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0xc3", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "Counter": "Fixed counter 2", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "Fixed counter 2" + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x0D", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued = by the front-end of the pipeilne to the back-end.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This event counts the number of micro-ops re= tired.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate)", - "EventCode": "0x3C", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. Th= is event is used in determining the 'Retiring' category of the Top-Down pip= eline slots characterization.", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json index a654ab771fce..4dd136d00a10 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json @@ -1,149 +1,149 @@ [ { - "EventCode": "0xAE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4F", + "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "This event counts load operations that miss = the first DTLB level but hit the second and do not cause any page walks. Th= e penalty in this case is approximately 7 cycles.", "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", + "BriefDescription": "Load misses at all DTLB levels that cause com= pleted page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event count cycles when Page Miss Handl= er (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", + "BriefDescription": "Cycles when PMH is busy with page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x85", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x08", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Load misses at all DTLB levels that cause com= pleted page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", - "EventCode": "0x08", + "BriefDescription": "Cycles when PMH is busy with page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts load operations that miss = the first DTLB level but hit the second and do not cause any page walks. Th= e penalty in this case is approximately 7 cycles.", - "EventCode": "0x08", + "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xBD", + "BriefDescription": "Cycles when PMH is busy with page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event count cycles when Page Miss Handl= er (PMH) is servicing page walks caused by ITLB misses.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F093C4332F for ; Tue, 1 Feb 2022 02:01:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232989AbiBACBP (ORCPT ); Mon, 31 Jan 2022 21:01:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232723AbiBACAQ (ORCPT ); Mon, 31 Jan 2022 21:00:16 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E668BC06176F for ; Mon, 31 Jan 2022 17:59:57 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id u185-20020a2560c2000000b0060fd98540f7so30568697ybb.0 for ; Mon, 31 Jan 2022 17:59:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=4pb0Nddg4WIwWc27yp59xrzSAzHIqAOxmK1rUo9Csvs=; b=ZMjnUX36apg3tqG/oZPOI7+lKjcwhiuCPldNJ2ysSlTLR52tUCxgJiA9l3apNx4I6r QvOW6iXcoB8gSzNZ3ysJNQebvqIDqSocXD41q7HhFPlVV97bo0pml6yKuejCdfblN0GD GcvuLAzFDEbSsKpZAdWwkNv9f/ipsHiVvnxAZCrUYweIZmmuPQ/TsoRq3CgSu3/zxjup 3ymVINzMqstil9aptfBy/F8+qET4zqx+3eNfbAL4nUVIqOCQqeb0R+J5zbTHYUkygwhf lRyjWrUR2V/pQFaYaVy6gA2C8JeGB9UJ+CUSWUbp55Y1BuUnRnByFBW2P5yXuwDFX00f DgRQ== X-Google-DKIM-Signature: v=1; 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charset="utf-8" Events are still at version 9: https://download.01.org/perfmon/KNL Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf The addition of a floating-point.json is due to events having their topic better identified by the converter script. Tested: Not tested on a Knights Landing, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/knightslanding/cache.json | 2602 ++++++++--------- .../x86/knightslanding/floating-point.json | 29 + .../arch/x86/knightslanding/frontend.json | 48 +- .../arch/x86/knightslanding/memory.json | 1226 ++++---- .../arch/x86/knightslanding/pipeline.json | 465 ++- .../x86/knightslanding/virtual-memory.json | 68 +- 6 files changed, 2217 insertions(+), 2221 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/floating-= point.json diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/too= ls/perf/pmu-events/arch/x86/knightslanding/cache.json index e847b0fd696d..1bd50b186e93 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json @@ -1,2305 +1,2303 @@ [ { - "EventCode": "0x30", + "BriefDescription": "Counts the number of MEC requests that were n= ot accepted into the L2Q because of any L2 queue reject condition. There i= s no concept of at-ret here. It might include requests due to instructions = in the speculative path.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "L2_REQUESTS_REJECT.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of MEC requests from the L2= Q that reference a cache line (cacheable requests) exlcuding SW prefetches = filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC= , WC) that were rejected - Multiple repeated rejects should be counted mult= iple times" - }, - { "EventCode": "0x31", - "Counter": "0,1", - "UMask": "0x0", "EventName": "CORE_REJECT_L2Q.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of MEC requests that were n= ot accepted into the L2Q because of any L2 queue reject condition. There i= s no concept of at-ret here. It might include requests due to instructions = in the speculative path." + "SampleAfterValue": "200003" }, { - "EventCode": "0x2E", + "BriefDescription": "Counts the number of core cycles the fetch st= alls because of an icache miss. This is a cummulative count of core cycles = the fetch stalled for all icache misses.", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_REQUESTS.REFERENCE", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "PublicDescription": "This event counts the number of core cycles = the fetch stalls because of an icache miss. This is a cumulative count of c= ycles the NIP stalled for all icache misses.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of L2 cache reference= s." + "UMask": "0x4" }, { - "EventCode": "0x2E", + "BriefDescription": "Counts the number of L2 cache misses", "Counter": "0,1", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "L2_REQUESTS.MISS", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of L2 cache misses" + "UMask": "0x41" }, { - "PublicDescription": "This event counts the number of core cycles = the fetch stalls because of an icache miss. This is a cumulative count of c= ycles the NIP stalled for all icache misses.", - "EventCode": "0x86", + "BriefDescription": "Counts the total number of L2 cache reference= s.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "EventCode": "0x2E", + "EventName": "L2_REQUESTS.REFERENCE", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles the fetch st= alls because of an icache miss. This is a cummulative count of core cycles = the fetch stalled for all icache misses." + "UMask": "0x4f" }, { - "PublicDescription": "This event counts the number of load micro-o= ps retired that miss in L1 Data cache. Note that prefetch misses will not b= e counted.", - "EventCode": "0x04", + "BriefDescription": "Counts the number of MEC requests from the L2= Q that reference a cache line (cacheable requests) exlcuding SW prefetches = filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC= , WC) that were rejected - Multiple repeated rejects should be counted mult= iple times", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load micro-ops retired t= hat miss in L1 D cache" + "EventCode": "0x30", + "EventName": "L2_REQUESTS_REJECT.ALL", + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "EventCode": "0x04", + "BriefDescription": "Counts all the load micro-ops retired", "Counter": "0,1", - "UMask": "0x2", - "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts the number of load micro-o= ps retired.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load micro-ops retired t= hat hit in the L2", - "Data_LA": "1" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0x04", + "BriefDescription": "Counts all the store micro-ops retired", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of load micro-ops retired t= hat miss in the L2", - "Data_LA": "1" - }, - { "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "This event counts the number of store micro-= ops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load micro-ops retired t= hat caused micro TLB miss" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0x04", + "BriefDescription": "Counts the loads retired that get the data fr= om the other core in the same tile in M state", "Counter": "0,1", - "UMask": "0x20", + "Data_LA": "1", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.HITM", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the loads retired that get the data fr= om the other core in the same tile in M state", - "Data_LA": "1" + "UMask": "0x20" }, { - "PublicDescription": "This event counts the number of load micro-o= ps retired.", - "EventCode": "0x04", + "BriefDescription": "Counts the number of load micro-ops retired t= hat miss in L1 D cache", "Counter": "0,1", - "UMask": "0x40", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "PublicDescription": "This event counts the number of load micro-o= ps retired that miss in L1 Data cache. Note that prefetch misses will not b= e counted.", "SampleAfterValue": "200003", - "BriefDescription": "Counts all the load micro-ops retired" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of store micro-= ops retired.", - "EventCode": "0x04", + "BriefDescription": "Counts the number of load micro-ops retired t= hat hit in the L2", "Counter": "0,1", - "UMask": "0x80", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "Data_LA": "1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts all the store micro-ops retired" + "UMask": "0x2" }, { - "EventCode": "0xB7", + "BriefDescription": "Counts the number of load micro-ops retired t= hat miss in the L2", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE", + "Data_LA": "1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", + "PEBS": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts the matrix events specified by MSR_OFF= CORE_RESPx" + "UMask": "0x4" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000070", + "BriefDescription": "Counts the number of load micro-ops retired t= hat caused micro TLB miss", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { + "BriefDescription": "Counts the matrix events specified by MSR_OFF= CORE_RESPx", + "Counter": "0,1", "EventCode": "0xB7", - "MSRValue": "0x1000400070", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for reponses from snoop request hit with data fo= rwarded from it Far(not in the same quadrant as the request)-other tile L2 = in E/F/M state. Valid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Far(not in the same quadrant as the request)-other tile= 's L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Far(not in the same quadrant as the request)-other tile= 's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for reponses from snoop request hit with data fo= rwarded from its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x40000032f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that are outstanding= , per weighted cycle, from the time of the request to when any response is = received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10004032f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Far(not in th= e same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x08004032f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Far(not in th= e same quadrant as the request)-other tile's L2 in E/F state. Valid only fo= r SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10000832f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Near-other ti= le's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x08000832f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Near-other ti= le's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00000132f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for an= y response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000044", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that are outstanding, per weighted cycle, from the time of the= request to when any response is received. The oustanding response should b= e programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that are outstanding, per weighted cycle, from the time of the= request to when any response is received. The oustanding response should b= e programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Far(not in the same quadrant as the request)-other tile= 's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for reponses from snoop request hit with = data forwarded from it Far(not in the same quadrant as the request)-other t= ile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800403091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Far(not in the same quadrant as the request)-other tile= 's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800403091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000403091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for reponses from snoop request hit with = data forwarded from its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800183091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000022", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that are outstanding, per weighted cycle, from the time of the request to w= hen any response is received. The oustanding response should be programmed = only on PMC0.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1000400022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800083091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Far(not in the same quadrant as the request)-other tile's L2 in M st= ate.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400022", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000083091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Far(not in the same quadrant as the request)-other tile's L2 in E/F = state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080022", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080022", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010022", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in S state", + "Counter": "0,1", "EventCode": "0xB7", - "MSRValue": "0x4000003091", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that are outstanding, per weighted cycle, from the time= of the request to when any response is received. The oustanding response s= hould be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that are outstanding, per weighted cycle, from the time= of the request to when any response is received. The oustanding response s= hould be programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000403091", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800403091", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r reponses from snoop request hit with data forwarded from it Far(not in th= e same quadrant as the request)-other tile L2 in E/F/M state. Valid only in= SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000083091", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800083091", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000013091", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r reponses from snoop request hit with data forwarded from its Near-other t= ile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000008000", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that are outstanding, per = weighted cycle, from the time of the request to when any response is receiv= ed. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1000408000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Far(not in the same= quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800408000", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Far(not in the same= quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4= cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000088000", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Near-other tile's L= 2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800088000", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Near-other tile's L= 2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000018000", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for any resp= onse", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000014800", + "BriefDescription": "Counts any Prefetch requests that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The oustanding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts all streaming stores (WC and should be= programmed on PMC1) that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000014000", + "BriefDescription": "Counts any Read request that accounts for an= y response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPON= SE", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00000132f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial streaming stores (WC and shoul= d be programmed on PMC1) that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000002000", + "BriefDescription": "Counts any Read request that accounts for re= ponses from snoop request hit with data forwarded from it Far(not in the sa= me quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC= 4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18004032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000402000", + "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Far(not in th= e same quadrant as the request)-other tile's L2 in E/F state. Valid only fo= r SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08004032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800402000", + "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Far(not in th= e same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000082000", + "BriefDescription": "Counts any Read request that accounts for re= ponses from snoop request hit with data forwarded from its Near-other tile = L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18001832f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800082000", + "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Near-other ti= le's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08000832f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000012000", + "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Near-other ti= le's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10000832f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000001000", + "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00040032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that are outstandi= ng, per weighted cycle, from the time of the request to when any response i= s received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000401000", + "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00100032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Far(not in = the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800401000", + "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00020032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Far(not in = the same quadrant as the request)-other tile's L2 in E/F state. Valid only = for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000081000", + "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00080032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Near-other = tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800081000", + "BriefDescription": "Counts any Read request that are outstanding= , per weighted cycle, from the time of the request to when any response is = received. The oustanding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x40000032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Near-other = tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000011000", + "BriefDescription": "Counts any request that accounts for any resp= onse", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010800", + "BriefDescription": "Counts any request that accounts for reponses= from snoop request hit with data forwarded from it Far(not in the same qua= drant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Clus= ter mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800408000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Full streaming stores (WC and should b= e programmed on PMC1) that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000400", + "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Far(not in the same= quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4= cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800408000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= are outstanding, per weighted cycle, from the time of the request to when = any response is received. The oustanding response should be programmed only= on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400400", + "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Far(not in the same= quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000408000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Far(not in the same quadrant as the request)-other tile's L2 in M state.= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400400", + "BriefDescription": "Counts any request that accounts for reponses= from snoop request hit with data forwarded from its Near-other tile L2 in = E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800188000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Far(not in the same quadrant as the request)-other tile's L2 in E/F stat= e. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080400", + "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Near-other tile's L= 2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800088000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080400", + "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Near-other tile's L= 2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000088000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010400", + "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004008000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000200", + "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that are outstanding, per weighted cycle, from the time= of the request to when any response is received. The oustanding response s= hould be programmed only on PMC0.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1000400200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010008000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400200", + "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002008000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080200", + "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008008000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080200", + "BriefDescription": "Counts any request that are outstanding, per = weighted cycle, from the time of the request to when any response is receiv= ed. The oustanding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000008000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010200", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400100", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for reponses from snoop request hit with data forwarded from = it Far(not in the same quadrant as the request)-other tile L2 in E/F/M stat= e. Valid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Far(not in the same quadrant as the reque= st)-other tile's L2 in M state.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x0800400100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Far(not in the same quadrant as the reque= st)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080100", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Far(not in the same quadrant as the request)-other tile's L2 in E/F = state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080100", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Far(not in the same quadrant as the request)-other tile's L2 in M st= ate.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F= ", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010100", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for reponses from snoop request hit with data forwarded from = its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000080", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that are outstanding, per weighted cyc= le, from the time of the request to when any response is received. The oust= anding response should be programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400080", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Far(not in the same quadrant as= the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400080", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in E stat= e", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Far(not in the same quadrant as= the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mod= e.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080080", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in F stat= e", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Near-other tile's L2 in M state= .", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080080", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in M stat= e", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Near-other tile's L2 in E/F sta= te.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010080", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in S stat= e", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000040", + "BriefDescription": "Counts Demand cacheable data write requests = that are outstanding, per weighted cycle, from the time of the request to w= hen any response is received. The oustanding response should be programmed = only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400040", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400040", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for reponses from snoop request hit with data forwarded from it F= ar(not in the same quadrant as the request)-other tile L2 in E/F/M state. V= alid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080040", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Far(not in the same quadrant as the request)-other tile's L2 in E/F stat= e. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080040", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Far(not in the same quadrant as the request)-other tile's L2 in M state.= ", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010040", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for reponses from snoop request hit with data forwarded from its = Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400020", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Far(not in the same quadrant as the request)-other= tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400020", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Far(not in the same quadrant as the request)-other= tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080020", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080020", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000020020", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that provides no supplier details", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010020", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000004", + "BriefDescription": "Counts Bus locks and split lock requests that= are outstanding, per weighted cycle, from the time of the request to when = any response is received. The oustanding response should be programmed only= on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that are outstanding, per weighted cycle, from the time of the request = to when any response is received. The oustanding response should be program= med only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400004", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Far(not in the same quadrant as the request)-other tile's L2 in = M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400004", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for reponses from snoop request hit with data forwarded f= rom it Far(not in the same quadrant as the request)-other tile L2 in E/F/M = state. Valid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Far(not in the same quadrant as the request)-other tile's L2 in = E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080004", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Far(not in the same quadrant as the request)-other tile's L2 in = E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080004", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Far(not in the same quadrant as the request)-other tile's L2 in = M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F= ", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010004", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for reponses from snoop request hit with data forwarded f= rom its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000002", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F= ", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that are = outstanding, per weighted cycle, from the time of the request to when any r= esponse is received. The oustanding response should be programmed only on P= MC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400002", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Fa= r(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400002", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in E = state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Fa= r(not in the same quadrant as the request)-other tile's L2 in E/F state. Va= lid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080002", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in F = state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Ne= ar-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080002", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in M = state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Ne= ar-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010002", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in S = state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000001", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that are outstanding, per weighted cycle, from the time of the request = to when any response is received. The oustanding response should be program= med only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that are outstanding, per weighted cycle, from the time of the r= equest to when any response is received. The oustanding response should be = programmed only on PMC0.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000400001", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Far(not in the same quadrant as the request)-other tile's= L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800400001", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Far(not in the same quadrant as the request)-other tile's= L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Far(not in the same quadrant as the request)-other tile's= L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000080001", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Far(not in the same quadrant as the request)-other tile's= L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0800080001", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010001", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000001", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000002", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000004", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in M = state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000020", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000080", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that are outstanding, per weighted cycle, from the time of the r= equest to when any response is received. The oustanding response should be = programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000100", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000200", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for reponses from snoop request hit with data forwarded from it Far(no= t in the same quadrant as the request)-other tile L2 in E/F/M state. Valid = only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000400", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Fa= r(not in the same quadrant as the request)-other tile's L2 in E/F state. Va= lid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002001000", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Fa= r(not in the same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002002000", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for reponses from snoop request hit with data forwarded from its Near-= other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002008000", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Ne= ar-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002003091", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Ne= ar-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000022", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in M stat= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000044", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00020032f7", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0002000070", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000001", + "BriefDescription": "Counts Demand cacheable data writes that are = outstanding, per weighted cycle, from the time of the request to when any r= esponse is received. The oustanding response should be programmed only on P= MC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000002", + "BriefDescription": "Counts Full streaming stores (WC and should b= e programmed on PMC1) that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010800", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000004", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in E = state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000020", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for reponses from snoop = request hit with data forwarded from it Far(not in the same quadrant as the= request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000040", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Far(not in the same quadrant as= the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mod= e.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000080", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Far(not in the same quadrant as= the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000100", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for reponses from snoop = request hit with data forwarded from its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000200", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Near-other tile's L2 in E/F sta= te.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000400", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Near-other tile's L2 in M state= .", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004001000", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004002000", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004008000", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004003091", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000022", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that are outstanding, per weighted cyc= le, from the time of the request to when any response is received. The oust= anding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in E stat= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0004000044", + "BriefDescription": "Counts Partial streaming stores (WC and shoul= d be programmed on PMC1) that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPON= SE", + "MSRIndex": "0x1a7", + "MSRValue": "0x0000014000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in E state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00040032f7", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "MSRValue": "0x0000010100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for reponses from snoop request hi= t with data forwarded from it Far(not in the same quadrant as the request)-= other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", - "MSRValue": "0x0004000070", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a7", + "MSRValue": "0x1800400100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Far(not in the same quadrant as the reque= st)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a7", + "MSRValue": "0x0800400100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in E state", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Far(not in the same quadrant as the reque= st)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", - "MSRValue": "0x0008000001", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a7", + "MSRValue": "0x1000400100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for reponses from snoop request hi= t with data forwarded from its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a7", + "MSRValue": "0x1800180100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in S state", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", - "MSRValue": "0x0008000002", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F= ", + "MSRIndex": "0x1a7", + "MSRValue": "0x0800080100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a7", + "MSRValue": "0x1000080100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000004", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a7", + "MSRValue": "0x0004000100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in S = state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000020", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a7", + "MSRValue": "0x0010000100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000080", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a7", + "MSRValue": "0x0002000100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000100", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a7", + "MSRValue": "0x0008000100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000200", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000400", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from it Far(not in th= e same quadrant as the request)-other tile L2 in E/F/M state. Valid only in= SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800402000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008001000", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800402000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008002000", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000402000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008008000", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from its Near-other t= ile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800182000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008003091", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800082000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000022", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000082000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in S stat= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0008000044", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00080032f7", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in S state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000001", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000002", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000004", + "BriefDescription": "Counts L1 data HW prefetches that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The oustanding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in F = state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000020", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000040", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from it Far(not in th= e same quadrant as the request)-other tile L2 in E/F/M state. Valid only in= SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000080", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000100", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000200", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from its Near-other t= ile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000400", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010001000", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010002000", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010008000", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010003091", + "BriefDescription": "Counts L2 code HW prefetches that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The oustanding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000022", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in F stat= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000044", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Far(not in the same quadrant as the request)-other= tile's L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00100032f7", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Far(not in the same quadrant as the request)-other= tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0010000070", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for reponses from snoop request hit with da= ta forwarded from its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in F state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180002", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for reponses from snoop request hit with data forwarded from its Near-= other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180004", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for reponses from snoop request hit with data forwarded f= rom its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180020", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for reponses from snoop request hit with da= ta forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180040", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from its Near-other t= ile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180080", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for reponses from snoop = request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180100", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for reponses from snoop request hi= t with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180200", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that provides no supplier details", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000020020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for reponses from snoop request hit with = data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180400", + "BriefDescription": "Counts Software Prefetches that accounts for = any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000011000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for reponses from snoop request hit with data forwarded from its = Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800181000", + "BriefDescription": "Counts Software Prefetches that accounts for = reponses from snoop request hit with data forwarded from it Far(not in the = same quadrant as the request)-other tile L2 in E/F/M state. Valid only in S= NC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800401000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = reponses from snoop request hit with data forwarded from its Near-other til= e L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800182000", + "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Far(not in = the same quadrant as the request)-other tile's L2 in E/F state. Valid only = for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800401000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from its Near-other t= ile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800188000", + "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Far(not in = the same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000401000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for reponses= from snoop request hit with data forwarded from its Near-other tile L2 in = E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800183091", + "BriefDescription": "Counts Software Prefetches that accounts for = reponses from snoop request hit with data forwarded from its Near-other til= e L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800181000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for reponses from snoop request hit with = data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180022", + "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Near-other = tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800081000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for reponses from snoop request hit with data forwarded from = its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180044", + "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Near-other = tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000081000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for reponses from snoop request hit with data fo= rwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18001832f7", + "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004001000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= ponses from snoop request hit with data forwarded from its Near-other tile = L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800180070", + "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010001000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r reponses from snoop request hit with data forwarded from its Near-other t= ile L2 in E/F/M state", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400002", + "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002001000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for reponses from snoop request hit with data forwarded from it Far(no= t in the same quadrant as the request)-other tile L2 in E/F/M state. Valid = only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400004", + "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008001000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for reponses from snoop request hit with data forwarded f= rom it Far(not in the same quadrant as the request)-other tile L2 in E/F/M = state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400040", + "BriefDescription": "Counts Software Prefetches that are outstandi= ng, per weighted cycle, from the time of the request to when any response i= s received. The oustanding response should be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000001000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from it Far(not in th= e same quadrant as the request)-other tile L2 in E/F/M state. Valid only in= SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts all streaming stores (WC and should be= programmed on PMC1) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", - "MSRValue": "0x1800400080", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "MSRValue": "0x0000014800", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for reponses from snoop = request hit with data forwarded from it Far(not in the same quadrant as the= request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400100", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for reponses from snoop request hi= t with data forwarded from it Far(not in the same quadrant as the request)-= other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400400", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for reponses from snoop request hit with data forwarded from it F= ar(not in the same quadrant as the request)-other tile L2 in E/F/M state. V= alid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800401000", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for reponses from snoop request hit with = data forwarded from its Near-other tile L2 in E/F/M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = reponses from snoop request hit with data forwarded from it Far(not in the = same quadrant as the request)-other tile L2 in E/F/M state. Valid only in S= NC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800402000", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in E/F state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r reponses from snoop request hit with data forwarded from it Far(not in th= e same quadrant as the request)-other tile L2 in E/F/M state. Valid only in= SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800408000", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for reponses= from snoop request hit with data forwarded from it Far(not in the same qua= drant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Clus= ter mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800403091", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in E state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for reponses from snoop request hit with = data forwarded from it Far(not in the same quadrant as the request)-other t= ile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400022", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in F state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for reponses from snoop request hit with data forwarded from = it Far(not in the same quadrant as the request)-other tile L2 in E/F/M stat= e. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400044", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in M state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for reponses from snoop request hit with data fo= rwarded from it Far(not in the same quadrant as the request)-other tile L2 = in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18004032f7", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in S state", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= ponses from snoop request hit with data forwarded from it Far(not in the sa= me quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC= 4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400070", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that are outstanding, per weighted cycle, from the time= of the request to when any response is received. The oustanding response s= hould be programmed only on PMC0.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r reponses from snoop request hit with data forwarded from it Far(not in th= e same quadrant as the request)-other tile L2 in E/F/M state. Valid only in= SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.j= son b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json new file mode 100644 index 000000000000..5fce5020efa1 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json @@ -0,0 +1,29 @@ +[ + { + "BriefDescription": "Counts the number of floating operations reti= red that required microcode assists", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PublicDescription": "This event counts the number of times that t= he pipeline stalled due to FP operations needing assists.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, A= VX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX= 2, AVX-512 micro-ops (both floating point and integer) except for loads (me= mory-to-register mov-type micro-ops), packed byte and word multiplies.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.PACKED_SIMD", + "PublicDescription": "This event counts the number of packed vecto= r SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer an= d store) except for loads (memory-to-register mov-type micro-ops), packed b= yte and word multiplies.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, A= VX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX= 2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro op= s), division, sqrt.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.SCALAR_SIMD", + "PublicDescription": "This event counts the number of scalar SSE, = AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) ex= cept for loads (memory-to-register mov-type micro ops), division, sqrt.", + "SampleAfterValue": "200003", + "UMask": "0x20" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/= tools/perf/pmu-events/arch/x86/knightslanding/frontend.json index 6d38636689a4..d075ab594d75 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -1,34 +1,58 @@ [ { - "EventCode": "0x80", + "BriefDescription": "Counts the number of times the front end rest= eers for any branch as a result of another branch handling mechanism in the= front end.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times the front end rest= eers for conditional branches as a result of another branch handling mechan= ism in the front end.", + "Counter": "0,1", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of times the front end rest= eers for RET branches as a result of another branch handling mechanism in t= he front end.", + "Counter": "0,1", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", - "BriefDescription": "Counts all instruction fetches, including unc= acheable fetches." + "UMask": "0x8" }, { + "BriefDescription": "Counts all instruction fetches, including unc= acheable fetches.", + "Counter": "0,1", "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts all instruction fetches that hit the i= nstruction cache.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200003", - "BriefDescription": "Counts all instruction fetches that hit the i= nstruction cache." + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Counts all instruction fetches that miss the = instruction cache or produce memory requests. An instruction fetch miss is = counted only once and not once for every cycle it is outstanding.", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", - "BriefDescription": "Counts all instruction fetches that miss the = instruction cache or produce memory requests. An instruction fetch miss is = counted only once and not once for every cycle it is outstanding." + "UMask": "0x2" }, { - "EventCode": "0xE7", + "BriefDescription": "Counts the number of times the MSROM starts a= flow of uops.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the MSROM starts a= flow of uops." + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/to= ols/perf/pmu-events/arch/x86/knightslanding/memory.json index c6bb16ba0f86..5e6ca6896af1 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json @@ -1,1110 +1,1110 @@ [ { - "EventCode": "0xC3", + "BriefDescription": "Counts the number of times the machine clears= due to memory ordering hazards", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the machine clears= due to memory ordering hazards" + "UMask": "0x2" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800070", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x01004032f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from MCDRAM Far or Other tile= L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for da= ta responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00802032f7", + "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for da= ta responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x01010032f7", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181803091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for da= ta responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x00808032f7", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for da= ta responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080803091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from MCDRAM Far or Other tile= L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from MCDRAM (local and far)= ", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180603091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from MCDRAM Far or Oth= er tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100403091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800044", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080203091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400022", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200022", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000022", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800022", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100403091", + "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from MCDRAM Far or Oth= er tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080203091", + "BriefDescription": "Counts any Read request that accounts for re= sponses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01818032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101003091", + "BriefDescription": "Counts any Read request that accounts for da= ta responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01010032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080803091", + "BriefDescription": "Counts any Read request that accounts for da= ta responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00808032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100408000", + "BriefDescription": "Counts any Read request that accounts for re= sponses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01806032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data res= ponses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080208000", + "BriefDescription": "Counts any Read request that accounts for da= ta responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01004032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data res= ponses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101008000", + "BriefDescription": "Counts any Read request that accounts for da= ta responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00802032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data res= ponses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080808000", + "BriefDescription": "Counts any request that accounts for response= s from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181808000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data res= ponses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100402000", + "BriefDescription": "Counts any request that accounts for data res= ponses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101008000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080202000", + "BriefDescription": "Counts any request that accounts for data res= ponses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080808000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101002000", + "BriefDescription": "Counts any request that accounts for response= s from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180608000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080802000", + "BriefDescription": "Counts any request that accounts for data res= ponses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100408000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100401000", + "BriefDescription": "Counts any request that accounts for data res= ponses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080208000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080201000", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101001000", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080801000", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400400", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200400", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000400", + "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800400", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400200", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from MCDRAM Far or Oth= er tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200200", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000200", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800200", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400100", + "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200400", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from MCDRAM Far= or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200100", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from MCDRAM Loc= al.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000100", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800100", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from DRAM Local= .", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2000020080", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from any N= ON_DRAM system address. This includes MMIO transactions", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400080", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from MCDRAM Far or Other tile L2 hit f= ar.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200080", + "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000080", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800080", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400040", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200040", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000040", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from MCDRAM Far or Other tile L= 2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800040", + "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2000020020", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from any NON_DRAM system addr= ess. This includes MMIO transactions", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400020", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from MCDRAM Far or Other= tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200020", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000020", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800020", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400004", + "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from MCDRAM Far or Other tile L2 hit f= ar.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200004", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from DDR (= local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000004", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800004", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400002", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from MCDRA= M (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200002", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000002", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800002", + "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from any N= ON_DRAM system address. This includes MMIO transactions", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400001", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0101000100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from MCDRAM Far or Other tile L= 2 hit far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080200001", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from DRAM Local= .", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0080800100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from MCDRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0101000001", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from MCDRAM (local a= nd far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", + "MSRIndex": "0x1a7", + "MSRValue": "0x0180600100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from DRAM Far.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080800001", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from MCDRAM Far= or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0100400100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from DRAM Local.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600001", + "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from MCDRAM Loc= al.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0080200100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600002", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181802000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600004", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600020", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080802000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600080", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100402000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from MCDRA= M (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600100", + "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", - "MSRIndex": "0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080202000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from MCDRAM (local a= nd far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600200", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from MCDRAM (local and far)= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600400", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180601000", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180608000", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180603091", + "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from MCDRAM (local and far)= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600022", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600044", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x01806032f7", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0180600070", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from MCDRAM (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800001", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from MCDRAM Far or Other= tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800002", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800004", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from any NON_DRAM system addr= ess. This includes MMIO transactions", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800020", + "BriefDescription": "Counts Software Prefetches that accounts for = responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181801000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800040", + "BriefDescription": "Counts Software Prefetches that accounts for = data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101001000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800080", + "BriefDescription": "Counts Software Prefetches that accounts for = data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080801000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from DDR (= local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800200", + "BriefDescription": "Counts Software Prefetches that accounts for = responses from MCDRAM (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180601000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800400", + "BriefDescription": "Counts Software Prefetches that accounts for = data responses from MCDRAM Far or Other tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100401000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181801000", + "BriefDescription": "Counts Software Prefetches that accounts for = data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080201000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for = responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181802000", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181808000", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for response= s from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181803091", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from DRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800022", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from MCDRAM (local and far)= ", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0181800044", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from MCDRAM Far or Oth= er tile L2 hit far.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x01818032f7", + "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from MCDRAM Local.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200200", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for re= sponses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/= tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json index 92e4ef2e22c6..8f4213e5fbfd 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json @@ -1,432 +1,377 @@ [ { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of branch instructions reti= red", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions reti= red" - }, - { "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_INST_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions reti= red that were conditional jumps." + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions reti= red that were conditional jumps and predicted taken." - }, - { - "PEBS": "1", "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xf9", "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near CALL branch instruc= tions retired." + "UMask": "0xf9" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of far branch instructions = retired.", "Counter": "0,1", - "UMask": "0xfd", - "EventName": "BR_INST_RETIRED.REL_CALL", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired." + "UMask": "0xbf" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", "Counter": "0,1", - "UMask": "0xfb", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired." + "UMask": "0xfb" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of branch instructions reti= red that were conditional jumps.", "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_INST_RETIRED.RETURN", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near RET branch instruct= ions retired." + "UMask": "0x7e" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of branch instructions reti= red that were near indirect CALL or near indirect JMP.", "Counter": "0,1", - "UMask": "0xeb", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions reti= red that were near indirect CALL or near indirect JMP." - }, - { "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xbf", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of far branch instructions = retired." + "UMask": "0xeb" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired" - }, - { + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_MISP_RETIRED.JCC", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were conditional jumps." + "UMask": "0xfd" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were conditional jumps and predicted taken." - }, - { + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0xfb", - "EventName": "BR_MISP_RETIRED.IND_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired." + "UMask": "0xf7" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of branch instructions reti= red that were conditional jumps and predicted taken.", "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_MISP_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired." - }, - { + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0xeb", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were near indirect CALL or near indirect JMP." + "UMask": "0xfe" }, { - "PublicDescription": "This event counts the number of micro-ops re= tired that were supplied from MSROM.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired", "Counter": "0,1", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.MS", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of micro-ops retired that a= re from the complex flows issued by the micro-sequencer (MS)." - }, - { - "PublicDescription": "This event counts the number of micro-ops (u= ops) retired. The processor decodes complex macro instructions into a seque= nce of simpler uops. Most instructions are composed of one or two uops. Som= e instructions are decoded into longer sequences such as repeat instruction= s, floating point transcendental instructions, and assists.", - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of micro-ops retired" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "SampleAfterValue": "200003" }, { - "PublicDescription": "This event counts the number of scalar SSE, = AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) ex= cept for loads (memory-to-register mov-type micro ops), division, sqrt.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted near CALL b= ranch instructions retired.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "UOPS_RETIRED.SCALAR_SIMD", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, A= VX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX= 2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro op= s), division, sqrt." + "UMask": "0xf9" }, { - "PublicDescription": "This event counts the number of packed vecto= r SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer an= d store) except for loads (memory-to-register mov-type micro-ops), packed b= yte and word multiplies.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted far branch = instructions retired.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "UOPS_RETIRED.PACKED_SIMD", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.FAR_BRANCH", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, A= VX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX= 2, AVX-512 micro-ops (both floating point and integer) except for loads (me= mory-to-register mov-type micro-ops), packed byte and word multiplies." + "UMask": "0xbf" }, { - "EventCode": "0xC3", + "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times that the machine c= lears due to program modifying data within 1K of a recently fetched code pa= ge" + "UMask": "0xfb" }, { - "PublicDescription": "This event counts the number of times that t= he pipeline stalled due to FP operations needing assists.", - "EventCode": "0xC3", + "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were conditional jumps.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.FP_ASSIST", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of floating operations reti= red that required microcode assists" + "UMask": "0x7e" }, { - "EventCode": "0xC3", + "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were near indirect CALL or near indirect JMP.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "MACHINE_CLEARS.ALL", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts all nukes" + "UMask": "0xeb" }, { - "EventCode": "0xCA", + "BriefDescription": "Counts the number of mispredicted near relati= ve CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.REL_CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and the ROB is full" + "UMask": "0xfd" }, { - "PublicDescription": "This event counts the number of core cycles = when no uops are allocated and the alloc pipe is stalled waiting for a misp= redicted branch to retire.", - "EventCode": "0xCA", + "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and the alloc pipe is stalled waiting for a mispredicte= d branch to retire." + "UMask": "0xf7" }, { - "EventCode": "0xCA", + "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were conditional jumps and predicted taken.", "Counter": "0,1", - "UMask": "0x20", - "EventName": "NO_ALLOC_CYCLES.RAT_STALL", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and a RATstall (caused by reservation station full) is = asserted." + "UMask": "0xfe" }, { - "PublicDescription": "This event counts the number of core cycles = when no uops are allocated, the instruction queue is empty and the alloc pi= pe is stalled waiting for instructions to be fetched.", - "EventCode": "0xCA", + "BriefDescription": "Counts the number of unhalted reference clock= cycles", "Counter": "0,1", - "UMask": "0x90", - "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated, the IQ is empty, and no other condition is blocking al= location." + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "NO_ALLOC_CYCLES.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles when n= o micro-ops are allocated for any reason." + "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0xCB", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "RS_FULL_STALL.MEC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when allocat= ion pipeline is stalled and is waiting for a free MEC reservation station e= ntry." + "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCB", + "BriefDescription": "Counts the number of unhalted core clock cycl= es", "Counter": "0,1", - "UMask": "0x1f", - "EventName": "RS_FULL_STALL.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles the Al= loc pipeline is stalled when any one of the reservation stations is full." + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" }, { - "EventCode": "0xC0", + "BriefDescription": "Cycles the number of core cycles when divider= is busy. Does not imply a stall waiting for the divider.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the total number of instructions retir= ed" - }, - { - "PublicDescription": "This event counts cycles when the divider is= busy. More specifically cycles when the divide unit is unable to accept a = new divide uop because it is busy processing a previously dispatched uop. T= he cycles will be counted irrespective of whether or not another divide uop= is waiting to enter the divide unit (from the RS). This event counts integ= er divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not co= unt vector divides.", "EventCode": "0xCD", - "Counter": "0,1", - "UMask": "0x1", "EventName": "CYCLES_DIV_BUSY.ALL", + "PublicDescription": "This event counts cycles when the divider is= busy. More specifically cycles when the divide unit is unable to accept a = new divide uop because it is busy processing a previously dispatched uop. T= he cycles will be counted irrespective of whether or not another divide uop= is waiting to enter the divide unit (from the RS). This event counts integ= er divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not co= unt vector divides.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles the number of core cycles when divider= is busy. Does not imply a stall waiting for the divider." + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of instructions= that retire. For instructions that consist of multiple micro-ops, this ev= ent counts exactly once, as the last micro-op of the instruction retires. = The event continues counting while instructions retire, including during in= terrupt service routines caused by hardware interrupts, faults or traps.", + "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", "Counter": "Fixed counter 1", - "UMask": "0x1", "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= that retire. For instructions that consist of multiple micro-ops, this ev= ent counts exactly once, as the last micro-op of the instruction retires. = The event continues counting while instructions retire, including during in= terrupt service routines caused by hardware interrupts, faults or traps.", "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired" + "UMask": "0x1" }, { - "EventCode": "0x3C", + "BriefDescription": "Counts the total number of instructions retir= ed", "Counter": "0,1", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted core clock cycl= es" + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x3C", + "BriefDescription": "Counts all nukes", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted reference clock= cycles" + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter", - "Counter": "Fixed counter 2", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles" + "BriefDescription": "Counts the number of times that the machine c= lears due to program modifying data within 1K of a recently fetched code pa= ge", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "Counter": "Fixed counter 3", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles" + "BriefDescription": "Counts the total number of core cycles when n= o micro-ops are allocated for any reason.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ALL", + "SampleAfterValue": "200003", + "UMask": "0x7f" + }, + { + "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and the alloc pipe is stalled waiting for a mispredicte= d branch to retire.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "PublicDescription": "This event counts the number of core cycles = when no uops are allocated and the alloc pipe is stalled waiting for a misp= redicted branch to retire.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0xE6", + "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated, the IQ is empty, and no other condition is blocking al= location.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BACLEARS.ALL", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "PublicDescription": "This event counts the number of core cycles = when no uops are allocated, the instruction queue is empty and the alloc pi= pe is stalled waiting for instructions to be fetched.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the front end rest= eers for any branch as a result of another branch handling mechanism in the= front end." + "UMask": "0x90" }, { - "EventCode": "0xE6", + "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and a RATstall (caused by reservation station full) is = asserted.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "BACLEARS.RETURN", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.RAT_STALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the front end rest= eers for RET branches as a result of another branch handling mechanism in t= he front end." + "UMask": "0x20" }, { - "EventCode": "0xE6", + "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and the ROB is full", "Counter": "0,1", - "UMask": "0x10", - "EventName": "BACLEARS.COND", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ROB_FULL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the front end rest= eers for conditional branches as a result of another branch handling mechan= ism in the front end." + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0x03", + "BriefDescription": "Counts any retired load that was pushed into = the recycle queue for any reason.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", + "EventCode": "0x03", + "EventName": "RECYCLEQ.ANY_LD", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired loa= d gets blocked because its address partially overlaps with a store", - "Data_LA": "1" + "UMask": "0x40" }, { + "BriefDescription": "Counts any retired store that was pushed into= the recycle queue for any reason.", + "Counter": "0,1", "EventCode": "0x03", + "EventName": "RECYCLEQ.ANY_ST", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of occurences a retired loa= d gets blocked because its address overlaps with a store whose data is not = ready", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x03", "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired loa= d gets blocked because its address overlaps with a store whose data is not = ready" + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of retired stor= e that experienced a cache line boundary split(Precise Event). Note that ea= ch spilt should be counted only once.", - "EventCode": "0x03", + "BriefDescription": "Counts the number of occurences a retired loa= d gets blocked because its address partially overlaps with a store", "Counter": "0,1", - "UMask": "0x4", - "EventName": "RECYCLEQ.ST_SPLITS", + "Data_LA": "1", + "EventCode": "0x03", + "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired sto= re that is a cache line split. Each split should be counted only once." + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0x03", + "BriefDescription": "Counts the number of occurences a retired loa= d that is a cache line split. Each split should be counted only once.", "Counter": "0,1", - "UMask": "0x8", + "Data_LA": "1", + "EventCode": "0x03", "EventName": "RECYCLEQ.LD_SPLITS", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired loa= d that is a cache line split. Each split should be counted only once.", - "Data_LA": "1" + "UMask": "0x8" }, { - "EventCode": "0x03", + "BriefDescription": "Counts all the retired locked loads. It does = not include stores because we would double count if we count stores", "Counter": "0,1", - "UMask": "0x10", + "EventCode": "0x03", "EventName": "RECYCLEQ.LOCK", "SampleAfterValue": "200003", - "BriefDescription": "Counts all the retired locked loads. It does = not include stores because we would double count if we count stores" + "UMask": "0x10" }, { - "EventCode": "0x03", + "BriefDescription": "Counts the store micro-ops retired that were = pushed in the rehad queue because the store address buffer is full", "Counter": "0,1", - "UMask": "0x20", + "EventCode": "0x03", "EventName": "RECYCLEQ.STA_FULL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the store micro-ops retired that were = pushed in the rehad queue because the store address buffer is full" + "UMask": "0x20" }, { - "EventCode": "0x03", + "BriefDescription": "Counts the number of occurences a retired sto= re that is a cache line split. Each split should be counted only once.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "RECYCLEQ.ANY_LD", + "EventCode": "0x03", + "EventName": "RECYCLEQ.ST_SPLITS", + "PublicDescription": "This event counts the number of retired stor= e that experienced a cache line boundary split(Precise Event). Note that ea= ch spilt should be counted only once.", "SampleAfterValue": "200003", - "BriefDescription": "Counts any retired load that was pushed into = the recycle queue for any reason." + "UMask": "0x4" }, { - "EventCode": "0x03", + "BriefDescription": "Counts the total number of core cycles the Al= loc pipeline is stalled when any one of the reservation stations is full.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "RECYCLEQ.ANY_ST", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts any retired store that was pushed into= the recycle queue for any reason." + "UMask": "0x1f" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of core cycles when allocat= ion pipeline is stalled and is waiting for a free MEC reservation station e= ntry.", "Counter": "0,1", - "UMask": "0xf9", - "EventName": "BR_MISP_RETIRED.CALL", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.MEC", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near CALL b= ranch instructions retired." + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of micro-ops retired", "Counter": "0,1", - "UMask": "0xfd", - "EventName": "BR_MISP_RETIRED.REL_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near relati= ve CALL branch instructions retired." + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "This event counts the number of micro-ops (u= ops) retired. The processor decodes complex macro instructions into a seque= nce of simpler uops. Most instructions are composed of one or two uops. Som= e instructions are decoded into longer sequences such as repeat instruction= s, floating point transcendental instructions, and assists.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of micro-ops retired that a= re from the complex flows issued by the micro-sequencer (MS).", "Counter": "0,1", - "UMask": "0xbf", - "EventName": "BR_MISP_RETIRED.FAR_BRANCH", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted far branch = instructions retired." + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PublicDescription": "This event counts the number of micro-ops re= tired that were supplied from MSROM.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.j= son b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json index 9e493977771f..eda299ef5ff8 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json @@ -1,65 +1,65 @@ [ { - "PEBS": "1", - "EventCode": "0x04", + "BriefDescription": "Counts the number of load micro-ops retired t= hat cause a DTLB miss", "Counter": "0,1", - "UMask": "0x8", + "Data_LA": "1", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load micro-ops retired t= hat cause a DTLB miss", - "Data_LA": "1" + "UMask": "0x8" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total number of core cycles for al= l the page walks. The cycles for page walks started in speculative path wil= l also be included.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total D-side page walks that are c= ompleted or started. The page walks started in the speculative path will al= so be counted", - "EdgeDetect": "1" + "EventCode": "0x05", + "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "This event counts every cycle when a data (D= ) page walk or instruction (I) page walk is in progress.", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total number of core cycles for al= l the D-side page walks. The cycles for page walks started in speculative p= ath will also be included.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles for al= l the D-side page walks. The cycles for page walks started in speculative p= ath will also be included." + "UMask": "0x1" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total D-side page walks that are c= ompleted or started. The page walks started in the speculative path will al= so be counted", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total I-side page walks that are c= ompleted.", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "PublicDescription": "This event counts every cycle when an I-side= (walks due to an instruction fetch) page walk is in progress.", - "EventCode": "0x05", + "BriefDescription": "Counts the total number of core cycles for al= l the I-side page walks. The cycles for page walks started in speculative p= ath will also be included.", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when an I-side= (walks due to an instruction fetch) page walk is in progress.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles for al= l the I-side page walks. The cycles for page walks started in speculative p= ath will also be included." + "UMask": "0x2" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total I-side page walks that are c= ompleted.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total page walks that are complete= d (I-side and D-side)", - "EdgeDetect": "1" + "UMask": "0x2" }, { - "PublicDescription": "This event counts every cycle when a data (D= ) page walk or instruction (I) page walk is in progress.", - "EventCode": "0x05", + "BriefDescription": "Counts the total page walks that are complete= d (I-side and D-side)", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles for al= l the page walks. The cycles for page walks started in speculative path wil= l also be included." + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.WALKS", + "SampleAfterValue": "100003", + "UMask": "0x3" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D58B2C433FE for ; Tue, 1 Feb 2022 02:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233019AbiBACBT (ORCPT ); Mon, 31 Jan 2022 21:01:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232734AbiBACAR (ORCPT ); Mon, 31 Jan 2022 21:00:17 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE312C061775 for ; Mon, 31 Jan 2022 18:00:00 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id n198-20020a2540cf000000b00614c2ee23b7so30232294yba.9 for ; Mon, 31 Jan 2022 18:00:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=ss8RQMsQ1DFNyExeSjuDe4CPc0pnsNgihwKDv8nN94I=; b=XbPHI/RZCjOv2JieWo6FUgAJ4B1UwAvhrtINiYZnLBeLv87ep91p+g4NrxcTKOvCjY adssNDhvPcH0S5Jf4PC6JWqbHFgArj55e1YabWo0VXtgGNXDZTOGdQkLFXf7uFgRAA/f 1RLocOnbnq846Gft88GjdeOykEmpyPe0WYvmaaCloMC/llmArPQrRbM1xo8c8urooNRK pDe6zcqu5//1FRILaR3sPMv/1OPddoPrRbJSpbmpGwHTkcdGKGoYOnXdcFn+/JUkyL64 BxHXiPqI5WS2bu052bNrjt6PD76ODqQOtfWUut1k+vudAOB2UoNqPFJsZ81GyDUNnrcv SVAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=ss8RQMsQ1DFNyExeSjuDe4CPc0pnsNgihwKDv8nN94I=; b=Xnj74ZEI9IbT2zlpQCutuYkV65uqLY1XDNKY9vKSCUFD3vcRc/5GjcuFDm8lPsc9VR LGZ5/uFNrAUHYLaZmqIWcTsGOz6GSQYZDuW30S7RdZVu30cvAWSjW19luMCkpzzNkRcU ezet2wQhaMS5yMXojESAwEBFcAWElC1yu8jBMgF7mljFuoM+HtwLZbD4PE/iJlnyq4Rx K34E0Jyl7E6JSMzq9sUz2roPBLuVBaG913741c8oc3pb72nez0g8Oy/cYeL6buu2ZK3v 1JS4RW9rm7Be1fiNvJ0W4IiXsiV4AX8ot6rI2kOuA8AmebwdLNbnD54c7NGfBiXmmm9N 7KSQ== X-Gm-Message-State: AOAM532epQiniyQiRFY8UYNd14z22JQ18m/AfU9oImrCjDnr+EBD5yGU zi+rjfPHamz3DZAK2wST89cahf+XY4n7 X-Google-Smtp-Source: ABdhPJwSRMm4oBOggyttQwaXU515ah6QYaLL8GDIYufxz19h1Uwtop5Dz/5kpf7sVgAXubbISyYKF6ol/5GV X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:cc4e:: with SMTP id l75mr16079165ybf.189.1643680799827; Mon, 31 Jan 2022 17:59:59 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:51 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-20-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 19/26] perf vendor events: Update Nehalem EP From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Events are still version 2: https://download.01.org/perfmon/NHM-EP Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Nehalem EP, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/nehalemep/cache.json | 3062 ++++++++--------- .../arch/x86/nehalemep/floating-point.json | 180 +- .../arch/x86/nehalemep/frontend.json | 18 +- .../pmu-events/arch/x86/nehalemep/memory.json | 670 ++-- .../pmu-events/arch/x86/nehalemep/other.json | 156 +- .../arch/x86/nehalemep/pipeline.json | 764 ++-- .../arch/x86/nehalemep/virtual-memory.json | 90 +- 7 files changed, 2470 insertions(+), 2470 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/pe= rf/pmu-events/arch/x86/nehalemep/cache.json index a11029efda2f..bcf74d793ae2 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json @@ -1,3229 +1,3229 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x43", + "BriefDescription": "All references to the L1 data cache", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x43", "EventName": "L1D_ALL_REF.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All references to the L1 data cache" + "UMask": "0x1" }, { - "EventCode": "0x43", + "BriefDescription": "L1 data cacheable reads and writes", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x43", "EventName": "L1D_ALL_REF.CACHEABLE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cacheable reads and writes" + "UMask": "0x2" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in E state" + "UMask": "0x4" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in I state (misses)", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.I_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache reads", "Counter": "0,1", - "UMask": "0x8", - "EventName": "L1D_CACHE_LD.M_STATE", + "EventCode": "0x40", + "EventName": "L1D_CACHE_LD.MESI", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in M state" + "UMask": "0xf" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in M state", "Counter": "0,1", - "UMask": "0xf", - "EventName": "L1D_CACHE_LD.MESI", + "EventCode": "0x40", + "EventName": "L1D_CACHE_LD.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache reads" + "UMask": "0x8" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in S state" + "UMask": "0x2" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in E state" + "UMask": "0x4" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load lock hits", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load lock hits" + "UMask": "0x1" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in M state" + "UMask": "0x8" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in S state" + "UMask": "0x2" }, { - "EventCode": "0x53", + "BriefDescription": "L1D load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x53", "EventName": "L1D_CACHE_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r" + "UMask": "0x1" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in E state" + "UMask": "0x4" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in M state" + "UMask": "0x8" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in S state" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0x8" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0x8" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0x80" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch reque= st" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" + "UMask": "0x10" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x20" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { + "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "UMask": "0xc0" + }, + { + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" + "UMask": "0x40" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch misses", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" + "UMask": "0x80" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xc" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO misses", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 transactions", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" - }, - { "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0x80" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0x8" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (= Precise Event)" + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "100", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)" + "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)" + "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "10000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired with a data source = of local DRAM or locally homed remote hitm (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", - "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired remote cache HIT da= ta source (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", - "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue f= ull" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", + "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)" - }, - { - "PEBS": "2", "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", + "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", + "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", + "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", + "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", + "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", + "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", + "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", + "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", + "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", + "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)" + "UMask": "0x10" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F11", + "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired with a data source = of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x20" + }, + { + "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load instructions retired remote cache HIT da= ta source (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", + "SampleAfterValue": "4000", + "UMask": "0x80" + }, + { + "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "UMask": "0x40" + }, + { + "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4711", + "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4744", + "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x47FF", + "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x47FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x38FF", + "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x38FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3808", + "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y location", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1A6", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1A6", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1A6", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1A6", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1A6", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1A6", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4780", + "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote c= ache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote c= ache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote = cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F30", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF30", + "BriefDescription": "All offcore prefetch data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8030", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x130", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x130", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x230", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x230", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x430", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x430", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x730", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4730", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1830", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3830", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1030", + "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x830", + "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b= /tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "MMX Uops", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { + "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" + "UMask": "0x80" }, { - "EventCode": "0x10", + "BriefDescription": "SSE and SSE2 FP Uops", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP packed Uops", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP scalar Uops", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" + "UMask": "0x20" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP single precision Uops", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" + "UMask": "0x40" }, { - "EventCode": "0x10", + "BriefDescription": "Computational floating-point operations execu= ted", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations execu= ted" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transition= s", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transition= s" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instru= ctions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instru= ctions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operation= s" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools= /perf/pmu-events/arch/x86/nehalemep/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/p= erf/pmu-events/arch/x86/nehalemep/memory.json index f914a4525b65..26138ae639f4 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json @@ -1,739 +1,739 @@ [ { - "EventCode": "0xB7", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by the local DRA= M", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by the local DRA= M", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that misse= d the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that misse= d the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2080", + "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6030", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF830", + "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4030", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2030", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/pe= rf/pmu-events/arch/x86/nehalemep/other.json index af0860622445..710b106ce12a 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/other.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json @@ -1,210 +1,210 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address ali= asing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address ali= asing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HIT to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HITE to snoop", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" + "UMask": "0x2" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HITM to snoop", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" + "UMask": "0x4" }, { - "EventCode": "0xF6", + "BriefDescription": "Super Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools= /perf/pmu-events/arch/x86/nehalemep/pipeline.json index 41006ddcd893..e64d685c128a 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json @@ -1,881 +1,881 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", + "BriefDescription": "Divide Operations executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", "EventName": "ARITH.DIV", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Divide Operations executed", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired near call instructions (Precise Event= )", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event= )" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted branches executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches execu= ted", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches execu= ted" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Even= t)" + "UMask": "0x2" }, { - "EventCode": "0x0", + "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed count= er)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed count= er)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", + "BriefDescription": "Total CPU cycles", "Counter": "0,1,2,3", - "UMask": "0x0", + "CounterMask": "2", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder = 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder = 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", + "EventCode": "0x17", + "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instru= ction queue" + "UMask": "0x1" }, { - "EventCode": "0x17", + "BriefDescription": "Cycles instructions are written to the instru= ction queue", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITES", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Ev= ent)" + "UMask": "0x2" }, { - "EventCode": "0x4C", + "BriefDescription": "Load operations conflicting with software pre= fetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software pre= fetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", + "BriefDescription": "Cycles no uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.INACTIVE", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction = queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction = queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)" + "UMask": "0x10" }, { - "EventCode": "0xDB", + "BriefDescription": "Stack pointer instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", + "BriefDescription": "Cycles no Uops are decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)= ", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" - }, - { + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on ports 0-4 (core count)", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x3f" }, { + "AnyThread": "1", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on any port (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", + "SampleAfterValue": "2000000", + "UMask": "0x3f" + }, + { "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", + "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x80", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT234_CORE", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", + "BriefDescription": "Cycles no Uops were issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles Uops are being retired", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Uop unfusions due to FP exceptions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json index 0596094e0ee9..6d3247c55bcd 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json @@ -1,109 +1,109 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", - "EventCode": "0xCB", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)" + "UMask": "0x1" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA14CC433F5 for ; Tue, 1 Feb 2022 02:01:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233160AbiBACBe (ORCPT ); Mon, 31 Jan 2022 21:01:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232331AbiBACAR (ORCPT ); Mon, 31 Jan 2022 21:00:17 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A14FEC061777 for ; Mon, 31 Jan 2022 18:00:03 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id a88-20020a25a1e1000000b00615c588ab22so30284711ybi.3 for ; Mon, 31 Jan 2022 18:00:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=EQ/qIViTq29jN9upUO1k7DpkmqZFGtTUSKDeurrdNAk=; b=i/xbSEH1oY+khiP1/ZY3xHzDTWW6FSG0/ZKbNV1G9SapLIY3Pd5z4fVMWEjDfpFsgW bwl2hho5SCWR5zqBQEuD20e/Q+WUhlv3NyeSg45Pmg1CqQozzVnKyS0ZM/WXDupFbWU3 yk2ZK8rPg04qaMK43NpATg7h8SxhXEZLVKlDA34rglnBV2UOx4KNvaaUCNWKmBPLJK4/ c8om287Fyr6TUoHX/PS+nFFDJTE8ews95C/cNDziT6FG3jytWlOwwO3NgufyOrKPrEhK MXPOYGXDkHpwgmM0XuAHZJuA88++p5t2Rp2U4I/JRuwoUu765+4s2q7b2byXyucOcAGi hObQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=EQ/qIViTq29jN9upUO1k7DpkmqZFGtTUSKDeurrdNAk=; b=QiOh1YyToiySBJuY9O8CrD9YjhTV/o+xp6iIAbIs0p46xVEmQ05+fzCuhY+B7BGt4h lZ8V8UW588iPu67NUsmckkQ/UhWhjStwmGEF+12g85/zp0wwhJydlLJCXNfGNy94/tFx jH054p7kR8nNKOy2pqeboxIMEEP/nbYj4j9+MIm/nX6ReJJF+o6eTIVMCW6RGTHk/Qfb Gbkzb9nvJuIAuFJ5x7hwwjguSBE1Yg+gGpm1Fdm1xiDt6Jqu1X6Sf/a8T0zCFflSDmtu Zn9lVbkmM1PNm2Q6k1jmFJhbJDcNwGAOUFh9gcCbMhmru0WObbjPNqpt5rtVKO0kPUyc rWpw== X-Gm-Message-State: AOAM533ONMVZyY1XEOhRyH1q/5bmW6Sr117El0ECxG4gd/M4c5h3Fusa i/bGzIGHOwEmgPTHSHkd+2hKCBRsWyeC X-Google-Smtp-Source: ABdhPJyb7Pb1o93+mds1XiXMedCGCv1eedgGvK7gIjC5aa5uVDHAvkZciRBd0DKrTFOH5rtx9xQVYNIr1zGO X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:a206:: with SMTP id b6mr11902411ybi.707.1643680802756; Mon, 31 Jan 2022 18:00:02 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:52 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-21-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 20/26] perf vendor events: Update metrics for Skylake From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on TMA_metrics-full.csv version 4.3 at 01.org: https://download.01.org/perfmon/ Events are still version 52: https://download.01.org/perfmon/SKL Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Skylake, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/skylake/cache.json | 2611 +++++++++-------- .../arch/x86/skylake/floating-point.json | 48 +- .../pmu-events/arch/x86/skylake/frontend.json | 578 ++-- .../pmu-events/arch/x86/skylake/memory.json | 1566 +++++----- .../pmu-events/arch/x86/skylake/other.json | 46 +- .../pmu-events/arch/x86/skylake/pipeline.json | 1083 +++---- .../arch/x86/skylake/skl-metrics.json | 497 +++- .../arch/x86/skylake/virtual-memory.json | 274 +- 8 files changed, 3496 insertions(+), 3207 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf= /pmu-events/arch/x86/skylake/cache.json index 27ea2b00ad00..529c5e6e117f 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -1,53 +1,570 @@ [ { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x1f" + }, + { + "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines are in Modified = state. Modified lines are written back to L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.NON_SILENT", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.SILENT", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.USELESS_PREF", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts the total number of L2 code requests.= ", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PublicDescription": "Demand requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", + "SampleAfterValue": "200003", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "All requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xd8" + }, + { + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x38" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "All L2 requests.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL057", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches from L1 and L2. It does not include all misses to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL057", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code read= s, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches= from L1 and L2. It does not include all accesses to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "All retired load instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "2000003", + "UMask": "0x83" + }, + { + "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions that split = across a cacheline boundary.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources= were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= T_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources= were HitM responses from shared L3.", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources= were hits in L3 without snoops required.", "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Retired load instructions missed L1 cache as = data sources", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDE= D", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "PublicDescription": "Retired load instructions with L2 cache hits= as data sources.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "Retired load instructions missed L2 cache as= data sources.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -62,113 +579,168 @@ "UMask": "0x4" }, { - "BriefDescription": "Counts all demand code readshave any response= type.", + "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", - "Offcore": "1", - "PublicDescription": "Counts all demand code readshave any respons= e type.", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Counts cycles when offcore outstanding cache= able Core Data Read transactions are present in the super queue. A transact= ion is considered to be in the Offcore outstanding state between L2 miss an= d transaction completion sent to requestor (SQ de-allocation). See correspo= nding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "PublicDescription": "Counts cycles when offcore outstanding Deman= d Data Read transactions are present in the super queue (SQ). A transaction= is considered to be in the Offcore outstanding state between L2 miss and t= ransaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Counts the number of offcore outstanding dem= and rfo Reads transactions in the super queue every cycle. The 'Offcore out= standing' state of the transaction lasts from the L2 miss until the sending= transaction completion to requestor (SQ deallocation). See the correspondi= ng Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.PF_MISS", - "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x38" + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "EventName": "OFFCORE_RESPONSE", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code readshave any response= type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040001", + "MSRValue": "0x10004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040100001", + "MSRValue": "0x3FC01C0004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Demand requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "PublicDescription": "Demand requests that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x27" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FW= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100002", + "MSRValue": "0x10001C0004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x4001C0004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -177,24 +749,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040080004", + "MSRValue": "0x2001C0004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0408000", + "MSRValue": "0x801C0004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -203,69 +775,37 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400400004", + "MSRValue": "0x1001C0004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L3_HIT", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", - "SampleAfterValue": "50021", - "UMask": "0x4" - }, - { - "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF0", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "Counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x40" - }, - { - "BriefDescription": "L2 cache lines filling L2", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF1", - "EventName": "L2_LINES_IN.ALL", - "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "UMask": "0x1f" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_= FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400408000", + "MSRValue": "0x401C0004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C0002", + "MSRValue": "0x3FC0080004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -274,21 +814,11 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040004", + "MSRValue": "0x1000080004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests sent to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -297,50 +827,50 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0400004", + "MSRValue": "0x400080004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000400001", + "MSRValue": "0x200080004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080002", + "MSRValue": "0x80080004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100001", + "MSRValue": "0x100080004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -349,11 +879,11 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", + "MSRValue": "0x40080004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -362,24 +892,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C0004", + "MSRValue": "0x3FC0040004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C0002", + "MSRValue": "0x1000040004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -388,96 +918,63 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100004", + "MSRValue": "0x400040004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions missed L3 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L3_MISS", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", - "SampleAfterValue": "100007", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HI= T", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040020001", + "MSRValue": "0x200040004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "All retired store instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.ALL_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", - "SampleAfterValue": "2000003", - "UMask": "0x82" - }, { "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80040004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared or Exclusive state. A non-threaded event.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.SILENT", - "SampleAfterValue": "200003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040048000", + "MSRValue": "0x100040004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000088000", + "MSRValue": "0x40040004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -486,367 +983,297 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_= HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040400004", + "MSRValue": "0x3FC0100004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C0002", + "MSRValue": "0x1000100004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x400100004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "PublicDescription": "Counts cycles when offcore outstanding cache= able Core Data Read transactions are present in the super queue. A transact= ion is considered to be in the Offcore outstanding state between L2 miss an= d transaction completion sent to requestor (SQ de-allocation). See correspo= nding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, { "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C0004", + "MSRValue": "0x200100004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FW= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040002", + "MSRValue": "0x80100004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000028000", + "MSRValue": "0x100100004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x40100004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C0001", + "MSRValue": "0x3FC0400004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", + "MSRValue": "0x1000400004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C8000", + "MSRValue": "0x400400004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080001", + "MSRValue": "0x200400004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x80400004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL057", - "EventCode": "0x2E", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches from L1 and L2. It does not include all misses to the L3.", - "SampleAfterValue": "100003", - "UMask": "0x41" - }, - { - "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", - "SampleAfterValue": "200003", - "UMask": "0xf8" - }, { "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0080004", + "MSRValue": "0x100400004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= T_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_= HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", + "MSRValue": "0x40400004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040040002", + "MSRValue": "0x3FC0020004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= TM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000400002", + "MSRValue": "0x1000020004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDE= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x400020004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, { "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080004", + "MSRValue": "0x200020004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "RFO requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_MISS", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x22" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040001", + "MSRValue": "0x80020004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines are in Modified = state. Modified lines are written back to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.NON_SILENT", - "SampleAfterValue": "200003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040028000", + "MSRValue": "0x100020004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HI= T", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040002", + "MSRValue": "0x40020004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data readshave any response typ= e.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200408000", + "MSRValue": "0x10001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.USELESS_HWPF", - "SampleAfterValue": "200003", - "UMask": "0x4" - }, { "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040001", + "MSRValue": "0x3FC01C0001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -855,183 +1282,141 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100001", + "MSRValue": "0x10001C0001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)have any = response type.", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x4001C0001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)have any= response type.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C0002", + "MSRValue": "0x2001C0001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C0004", + "MSRValue": "0x801C0001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "All requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.MISS", - "PublicDescription": "All requests that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x3f" - }, - { - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "Counts the total number of L2 code requests.= ", - "SampleAfterValue": "200003", - "UMask": "0xe4" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0100002", + "MSRValue": "0x1001C0001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100004", + "MSRValue": "0x401C0001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "RFO requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_HIT", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0xc2" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080048000", + "MSRValue": "0x3FC0080001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", - "PEBS": "1", - "PublicDescription": "Retired load instructions which data sources= were L3 and cross-core snoop hits in on-pkg core cache.", - "SampleAfterValue": "20011", - "UMask": "0x2" - }, { "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C0001", + "MSRValue": "0x1000080001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080002", + "MSRValue": "0x400080001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040002", + "MSRValue": "0x200080001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0028000", + "MSRValue": "0x80080001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1040,82 +1425,63 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080001", + "MSRValue": "0x100080001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080004", + "MSRValue": "0x40080001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L1_MISS", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "L2 cache misses when fetching instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", - "SampleAfterValue": "200003", - "UMask": "0x24" + "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C0001", + "MSRValue": "0x1000040001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040080002", + "MSRValue": "0x400040001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1124,37 +1490,37 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C0001", + "MSRValue": "0x200040001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FW= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x80040001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400088000", + "MSRValue": "0x100040001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1163,37 +1529,37 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400001", + "MSRValue": "0x40040001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= NE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400002", + "MSRValue": "0x3FC0100001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C8000", + "MSRValue": "0x1000100001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1202,71 +1568,50 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x400100001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDE= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080002", + "MSRValue": "0x200100001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", - "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Demand requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "PublicDescription": "Demand requests to L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0xe7" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100048000", + "MSRValue": "0x80100001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100108000", + "MSRValue": "0x100100001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1275,87 +1620,76 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000020001", + "MSRValue": "0x40100001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040020002", + "MSRValue": "0x3FC0400001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000108000", + "MSRValue": "0x1000400001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040100002", + "MSRValue": "0x400400001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0040002", + "MSRValue": "0x200400001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "AnyThread": "1", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C8000", + "MSRValue": "0x80400001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1364,24 +1698,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C0001", + "MSRValue": "0x100400001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_= HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200088000", + "MSRValue": "0x40400001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1390,35 +1724,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100001", + "MSRValue": "0x3FC0020001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL057", - "EventCode": "0x2E", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code read= s, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches= from L1 and L2. It does not include all accesses to the L3.", - "SampleAfterValue": "100003", - "UMask": "0x4f" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200048000", + "MSRValue": "0x1000020001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1427,37 +1750,37 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0400001", + "MSRValue": "0x400020001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0020004", + "MSRValue": "0x200020001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080108000", + "MSRValue": "0x80020001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1466,188 +1789,180 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040080001", + "MSRValue": "0x100020001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDE= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HI= T", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100002", + "MSRValue": "0x40020001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)have any = response type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0040004", + "MSRValue": "0x10002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040040001", + "MSRValue": "0x3FC01C0002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x10001C0002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x4001C0002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions that miss the STLB.= ", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", - "PEBS": "1", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x11" + "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200108000", + "MSRValue": "0x801C0002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200400001", + "MSRValue": "0x1001C0002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readshave any response typ= e.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x401C0002", "Offcore": "1", - "PublicDescription": "Counts demand data readshave any response ty= pe.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000400004", + "MSRValue": "0x3FC0080002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080004", + "MSRValue": "0x1000080002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C8000", + "MSRValue": "0x400080002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "L1D data line replacements", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x51", - "EventName": "L1D.REPLACEMENT", - "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040004", + "MSRValue": "0x200080002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1656,318 +1971,193 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOO= P", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0400002", + "MSRValue": "0x80080002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD4", - "EventName": "MEM_LOAD_MISC_RETIRED.UC", - "PEBS": "1", - "SampleAfterValue": "100007", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040004", + "MSRValue": "0x100080002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.FB_HIT", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", - "SampleAfterValue": "100007", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0020001", + "MSRValue": "0x40080002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.USELESS_PREF", - "SampleAfterValue": "200003", - "UMask": "0x4" - }, { "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM= ", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000020002", + "MSRValue": "0x3FC0040002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.PF_HIT", - "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0xd8" - }, - { - "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "UMask": "0x21" - }, - { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HI= T", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040020004", + "MSRValue": "0x1000040002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100001", + "MSRValue": "0x400040002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", - "PEBS": "1", - "PublicDescription": "Retired load instructions which data sources= were hits in L3 without snoops required.", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "All retired load instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "PEBS": "1", - "SampleAfterValue": "2000003", - "UMask": "0x81" - }, - { - "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "PEBS": "1", - "SampleAfterValue": "20011", "UMask": "0x1" }, - { - "BriefDescription": "Demand Data Read requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", - "SampleAfterValue": "200003", - "UMask": "0xe1" - }, { "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE= ", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020002", + "MSRValue": "0x80040002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "All L2 requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.REFERENCES", - "PublicDescription": "All L2 requests.", - "SampleAfterValue": "200003", - "UMask": "0xff" - }, { "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100002", + "MSRValue": "0x100040002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100088000", + "MSRValue": "0x40040002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200400004", + "MSRValue": "0x3FC0100002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "PublicDescription": "Counts the number of offcore outstanding dem= and rfo Reads transactions in the super queue every cycle. The 'Offcore out= standing' state of the transaction lasts from the L2 miss until the sending= transaction completion to requestor (SQ deallocation). See the correspondi= ng Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0048000", + "MSRValue": "0x1000100002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C8000", + "MSRValue": "0x400100002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Number of cache line split locks sent to unco= re.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF4", - "EventName": "SQ_MISC.SPLIT_LOCK", - "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, { "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C0002", + "MSRValue": "0x200100002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040408000", + "MSRValue": "0x80100002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1976,11 +2166,11 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C0002", + "MSRValue": "0x100100002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1989,49 +2179,37 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FW= D", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080002", + "MSRValue": "0x40100002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "PEBS": "1", - "PublicDescription": "Retired load instructions with L2 cache hits= as data sources.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0040001", + "MSRValue": "0x3FC0400002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= TM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100001", + "MSRValue": "0x1000400002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2040,108 +2218,76 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= T_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100002", + "MSRValue": "0x400400002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040004", + "MSRValue": "0x200400002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000020004", + "MSRValue": "0x80400002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "L1D miss outstandings duration in cycles", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", - "SampleAfterValue": "200003", - "UMask": "0xc1" - }, { "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= T_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040400002", + "MSRValue": "0x100400002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C0004", + "MSRValue": "0x40400002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", - "PEBS": "1", - "PublicDescription": "Retired load instructions which data sources= were HitM responses from shared L3.", - "SampleAfterValue": "20011", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0100001", + "MSRValue": "0x3FC0020002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2150,63 +2296,50 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C0002", + "MSRValue": "0x1000020002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", - "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", - "SampleAfterValue": "100003", - "UMask": "0x42" - }, - { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400004", + "MSRValue": "0x400020002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100004", + "MSRValue": "0x200020002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C0004", + "MSRValue": "0x80020002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2215,34 +2348,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0020002", + "MSRValue": "0x100020002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Any memory transaction that reached the SQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", - "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", - "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_= HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040400001", + "MSRValue": "0x40020002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2253,32 +2376,22 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x18000", "Offcore": "1", - "PublicDescription": "Counts any other requestshave any response t= ype.", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040040004", + "MSRValue": "0x3FC01C8000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2287,23 +2400,25 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEE= DED", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100408000", + "MSRValue": "0x10001C8000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "PublicDescription": "Counts cycles when offcore outstanding Deman= d Data Read transactions are present in the super queue (SQ). A transaction= is considered to be in the Offcore outstanding state between L2 miss and t= ransaction completion sent to requestor (SQ de-allocation).", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -2311,47 +2426,37 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0088000", + "MSRValue": "0x2001C8000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", - "SampleAfterValue": "200003", - "UMask": "0xc4" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040001", + "MSRValue": "0x801C8000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040004", + "MSRValue": "0x1001C8000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2360,24 +2465,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080088000", + "MSRValue": "0x401C8000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040001", + "MSRValue": "0x3FC0088000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2386,73 +2491,63 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040088000", + "MSRValue": "0x1000088000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS= ", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020002", + "MSRValue": "0x400088000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100004", + "MSRValue": "0x200088000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040100004", + "MSRValue": "0x80088000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL", - "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, { "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400048000", + "MSRValue": "0x100088000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2461,11 +2556,11 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040108000", + "MSRValue": "0x40088000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2474,11 +2569,11 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0108000", + "MSRValue": "0x3FC0048000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2491,325 +2586,267 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000048000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080004", + "MSRValue": "0x400048000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080004", + "MSRValue": "0x200048000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100004", + "MSRValue": "0x80048000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C0001", + "MSRValue": "0x100048000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L1_HIT", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, { "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000408000", + "MSRValue": "0x40048000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x3FC0108000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0100004", + "MSRValue": "0x1000108000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400400001", + "MSRValue": "0x400108000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Retired load instructions with locked access.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.LOCK_LOADS", - "PEBS": "1", - "SampleAfterValue": "100007", - "UMask": "0x21" - }, { "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C8000", + "MSRValue": "0x200108000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040002", + "MSRValue": "0x80108000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C0004", + "MSRValue": "0x100108000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, { "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080408000", + "MSRValue": "0x40108000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0408000", + "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions that split = across a cacheline boundary.", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x41" + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080001", + "MSRValue": "0x400408000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB2", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "6", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080002", + "MSRValue": "0x200408000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x80408000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100002", + "MSRValue": "0x100408000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired store instructions that miss the STLB= .", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x12" + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080001", + "MSRValue": "0x3FC0028000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2818,109 +2855,87 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C8000", + "MSRValue": "0x1000028000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", - "SampleAfterValue": "200003", - "UMask": "0xe2" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MI= SS", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200400002", + "MSRValue": "0x400028000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Retired load instructions missed L2 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L2_MISS", - "PEBS": "1", - "PublicDescription": "Retired load instructions missed L2 cache as= data sources.", - "SampleAfterValue": "50021", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020002", + "MSRValue": "0x200028000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080001", + "MSRValue": "0x80028000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0080002", + "MSRValue": "0x100028000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C0001", + "MSRValue": "0x40028000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" + }, + { + "BriefDescription": "Number of cache line split locks sent to unco= re.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/skylake/floating-point.json index 834e1cd841fc..73cfb2a39722 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -1,67 +1,73 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 c= alculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, { - "BriefDescription": "Cycles with any input/output SSE or FP assist= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xCA", - "EventName": "FP_ASSIST.ANY", - "PublicDescription": "Counts cycles with any input and output SSE = or x87 FP assist. If an input and output assist are detected on the same cy= cle the event increments by 1.", - "SampleAfterValue": "100003", - "UMask": "0x1e" - }, - { - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "UMask": "0x8" + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Counts cycles with any input and output SSE = or x87 FP assist. If an input and output assist are detected on the same cy= cle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/p= erf/pmu-events/arch/x86/skylake/frontend.json index e84504d6adea..ecce4273ae52 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -1,96 +1,127 @@ [ { - "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x80", - "EventName": "ICACHE_16B.IFDATA_STALL", - "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking= MITE requires two or three cycles delay.", "SampleAfterValue": "2000003", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired Instructions who experienced DSB miss= .", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x14", + "MSRValue": "0x1", "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x408006", + "MSRValue": "0x11", "PEBS": "1", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES", - "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DS= B) path. Counting includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x8" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "PublicDescription": "Counts, on the per-thread basis, cycles when= less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_= Not_Delivered.core >=3D 3.", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xE6", - "EventName": "BACLEARS.ANY", - "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Retired Instructions who experienced decode s= tream buffer (DSB - the decoded instruction-cache) miss.", + "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.DSB_MISS", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", - "MSRValue": "0x11", - "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "MSRValue": "0x400106", + "PEBS": "2", + "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "PublicDescription": "Counts, on the per-thread basis, cycles when= no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Del= ivered.core =3D4.", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "MSRValue": "0x408006", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { @@ -108,92 +139,110 @@ "UMask": "0x1" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x79", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "UMask": "0x4" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "MSRIndex": "0x3F7", + "MSRValue": "0x400206", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "PublicDescription": "Cycles with less than 2 uops delivered by th= e front-end.", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "MSRIndex": "0x3F7", + "MSRValue": "0x410006", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS= ) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe ini= tiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "UMask": "0x30" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Cycles MITE is delivering any Uop", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. Counting includes uops that may 'bypass' the IDQ. During these = cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "UMask": "0x24" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", + "MSRIndex": "0x3F7", + "MSRValue": "0x200206", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_HIT", - "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", + "MSRIndex": "0x3F7", + "MSRValue": "0x300206", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_SWITCHES", - "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "SampleAfterValue": "2000003", - "UMask": "0x30" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "MSRIndex": "0x3F7", + "MSRValue": "0x402006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.L2_MISS", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", - "MSRValue": "0x13", + "MSRValue": "0x400406", "PEBS": "1", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES", - "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) from the MITE path. Counting incl= udes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x4" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "MSRValue": "0x420006", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", @@ -209,24 +258,60 @@ "UMask": "0x1" }, { - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "MSRValue": "0x400806", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x79", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x80", + "EventName": "ICACHE_16B.IFDATA_STALL", + "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", "SampleAfterValue": "2000003", - "UMask": "0x20" + "UMask": "0x4" + }, + { + "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_HIT", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_MISS", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", @@ -238,14 +323,15 @@ "UMask": "0x4" }, { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xAB", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts the number of cycles 4 uops were deli= vered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB)= path. Count includes uops that may 'bypass' the IDQ.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x18" }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", @@ -259,106 +345,79 @@ "UMask": "0x18" }, { - "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.STLB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x15", - "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", "EventCode": "0x79", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts the number of cycles 4 uops were deli= vered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pi= peline) path. Counting includes uops that may 'bypass' the IDQ. During thes= e cycles uops are not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "UMask": "0x8" + "UMask": "0x24" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", - "MSRIndex": "0x3F7", - "MSRValue": "0x420006", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. Counting includes uops that may 'bypass' the IDQ. During these = cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", - "MSRIndex": "0x3F7", - "MSRValue": "0x400806", - "PEBS": "1", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DS= B) path. Counting includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x400106", - "PEBS": "2", - "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", - "MSRIndex": "0x3F7", - "MSRValue": "0x400206", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) from the MITE path. Counting incl= udes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", - "MSRIndex": "0x3F7", - "MSRValue": "0x400406", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "BriefDescription": "Cycles MITE is delivering 4 Uops", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", + "CounterMask": "1", "EventCode": "0x79", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "PublicDescription": "Counts the number of cycles 4 uops were deli= vered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pi= peline) path. Counting includes uops that may 'bypass' the IDQ. During thes= e cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS= ) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe ini= tiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "UMask": "0x24" + "UMask": "0x30" }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", @@ -372,101 +431,56 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", "SampleAfterValue": "2000003", - "UMask": "0x30" - }, - { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", - "MSRIndex": "0x3F7", - "MSRValue": "0x410006", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", - "MSRIndex": "0x3F7", - "MSRValue": "0x200206", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", - "MSRIndex": "0x3F7", - "MSRValue": "0x300206", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x100206", - "PEBS": "1", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", "EventCode": "0x79", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "PublicDescription": "Counts the number of cycles 4 uops were deli= vered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB)= path. Count includes uops that may 'bypass' the IDQ.", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", "SampleAfterValue": "2000003", - "UMask": "0x18" + "UMask": "0x30" }, { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xAB", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking= MITE requires two or three cycles delay.", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", - "MSRIndex": "0x3F7", - "MSRValue": "0x402006", - "PEBS": "1", - "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "Counts, on the per-thread basis, cycles when= no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Del= ivered.core =3D4.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { @@ -481,25 +495,25 @@ "UMask": "0x1" }, { - "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_MISS", - "SampleAfterValue": "200003", - "UMask": "0x2" + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "PublicDescription": "Counts, on the per-thread basis, cycles when= less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_= Not_Delivered.core >=3D 3.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.L1I_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x12", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "PublicDescription": "Cycles with less than 2 uops delivered by th= e front-end.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/per= f/pmu-events/arch/x86/skylake/memory.json index 7bd3ae338343..8500fc65e0e8 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json @@ -1,53 +1,320 @@ [ + { + "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_MEM", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", + "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an HLE execution successfully= committed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL089", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "Counts the number of memory ordering Machine= Clears detected. Memory Ordering Machine Clears can result from one of the= following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-th= read snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand Data Read requests who miss L3 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, { "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_D= RAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000080004", + "MSRValue": "0x20001C0004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x2000080004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000100002", + "MSRValue": "0x2000040004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x2000100004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -56,24 +323,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C400004", + "MSRValue": "0x3FFC400004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C408000", + "MSRValue": "0x103C400004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -82,205 +349,141 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x43C400004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000088000", + "MSRValue": "0x23C400004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "6", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC408000", + "MSRValue": "0xBC400004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DR= AM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C408000", + "MSRValue": "0x203C400004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_TIMER", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C400001", + "MSRValue": "0x13C400004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000002", + "MSRValue": "0x7C400004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_MEM", - "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", - "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", - "SampleAfterValue": "2000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000080002", + "MSRValue": "0x3FC4000004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM= ", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004008000", + "MSRValue": "0x1004000004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000028000", + "MSRValue": "0x404000004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC408000", + "MSRValue": "0x204000004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C400002", + "MSRValue": "0x84000004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -289,83 +492,63 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000020004", + "MSRValue": "0x2004000004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_H= IT", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044000002", + "MSRValue": "0x104000004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= PL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x44000004", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C400001", + "MSRValue": "0x2000400004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache confl= ict.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand code reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004000001", + "MSRValue": "0x2000020004", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -374,112 +557,38 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_D= RAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000080001", + "MSRValue": "0x20001C0001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" - }, { "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x2000080001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_= DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC5", - "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", + "MSRValue": "0x2000040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -487,182 +596,154 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x2000100001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x3FFC400001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Number of times an RTM execution successfully= committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, { "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_D= RAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000100001", + "MSRValue": "0x103C400001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C400004", + "MSRValue": "0x43C400001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000048000", + "MSRValue": "0x23C400001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000002", + "MSRValue": "0xBC400001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DR= AM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DR= AM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C400004", + "MSRValue": "0x203C400001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C408000", + "MSRValue": "0x13C400001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x7C400001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_TIMER", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004000004", + "MSRValue": "0x3FC4000001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004000004", + "MSRValue": "0x1004000001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044008000", + "MSRValue": "0x404000001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -671,98 +752,89 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= PL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044000001", + "MSRValue": "0x204000001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000002", + "MSRValue": "0x84000001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C400004", + "MSRValue": "0x2004000001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC400002", + "MSRValue": "0x104000001", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRA= M", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= PL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000408000", + "MSRValue": "0x44000001", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_D= RAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000040004", + "MSRValue": "0x2000400001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts demand data reads", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000400004", + "MSRValue": "0x2000020001", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -771,24 +843,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= N_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000400002", + "MSRValue": "0x20001C0002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C0004", + "MSRValue": "0x2000080002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -797,112 +869,102 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C400002", + "MSRValue": "0x2000040002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C400004", + "MSRValue": "0x2000100002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_= NO_FWD", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x3FFC400002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_= NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x103C400002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000400001", + "MSRValue": "0x43C400002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C408000", + "MSRValue": "0x23C400002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution successfully= committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000020001", + "MSRValue": "0xBC400002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C408000", + "MSRValue": "0x203C400002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -911,11 +973,11 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C400002", + "MSRValue": "0x13C400002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -924,34 +986,24 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000040002", + "MSRValue": "0x7C400002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Demand Data Read requests who miss L3 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", - "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC400001", + "MSRValue": "0x3FC4000002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -960,97 +1012,76 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004000002", + "MSRValue": "0x1004000002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C400004", + "MSRValue": "0x404000002", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC400001", + "MSRValue": "0x204000002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", - "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_MEM", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C400001", + "MSRValue": "0x2004000002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DR= AM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C400001", + "MSRValue": "0x104000002", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1059,88 +1090,64 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_H= IT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C400002", + "MSRValue": "0x44000002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= N_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4008000", + "MSRValue": "0x2000400002", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED", - "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED", - "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, { "BriefDescription": "Counts all demand data writes (RFOs)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C400002", + "MSRValue": "0x2000020002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x20001C8000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", - "SampleAfterValue": "20011", - "TakenAlone": "1", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -1148,242 +1155,272 @@ "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_= DRAM", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004008000", + "MSRValue": "0x2000048000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "2000003", - "UMask": "0x20" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", - "SampleAfterValue": "2000003", - "UMask": "0x10" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFC408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4000004", + "MSRValue": "0x103C408000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "MSRValue": "0x200", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "101", - "TakenAlone": "1", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x43C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY", - "SampleAfterValue": "2000003", - "UMask": "0x2" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0xBC408000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", - "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", - "SampleAfterValue": "2000003", - "UMask": "0x40" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x13C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL089", - "EventCode": "0xC3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "Counts the number of memory ordering Machine= Clears detected. Memory Ordering Machine Clears can result from one of the= following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-th= read snoop (stores) hitting load buffer.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", - "SampleAfterValue": "2000003", - "UMask": "0x10" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC4008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C0002", + "MSRValue": "0x1004008000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HITM", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004000002", + "MSRValue": "0x404008000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRA= M", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C0001", + "MSRValue": "0x204008000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4000002", + "MSRValue": "0x84008000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C400001", + "MSRValue": "0x2004008000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_D= RAM", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000100004", + "MSRValue": "0x104008000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC400004", + "MSRValue": "0x44008000", "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C400001", + "MSRValue": "0x2000408000", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC400002", + "MSRValue": "0x2000028000", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", @@ -1395,217 +1432,180 @@ "UMask": "0x80" }, { - "BriefDescription": "Number of times an HLE execution started.", + "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "BriefDescription": "Number of times an RTM execution successfully= committed", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "BriefDescription": "Number of times an RTM execution started.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock B= uffer.", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", "SampleAfterValue": "2000003", - "UMask": "0x40" + "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= PL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "6", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", "SampleAfterValue": "2000003", - "UMask": "0x6" + "UMask": "0x8" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY", "SampleAfterValue": "2000003", - "UMask": "0x80" + "UMask": "0x2" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache confl= ict.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_D= RAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", - "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock B= uffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf= /pmu-events/arch/x86/skylake/other.json index 1a3683f1de91..5c0e81f76a5b 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -1,56 +1,56 @@ [ { - "BriefDescription": "Number of PREFETCHW instructions executed.", + "BriefDescription": "Number of hardware interrupts received by the= processor.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "SampleAfterValue": "2000003", - "UMask": "0x8" + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.RECEIVED", + "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", + "SampleAfterValue": "203", + "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", + "EventCode": "0x09", + "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Number of hardware interrupts received by the= processor.", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xCB", - "EventName": "HW_INTERRUPTS.RECEIVED", - "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", - "SampleAfterValue": "203", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "BriefDescription": "Number of PREFETCHW instructions executed.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "EventName": "SW_PREFETCH_ACCESS.T0", "SampleAfterValue": "2000003", - "UMask": "0x4" + "UMask": "0x2" }, { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x09", - "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/p= erf/pmu-events/arch/x86/skylake/pipeline.json index f46e93a57fb4..12eabae3e224 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -1,55 +1,58 @@ [ { - "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091, SKL044", - "EventCode": "0xC0", - "EventName": "INST_RETIRED.ANY_P", - "PublicDescription": "Counts the number of instructions (EOMs) ret= ired. Counting covers macro-fused instructions individually (that is, incre= ments by two).", - "SampleAfterValue": "2000003" - }, - { - "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", - "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_ACTIVE", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", - "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "UMask": "0x10" + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Counts all (macro) branch instructions retir= ed.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x14", - "EventName": "ARITH.DIVIDER_ACTIVE", - "SampleAfterValue": "2000003", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instruc= tions retired.", + "SampleAfterValue": "400009", "UMask": "0x1" }, { - "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", - "SampleAfterValue": "100003", - "UMask": "0x1" + "Errata": "SKL091", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PublicDescription": "This event counts not taken branch instructi= ons retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { "BriefDescription": "Far branch instructions retired.", @@ -64,309 +67,305 @@ "UMask": "0x40" }, { - "BriefDescription": "Counts the number of x87 uops dispatched.", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.X87", - "PublicDescription": "Counts the number of x87 uops executed.", - "SampleAfterValue": "2000003", - "UMask": "0x10" + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect n= ear call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x4C", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", - "SampleAfterValue": "100003", - "UMask": "0x1" + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This event counts return instructions retire= d.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", - "PublicDescription": "Counts both taken and not taken retired misp= redicted direct and indirect near calls, including both register and memory= indirect.", + "PublicDescription": "This event counts taken branch instructions = retired.", "SampleAfterValue": "400009", - "UMask": "0x2" + "UMask": "0x20" }, { - "BriefDescription": "Total execution stalls.", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "SampleAfterValue": "2000003", - "UMask": "0x4" + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructi= ons retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "UMask": "0x20" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "BriefDescription": "Mispredicted macro branch instructions retire= d.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xC2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", - "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "2000003", - "UMask": "0x2" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", - "SampleAfterValue": "2000003" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional b= ranch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "Counts both taken and not taken retired misp= redicted direct and indirect near calls, including both register and memory= indirect.", + "SampleAfterValue": "400009", + "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "25003", - "UMask": "0x1" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xC3", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "AnyThread": "1", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "25003", "UMask": "0x2" }, { - "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", - "SampleAfterValue": "2000003", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "25003", "UMask": "0x1" }, { - "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "AnyThread": "1", + "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", - "SampleAfterValue": "2000003", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "25003", "UMask": "0x1" }, { - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "Invert": "1", - "SampleAfterValue": "2000003", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "25003", "UMask": "0x2" }, { - "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", - "UMask": "0x40" + "UMask": "0x3" }, { - "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "SampleAfterValue": "2000003", - "UMask": "0x8" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "25003", + "UMask": "0x1" }, { - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "AnyThread": "1", + "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_ACTIVE", - "PublicDescription": "Counts the cycles when at least one uop is d= elivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "25003", "UMask": "0x1" }, { - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.RING0_TRANS", + "PublicDescription": "Counts when the Current Privilege Level (CPL= ) transitions from ring 1, 2 or 3 to ring 0 (Kernel).", + "SampleAfterValue": "100007" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "25003", - "UMask": "0x1" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "BriefDescription": "Thread cycles when thread is not in halt stat= e", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", + "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", - "SampleAfterValue": "2000003", - "UMask": "0x2" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "SampleAfterValue": "2000003", - "UMask": "0x4" + "UMask": "0x8" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "SampleAfterValue": "2000003", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", + "CounterMask": "16", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "UMask": "0x20" + "UMask": "0xc" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "UMask": "0x40" + "UMask": "0x5" }, { - "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "20", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "UMask": "0x80" + "UMask": "0x14" }, { - "AnyThread": "1", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x4" }, { - "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "Counter": "1", - "CounterHTOff": "1", - "Errata": "SKL091, SKL044", - "EventCode": "0xC0", - "EventName": "INST_RETIRED.PREC_DIST", - "PEBS": "2", - "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled.", + "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_4_UOPS", - "PublicDescription": "Counts the cycles when 4 uops are delivered = by the LSD (Loop-stream detector).", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x4" }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", @@ -379,241 +378,270 @@ "UMask": "0x8" }, { - "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "AnyThread": "1", - "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "25003", - "UMask": "0x1" + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", + "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x59", - "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", - "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "Invert": "1", - "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_NTAKEN", - "PublicDescription": "This event counts not taken branch instructi= ons retired.", - "SampleAfterValue": "400009", - "UMask": "0x10" + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Counts the number of instructions (EOMs) ret= ired. Counting covers macro-fused instructions individually (that is, incre= ments by two).", + "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Number of all retired NOP instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", + "Counter": "0,2,3", + "CounterHTOff": "0,2,3", + "CounterMask": "10", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "PublicDescription": "Number of cycles using an always true condit= ion applied to PEBS instructions retired event. (inst_ret< 16)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "EventCode": "0x0D", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x80" }, { - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 2", - "CounterHTOff": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "UMask": "0x3" + "UMask": "0x1" }, { - "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", - "SampleAfterValue": "400009" + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", + "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC1", - "EventName": "OTHER_ASSISTS.ANY", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", "SampleAfterValue": "100003", - "UMask": "0x3f" + "UMask": "0x1" }, { - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xC2", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "Invert": "1", - "PublicDescription": "This event counts cycles without actually re= tired uops.", - "SampleAfterValue": "2000003", - "UMask": "0x2" + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", "EventCode": "0xA8", - "EventName": "LSD.UOPS", - "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", + "EventName": "LSD.CYCLES_4_UOPS", + "PublicDescription": "Counts the cycles when 4 uops are delivered = by the LSD (Loop-stream detector).", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "25003", - "UMask": "0x2" + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Counts the cycles when at least one uop is d= elivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", - "EventCode": "0x5E", - "EventName": "RS_EVENTS.EMPTY_END", - "Invert": "1", - "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to precisely locate front-end Laten= cy Bound issues.", - "SampleAfterValue": "2000003", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "16", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Taken branch instructions retired.", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "PublicDescription": "This event counts taken branch instructions = retired.", - "SampleAfterValue": "400009", - "UMask": "0x20" + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY", "SampleAfterValue": "100003", - "UMask": "0x8" + "UMask": "0x3f" }, { - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", + "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Counts resource-related stall cycles.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { - "AnyThread": "1", - "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "25003", - "UMask": "0x1" + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "BriefDescription": "Direct and indirect near call instructions re= tired.", + "BriefDescription": "Increments whenever there is an update to the= LBR array.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", - "PublicDescription": "This event counts both direct and indirect n= ear call instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x2" + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { "BriefDescription": "Number of retired PAUSE instructions (that do= not end up with a VMExit to the VMM; TSX aborted Instructions may be count= ed). This event is not supported on first SKL and KBL products.", @@ -625,345 +653,328 @@ "UMask": "0x40" }, { - "BriefDescription": "Resource-related stall cycles", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "Counts resource-related stall cycles.", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", - "SampleAfterValue": "100003", - "UMask": "0x4" + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to precisely locate front-end Laten= cy Bound issues.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "5", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", "SampleAfterValue": "2000003", - "UMask": "0x5" + "UMask": "0x1" }, { - "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "25003", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", + "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x4" }, { - "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "SampleAfterValue": "400009", - "UMask": "0x20" + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "CounterMask": "20", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", "SampleAfterValue": "2000003", - "UMask": "0x14" + "UMask": "0x10" }, { - "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", - "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", - "Counter": "0,2,3", - "CounterHTOff": "0,2,3", - "CounterMask": "10", - "Errata": "SKL091, SKL044", - "EventCode": "0xC0", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", - "Invert": "1", - "PEBS": "2", - "PublicDescription": "Number of cycles using an always true condit= ion applied to PEBS instructions retired event. (inst_ret< 16)", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x40" }, { - "BriefDescription": "Retirement slots used.", + "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "Counts the retirement slots used.", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "AnyThread": "1", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003" + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.MACRO_FUSED", - "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "UMask": "0x4" + "UMask": "0x2" }, { - "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xCC", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "UMask": "0x20" + "UMask": "0x2" }, { - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5E", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "CounterHTOff": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA2", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", "SampleAfterValue": "2000003", - "UMask": "0x8" + "UMask": "0x1" }, { - "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.RING0_TRANS", - "PublicDescription": "Counts when the Current Privilege Level (CPL= ) transitions from ring 1, 2 or 3 to ring 0 (Kernel).", - "SampleAfterValue": "100007" - }, - { - "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "PEBS": "2", - "PublicDescription": "This is a precise version of BR_INST_RETIRED= .ALL_BRANCHES that counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x4" - }, - { - "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "PEBS": "2", - "PublicDescription": "This is a precise version of BR_MISP_RETIRED= .ALL_BRANCHES that counts all mispredicted macro branch instructions retire= d.", - "SampleAfterValue": "400009", - "UMask": "0x4" + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Return instructions retired.", + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", - "PublicDescription": "This event counts return instructions retire= d.", - "SampleAfterValue": "100007", - "UMask": "0x8" + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", - "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Counts the number of x87 uops dispatched.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "This event counts not taken branch instructi= ons retired.", - "SampleAfterValue": "400009", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.X87", + "PublicDescription": "Counts the number of x87 uops executed.", + "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Conditional branch instructions retired.", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PEBS": "1", - "PublicDescription": "This event counts conditional branch instruc= tions retired.", - "SampleAfterValue": "400009", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PEBS": "1", - "PublicDescription": "This event counts mispredicted conditional b= ranch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "BriefDescription": "Number of uops executed on the core.", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE", - "PublicDescription": "Number of uops executed from any thread.", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", "SampleAfterValue": "2000003", - "UMask": "0xc" + "UMask": "0x2" }, { - "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", - "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PublicDescription": "Counts the retirement slots used.", "SampleAfterValue": "2000003", - "UMask": "0x80" - }, - { - "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PublicDescription": "Counts all (macro) branch instructions retir= ed.", - "SampleAfterValue": "400009" + "UMask": "0x2" }, { - "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually re= tired uops.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition= (uops_ret < 16) applied to non PEBS uops retired event.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tool= s/perf/pmu-events/arch/x86/skylake/skl-metrics.json index 4cd246782dde..defbca9a6038 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -1,371 +1,614 @@ [ { - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound.", "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", - "MetricName": "Frontend_Bound" + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU.", "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Frontend_Bound_SMT" + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", - "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", - "MetricName": "Bad_Speculation" + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", - "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU.", "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Bad_Speculation_SMT" + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNH= ALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * = CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", - "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", - "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", - "MetricName": "Backend_Bound" + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", - "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU.", "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK= _UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK= _UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCL= ES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNH= ALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Backend_Bound_SMT" + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. ", "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", - "MetricName": "Retiring" + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU.", "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Retiring_SMT" + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_= RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALT= ED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * = CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES = / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_= RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNH= ALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIR= ED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) = * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS= _NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts_SMT", + "MetricName": "Mispredictions_SMT" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_= ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALL= S_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (= ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_H= IT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1= @ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS )= / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_AC= TIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_P= ORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * E= XE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + = 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min= ( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,= cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS= / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTI= VITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_= HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (ME= M_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L= 1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVI= TY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THR= EAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MI= SS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_= ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1= _PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) *= EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UO= PS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY = + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (O= FFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIV= ITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THR= EAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_= L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_ME= M_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EX= E_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTE= D.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * = (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS= _ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD= ))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_R= ETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ / CPU_CLK_UNHAL= TED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALL= S_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK= _UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL= S_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 = + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RET= IRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ))= + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_= L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #= ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE= _ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_= SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE= _THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTI= L) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (= 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_A= CTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MIS= C.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( = 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )= * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_D= ATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALL= S_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - C= YCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RE= TIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )= ) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_= RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYC= LE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNH= ALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STA= LLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_A= NY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_A= CTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD= / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XC= LK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER= .SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.ST= ALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) )= ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MI= SS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY = + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTI= VITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.= THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.= REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)= ) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / = 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK = ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4= * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_AC= TIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( M= EM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB= _FULL\\,cmask\\=3D1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.S= TALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD = , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore_SMT", + "MetricName": "Memory_Bandwidth_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_= ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALL= S_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (= ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_H= IT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1= @ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS )= / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_AC= TIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_P= ORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * E= XE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + = 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min= ( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_R= D ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE= _REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHALTED.THREA= D)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_= ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALT= ED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT /= MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL= \\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.ST= ALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_= L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #(((= CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_AC= TIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLO= TS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTI= VITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 = * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU= _CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * (= (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 100000000= 0 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB= _HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCL= E_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHAL= TED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (ME= M_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB= _FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVI= TY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALL= S_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL += (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNH= ALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)= ) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( = UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK= _UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL= S_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 = + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RET= IRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ))= + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_= L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #= ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE= _ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_= SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE= _THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTI= L) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (= 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_A= CTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MIS= C.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( = 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )= * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WI= TH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cp= u@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@ ) / CPU_CLK_UNHAL= TED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + = (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_C= LK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 += (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MIS= S.FB_FULL\\,cmask\\=3D1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_AC= TIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVIT= Y.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREA= D) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / = (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.R= ETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALT= ED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_POR= TS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CO= RE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_TH= READ_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( I= NT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) *= msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD= / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * = MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.= L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MIS= S - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (ME= M_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L= 1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / = MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D1@ ) )= * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CP= U_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY= .BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_U= TIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) *= ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))= * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_= UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CP= U_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS= _ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK= _UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK= _UNHALTED.REF_XCLK ) )))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore_SMT", + "MetricName": "Memory_Latency_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( (= CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK= _UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * c= pu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE = , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 )= ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYC= LE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_A= CTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTL= B_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BO= UND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Memory_Data_TLBs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - = CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (m= in( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WAL= K_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_M= ISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_= ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) += ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * = cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_STORE_MISSES.WALK_ACTI= VE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREA= D_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES = / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricName": "Memory_Data_TLBs_SMT" + }, + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_= RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITI= ONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 = * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_= RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITI= ONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "Ret_SMT", + "MetricName": "Branching_Overhead_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_= CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDA= TA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS= .ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_ST= ALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACH= E_16B.IFDATA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 = * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.= CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + C= PU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT", + "MetricName": "Big_Code_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK= _UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE /= (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MIS= P_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT= _DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (I= CACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STA= LL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHA= LTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_U= OPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))= )", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DE= LIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.= ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL= _BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_= MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_D= ELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) = * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))= ) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNH= ALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STAL= L\\,cmask\\=3D1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / = CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DEL= IV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O= NE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "Fed;FetchBW;Frontend_SMT", + "MetricName": "Instruction_Fetch_BW_SMT" }, { - "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", - "MetricGroup": "Summary", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", "BriefDescription": "Uops Per Instruction", - "MetricGroup": "Pipeline;Retire", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Instruction per taken branch", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricGroup": "Pipeline", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", - "MetricGroup": "Summary", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "MetricExpr": "4 * cycles", "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", - "MetricGroup": "TopDownL1", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", - "MetricGroup": "TopDownL1_SMT", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "MetricExpr": "INST_RETIRED.ANY / cycles", - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricGroup": "SMT;TopDownL1", + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricGroup": "SMT;TopDownL1", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { - "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = cycles", "BriefDescription": "Floating Point Operations Per Cycle", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { - "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIV= E / CPU_CLK_UNHALTED.REF_XCLK ) )", "BriefDescription": "Floating Point Operations Per Cycle", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / = ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIV= E / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { - "MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_= GE_1 / 2 )", + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + }, + { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", - "MetricGroup": "Pipeline;Ports_Utilization", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (( INT_MISC.= CLEAR_RESTEER_CYCLES + 9 * BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DEL= IVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_= RETIRED.ALL_BRANCHES", "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricGroup": "BrMispredicts", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, { - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DE= LIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.= ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (( INT_MISC.CLEAR_RES= TEER_CYCLES + 9 * BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CY= CLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * = ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIV= E / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricGroup": "BrMispredicts_SMT", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", + "MetricGroup": "Bad;BrMispredicts_SMT", "MetricName": "Branch_Misprediction_Cost_SMT" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricGroup": "BrMispredicts", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { - "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else= CPU_CLK_UNHALTED.THREAD", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", - "MetricGroup": "Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", "MetricName": "IpLoad" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", - "MetricGroup": "Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", "MetricName": "IpStore" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", - "MetricGroup": "Branches;Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", - "MetricGroup": "Branches", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, { - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { "BriefDescription": "Branch instructions per taken branch. ", - "MetricGroup": "Branches;PGO", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B= _PACKED_SINGLE )", "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricGroup": "FLOPS;FP_Arith;Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B= _PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", - "BriefDescription": "Total number of retired Instructions", - "MetricGroup": "Summary;TopDownL1", + "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, { - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, + { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricGroup": "DSB;Fetch_BW", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.C= ORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 *= CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELI= V.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS = - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses_Cost" }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricGroup": "Memory_Bound;Memory_BW", - "MetricName": "MLP" + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_D= ELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NO= T_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_= 0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "DSBmiss;Fed_SMT", + "MetricName": "DSB_Misses_Cost_SMT" }, { - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * cycle= s )", - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" }, { - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ) )", - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT= _TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_= RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CON= DITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / B= R_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricGroup": "Memory_BW", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricGroup": "Memory_BW", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricGroup": "Memory_BW", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricGroup": "Memory_BW;Offcore", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, + { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", - "MetricGroup": "Cache_Misses;Offcore", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", + "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_C= LK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( C= PU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / C= PU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, + { "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, { - "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, + { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricGroup": "FLOPS;HPC", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, { - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 )", "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, { - "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", - "MetricGroup": "HPC;Memory_BW;SoC", + "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { - "MetricExpr": "arb@event\\=3D0x80\\,umask\\=3D0x2@ / arb@event\\= =3D0x80\\,umask\\=3D0x2\\,cmask\\=3D1@", + "BriefDescription": "Average latency of all requests to external m= emory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricGroup": "Memory_BW;SoC", + "MetricExpr": "arb@event\\=3D0x80\\,umask\\=3D0x2@ / arb@event\\= =3D0x80\\,umask\\=3D0x2\\,cmask\\=3D1@", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, { - "MetricExpr": "INST_RETIRED.ANY / ( BR_INST_RETIRED.FAR_BRANCH / 2= )", "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "Branches;OS", "MetricName": "IpFarBranch" }, { - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Core_Residency" }, { - "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per core", + "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Core_Residency" }, { - "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Core_Residency" }, { - "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C2_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per package", + "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" } diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/skylake/virtual-memory.json index 432530d15c26..792ca39f013a 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json @@ -1,104 +1,104 @@ [ { - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", - "SampleAfterValue": "100003", - "UMask": "0x4" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_PENDING", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake michroarchitecture.", + "CounterMask": "1", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a load.", "SampleAfterValue": "100003", "UMask": "0x10" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "UMask": "0x2" + "UMask": "0xe" }, { - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xAE", - "EventName": "ITLB.ITLB_FLUSH", - "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", - "SampleAfterValue": "100007", - "UMask": "0x1" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", + "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_ACTIVE", - "PublicDescription": "Cycles when at least one PMH is busy with a = page walk for code (instruction fetch) request. EPT page walk duration are = excluded in Skylake microarchitecture.", - "SampleAfterValue": "100003", - "UMask": "0x10" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", "SampleAfterValue": "2000003", - "UMask": "0x20" + "UMask": "0x2" }, { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", - "SampleAfterValue": "100007", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", - "SampleAfterValue": "2000003", - "UMask": "0x10" + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store. EPT page walk duration are excluded in Skylake.", @@ -112,34 +112,34 @@ "UMask": "0x10" }, { - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0xe" }, { - "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", "SampleAfterValue": "100003", - "UMask": "0x20" + "UMask": "0x8" }, { - "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", "SampleAfterValue": "100003", - "UMask": "0xe" + "UMask": "0x4" }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", @@ -152,133 +152,133 @@ "UMask": "0x2" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", - "SampleAfterValue": "100003", - "UMask": "0x8" + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", - "SampleAfterValue": "100003", - "UMask": "0xe" + "EventCode": "0x4f", + "EventName": "EPT.WALK_PENDING", + "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", - "SampleAfterValue": "2000003", - "UMask": "0x2" + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", - "EventName": "ITLB_MISSES.STLB_HIT", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", "SampleAfterValue": "100003", - "UMask": "0x20" + "UMask": "0x1" }, { - "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", + "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", - "SampleAfterValue": "2000003", - "UMask": "0x4" + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", + "CounterMask": "1", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "PublicDescription": "Cycles when at least one PMH is busy with a = page walk for code (instruction fetch) request. EPT page walk duration are = excluded in Skylake microarchitecture.", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x10" }, { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x4f", - "EventName": "EPT.WALK_PENDING", - "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", - "SampleAfterValue": "2000003", - "UMask": "0x10" + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", + "SampleAfterValue": "100003", + "UMask": "0xe" }, { - "BriefDescription": "STLB flush attempts", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.STLB_ANY", - "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", - "SampleAfterValue": "100007", - "UMask": "0x20" + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", - "SampleAfterValue": "2000003", - "UMask": "0x8" + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", - "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a load.", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", "SampleAfterValue": "100003", - "UMask": "0x10" + "UMask": "0x2" }, { - "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake michroarchitecture.", "SampleAfterValue": "100003", - "UMask": "0x4" + "UMask": "0x10" }, { - "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0xe" + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", + "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", - "SampleAfterValue": "100003", - "UMask": "0x8" + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "SampleAfterValue": "100007", + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CFC3C433EF for ; Tue, 1 Feb 2022 02:01:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232452AbiBACBh (ORCPT ); Mon, 31 Jan 2022 21:01:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232151AbiBACAS (ORCPT ); Mon, 31 Jan 2022 21:00:18 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78EAAC06177C for ; Mon, 31 Jan 2022 18:00:06 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id t91-20020a25aae4000000b0061963cce3c1so17914096ybi.11 for ; Mon, 31 Jan 2022 18:00:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=PVwFHVhsHwLOV2/esWM0LhO7va37CQEZYE6WL0bU4II=; b=Yi7a/elzvh48F1lTDpOurLXjlPTfXij0tSns7Arq8meZPk2XHJlJyPB32I1Tj7BicR sJO27ri5OO+6lQccD47upzNeK96NNsdJC1LrCfJ1XhXdpxzIBcXKU16/4lKCIJFrH1gf lH1i9nPdfOolnNuTnf2v7RtOyHnzFFqt5wpWit+UCDyzFbjoCvVqtUrKmJNADKf4KLHl Q2Gy++V4bngb++Oh0fCeYxzVZa9UTkXnILPHzVBtm8cb0OqRaMJMpZfp1F1Gdx/WpTbF 7wEEWnHci6ebOYvTI8pK+SGTZOVM7xLTeFGORGJHvJ8WdUIkedojubbhMFhL6l3jj0Ua ovJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=PVwFHVhsHwLOV2/esWM0LhO7va37CQEZYE6WL0bU4II=; b=VPqf5Z+P7Ce//Rn+zC0xapC6GdTGQWZ26wCH660TJcWZoFYPq8EOHiRV9i4AeM2EOX G6ymmuFsoOzbFeSczZoTN4c3lJWQQgnmDLxySOJfY2V/CPefR4D3wrj/Fp7+gdCeq88b zh37Doz+SCPbuc5NquBHTgKnSnndDZQHWWnu4dFn6j55G9iqF+BfQ53+1vBsjrAHDdF4 svIuTfzZ44aC0p6s4nuKdzUtEXm4+3J4afr7AkCUs6guxTr6EIxv3Ll7e9ox8bWmb0/Y eVEUPjkauqQ20PVcKp0PksB4Q5kWTxK0Sl53uRDcCfaEo72jJF3AdVXprE7d6T/pLH9O jKNQ== X-Gm-Message-State: AOAM5338+FVyV9BxpIjFJ1dnA5uDF3J/uzqpP4UR9xedGQENwsGFXHsW qs6CL2vW+1WuXKTibru+wGPlJPyki4lj X-Google-Smtp-Source: ABdhPJzDltWSGUdSIzhPN+xDPASkcTSLPlbQ/KF4ZNixU+8uLZjpykFuycfO6/1PhtMStk6+p9PAZX18eCig X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:705:: with SMTP id 5mr32895843ybh.425.1643680805593; Mon, 31 Jan 2022 18:00:05 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:53 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-22-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 21/26] perf vendor events: Update Sandybridge From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Events are still at version 16: https://download.01.org/perfmon/SNB Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Sandybridge, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/sandybridge/cache.json | 2298 ++++++++--------- .../arch/x86/sandybridge/floating-point.json | 172 +- .../arch/x86/sandybridge/frontend.json | 365 +-- .../arch/x86/sandybridge/memory.json | 520 ++-- .../arch/x86/sandybridge/other.json | 66 +- .../arch/x86/sandybridge/pipeline.json | 1634 ++++++------ .../arch/x86/sandybridge/snb-metrics.json | 150 +- .../arch/x86/sandybridge/uncore-cache.json | 252 ++ .../arch/x86/sandybridge/uncore-other.json | 91 + .../arch/x86/sandybridge/uncore.json | 314 --- .../arch/x86/sandybridge/virtual-memory.json | 160 +- 11 files changed, 3039 insertions(+), 2983 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache= .json create mode 100644 tools/perf/pmu-events/arch/x86/sandybridge/uncore-other= .json delete mode 100644 tools/perf/pmu-events/arch/x86/sandybridge/uncore.json diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/= perf/pmu-events/arch/x86/sandybridge/cache.json index bb79e89c2049..92a7269eb444 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -1,1879 +1,1879 @@ [ { - "EventCode": "0x24", + "BriefDescription": "Allocated L1D data cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.ALLOCATED_IN_M", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "Cache lines in M state evicted out of L1D due= to Snoop HitM or dirty line replacement.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.ALL_M_REPLACEMENT", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L1D data cache lines in M state evicted due t= o replacement.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.EVICTION", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements= . Replacements occur when a new line is brought into the cache, causing ev= iction of a line loaded earlier.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "Cycles when dispatched loads are cancelled du= e to L1D bank conflicts with other load ports.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xBF", + "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", + "SampleAfterValue": "100003", + "UMask": "0x5" }, { - "EventCode": "0x24", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "L1D miss oustandings duration in cycles.", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "EventCode": "0x24", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state.", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x27", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x27", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in S state.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_S", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x27", + "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.).", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "L2 cache lines filling L2.", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cache lines in E state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cache lines in I state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_L1D_WB_RQSTS.HIT_S", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in S state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "L2 cache lines in S state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x28", + "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "Dirty L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Dirty L2 cache lines filling the L2.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" }, { - "EventCode": "0x2E", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles.", - "CounterHTOff": "2" + "UMask": "0x4" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" + "BriefDescription": "L2 code requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "EventCode": "0x48", + "BriefDescription": "Demand Data Read requests.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "PublicDescription": "This event counts L1D data line replacements= . Replacements occur when a new line is brought into the cache, causing ev= iction of a line loaded earlier.", - "EventCode": "0x51", + "BriefDescription": "Requests from L2 hardware prefetchers.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0xc0" }, { - "EventCode": "0x51", + "BriefDescription": "RFO requests to L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D.ALLOCATED_IN_M", - "SampleAfterValue": "2000003", - "BriefDescription": "Allocated L1D data cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "UMask": "0xc" }, { - "EventCode": "0x51", + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L1D.EVICTION", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data cache lines in M state evicted due t= o replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "EventCode": "0x51", + "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D.ALL_M_REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "Cache lines in M state evicted out of L1D due= to Snoop HitM or dirty line replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "EventCode": "0x60", + "BriefDescription": "Demand Data Read requests that hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0x60", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "EventCode": "0x60", + "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0x60", + "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0x60", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0x60", + "BriefDescription": "RFOs that access cache lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "UMask": "0xf" }, { - "EventCode": "0x60", + "BriefDescription": "RFOs that hit cache lines in E state.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0x63", + "BriefDescription": "RFOs that hit cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0xB0", + "BriefDescription": "RFOs that miss cache lines.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xB0", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.= ", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0xB0", + "BriefDescription": "Transactions accessing L2 pipe.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0xB0", + "BriefDescription": "L2 cache accesses when fetching instructions.= ", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0xB2", + "BriefDescription": "Demand Data Read requests that access L2 cach= e.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xBF", + "BriefDescription": "L1D writebacks that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles when dispatched loads are cancelled du= e to L1D bank conflicts with other load ports.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "L2 fill requests that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "L2 writebacks that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "RFO requests that access L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K). (Precise Event - PEBS)", - "EventCode": "0xD0", + "BriefDescription": "Cycles when L1D is locked.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K). (Precise Event - PEBS)", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC.", "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of load uops re= tired (Precise Event)", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event - PEBS)= .", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "UMask": "0x4f" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of store uops r= etired. (Precise Event - PEBS)", - "EventCode": "0xD0", + "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (Precise Event - PEBS= ).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a non-modified state. (Precise E= vent - PEBS)", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a modified state, so the line ha= d to be invalidated in that L2 cache and transferred to the requesting L2. = (Precise Event - PEBS)", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { + "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEB= S).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", - "EventCode": "0xD1", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data = sources. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit= in the last-level (L3) cache without snoops required. (Precise Event - PEB= S)", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops with unknown information as= data source in cache serviced the load. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired demand loads that = missed the last-level (L3) cache. This means that the load is usually sati= sfied from memory in a client system or possibly from the remote socket in = a server. Demand loads are non speculative load uops. (Precise Event - PEBS= )", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEB= S).", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a non-modified state. (Precise E= vent - PEBS)", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a modified state, so the line ha= d to be invalidated in that L2 cache and transferred to the requesting L2. = (Precise Event - PEBS)", - "EventCode": "0xD2", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { + "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PEBS": "1", - "PublicDescription": "This event counts retired demand loads that = missed the last-level (L3) cache. This means that the load is usually sati= sfied from memory in a client system or possibly from the remote socket in = a server. Demand loads are non speculative load uops. (Precise Event - PEBS= )", - "EventCode": "0xD4", + "PublicDescription": "This event counts retired load uops that hit= in the last-level (L3) cache without snoops required. (Precise Event - PEB= S)", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "All retired load uops. (Precise Event - PEBS)= .", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with unknown information as= data source in cache serviced the load. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load uops re= tired (Precise Event)", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "EventCode": "0xF0", + "BriefDescription": "All retired store uops. (Precise Event - PEBS= ).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cach= e.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PublicDescription": "This event counts the number of store uops r= etired. (Precise Event - PEBS)", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K). (Precise Event - PEBS)", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K). (Precise Event - PEBS)", + "SampleAfterValue": "100003", + "UMask": "0x42" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "EventCode": "0xF0", + "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "EventCode": "0xF0", + "BriefDescription": "Demand and prefetch data reads.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "Cacheable and noncachaeble code read requests= .", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF1", + "BriefDescription": "Demand Data Read requests sent to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF1", + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", - "EventCode": "0xF1", + "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF2", + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF2", + "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF4", + "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0244", + "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0244", + "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0244", + "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0091", + "BriefDescription": "Counts all demand & prefetch data reads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000105B3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that = hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", + "BriefDescription": "Counts all demand & prefetch data reads that = hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0240", + "BriefDescription": "Counts all prefetch code reads that hit in th= e LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in th= e LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0240", + "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0240", + "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0240", + "BriefDescription": "Counts prefetch code reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0240", + "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090", + "BriefDescription": "Counts all prefetch data reads that hit in th= e LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in th= e LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0090", + { + "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0120", + "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.= ", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0120", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoop to one of the sibling cores hits the line in M state and the line= is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoops to sibling cores hit in either E/S state and the line is not for= warded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0120", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoops to sibling cores hit in either E/S state and the line is not for= warded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoop to one of the sibling cores hits the line in M state and the line= is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0120", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = sibling core snoops are not needed as either the core-valid bit is not set = or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = sibling core snoops are not needed as either the core-valid bit is not set = or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0120", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c03f7", + "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch) .", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000107F7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoops to sibling cores hit in either E/S sta= te and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c03f7", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoop to one of the sibling cores hits the li= ne in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoop to one of the sibling cores hits the li= ne in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c03f7", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoops to sibling cores hit in either E/S sta= te and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and sibling core snoops are not needed as either the = core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c03f7", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and sibling core snoops are not needed as either the = core-valid bit is not set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoops sent to sibling cores return clean res= ponse.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0122", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoops sent to sibling cores return clean res= ponse.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0122", + "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoops to sibling cores hit in either E/S state and the line i= s not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0122", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0122", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0122", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoops to sibling cores hit in either E/S state and the line i= s not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & ANY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the = LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0004", + "BriefDescription": "COREWB & ANY_RESPONSE", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0004", + "BriefDescription": "REQUEST =3D DATA_INTO_CORE and RESPONSE =3D A= NY_RESPONSE", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10433", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0004", + "BriefDescription": "Counts all demand code reads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0004", + "BriefDescription": "Counts all demand code reads that hit in the = LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", + "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the = LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", + "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", + "BriefDescription": "Counts demand code reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", + "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0001", + "BriefDescription": "Counts all demand data reads .", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0002", + "BriefDescription": "Counts all demand data reads that hit in the = LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0002", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0002", + "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0002", + "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18000", + "BriefDescription": "Counts all demand rfo's .", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sen= t to LLC to keep a line from being evicted out of the core caches.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803c8000", + "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2380408000", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0040", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0040", + "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CO= RE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0040", + "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_M and SNOOP =3D HITM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEED= ED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0040", + "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sen= t to LLC to keep a line from being evicted out of the core caches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoops sent to sibling cores return clean= response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803c8000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) d= ata reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0010", + "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2380408000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_RESPO= NSE", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0010", + "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0020", + "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0020", + "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoops to sibling cores hit in either E/S state= and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0020", + "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoops sent to sibling cores return clean= response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0020", + "BriefDescription": "Counts all prefetch (that bring data to L2) d= ata reads that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and sibling core snoops are not needed as either the co= re-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0020", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoops sent to sibling cores return clean respo= nse.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0200", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0200", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0200", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0020", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0200", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0020", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoops sent to sibling cores return= clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoops to sibling cores hit in either E/S state= and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0020", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0080", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and sibling core snoops are not needed as either the co= re-valid bit is not set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0020", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoops sent to sibling cores return clean respo= nse.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0020", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0080", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0100", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the LLC.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0100", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0100", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoops sent to sibling cores return= clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0100", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0100", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoops sent to sibling cores return clean= response.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010001", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010002", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0100", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand rfo's .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010004", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0100", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000105B3", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0100", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010122", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0100", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000107F7", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoops sent to sibling cores return clean= response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0100", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch) .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10433", + "BriefDescription": "REQUEST =3D PF_LLC_DATA_RD and RESPONSE =3D A= NY_RESPONSE", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D DATA_INTO_CORE and RESPONSE =3D A= NY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000040002", + "BriefDescription": "REQUEST =3D PF_LLC_IFETCH and RESPONSE =3D AN= Y_RESPONSE", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_M and SNOOP =3D HITM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10040", + "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_RESPO= NSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10080", + "BriefDescription": "Counts non-temporal stores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_LLC_DATA_RD and RESPONSE =3D A= NY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10200", + "BriefDescription": "Split locks in SQ.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_LLC_IFETCH and RESPONSE =3D AN= Y_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json= b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json index ce26537c7d47..713878fd062b 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json @@ -1,138 +1,138 @@ [ { - "EventCode": "0x10", + "BriefDescription": "Cycles with any input/output SSE or FP assist= .", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "EventCode": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values= .", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "Number of SIMD FP assists due to Output value= s.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0x10", + "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x11", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of GSSE-256 Computational FP single pr= ecision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x11", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of AVX-256 Computational FP double pre= cision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs= , FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish = an FADD used in the middle of a transcendental flow from a s.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output value= s.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of AVX-256 Computational FP double pre= cision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCA", + "BriefDescription": "Number of GSSE-256 Computational FP single pr= ecision uops issued this cycle.", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist= .", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/frontend.json index e58ed14a204c..fa22f9463b66 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json @@ -1,305 +1,314 @@ [ { - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts the cycles attributed to a= switch from the Decoded Stream Buffer (DSB), which holds decoded instructi= ons, to the legacy decode pipeline. It excludes cycles when the back-end c= annot accept new micro-ops. The penalty for these switches is potentially= several cycles of instruction starvation, where no micro-ops are delivered= to the back-end.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Cases of cancelling valid Decode Stream Buffe= r (DSB) fill not because of exceeding way limit.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.ALL_CANCEL", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", + "BriefDescription": "Cases of cancelling valid DSB fill not becaus= e of exceeding way limit.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.OTHER_CANCEL", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", + "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes unchache= able accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops.", "Counter": "0,1,2,3", - "UMask": "0x18", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering 4 Uops.", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles MITE is delivering any Uop.", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance. See the Intel\u00ae 64 and IA-32 Architectures Opti= mization Reference Manual for more information.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x3c", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "EventCode": "0x80", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes unchache= able accesses.", - "EventCode": "0x80", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of uops not del= ivered to the back-end per cycle, per thread, when the back-end was not sta= lled. In the ideal case 4 uops can be delivered each cycle. The event cou= nts the undelivered uops - so if 3 were delivered in one cycle, the counter= would be incremented by 1 for that cycle (4 - 3). If the back-end is stall= ed, the count for this event is not incremented even when uops were not del= ivered, because the back-end would not have been able to accept them. This= event is used in determining the front-end bound category of the top-down = pipeline slots characterization.", - "EventCode": "0x9C", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance. See the Intel 64 and IA-32 Architectures Optimizati= on Reference Manual for more information.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x30" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0x9C", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x9C", - "Invert": "1", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when 1 or more uops were delivered to = the by the front end.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x30" }, { + "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0x9C", - "Invert": "1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not del= ivered to the back-end per cycle, per thread, when the back-end was not sta= lled. In the ideal case 4 uops can be delivered each cycle. The event cou= nts the undelivered uops - so if 3 were delivered in one cycle, the counter= would be incremented by 1 for that cycle (4 - 3). If the back-end is stall= ed, the count for this event is not incremented even when uops were not del= ivered, because the back-end would not have been able to accept them. This= event is used in determining the front-end bound category of the top-down = pipeline slots characterization.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xAB", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DSB2MITE_SWITCHES.COUNT", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the cycles attributed to a= switch from the Decoded Stream Buffer (DSB), which holds decoded instructi= ons, to the legacy decode pipeline. It excludes cycles when the back-end c= annot accept new micro-ops. The penalty for these switches is potentially= several cycles of instruction starvation, where no micro-ops are delivered= to the back-end.", - "EventCode": "0xAB", + "BriefDescription": "Cycles when 1 or more uops were delivered to = the by the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xAC", + "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB_FILL.OTHER_CANCEL", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid DSB fill not becaus= e of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xAC", + "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xAC", + "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "DSB_FILL.ALL_CANCEL", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid Decode Stream Buffe= r (DSB) fill not because of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools= /perf/pmu-events/arch/x86/sandybridge/memory.json index 78c1a987f9a2..931892d34076 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json @@ -1,445 +1,445 @@ [ { - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xBE", + "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.LLC_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Number of any page walk that had a miss in LL= C. Does not necessary cause a SUSPEND.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stor= es) hitting load buffers. Machine clears can have a significant performanc= e impact if they are happening frequently.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stor= es) hitting load buffers. Machine clears can have a significant performanc= e impact if they are happening frequently.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4 .", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1009", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 16.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8.", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x10", + "BriefDescription": "Loads with latency value being above 256.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16.", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "503", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", + "BriefDescription": "Loads with latency value being above 32.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", + "BriefDescription": "Loads with latency value being above 4 .", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64.", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", + "BriefDescription": "Loads with latency value being above 512.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128.", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 64.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256.", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 8.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512.", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", + "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only. (Precise Event - PEBS).", "Counter": "3", - "UMask": "0x2", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only. (Precise Event - PEBS).", + "PEBS": "2", "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400244", + "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400091", + "BriefDescription": "Counts all demand & prefetch data reads that = miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that = miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400240", + "BriefDescription": "Counts all prefetch code reads that miss the = LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that miss the = LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400090", + "BriefDescription": "Counts all prefetch data reads that miss the = LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that miss the = LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400120", + "BriefDescription": "Counts all prefetch RFOs that miss the LLC a= nd the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch RFOs that miss the LLC a= nd the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3004003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400122", + "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400004", + "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= MISS_LOCAL and SNOOP =3D DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80408fff", + "Offcore": "1", + "PublicDescription": "This event counts any requests that miss the= LLC where the data was returned from local DRAM", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that miss the LLC an= d the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400001", + "BriefDescription": "Counts LLC replacements.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004001b3", + "Offcore": "1", + "PublicDescription": "This event counts all data requests (demand/= prefetch data reads and demand data writes (RFOs) that miss the LLC where = the data is returned from local DRAM", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC an= d the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400002", + "BriefDescription": "REQUEST =3D DATA_IN_SOCKET and RESPONSE =3D L= LC_MISS_LOCAL and SNOOP =3D ANY_LLC_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_L= LC_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x17004001b3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that miss th= e LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400040", + "BriefDescription": "Counts demand code reads that miss the LLC an= d the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400010", + "BriefDescription": "Counts demand data reads that miss the LLC an= d the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400020", + "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_MISS_LOCAL and SNOOP =3D DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400200", + "BriefDescription": "Counts demand data writes (RFOs) that miss th= e LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400080", + "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_M= ISS_LOCAL and SNOOP =3D DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400100", + "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_MISS_= LOCAL and SNOOP =3D DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "This event counts all data requests (demand/= prefetch data reads and demand data writes (RFOs) that miss the LLC where = the data is returned from local DRAM", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004001b3", + "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts LLC replacements.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "This event counts any requests that miss the= LLC where the data was returned from local DRAM", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80408fff", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= MISS_LOCAL and SNOOP =3D DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x17004001b3", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_L= LC_HIT", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400020", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D DATA_IN_SOCKET and RESPONSE =3D L= LC_MISS_LOCAL and SNOOP =3D ANY_LLC_HIT", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400004", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_MISS_LOCAL and SNOOP =3D DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400010", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_M= ISS_LOCAL and SNOOP =3D DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400040", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400100", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_MISS_= LOCAL and SNOOP =3D DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400080", + "BriefDescription": "REQUEST =3D PF_LLC_DATA_RD and RESPONSE =3D L= LC_MISS_LOCAL and SNOOP =3D DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_LLC_DATA_RD and RESPONSE =3D L= LC_MISS_LOCAL and SNOOP =3D DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400200", + "BriefDescription": "REQUEST =3D PF_LLC_IFETCH and RESPONSE =3D LL= C_MISS_LOCAL and SNOOP =3D DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST =3D PF_LLC_IFETCH and RESPONSE =3D LL= C_MISS_LOCAL and SNOOP =3D DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Number of any page walk that had a miss in LL= C. Does not necessary cause a SUSPEND.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBE", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/= perf/pmu-events/arch/x86/sandybridge/other.json index 874eb40a2e0f..e251f535ec09 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -1,58 +1,58 @@ [ { - "EventCode": "0x17", + "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", - "BriefDescription": "Valid instructions written to IQ per cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HW_PRE_REQ.DL1_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Hardware Prefetch requests that miss the L1D = cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers= . A request is being counted each time it access the cache & miss it, inclu= ding if a block is applicable or if hit the Fill Buffer for .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPL_CYCLES.RING0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x5C", + "BriefDescription": "Hardware Prefetch requests that miss the L1D = cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers= . A request is being counted each time it access the cache & miss it, inclu= ding if a block is applicable or if hit the Fill Buffer for .", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "CPL_CYCLES.RING0_TRANS", - "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4E", + "EventName": "HW_PRE_REQ.DL1_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x5C", + "BriefDescription": "Valid instructions written to IQ per cycle.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPL_CYCLES.RING123", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x17", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/pipeline.json index b7150f65f16d..b9a3f194a00a 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -1,1226 +1,1212 @@ [ { - "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt= state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" + "BriefDescription": "This event counts executed load operations wi= th all the following traits: 1. addressing of the format [base + offset], 2= . the offset is between 1 and 2047, 3. the address specified in the base re= gister is in one page and the address [base+offset] is in an.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB6", + "EventName": "AGU_BYPASS_CANCEL.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "CounterHTOff": "Fixed counter 1" + "BriefDescription": "Divide operations executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "This event counts the number of the divide o= perations executed.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "BriefDescription": "Cycles when divider is busy executing divide = operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" + "UMask": "0x1" }, { - "EventCode": "0x03", + "BriefDescription": "Speculative and retired branches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "SampleAfterValue": "100003", - "BriefDescription": "Loads delayed due to SB blocks, preceding sto= re operations with known addresses but unknown data.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a preceed= ing smaller uncompleted store. See the table of not supported store forwar= ds in the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Man= ual. The penalty for blocked store forwarding is that the load must wait f= or the store to complete before it can be issued.", - "EventCode": "0x03", + "BriefDescription": "Speculative and retired macro-conditional bra= nches.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x03", + "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x03", + "BriefDescription": "Speculative and retired direct near calls.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "LD_BLOCKS.ALL_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Number of cases where any load ends up with a= valid block-code written to the load buffer (including blocks due to Memor= y Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline. The enhanced address check typically ha= s a performance penalty of 5 cycles.", - "EventCode": "0x07", + "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial comp= are.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x07", + "BriefDescription": "Speculative and retired indirect return branc= hes.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that lo= ad operations are temporarily blocked because of older stores, with address= es that are not yet known. A load operation may incur more than one block o= f this type.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "EventCode": "0x0D", + "BriefDescription": "Not taken macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x0D", + "BriefDescription": "Taken speculative and retired macro-condition= al branches.", "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x0D", + "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x0D", + "BriefDescription": "Taken speculative and retired direct near cal= ls.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "PublicDescription": "This event counts the number of Uops issued = by the front-end of the pipeilne to the back-end.", - "EventCode": "0x0E", + "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Taken speculative and retired indirect calls.= ", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x0E", - "Invert": "1", + "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x14", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide = operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" }, { - "PublicDescription": "This event counts the number of the divide o= perations executed.", - "EventCode": "0x14", + "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", - "BriefDescription": "Divide operations executed.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", + "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt stat= e.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x3C", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate)", - "EventCode": "0x3C", + "BriefDescription": "Return instructions retired. (Precise Event -= PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x3C", + "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x3C", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x3C", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x4C", + "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x4C", + "BriefDescription": "Speculative and retired mispredicted direct n= ear calls.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x59", + "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Increments the number of flags-merge uops in = flight each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "This event counts the number of cycles spent= executing performance-sensitive flags-merging uops. For example, shift CL = (merge_arith_flags). For more details, See the Intel\u00ae 64 and IA-32 Arc= hitectures Optimization Reference Manual.", - "EventCode": "0x59", + "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Performance sensitive flags-merging uops adde= d by Sandy Bridge u-arch.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel\u00ae 64 and IA-32 Architectur= es Optimization Reference Manual for more details about slow LEA instructio= ns.", - "EventCode": "0x59", + "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least one slow LEA uop being a= llocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x59", + "BriefDescription": "Taken speculative and retired mispredicted di= rect near calls.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Multiply packed/scalar single precision uops = allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0x5B", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with either free list is empty.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x5B", + "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls2 control structures full for = physical registers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x5B", + "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RESOURCE_STALLS2.BOB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Allocator is stalled if BOB is fu= ll and new branch needs it.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x5B", + "BriefDescription": "All mispredicted macro branch instructions re= tired.", "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "RESOURCE_STALLS2.OOO_RSRC", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls out of order resources full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" }, { - "EventCode": "0x5E", + "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "Mispredicted macro branch instructions retir= ed. (Precise Event - PEBS)", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x5E", - "Invert": "1", + "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Direct and indirect mispredicted near call in= structions retired. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Mispredicted not taken branch instructions re= tired.(Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Mispredicted taken branch instructions retire= d. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near cal= ls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0x88", + "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.= ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional bra= nches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Thread cycles when thread is not in halt stat= e.", "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branc= hes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x88", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread, increment by 1. Note this is in DCU and connected to Umask = 1. Miss Pending demand load should be deduced by OR-ing increment bits of D= CACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load this thread (i.e. Non-completed valid SQ entry allocated for demand = load and waiting for Uncore), increment by 1. Note this is in MLC and conne= cted to Umask 0.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Each cycle there was no dispatch for this thr= ead, increment by 1. Note this is connect to Umask 2. No dispatch can be de= duced from the UOPS_EXECUTED event.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread and no uops dispatched, increment by 1. Note this is in DCU = and connected to Umask 1 and 2. Miss Pending demand load should be deduced = by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x6" }, { - "EventCode": "0x89", + "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load and no uops dispatched on this thread (i.e. Non-completed valid SQ e= ntry allocated for demand load and waiting for Uncore), increment by 1. Not= e this is in MLC and connected to Umask 0 and 2.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x5" }, { - "EventCode": "0x89", + "BriefDescription": "Stall cycles because IQ is full.", "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted di= rect near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Number of instructions retired. General Count= er - architectural event.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted direct n= ear calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Instructions retired. (Precise Event - PEBS).= ", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xA1", + "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc...).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", + "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc...).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", + "BriefDescription": "Number of cases where any load ends up with a= valid block-code written to the load buffer (including blocks due to Memor= y Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)= .", "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xA1", + "BriefDescription": "Loads delayed due to SB blocks, preceding sto= re operations with known addresses but unknown data.", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", "Counter": "0,1,2,3", - "UMask": "0xc", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", + "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding.", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a preceed= ing smaller uncompleted store. See the table of not supported store forwar= ds in the Intel 64 and IA-32 Architectures Optimization Reference Manual. = The penalty for blocked store forwarding is that the load must wait for the= store to complete before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "False dependencies in MOB due to partial comp= are.", "Counter": "0,1,2,3", - "UMask": "0x30", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline. The enhanced address check typically ha= s a performance penalty of 5 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "This event counts the number of times that lo= ad operations are temporarily blocked because of older stores, with address= es that are not yet known. A load operation may incur more than one block o= f this type.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch.", "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", + "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to= port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RESOURCE_STALLS.LB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the cycles of stall due to lack of loa= d buffers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "Number of machine clears (nukes) of any type.= ", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "RESOURCE_STALLS.LB_SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to load or store buffers = all being in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Retired instructions experiencing ITLB misses= .", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "RESOURCE_STALLS.MEM_RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to memory buffers or Rese= rvation Station (RS) being fully utilized.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "Increments the number of flags-merge uops in = flight each cycle.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Performance sensitive flags-merging uops adde= d by Sandy Bridge u-arch.", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "RESOURCE_STALLS.OOO_RSRC", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "PublicDescription": "This event counts the number of cycles spent= executing performance-sensitive flags-merging uops. For example, shift CL = (merge_arith_flags). For more details, See the Intel 64 and IA-32 Architect= ures Optimization Reference Manual.", "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to Rob being full, FCSW, = MXCSR and OTHER.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xA3", + "BriefDescription": "Multiply packed/scalar single precision uops = allocated.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load this thread (i.e. Non-completed valid SQ entry allocated for demand = load and waiting for Uncore), increment by 1. Note this is in MLC and conne= cted to Umask 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "BriefDescription": "Cycles with at least one slow LEA uop being a= llocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", + "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel 64 and IA-32 Architectures Opt= imization Reference Manual for more details about slow LEA instructions.", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread, increment by 1. Note this is in DCU and connected to Umask = 1. Miss Pending demand load should be deduced by OR-ing increment bits of D= CACHE_MISS_PEND.PENDING.", - "CounterMask": "2", - "CounterHTOff": "2" + "UMask": "0x40" }, { - "EventCode": "0xA3", + "BriefDescription": "Resource-related stall cycles.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was no dispatch for this thr= ead, increment by 1. Note this is connect to Umask 2. No dispatch can be de= duced from the UOPS_EXECUTED event.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", + "BriefDescription": "Counts the cycles of stall due to lack of loa= d buffers.", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load and no uops dispatched on this thread (i.e. Non-completed valid SQ e= ntry allocated for demand load and waiting for Uncore), increment by 1. Not= e this is in MLC and connected to Umask 0 and 2.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "BriefDescription": "Resource stalls due to load or store buffers = all being in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB_SB", "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread and no uops dispatched, increment by 1. Note this is in DCU = and connected to Umask 1 and 2. Miss Pending demand load should be deduced = by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", - "CounterMask": "6", - "CounterHTOff": "2" + "UMask": "0xa" }, { - "EventCode": "0xA8", + "BriefDescription": "Resource stalls due to memory buffers or Rese= rvation Station (RS) being fully utilized.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.MEM_RS", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0xA8", + "BriefDescription": "Resource stalls due to Rob being full, FCSW, = MXCSR and OTHER.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.OOO_RSRC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf0" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED.THREAD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched per thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched from any thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles with either free list is empty.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xB1", + "BriefDescription": "Resource stalls2 control structures full for = physical registers.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "EventCode": "0xB1", + "BriefDescription": "Cycles when Allocator is stalled if BOB is fu= ll and new branch needs it.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.BOB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Resource stalls out of order resources full.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.OOO_RSRC", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Count cases of saving new LBR.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xB6", + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "AGU_BYPASS_CANCEL.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts executed load operations wi= th all the following traits: 1. addressing of the format [base + offset], 2= . the offset is between 1 and 2047, 3. the address specified in the base re= gister is in one page and the address [base+offset] is in an.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC0", + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Count= er - architectural event.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Uops dispatched from any thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired. (Precise Event - PEBS).= ", - "TakenAlone": "1", - "CounterHTOff": "1" + "UMask": "0x2" }, { - "EventCode": "0xC1", + "BriefDescription": "Uops dispatched per thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", - "SampleAfterValue": "100003", - "BriefDescription": "Retired instructions experiencing ITLB misses= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of micro-ops re= tired. (Precise Event)", - "EventCode": "0xC2", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC2", - "Invert": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 1.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC2", - "Invert": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. Th= is event is used in determining the 'Retiring' category of the Top-Down pip= eline slots characterization. (Precise Event - PEBS)", - "EventCode": "0xC2", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xc3", + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.= ", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0xc" }, { - "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", + "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", - "EventCode": "0xC3", + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 4.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Cycles per thread when uops are dispatched to= port 5.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC4", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "2", - "EventCode": "0xC4", + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired. (Precise Event -= PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xC4", + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xC4", + "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xC5", + "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS).", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued = by the front-end of the pipeilne to the back-end.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect mispredicted near call in= structions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Mispredicted macro branch instructions retir= ed. (Precise Event - PEBS)", - "EventCode": "0xC5", + "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= .", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This event counts the number of micro-ops re= tired. (Precise Event)", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_MISP_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted not taken branch instructions re= tired.(Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= .", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted taken branch instructions retire= d. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement s= lots used each cycle. There are potentially 4 slots that can be used each = cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. Th= is event is used in determining the 'Retiring' category of the Top-Down pip= eline slots characterization. (Precise Event - PEBS)", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCC", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xE6", + "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/= tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index fb2d7b8875f8..c8e7050d9c26 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -1,142 +1,132 @@ [ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED= .THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. SMT version; use wh= en SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNH= ALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNH= ALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHA= LTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHA= LTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= ps (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend= . Frontend Bound denotes unutilized issue-slots when there is no Backend st= all; i.e. bubbles where Frontend delivered no uops while Backend could have= accepted them. For example; stalls due to instruction-cache misses would b= e categorized under Frontend Bound. SMT version; use when SMT is enabled an= d measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. SMT version; use whe= n SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example." }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. SMT version; use when SMT is enabled an= d measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *= ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example. SMT version; use when SMT is enabled and measuring p= er logical CPU." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) = + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CY= CLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_U= NHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound." }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. SMT version; use when SMT is enabled and me= asuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLO= TS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_C= LK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_C= LK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS= + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.T= HREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.R= EF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THRE= AD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_= XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. SMT version; use when SMT is enabled and measuring per lo= gical CPU." }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHAL= TED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHAL= TED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALT= ED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALT= ED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum 4 uops retired per cycle has been ach= ieved. Maximizing Retiring typically increases the Instruction-Per-Cycle m= etric. Note that a high Retiring value does not necessary mean there is no = room for more performance. For example; Microcode assists are categorized = under Retiring. They hurt performance and can often be avoided. SMT version= ; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. SMT version; use when SMT= is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines= bytes that were likely (includes speculatively fetches) consumed by progra= m instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_S= LOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" - }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= )", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COM= P_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 *= ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SI= MD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP= _OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * = ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIM= D_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\= =3D1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { @@ -145,16 +135,34 @@ "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, + { + "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC= ) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_C= OMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4= * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * = SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -165,22 +173,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( C= PU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD= ", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external m= emory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b= /tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json new file mode 100644 index 000000000000..6b0639944d78 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json @@ -0,0 +1,252 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in E or S-state.", + "UMask": "0x46", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in I-state.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in M-state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access= cache and found line in MESI-state.", + "UMask": "0x4f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in I-state.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which hits a modified line in some processor core.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a modified line in som= e processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a modified line in so= me processor core.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a modified line in some proce= ssor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which hits a non-modified line in some processor core.", + "UMask": "0x84", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a non-modified line in= some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a non-modified line i= n some processor core.", + "UMask": "0x24", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a non-modified line in some p= rocessor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop misses in some processor co= re.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop misses in some processor c= ore.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b= /tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json new file mode 100644 index 000000000000..6278068908cf --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json @@ -0,0 +1,91 @@ +[ + { + "BriefDescription": "Cycles weighted by number of requests pending= in Coherency Tracker.", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Cycles weighted by number of requests pendin= g in Coherency Tracker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tra= cker.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of requests allocated in Coherency Tr= acker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts cycles weighted by the number of reque= sts waiting for data returning from the memory controller. Accounts for coh= erent and non-coherent requests initiated by IA cores, processor graphic un= its, or LLC.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Counts cycles weighted by the number of requ= ests waiting for data returning from the memory controller. Accounts for co= herent and non-coherent requests initiated by IA cores, processor graphic u= nits, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least half of the requests out= standing are waiting for data return from memory controller. Account for co= herent and non-coherent requests initiated by IA Cores, Processor Graphics = Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "10", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "PerPkg": "1", + "PublicDescription": "Cycles with at least half of the requests ou= tstanding are waiting for data return from memory controller. Account for c= oherent and non-coherent requests initiated by IA Cores, Processor Graphics= Unit, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0,1", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding= is waiting for data return from memory controller. Account for coherent an= d non-coherent requests initiated by IA Cores, Processor Graphics Unit, or = LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherent and in-coheren= t requests initiated by IA cores, processor graphic units, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of LLC evictions allocated.= ", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "PerPkg": "1", + "PublicDescription": "Counts the number of LLC evictions allocated= .", + "UMask": "0x80", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of allocated write entries,= include full, partial, and LLC evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocated write entries= , include full, partial, and LLC evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "Fixed", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "UMask": "0x01", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore.json b/tools= /perf/pmu-events/arch/x86/sandybridge/uncore.json deleted file mode 100644 index 42c70eed05a2..000000000000 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore.json +++ /dev/null @@ -1,314 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x01", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS", - "BriefDescription": "A snoop misses in some processor core.", - "PublicDescription": "A snoop misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x02", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL", - "BriefDescription": "A snoop invalidates a non-modified line in some p= rocessor core.", - "PublicDescription": "A snoop invalidates a non-modified line in some = processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x04", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT", - "BriefDescription": "A snoop hits a non-modified line in some processo= r core.", - "PublicDescription": "A snoop hits a non-modified line in some process= or core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x08", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM", - "BriefDescription": "A snoop hits a modified line in some processor co= re.", - "PublicDescription": "A snoop hits a modified line in some processor c= ore.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x10", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M", - "BriefDescription": "A snoop invalidates a modified line in some proce= ssor core.", - "PublicDescription": "A snoop invalidates a modified line in some proc= essor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x20", - "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbo= x due to external snoop request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cb= ox due to external snoop request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x40", - "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbo= x due to processor core memory request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cb= ox due to processor core memory request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x80", - "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbo= x due to LLC eviction.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cb= ox due to LLC eviction.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x01", - "EventName": "UNC_CBO_CACHE_LOOKUP.M", - "BriefDescription": "LLC lookup request that access cache and found li= ne in M-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x02", - "EventName": "UNC_CBO_CACHE_LOOKUP.E", - "BriefDescription": "LLC lookup request that access cache and found li= ne in E-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in E-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x04", - "EventName": "UNC_CBO_CACHE_LOOKUP.S", - "BriefDescription": "LLC lookup request that access cache and found li= ne in S-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x08", - "EventName": "UNC_CBO_CACHE_LOOKUP.I", - "BriefDescription": "LLC lookup request that access cache and found li= ne in I-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x10", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable read= requests.", - "PublicDescription": "Filter on processor core initiated cacheable rea= d requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x20", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable writ= e requests.", - "PublicDescription": "Filter on processor core initiated cacheable wri= te requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x40", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", - "BriefDescription": "Filter on external snoop requests.", - "PublicDescription": "Filter on external snoop requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x80", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", - "BriefDescription": "Filter on any IRQ or IPQ initiated requests inclu= ding uncacheable, non-coherent requests.", - "PublicDescription": "Filter on any IRQ or IPQ initiated requests incl= uding uncacheable, non-coherent requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Counts cycles weighted by the number of requests = waiting for data returning from the memory controller. Accounts for coheren= t and non-coherent requests initiated by IA cores, processor graphic units,= or LLC.", - "PublicDescription": "Counts cycles weighted by the number of requests= waiting for data returning from the memory controller. Accounts for cohere= nt and non-coherent requests initiated by IA cores, processor graphic units= , or LLC.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Counts the number of coherent and in-coherent req= uests initiated by IA cores, processor graphic units, or LLC.", - "PublicDescription": "Counts the number of coherent and in-coherent re= quests initiated by IA cores, processor graphic units, or LLC.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Counts the number of allocated write entries, inc= lude full, partial, and LLC evictions.", - "PublicDescription": "Counts the number of allocated write entries, in= clude full, partial, and LLC evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x80", - "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", - "BriefDescription": "Counts the number of LLC evictions allocated.", - "PublicDescription": "Counts the number of LLC evictions allocated.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x83", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", - "BriefDescription": "Cycles weighted by number of requests pending in = Coherency Tracker.", - "PublicDescription": "Cycles weighted by number of requests pending in= Coherency Tracker.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of requests allocated in Coherency Tracker= .", - "PublicDescription": "Number of requests allocated in Coherency Tracke= r.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "BriefDescription": "Cycles with at least one request outstanding is w= aiting for data return from memory controller. Account for coherent and non= -coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "PublicDescription": "Cycles with at least one request outstanding is = waiting for data return from memory controller. Account for coherent and no= n-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.= ", - "Counter": "0,1", - "CounterMask": "1", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", - "BriefDescription": "Cycles with at least half of the requests outstan= ding are waiting for data return from memory controller. Account for cohere= nt and non-coherent requests initiated by IA Cores, Processor Graphics Unit= , or LLC.", - "PublicDescription": "Cycles with at least half of the requests outsta= nding are waiting for data return from memory controller. Account for coher= ent and non-coherent requests initiated by IA Cores, Processor Graphics Uni= t, or LLC.", - "Counter": "0,1", - "CounterMask": "10", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.= ", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles= .", - "Counter": "Fixed", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x06", - "EventName": "UNC_CBO_CACHE_LOOKUP.ES", - "BriefDescription": "LLC lookup request that access cache and found li= ne in E-state or S-state.", - "PublicDescription": "LLC lookup request that access cache and found l= ine in E-state or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json index b8eccce5d75d..4dd136d00a10 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json @@ -1,149 +1,149 @@ [ { - "EventCode": "0x08", + "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { + "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "This event counts load operations that miss = the first DTLB level but hit the second and do not cause any page walks. Th= e penalty in this case is approximately 7 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Load misses at all DTLB levels that cause com= pleted page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Load misses at all DTLB levels that cause com= pleted page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", - "EventCode": "0x08", + "BriefDescription": "Cycles when PMH is busy with page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts load operations that miss = the first DTLB level but hit the second and do not cause any page walks. Th= e penalty in this case is approximately 7 cycles.", - "EventCode": "0x08", + "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "Cycles when PMH is busy with page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4F", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page wal= ks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "Misses at all ITLB levels that cause page wal= ks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event count cycles when Page Miss Handl= er (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0x85", + "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xAE", + "BriefDescription": "Cycles when PMH is busy with page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event count cycles when Page Miss Handl= er (PMH) is servicing page walks caused by ITLB misses.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xBD", + "BriefDescription": "DTLB flush attempts of the thread-specific en= tries.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific en= tries.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 872F5C433EF for ; Tue, 1 Feb 2022 02:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232821AbiBACBy (ORCPT ); Mon, 31 Jan 2022 21:01:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232339AbiBACAS (ORCPT ); Mon, 31 Jan 2022 21:00:18 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23D75C06177F for ; Mon, 31 Jan 2022 18:00:09 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id u185-20020a2560c2000000b0060fd98540f7so30569887ybb.0 for ; Mon, 31 Jan 2022 18:00:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=j3S4ZR/IagzNtG6EqZ5bb/AQKQ3I8OQtGvRFcxhg9pY=; b=pUA4PfX9YPPt2eP5mhf9y5USnYj2veYFOn1D60zvLvTWtv4tNBi/+i2nuayar/gOIA f4HpxuUGEQPakppGSbw2VzfkppdVn58hen4rO/2NaHj79DIKjVIY3BsZhGy+vlUVtu7x P0nnoE6oPRvy2W0jyDkuBcN8971g++KfDF78FvN5ojfBxCsAxYNTjO3bs2bThD6uEfs2 9LwLvW2zZTZRZ/8wU7QwrdvbMeNvVptg5QvzMilMcZPN0JFV5VLGzMBolrF5YLfVRNlw jb/wDQAj1uRv4WFQUQv1nym9URkwWGBjMbf0LUGxak0UdV0hpGDiwWxWXEaGPQjuNxQJ /NSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=j3S4ZR/IagzNtG6EqZ5bb/AQKQ3I8OQtGvRFcxhg9pY=; b=cwjLtVPsS33kNG2pJ+L0ZuJg+GLUZYj0D3xsoGiTwVZC3WdW8uOEpbo0TLayoeN9pP bD2r5VyuLyAeITzBYT7jFLBV3s+WT1q1H3FAp5lO3wFbFZmaZQ6RaX71IyR17aWwQyLE vEvVJQiPXPO11sypPj2athNOcAHktwz0beDV67hzV27t7nRkt8POMCCAfE8QCoBq4p5H CgZocxedzAjcYFq67Pr2/kkW3N8KWKTWo90A2GtpE7G7TTsi18gJbbacKKGeqXgTjPpA MhOsnDJzZQn/GIQg0393fSOz9x1xrmbielox7B8R0KeQxMYxEBQ4MwYlNrS+WO9KjPrF yXxg== X-Gm-Message-State: AOAM532j7Ftrc9GYfuKP9t7SsrJ9w9ucWmj3YOSGe4Dl4wjz1j3IyCJ0 SQE2HuL1pp0lFmn3kcOb1Zi8QGvXrhtY X-Google-Smtp-Source: ABdhPJxu6yBPZTq+4YQwYiOYDv4Ew5gqnaSbM1VqNBRufA5Jn+aHlvcWk+aiPaf3RChlwvrYKwJxKHS+ZSgA X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:5508:: with SMTP id j8mr33012862ybb.89.1643680808231; Mon, 31 Jan 2022 18:00:08 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:54 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-23-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 22/26] perf vendor events: Update Silvermont From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Events are still at version 14: https://download.01.org/perfmon/SLM Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf The addition of a floating-point.json is due to events having their topic better identified by the converter script. Tested: Not tested on a Silvermont, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/silvermont/cache.json | 940 +++++++++--------- .../arch/x86/silvermont/floating-point.json | 11 + .../arch/x86/silvermont/frontend.json | 75 +- .../arch/x86/silvermont/memory.json | 8 +- .../pmu-events/arch/x86/silvermont/other.json | 20 +- .../arch/x86/silvermont/pipeline.json | 422 ++++---- .../arch/x86/silvermont/virtual-memory.json | 76 +- 7 files changed, 774 insertions(+), 778 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/silvermont/floating-poin= t.json diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/p= erf/pmu-events/arch/x86/silvermont/cache.json index 805ef1436539..e16e1d910e4a 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -1,812 +1,810 @@ [ { - "PublicDescription": "This event counts the number of demand and p= refetch transactions that the L2 XQ rejects due to a full or near full cond= ition which likely indicates back pressure from the IDI link. The XQ may re= ject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) an= d WOB (L2 write-back victims).", - "EventCode": "0x30", + "BriefDescription": "Counts the number of request that were not ac= cepted into the L2Q because the L2Q is FULL.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "L2_REJECT_XQ.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of request from the L2 that= were not accepted into the XQ" - }, - { - "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2Q due to a full or nearly full w condi= tion which likely indicates back pressure from L2Q. It also counts request= s that would have gone directly to the XQ, but are rejected due to a full o= r nearly full condition, indicating back pressure from the IDI link. The L= 2Q may also reject transactions from a core to insure fairness between cor= es, or to delay a core?s dirty eviction when the address conflicts incoming= external snoops. (Note that L2 prefetcher requests that are dropped are n= ot counted by this event.)", "EventCode": "0x31", - "Counter": "0,1", - "UMask": "0x0", "EventName": "CORE_REJECT_L2Q.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of request that were not ac= cepted into the L2Q because the L2Q is FULL." - }, - { - "PublicDescription": "This event counts requests originating from = the core that references a cache line in the L2 cache.", - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests from this core" + "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2Q due to a full or nearly full w condi= tion which likely indicates back pressure from L2Q. It also counts request= s that would have gone directly to the XQ, but are rejected due to a full o= r nearly full condition, indicating back pressure from the IDI link. The L= 2Q may also reject transactions from a core to insure fairness between cor= es, or to delay a core?s dirty eviction when the address conflicts incoming= external snoops. (Note that L2 prefetcher requests that are dropped are n= ot counted by this event.)", + "SampleAfterValue": "200003" }, { - "PublicDescription": "This event counts the total number of L2 cac= he references and the number of L2 cache misses respectively.", - "EventCode": "0x2E", + "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", "Counter": "0,1", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" - }, - { - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.\r\nCounts cycles tha= t fetch is stalled due to any reason. That is, the decoder queue is able to= accept bytes, but the fetch unit is unable to provide bytes. This will in= clude cycles due to an ITLB miss, ICache miss and other events.", "EventCode": "0x86", - "Counter": "0,1", - "UMask": "0x4", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.\r\nCounts cycles tha= t fetch is stalled due to any reason. That is, the decoder queue is able to= accept bytes, but the fetch unit is unable to provide bytes. This will in= clude cycles due to an ITLB miss, ICache miss and other events.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss." - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of retired load= s that were prohibited from receiving forwarded data from the store because= of address mismatch.", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restrictio= n" + "UMask": "0x4" }, { - "PublicDescription": "This event counts the cases where a forward = was technically possible, but did not occur because the store data was not = available at the right time.", - "EventCode": "0x03", + "BriefDescription": "Counts the number of request from the L2 that= were not accepted into the XQ", "Counter": "0,1", - "UMask": "0x2", - "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready" + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", + "PublicDescription": "This event counts the number of demand and p= refetch transactions that the L2 XQ rejects due to a full or near full cond= ition which likely indicates back pressure from the IDI link. The XQ may re= ject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) an= d WOB (L2 write-back victims).", + "SampleAfterValue": "200003" }, { - "PublicDescription": "This event counts the number of retire store= s that experienced cache line boundary splits.", - "EventCode": "0x03", + "BriefDescription": "L2 cache request misses", "Counter": "0,1", - "UMask": "0x4", - "EventName": "REHABQ.ST_SPLITS", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts the total number of L2 cac= he references and the number of L2 cache misses respectively.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split cache line boundary" + "UMask": "0x41" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of retire loads= that experienced cache line boundary splits.", - "EventCode": "0x03", + "BriefDescription": "L2 cache requests from this core", "Counter": "0,1", - "UMask": "0x8", - "EventName": "REHABQ.LD_SPLITS", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from = the core that references a cache line in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split cache line boundary" + "UMask": "0x4f" }, { - "PublicDescription": "This event counts the number of retired memo= ry operations with lock semantics. These are either implicit locked instruc= tions such as the XCHG instruction or instructions with an explicit LOCK pr= efix (0xF0).", - "EventCode": "0x03", + "BriefDescription": "All Loads", "Counter": "0,1", - "UMask": "0x10", - "EventName": "REHABQ.LOCK", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts the number of load ops ret= ired.", "SampleAfterValue": "200003", - "BriefDescription": "Uops with lock semantics" + "UMask": "0x40" }, { - "PublicDescription": "This event counts the number of retired stor= es that are delayed because there is not a store address buffer available.", - "EventCode": "0x03", + "BriefDescription": "All Stores", "Counter": "0,1", - "UMask": "0x20", - "EventName": "REHABQ.STA_FULL", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "This event counts the number of store ops re= tired.", "SampleAfterValue": "200003", - "BriefDescription": "Store address buffer full" + "UMask": "0x80" }, { - "PublicDescription": "This event counts the number of load uops re= issued from Rehabq.", - "EventCode": "0x03", + "BriefDescription": "Cross core or cross module hitm", "Counter": "0,1", - "UMask": "0x40", - "EventName": "REHABQ.ANY_LD", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.HITM", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops ret= ired that got data from the other core or from the other module.", "SampleAfterValue": "200003", - "BriefDescription": "Any reissued load uops" + "UMask": "0x20" }, { - "PublicDescription": "This event counts the number of store uops r= eissued from Rehabq.", - "EventCode": "0x03", + "BriefDescription": "Loads missed L1", "Counter": "0,1", - "UMask": "0x80", - "EventName": "REHABQ.ANY_ST", - "SampleAfterValue": "200003", - "BriefDescription": "Any reissued store uops" - }, - { - "PublicDescription": "This event counts the number of load ops ret= ired that miss in L1 Data cache. Note that prefetch misses will not be coun= ted.", "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x1", "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "PublicDescription": "This event counts the number of load ops ret= ired that miss in L1 Data cache. Note that prefetch misses will not be coun= ted.", "SampleAfterValue": "200003", - "BriefDescription": "Loads missed L1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops ret= ired that hit in the L2.", - "EventCode": "0x04", + "BriefDescription": "Loads hit L2", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops ret= ired that hit in the L2.", "SampleAfterValue": "200003", - "BriefDescription": "Loads hit L2" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops ret= ired that miss in the L2.", - "EventCode": "0x04", + "BriefDescription": "Loads missed L2", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops ret= ired that miss in the L2.", "SampleAfterValue": "100007", - "BriefDescription": "Loads missed L2" + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of load ops ret= ired that had UTLB miss.", - "EventCode": "0x04", + "BriefDescription": "Loads missed UTLB", "Counter": "0,1", - "UMask": "0x10", - "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Loads missed UTLB" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops ret= ired that got data from the other core or from the other module.", "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "MEM_UOPS_RETIRED.HITM", + "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", + "PublicDescription": "This event counts the number of load ops ret= ired that had UTLB miss.", "SampleAfterValue": "200003", - "BriefDescription": "Cross core or cross module hitm" + "UMask": "0x10" }, { - "PublicDescription": "This event counts the number of load ops ret= ired.", - "EventCode": "0x04", + "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", "Counter": "0,1", - "UMask": "0x40", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "All Loads" + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of store ops re= tired.", - "EventCode": "0x04", + "BriefDescription": "Counts any code reads (demand & prefetch) tha= t have any response type.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "All Stores" - }, - { - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "EventCode": "0xB7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000044", + "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000044", + "BriefDescription": "Counts any code reads (demand & prefetch) tha= t hit in the other module where modified copies were found in other core's = L1 cache.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) tha= t hit in the other module where modified copies were found in other core's = L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000044", + "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000044", + "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010044", + "BriefDescription": "Counts any data read (demand & prefetch) that= have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) tha= t have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000022", + "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000022", + "BriefDescription": "Counts any data read (demand & prefetch) that= hit in the other module where modified copies were found in other core's L= 1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that= hit in the other module where modified copies were found in other core's L= 1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000022", + "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_F= WD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000022", + "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010022", + "BriefDescription": "Counts any request that have any response typ= e.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that= have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680003091", + "BriefDescription": "Counts any request that hit in the other modu= le where modified copies were found in other core's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000008008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000003091", + "BriefDescription": "Counts any request that miss L2 and the snoop= s to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400008008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that= hit in the other module where modified copies were found in other core's L= 1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400003091", + "BriefDescription": "Counts any request that miss L2 with a snoop = miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200008008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200003091", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that= have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000013091", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that= have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680004800", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that= hit in the other module where modified copies were found in other core's L= 1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts streaming store that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000008008", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that hit in the other modu= le where modified copies were found in other core's L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400008008", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_= NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that miss L2 and the snoop= s to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200008008", + "BriefDescription": "Counts writeback (modified to exclusive) that= miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that miss L2 with a snoop = miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000018008", + "BriefDescription": "Counts writeback (modified to exclusive) that= miss L2 with no details on snoop-related information.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080000008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that have any response typ= e.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680002000", + "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000002000", + "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that= hit in the other module where modified copies were found in other core's L= 1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400002000", + "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2 and the snoops to sibling cores hit in either E/S stat= e and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200002000", + "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000012000", + "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that are are outstanding, per cycle, from the time of the L2 miss t= o when any response is received.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that= have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000100", + "BriefDescription": "Counts demand and DCU prefetch data read that= have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Countsof demand RFO requests to write to part= ial cache lines that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000080", + "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads of partial cache lines (i= ncluding UC and WC) that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000040", + "BriefDescription": "Counts demand and DCU prefetch data read that= hit in the other module where modified copies were found in other core's L= 1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000040", + "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2 and the snoops to sibling cores hit in either E/S state and t= he line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000040", + "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000020", + "BriefDescription": "Counts demand and DCU prefetch data read that= are are outstanding, per cycle, from the time of the L2 miss to when any r= esponse is received.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000020", + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that hit in the other module where modified copies were found in other c= ore's L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000020", + "BriefDescription": "Counts demand and DCU prefetch RFOs that hit = in the other module where modified copies were found in other core's L1 cac= he.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO= _FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2 and the snoops to sibling cores hit in either E/S state and= the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000020", + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000010", + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000010", + "BriefDescription": "Counts demand and DCU prefetch RFOs that are = are outstanding, per cycle, from the time of the L2 miss to when any respon= se is received.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that hit in the other module where modified copies were found in= other core's L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000010", + "BriefDescription": "Counts demand reads of partial cache lines (i= ncluding UC and WC) that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000080", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2 and the snoops to sibling cores hit in either E/S s= tate and the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000010", + "BriefDescription": "Countsof demand RFO requests to write to part= ial cache lines that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000100", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000008", + "BriefDescription": "Counts DCU hardware prefetcher data read that= have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts writeback (modified to exclusive) that= miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080000008", + "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts writeback (modified to exclusive) that= miss L2 with no details on snoop-related information.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000004", + "BriefDescription": "Counts DCU hardware prefetcher data read that= hit in the other module where modified copies were found in other core's L= 1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that are are outstanding, per cycle, from the time of the L2 miss t= o when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000004", + "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000004", + "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2 and the snoops to sibling cores hit in either E/S stat= e and the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000004", + "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010004", + "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2 and the snoops to sibling cores hit in either E/S state and t= he line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000002", + "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000040", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that are = are outstanding, per cycle, from the time of the L2 miss to when any respon= se is received.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000002", + "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000010", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000002", + "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that hit in the other module where modified copies were found in= other core's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that hit = in the other module where modified copies were found in other core's L1 cac= he.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000002", + "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2 and the snoops to sibling cores hit in either E/S s= tate and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_N= O_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000010", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000002", + "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000001", + "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that= are are outstanding, per cycle, from the time of the L2 miss to when any r= esponse is received.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000001", + "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that hit in the other module where modified copies were found in other c= ore's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000001", + "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2 and the snoops to sibling cores hit in either E/S state and= the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that= hit in the other module where modified copies were found in other core's L= 1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000001", + "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000001", + "BriefDescription": "Counts streaming store that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680004800", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010001", + "BriefDescription": "Any reissued load uops", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that= have any response type.", - "Offcore": "1" + "EventCode": "0x03", + "EventName": "REHABQ.ANY_LD", + "PublicDescription": "This event counts the number of load uops re= issued from Rehabq.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Any reissued store uops", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.ANY_ST", + "PublicDescription": "This event counts the number of store uops r= eissued from Rehabq.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Loads blocked due to store data not ready", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", + "PublicDescription": "This event counts the cases where a forward = was technically possible, but did not occur because the store data was not = available at the right time.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Loads blocked due to store forward restrictio= n", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", + "PEBS": "1", + "PublicDescription": "This event counts the number of retired load= s that were prohibited from receiving forwarded data from the store because= of address mismatch.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Load uops that split cache line boundary", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LD_SPLITS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retire loads= that experienced cache line boundary splits.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops with lock semantics", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LOCK", + "PublicDescription": "This event counts the number of retired memo= ry operations with lock semantics. These are either implicit locked instruc= tions such as the XCHG instruction or instructions with an explicit LOCK pr= efix (0xF0).", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Store address buffer full", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.STA_FULL", + "PublicDescription": "This event counts the number of retired stor= es that are delayed because there is not a store address buffer available.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Store uops that split cache line boundary", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.ST_SPLITS", + "PublicDescription": "This event counts the number of retire store= s that experienced cache line boundary splits.", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json = b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json new file mode 100644 index 000000000000..1d75b35694ac --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json @@ -0,0 +1,11 @@ +[ + { + "BriefDescription": "Stalls due to FP assists", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PublicDescription": "This event counts the number of times that p= ipeline stalled due to FP operations needing assists.", + "SampleAfterValue": "200003", + "UMask": "0x4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tool= s/perf/pmu-events/arch/x86/silvermont/frontend.json index 204473badf5a..a4c98e43f677 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json @@ -1,47 +1,74 @@ [ { - "PublicDescription": "This event counts all instruction fetches, n= ot including most uncacheable\r\nfetches.", - "EventCode": "0x80", + "BriefDescription": "Counts the number of baclears", "Counter": "0,1", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", + "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.ANY event counts the number of ba= clears for any type of branch.", "SampleAfterValue": "200003", - "BriefDescription": "Instruction fetches" + "UMask": "0x1" }, { - "PublicDescription": "This event counts all instruction fetches fr= om the instruction cache.", - "EventCode": "0x80", + "BriefDescription": "Counts the number of JCC baclears", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.COND event counts the number of J= CC (Jump on Condtional Code) baclears.", "SampleAfterValue": "200003", - "BriefDescription": "Instruction fetches from Icache" + "UMask": "0x10" }, { - "PublicDescription": "This event counts all instruction fetches th= at miss the Instruction cache or produce memory requests. This includes unc= acheable fetches. An instruction fetch miss is counted only once and not on= ce for every cycle it is outstanding.", + "BriefDescription": "Counts the number of RETURN baclears", + "Counter": "0,1", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", + "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.RETURN event counts the number of= RETURN baclears.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times a decode restricti= on reduced the decode throughput due to wrong instruction length prediction= ", + "Counter": "0,1", + "EventCode": "0xE9", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PublicDescription": "Counts the number of times a decode restrict= ion reduced the decode throughput due to wrong instruction length predictio= n.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction fetches", + "Counter": "0,1", "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PublicDescription": "This event counts all instruction fetches, n= ot including most uncacheable\r\nfetches.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Instruction fetches from Icache", "Counter": "0,1", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts all instruction fetches fr= om the instruction cache.", "SampleAfterValue": "200003", - "BriefDescription": "Icache miss" + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of times the MSROM starts = a flow of UOPS. It does not count every time a UOP is read from the microco= de ROM. The most common case that this counts is when a micro-coded instru= ction is encountered by the front end of the machine. Other cases include = when an instruction encounters a fault, trap, or microcode assist of any so= rt. The event will count MSROM startups for UOPS that are speculative, and= subsequently cleared by branch mispredict or machine clear. Background: U= OPS are produced by two mechanisms. Either they are generated by hardware = that decodes instructions into UOPS, or they are delivered by a ROM (called= the MSROM) that holds UOPS associated with a specific instruction. MSROM = UOPS might also be delivered in response to some condition such as a fault = or other exceptional condition. This event is an excellent mechanism for d= etecting instructions that require the use of MSROM instructions.", - "EventCode": "0xE7", + "BriefDescription": "Icache miss", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MS_DECODED.MS_ENTRY", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts all instruction fetches th= at miss the Instruction cache or produce memory requests. This includes unc= acheable fetches. An instruction fetch miss is counted only once and not on= ce for every cycle it is outstanding.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times entered into a uco= de flow in the FEC. Includes inserted flows due to front-end detected faul= ts or assists. Speculative count." + "UMask": "0x2" }, { - "PublicDescription": "Counts the number of times a decode restrict= ion reduced the decode throughput due to wrong instruction length predictio= n.", - "EventCode": "0xE9", + "BriefDescription": "Counts the number of times entered into a uco= de flow in the FEC. Includes inserted flows due to front-end detected faul= ts or assists. Speculative count.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", + "PublicDescription": "Counts the number of times the MSROM starts = a flow of UOPS. It does not count every time a UOP is read from the microco= de ROM. The most common case that this counts is when a micro-coded instru= ction is encountered by the front end of the machine. Other cases include = when an instruction encounters a fault, trap, or microcode assist of any so= rt. The event will count MSROM startups for UOPS that are speculative, and= subsequently cleared by branch mispredict or machine clear. Background: U= OPS are produced by two mechanisms. Either they are generated by hardware = that decodes instructions into UOPS, or they are delivered by a ROM (called= the MSROM) that holds UOPS associated with a specific instruction. MSROM = UOPS might also be delivered in response to some condition such as a fault = or other exceptional condition. This event is an excellent mechanism for d= etecting instructions that require the use of MSROM instructions.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times a decode restricti= on reduced the decode throughput due to wrong instruction length prediction" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/= perf/pmu-events/arch/x86/silvermont/memory.json index d72e09a5f929..5e21fc3fd078 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json @@ -1,11 +1,11 @@ [ { - "PublicDescription": "This event counts the number of times that p= ipeline was cleared due to memory ordering issues.", - "EventCode": "0xC3", + "BriefDescription": "Stalls due to Memory ordering", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of times that p= ipeline was cleared due to memory ordering issues.", "SampleAfterValue": "200003", - "BriefDescription": "Stalls due to Memory ordering" + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/other.json b/tools/p= erf/pmu-events/arch/x86/silvermont/other.json index 47814046fa9d..16d16a1ce6de 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/other.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/other.json @@ -1,20 +1,20 @@ [ { - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", - "EventCode": "0x86", + "BriefDescription": "Cycles code-fetch stalled due to any reason.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ALL", + "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ITLB miss." + "UMask": "0x3f" }, { - "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", - "EventCode": "0x86", + "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ITLB miss.", "Counter": "0,1", - "UMask": "0x3f", - "EventName": "FETCH_STALL.ALL", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tool= s/perf/pmu-events/arch/x86/silvermont/pipeline.json index 1ed62ad4cf77..03a4c7f26698 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json @@ -1,356 +1,316 @@ [ { - "PEBS": "1", - "PublicDescription": "ALL_BRANCHES counts the number of any branch= instructions retired. Branch prediction predicts the branch target and en= ables the processor to begin executing instructions long before the branch = true execution path is known. All branches utilize the branch prediction un= it (BPU) for prediction. This unit predicts the target address not only bas= ed on the EIP of the branch but also based on the execution path through wh= ich execution reached this EIP. The BPU can efficiently predict the followi= ng branch types: conditional branches, direct calls and jumps, indirect cal= ls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of branch instructions reti= red...", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions reti= red..." - }, - { "PEBS": "1", - "PublicDescription": "JCC counts the number of conditional branch = (JCC) instructions retired. Branch prediction predicts the branch target an= d enables the processor to begin executing instructions long before the bra= nch true execution path is known. All branches utilize the branch predictio= n unit (BPU) for prediction. This unit predicts the target address not only= based on the EIP of the branch but also based on the execution path throug= h which execution reached this EIP. The BPU can efficiently predict the fol= lowing branch types: conditional branches, direct calls and jumps, indirect= calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_INST_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of JCC branch instructions = retired" + "PublicDescription": "ALL_BRANCHES counts the number of any branch= instructions retired. Branch prediction predicts the branch target and en= ables the processor to begin executing instructions long before the branch = true execution path is known. All branches utilize the branch prediction un= it (BPU) for prediction. This unit predicts the target address not only bas= ed on the EIP of the branch but also based on the execution path through wh= ich execution reached this EIP. The BPU can efficiently predict the followi= ng branch types: conditional branches, direct calls and jumps, indirect cal= ls and jumps, returns.", + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "PublicDescription": "TAKEN_JCC counts the number of taken conditi= onal branch (JCC) instructions retired. Branch prediction predicts the bran= ch target and enables the processor to begin executing instructions long be= fore the branch true execution path is known. All branches utilize the bran= ch prediction unit (BPU) for prediction. This unit predicts the target addr= ess not only based on the EIP of the branch but also based on the execution= path through which execution reached this EIP. The BPU can efficiently pre= dict the following branch types: conditional branches, direct calls and jum= ps, indirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of taken branch instruction= s retired", "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", + "PEBScounters": "0,1", + "PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all = taken branch instructions retired. Branch prediction predicts the branch t= arget and enables the processor to begin executing instructions long before= the branch true execution path is known. All branches utilize the branch p= rediction unit (BPU) for prediction. This unit predicts the target address = not only based on the EIP of the branch but also based on the execution pat= h through which execution reached this EIP. The BPU can efficiently predict= the following branch types: conditional branches, direct calls and jumps, = indirect calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of taken JCC branch instruc= tions retired" + "UMask": "0x80" }, { - "PEBS": "1", - "PublicDescription": "CALL counts the number of near CALL branch i= nstructions retired. Branch prediction predicts the branch target and enab= les the processor to begin executing instructions long before the branch tr= ue execution path is known. All branches utilize the branch prediction unit= (BPU) for prediction. This unit predicts the target address not only based= on the EIP of the branch but also based on the execution path through whic= h execution reached this EIP. The BPU can efficiently predict the following= branch types: conditional branches, direct calls and jumps, indirect calls= and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near CALL branch instruc= tions retired", "Counter": "0,1", - "UMask": "0xf9", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", + "PublicDescription": "CALL counts the number of near CALL branch i= nstructions retired. Branch prediction predicts the branch target and enab= les the processor to begin executing instructions long before the branch tr= ue execution path is known. All branches utilize the branch prediction unit= (BPU) for prediction. This unit predicts the target address not only based= on the EIP of the branch but also based on the execution path through whic= h execution reached this EIP. The BPU can efficiently predict the following= branch types: conditional branches, direct calls and jumps, indirect calls= and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near CALL branch instruc= tions retired" + "UMask": "0xf9" }, { - "PEBS": "1", - "PublicDescription": "REL_CALL counts the number of near relative = CALL branch instructions retired. Branch prediction predicts the branch ta= rget and enables the processor to begin executing instructions long before = the branch true execution path is known. All branches utilize the branch pr= ediction unit (BPU) for prediction. This unit predicts the target address n= ot only based on the EIP of the branch but also based on the execution path= through which execution reached this EIP. The BPU can efficiently predict = the following branch types: conditional branches, direct calls and jumps, i= ndirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of far branch instructions = retired", "Counter": "0,1", - "UMask": "0xfd", - "EventName": "BR_INST_RETIRED.REL_CALL", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PublicDescription": "FAR counts the number of far branch instruct= ions retired. Branch prediction predicts the branch target and enables the= processor to begin executing instructions long before the branch true exec= ution path is known. All branches utilize the branch prediction unit (BPU) = for prediction. This unit predicts the target address not only based on the= EIP of the branch but also based on the execution path through which execu= tion reached this EIP. The BPU can efficiently predict the following branch= types: conditional branches, direct calls and jumps, indirect calls and ju= mps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired" + "UMask": "0xbf" }, { - "PEBS": "1", - "PublicDescription": "IND_CALL counts the number of near indirect = CALL branch instructions retired. Branch prediction predicts the branch ta= rget and enables the processor to begin executing instructions long before = the branch true execution path is known. All branches utilize the branch pr= ediction unit (BPU) for prediction. This unit predicts the target address n= ot only based on the EIP of the branch but also based on the execution path= through which execution reached this EIP. The BPU can efficiently predict = the following branch types: conditional branches, direct calls and jumps, i= ndirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired", "Counter": "0,1", - "UMask": "0xfb", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PublicDescription": "IND_CALL counts the number of near indirect = CALL branch instructions retired. Branch prediction predicts the branch ta= rget and enables the processor to begin executing instructions long before = the branch true execution path is known. All branches utilize the branch pr= ediction unit (BPU) for prediction. This unit predicts the target address n= ot only based on the EIP of the branch but also based on the execution path= through which execution reached this EIP. The BPU can efficiently predict = the following branch types: conditional branches, direct calls and jumps, i= ndirect calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired" + "UMask": "0xfb" }, { - "PEBS": "1", - "PublicDescription": "RETURN counts the number of near RET branch = instructions retired. Branch prediction predicts the branch target and ena= bles the processor to begin executing instructions long before the branch t= rue execution path is known. All branches utilize the branch prediction uni= t (BPU) for prediction. This unit predicts the target address not only base= d on the EIP of the branch but also based on the execution path through whi= ch execution reached this EIP. The BPU can efficiently predict the followin= g branch types: conditional branches, direct calls and jumps, indirect call= s and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of JCC branch instructions = retired", "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_INST_RETIRED.RETURN", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PublicDescription": "JCC counts the number of conditional branch = (JCC) instructions retired. Branch prediction predicts the branch target an= d enables the processor to begin executing instructions long before the bra= nch true execution path is known. All branches utilize the branch predictio= n unit (BPU) for prediction. This unit predicts the target address not only= based on the EIP of the branch but also based on the execution path throug= h which execution reached this EIP. The BPU can efficiently predict the fol= lowing branch types: conditional branches, direct calls and jumps, indirect= calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near RET branch instruct= ions retired" + "UMask": "0x7e" }, { - "PEBS": "1", - "PublicDescription": "NON_RETURN_IND counts the number of near ind= irect JMP and near indirect CALL branch instructions retired. Branch predi= ction predicts the branch target and enables the processor to begin executi= ng instructions long before the branch true execution path is known. All br= anches utilize the branch prediction unit (BPU) for prediction. This unit p= redicts the target address not only based on the EIP of the branch but also= based on the execution path through which execution reached this EIP. The = BPU can efficiently predict the following branch types: conditional branche= s, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired", "Counter": "0,1", - "UMask": "0xeb", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PublicDescription": "NON_RETURN_IND counts the number of near ind= irect JMP and near indirect CALL branch instructions retired. Branch predi= ction predicts the branch target and enables the processor to begin executi= ng instructions long before the branch true execution path is known. All br= anches utilize the branch prediction unit (BPU) for prediction. This unit p= redicts the target address not only based on the EIP of the branch but also= based on the execution path through which execution reached this EIP. The = BPU can efficiently predict the following branch types: conditional branche= s, direct calls and jumps, indirect calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired" + "UMask": "0xeb" }, { - "PEBS": "1", - "PublicDescription": "FAR counts the number of far branch instruct= ions retired. Branch prediction predicts the branch target and enables the= processor to begin executing instructions long before the branch true exec= ution path is known. All branches utilize the branch prediction unit (BPU) = for prediction. This unit predicts the target address not only based on the= EIP of the branch but also based on the execution path through which execu= tion reached this EIP. The BPU can efficiently predict the following branch= types: conditional branches, direct calls and jumps, indirect calls and ju= mps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired", "Counter": "0,1", - "UMask": "0xbf", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PublicDescription": "REL_CALL counts the number of near relative = CALL branch instructions retired. Branch prediction predicts the branch ta= rget and enables the processor to begin executing instructions long before = the branch true execution path is known. All branches utilize the branch pr= ediction unit (BPU) for prediction. This unit predicts the target address n= ot only based on the EIP of the branch but also based on the execution path= through which execution reached this EIP. The BPU can efficiently predict = the following branch types: conditional branches, direct calls and jumps, i= ndirect calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of far branch instructions = retired" + "UMask": "0xfd" }, { - "PEBS": "1", - "PublicDescription": "ALL_BRANCHES counts the number of any mispre= dicted branch instructions retired. This umask is an architecturally define= d event. This event counts the number of retired branch instructions that w= ere mispredicted by the processor, categorized by type. A branch mispredict= ion occurs when the processor predicts that the branch would be taken, but = it is not, or vice-versa. When the misprediction is discovered, all the in= structions executed in the wrong (speculative) path must be discarded, and = the processor must start fetching from the correct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of near RET branch instruct= ions retired", "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PublicDescription": "RETURN counts the number of near RET branch = instructions retired. Branch prediction predicts the branch target and ena= bles the processor to begin executing instructions long before the branch t= rue execution path is known. All branches utilize the branch prediction uni= t (BPU) for prediction. This unit predicts the target address not only base= d on the EIP of the branch but also based on the execution path through whi= ch execution reached this EIP. The BPU can efficiently predict the followin= g branch types: conditional branches, direct calls and jumps, indirect call= s and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired" + "UMask": "0xf7" }, { - "PEBS": "1", - "PublicDescription": "JCC counts the number of mispredicted condit= ional branches (JCC) instructions retired. This event counts the number of= retired branch instructions that were mispredicted by the processor, categ= orized by type. A branch misprediction occurs when the processor predicts t= hat the branch would be taken, but it is not, or vice-versa. When the misp= rediction is discovered, all the instructions executed in the wrong (specul= ative) path must be discarded, and the processor must start fetching from t= he correct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of taken JCC branch instruc= tions retired", "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_MISP_RETIRED.JCC", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PublicDescription": "TAKEN_JCC counts the number of taken conditi= onal branch (JCC) instructions retired. Branch prediction predicts the bran= ch target and enables the processor to begin executing instructions long be= fore the branch true execution path is known. All branches utilize the bran= ch prediction unit (BPU) for prediction. This unit predicts the target addr= ess not only based on the EIP of the branch but also based on the execution= path through which execution reached this EIP. The BPU can efficiently pre= dict the following branch types: conditional branches, direct calls and jum= ps, indirect calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted JCC branch = instructions retired" + "UMask": "0xfe" }, { - "PEBS": "1", - "PublicDescription": "TAKEN_JCC counts the number of mispredicted = taken conditional branch (JCC) instructions retired. This event counts the= number of retired branch instructions that were mispredicted by the proces= sor, categorized by type. A branch misprediction occurs when the processor = predicts that the branch would be taken, but it is not, or vice-versa. Whe= n the misprediction is discovered, all the instructions executed in the wro= ng (speculative) path must be discarded, and the processor must start fetch= ing from the correct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired", "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted taken JCC b= ranch instructions retired" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "ALL_BRANCHES counts the number of any mispre= dicted branch instructions retired. This umask is an architecturally define= d event. This event counts the number of retired branch instructions that w= ere mispredicted by the processor, categorized by type. A branch mispredict= ion occurs when the processor predicts that the branch would be taken, but = it is not, or vice-versa. When the misprediction is discovered, all the in= structions executed in the wrong (speculative) path must be discarded, and = the processor must start fetching from the correct path.", + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "PublicDescription": "IND_CALL counts the number of mispredicted n= ear indirect CALL branch instructions retired. This event counts the numbe= r of retired branch instructions that were mispredicted by the processor, c= ategorized by type. A branch misprediction occurs when the processor predic= ts that the branch would be taken, but it is not, or vice-versa. When the = misprediction is discovered, all the instructions executed in the wrong (sp= eculative) path must be discarded, and the processor must start fetching fr= om the correct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired", "Counter": "0,1", - "UMask": "0xfb", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", + "PublicDescription": "IND_CALL counts the number of mispredicted n= ear indirect CALL branch instructions retired. This event counts the numbe= r of retired branch instructions that were mispredicted by the processor, c= ategorized by type. A branch misprediction occurs when the processor predic= ts that the branch would be taken, but it is not, or vice-versa. When the = misprediction is discovered, all the instructions executed in the wrong (sp= eculative) path must be discarded, and the processor must start fetching fr= om the correct path.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired" + "UMask": "0xfb" }, { - "PEBS": "1", - "PublicDescription": "RETURN counts the number of mispredicted nea= r RET branch instructions retired. This event counts the number of retired= branch instructions that were mispredicted by the processor, categorized b= y type. A branch misprediction occurs when the processor predicts that the = branch would be taken, but it is not, or vice-versa. When the mispredictio= n is discovered, all the instructions executed in the wrong (speculative) p= ath must be discarded, and the processor must start fetching from the corre= ct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted JCC branch = instructions retired", "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_MISP_RETIRED.RETURN", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", + "PublicDescription": "JCC counts the number of mispredicted condit= ional branches (JCC) instructions retired. This event counts the number of= retired branch instructions that were mispredicted by the processor, categ= orized by type. A branch misprediction occurs when the processor predicts t= hat the branch would be taken, but it is not, or vice-versa. When the misp= rediction is discovered, all the instructions executed in the wrong (specul= ative) path must be discarded, and the processor must start fetching from t= he correct path.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired" + "UMask": "0x7e" }, { - "PEBS": "1", - "PublicDescription": "NON_RETURN_IND counts the number of mispredi= cted near indirect JMP and near indirect CALL branch instructions retired. = This event counts the number of retired branch instructions that were misp= redicted by the processor, categorized by type. A branch misprediction occu= rs when the processor predicts that the branch would be taken, but it is no= t, or vice-versa. When the misprediction is discovered, all the instructio= ns executed in the wrong (speculative) path must be discarded, and the proc= essor must start fetching from the correct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired", "Counter": "0,1", - "UMask": "0xeb", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PublicDescription": "NON_RETURN_IND counts the number of mispredi= cted near indirect JMP and near indirect CALL branch instructions retired. = This event counts the number of retired branch instructions that were misp= redicted by the processor, categorized by type. A branch misprediction occu= rs when the processor predicts that the branch would be taken, but it is no= t, or vice-versa. When the misprediction is discovered, all the instructio= ns executed in the wrong (speculative) path must be discarded, and the proc= essor must start fetching from the correct path.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired" + "UMask": "0xeb" }, { - "PublicDescription": "This event counts the number of micro-ops re= tired that were supplied from MSROM.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired", "Counter": "0,1", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.MS", - "SampleAfterValue": "2000003", - "BriefDescription": "MSROM micro-ops retired" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PublicDescription": "RETURN counts the number of mispredicted nea= r RET branch instructions retired. This event counts the number of retired= branch instructions that were mispredicted by the processor, categorized b= y type. A branch misprediction occurs when the processor predicts that the = branch would be taken, but it is not, or vice-versa. When the mispredictio= n is discovered, all the instructions executed in the wrong (speculative) p= ath must be discarded, and the processor must start fetching from the corre= ct path.", + "SampleAfterValue": "200003", + "UMask": "0xf7" }, { - "PublicDescription": "This event counts the number of micro-ops re= tired. The processor decodes complex macro instructions into a sequence of = simpler micro-ops. Most instructions are composed of one or two micro-ops. = Some instructions are decoded into longer sequences such as repeat instruct= ions, floating point transcendental instructions, and assists. In some case= s micro-op sequences are fused or whole instructions are fused into one mic= ro-op. See other UOPS_RETIRED events for differentiating retired fused and = non-fused micro-ops.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted taken JCC b= ranch instructions retired", "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Micro-ops retired" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PublicDescription": "TAKEN_JCC counts the number of mispredicted = taken conditional branch (JCC) instructions retired. This event counts the= number of retired branch instructions that were mispredicted by the proces= sor, categorized by type. A branch misprediction occurs when the processor = predicts that the branch would be taken, but it is not, or vice-versa. Whe= n the misprediction is discovered, all the instructions executed in the wro= ng (speculative) path must be discarded, and the processor must start fetch= ing from the correct path.", + "SampleAfterValue": "200003", + "UMask": "0xfe" }, { - "PublicDescription": "This event counts the number of times that a= program writes to a code section. Self-modifying code causes a severe pena= lty in all Intel? architecture processors.", - "EventCode": "0xC3", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "200003", - "BriefDescription": "Self-Modifying Code detected" + "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. This event is a component in many key event ratios.= The core frequency may change from time to time. For this reason this eve= nt may have a changing ratio with regards to time. In systems with a consta= nt core frequency, this event can give you a measurement of the elapsed tim= e while the core was not in halt state by dividing the event count by the c= ore frequency. This event is architecturally defined and is a designated fi= xed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the cor= e frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC an= d CPU_CLK_UNHALTED.REF are not affected by core frequency changes but count= s as if the core is running at the maximum frequency all the time. The fix= ed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the pr= ogrammable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of times that p= ipeline stalled due to FP operations needing assists.", - "EventCode": "0xC3", + "BriefDescription": "Core cycles when core is not halted", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.FP_ASSIST", - "SampleAfterValue": "200003", - "BriefDescription": "Stalls due to FP assists" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PublicDescription": "This event counts the number of core cycles = while the core is not in a halt state. The core enters the halt state when = it is running the HLT instruction. In mobile systems the core frequency may= change from time to time. For this reason this event may have a changing r= atio with regards to time.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Machine clears happen when something happens= in the machine that causes the hardware to need to take special care to ge= t the right answer. When such a condition is signaled on an instruction, th= e front end of the machine is notified that it must restart, so no more ins= tructions will be decoded from the current path. All instructions \"older\= " than this one will be allowed to finish. This instruction and all \"youn= ger\" instructions must be cleared, since they must not be allowed to compl= ete. Essentially, the hardware waits until the problematic instruction is = the oldest instruction in the machine. This means all older instructions a= re retired, and all pending stores (from older instructions) are completed.= Then the new path of instructions from the front end are allowed to start= into the machine. There are many conditions that might cause a machine cl= ear (including the receipt of an interrupt, or a trap or a fault). All tho= se conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING,= MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY = event. In addition, some conditions can be specifically counted (i.e. SMC, = MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and= FP_ASSIST machine clears will not necessarily equal the number of ANY.", - "EventCode": "0xC3", + "BriefDescription": "Reference cycles when core is not halted", "Counter": "0,1", - "UMask": "0x8", - "EventName": "MACHINE_CLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts all machine clears" + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", + "PublicDescription": "This event counts the number of reference cy= cles that the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction. In mobile systems the core frequency= may change from time. This event is not affected by core frequency changes= but counts as if the core is running at the maximum frequency all the time= .", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of cycles when no uops are= allocated and the ROB is full (less than 2 entries available).", - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "NO_ALLOC_CYCLES.ROB_FULL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are = allocated and the ROB is full (less than 2 entries available)" + "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles while = the core is not in a halt state. The core enters the halt state when it is = running the HLT instruction. This event is a component in many key event ra= tios. The core frequency may change from time. This event is not affected = by core frequency changes but counts as if the core is running at the maxim= um frequency all the time. Divide this event count by core frequency to de= termine the elapsed time while the core was not in halt state. Divide this= event count by core frequency to determine the elapsed time while the core= was not in halt state. This event is architecturally defined and is a des= ignated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P u= se the core frequency which may change from time to time. CPU_CLK_UNHALTE.= REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes= but counts as if the core is running at the maximum frequency all the time= . The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC = and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTE= D.REF.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PublicDescription": "Counts the number of cycles when no uops are= allocated and the alloc pipe is stalled waiting for a mispredicted jump to= retire. After the misprediction is detected, the front end will start imm= ediately but the allocate pipe stalls until the mispredicted.", - "EventCode": "0xCA", + "BriefDescription": "Cycles the divider is busy. Does not imply a= stall waiting for the divider.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are = allocated and the alloc pipe is stalled waiting for a mispredicted jump to = retire. After the misprediction is detected, the front end will start imme= diately but the allocate pipe stalls until the mispredicted" + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", + "PublicDescription": "Cycles the divider is busy.This event counts= the cycles when the divide unit is unable to accept a new divide UOP becau= se it is busy processing a previously dispatched UOP. The cycles will be co= unted irrespective of whether or not another divide UOP is waiting to enter= the divide unit (from the RS). This event might count cycles while a divid= e is in progress even if the RS is empty. The divide instruction is one of= the longest latency instructions in the machine. Hence, it has a special = event associated with it to help determine if divides are delaying the reti= rement of instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "NO_ALLOC_CYCLES.RAT_STALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are = allocated and a RATstall is asserted." + "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions= that retire. For instructions that consist of multiple micro-ops, this ev= ent counts exactly once, as the last micro-op of the instruction retires. = The event continues counting while instructions retire, including during in= terrupt service routines caused by hardware interrupts, faults or traps. B= ackground: Modern microprocessors employ extensive pipelining and speculati= ve techniques. Since sometimes an instruction is started but never complet= ed, the notion of \"retirement\" is introduced. A retired instruction is o= ne that commits its states. Or stated differently, an instruction might be = abandoned at some point. No instruction is truly finished until it retires.= This counter measures the number of completed instructions. The fixed ev= ent is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is u= sed to measure front-end inefficiencies, i.e. when front-end of the machine= is not delivering micro-ops to the back-end and the back-end is not stalle= d. This event can be used to identify if the machine is truly front-end bou= nd. When this event occurs, it is an indication that the front-end of the = machine is operating at less than its theoretical peak performance. Backgr= ound: We can think of the processor pipeline as being divided into 2 broade= r parts: Front-end and Back-end. Front-end is responsible for fetching the = instruction, decoding into micro-ops (uops) in machine understandable forma= t and putting them into a micro-op queue to be consumed by back end. The ba= ck-end then takes these micro-ops, allocates the required resources. When = all resources are ready, micro-ops are executed. If the back-end is not rea= dy to accept micro-ops from the front-end, then we do not want to count the= se as front-end bottlenecks. However, whenever we have bottlenecks in the = back-end, we will have allocation unit stalls and eventually forcing the fr= ont-end to wait until the back-end is ready to receive more UOPS. This even= t counts the cycles only when back-end is requesting more uops and front-en= d is not able to provide them. Some examples of conditions that cause front= -end efficiencies are: Icache misses, ITLB misses, and decoder restrictions= that limit the the front-end bandwidth.", - "EventCode": "0xCA", + "BriefDescription": "Instructions retired", "Counter": "0,1", - "UMask": "0x50", - "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are = allocated, the IQ is empty, and no other condition is blocking allocation." + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions= that retire execution. For instructions that consist of multiple micro-ops= , this event counts the retirement of the last micro-op of the instruction.= The counter continues counting during hardware interrupts, traps, and insi= de interrupt handlers.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the num= ber of cycles when the front-end does not provide any instructions to be al= located for any reason. This event indicates the cycles where an allocation= stalls occurs, and no UOPS are allocated in that cycle.", - "EventCode": "0xCA", + "BriefDescription": "Counts all machine clears", "Counter": "0,1", - "UMask": "0x3f", - "EventName": "NO_ALLOC_CYCLES.ALL", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "PublicDescription": "Machine clears happen when something happens= in the machine that causes the hardware to need to take special care to ge= t the right answer. When such a condition is signaled on an instruction, th= e front end of the machine is notified that it must restart, so no more ins= tructions will be decoded from the current path. All instructions \"older\= " than this one will be allowed to finish. This instruction and all \"youn= ger\" instructions must be cleared, since they must not be allowed to compl= ete. Essentially, the hardware waits until the problematic instruction is = the oldest instruction in the machine. This means all older instructions a= re retired, and all pending stores (from older instructions) are completed.= Then the new path of instructions from the front end are allowed to start= into the machine. There are many conditions that might cause a machine cl= ear (including the receipt of an interrupt, or a trap or a fault). All tho= se conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING,= MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY = event. In addition, some conditions can be specifically counted (i.e. SMC, = MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and= FP_ASSIST machine clears will not necessarily equal the number of ANY.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are = allocated for any reason." + "UMask": "0x8" }, { - "PublicDescription": "Counts the number of cycles and allocation p= ipeline is stalled and is waiting for a free MEC reservation station entry.= The cycles should be appropriately counted in case of the cracked ops e.g= . In case of a cracked load-op, the load portion is sent to M.", - "EventCode": "0xCB", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1", - "UMask": "0x1", - "EventName": "RS_FULL_STALL.MEC", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts the number of times that a= program writes to a code section. Self-modifying code causes a severe pena= lty in all Intel? architecture processors.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles and allocation pi= peline is stalled and is waiting for a free MEC reservation station entry. = The cycles should be appropriately counted in case of the cracked ops e.g.= In case of a cracked load-op, the load portion is sent to M" + "UMask": "0x1" }, { - "EventCode": "0xCB", + "BriefDescription": "Counts the number of cycles when no uops are = allocated for any reason.", "Counter": "0,1", - "UMask": "0x1f", - "EventName": "RS_FULL_STALL.ALL", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ALL", + "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the num= ber of cycles when the front-end does not provide any instructions to be al= located for any reason. This event indicates the cycles where an allocation= stalls occurs, and no UOPS are allocated in that cycle.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles the Alloc pipelin= e is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event= is a superset of all the individual RS stall event counts." + "UMask": "0x3f" }, { - "PublicDescription": "This event counts the number of instructions= that retire execution. For instructions that consist of multiple micro-ops= , this event counts the retirement of the last micro-op of the instruction.= The counter continues counting during hardware interrupts, traps, and insi= de interrupt handlers.", - "EventCode": "0xC0", + "BriefDescription": "Counts the number of cycles when no uops are = allocated and the alloc pipe is stalled waiting for a mispredicted jump to = retire. After the misprediction is detected, the front end will start imme= diately but the allocate pipe stalls until the mispredicted", "Counter": "0,1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired" + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "PublicDescription": "Counts the number of cycles when no uops are= allocated and the alloc pipe is stalled waiting for a mispredicted jump to= retire. After the misprediction is detected, the front end will start imm= ediately but the allocate pipe stalls until the mispredicted.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles the divider is busy.This event counts= the cycles when the divide unit is unable to accept a new divide UOP becau= se it is busy processing a previously dispatched UOP. The cycles will be co= unted irrespective of whether or not another divide UOP is waiting to enter= the divide unit (from the RS). This event might count cycles while a divid= e is in progress even if the RS is empty. The divide instruction is one of= the longest latency instructions in the machine. Hence, it has a special = event associated with it to help determine if divides are delaying the reti= rement of instructions.", - "EventCode": "0xCD", + "BriefDescription": "Counts the number of cycles when no uops are = allocated, the IQ is empty, and no other condition is blocking allocation.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_DIV_BUSY.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles the divider is busy. Does not imply a= stall waiting for the divider." - }, - { - "PublicDescription": "This event counts the number of instructions= that retire. For instructions that consist of multiple micro-ops, this ev= ent counts exactly once, as the last micro-op of the instruction retires. = The event continues counting while instructions retire, including during in= terrupt service routines caused by hardware interrupts, faults or traps. B= ackground: Modern microprocessors employ extensive pipelining and speculati= ve techniques. Since sometimes an instruction is started but never complet= ed, the notion of \"retirement\" is introduced. A retired instruction is o= ne that commits its states. Or stated differently, an instruction might be = abandoned at some point. No instruction is truly finished until it retires.= This counter measures the number of completed instructions. The fixed ev= ent is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", - "Counter": "Fixed counter 1", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired" - }, - { - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. This event is a component in many key event ratios.= The core frequency may change from time to time. For this reason this eve= nt may have a changing ratio with regards to time. In systems with a consta= nt core frequency, this event can give you a measurement of the elapsed tim= e while the core was not in halt state by dividing the event count by the c= ore frequency. This event is architecturally defined and is a designated fi= xed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the cor= e frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC an= d CPU_CLK_UNHALTED.REF are not affected by core frequency changes but count= s as if the core is running at the maximum frequency all the time. The fix= ed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the pr= ogrammable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", - "Counter": "Fixed counter 2", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles" - }, - { - "PublicDescription": "Counts the number of reference cycles while = the core is not in a halt state. The core enters the halt state when it is = running the HLT instruction. This event is a component in many key event ra= tios. The core frequency may change from time. This event is not affected = by core frequency changes but counts as if the core is running at the maxim= um frequency all the time. Divide this event count by core frequency to de= termine the elapsed time while the core was not in halt state. Divide this= event count by core frequency to determine the elapsed time while the core= was not in halt state. This event is architecturally defined and is a des= ignated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P u= se the core frequency which may change from time to time. CPU_CLK_UNHALTE.= REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes= but counts as if the core is running at the maximum frequency all the time= . The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC = and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTE= D.REF.", - "Counter": "Fixed counter 3", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles" + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is u= sed to measure front-end inefficiencies, i.e. when front-end of the machine= is not delivering micro-ops to the back-end and the back-end is not stalle= d. This event can be used to identify if the machine is truly front-end bou= nd. When this event occurs, it is an indication that the front-end of the = machine is operating at less than its theoretical peak performance. Backgr= ound: We can think of the processor pipeline as being divided into 2 broade= r parts: Front-end and Back-end. Front-end is responsible for fetching the = instruction, decoding into micro-ops (uops) in machine understandable forma= t and putting them into a micro-op queue to be consumed by back end. The ba= ck-end then takes these micro-ops, allocates the required resources. When = all resources are ready, micro-ops are executed. If the back-end is not rea= dy to accept micro-ops from the front-end, then we do not want to count the= se as front-end bottlenecks. However, whenever we have bottlenecks in the = back-end, we will have allocation unit stalls and eventually forcing the fr= ont-end to wait until the back-end is ready to receive more UOPS. This even= t counts the cycles only when back-end is requesting more uops and front-en= d is not able to provide them. Some examples of conditions that cause front= -end efficiencies are: Icache misses, ITLB misses, and decoder restrictions= that limit the the front-end bandwidth.", + "SampleAfterValue": "200003", + "UMask": "0x50" }, { - "PublicDescription": "This event counts the number of core cycles = while the core is not in a halt state. The core enters the halt state when = it is running the HLT instruction. In mobile systems the core frequency may= change from time to time. For this reason this event may have a changing r= atio with regards to time.", - "EventCode": "0x3C", + "BriefDescription": "Counts the number of cycles when no uops are = allocated and a RATstall is asserted.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.RAT_STALL", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "This event counts the number of reference cy= cles that the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction. In mobile systems the core frequency= may change from time. This event is not affected by core frequency changes= but counts as if the core is running at the maximum frequency all the time= .", - "EventCode": "0x3C", + "BriefDescription": "Counts the number of cycles when no uops are = allocated and the ROB is full (less than 2 entries available)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "PublicDescription": "Counts the number of cycles when no uops are= allocated and the ROB is full (less than 2 entries available).", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.ANY event counts the number of ba= clears for any type of branch.", - "EventCode": "0xE6", + "BriefDescription": "Counts the number of cycles the Alloc pipelin= e is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event= is a superset of all the individual RS stall event counts.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BACLEARS.ALL", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of baclears" + "UMask": "0x1f" }, { - "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.RETURN event counts the number of= RETURN baclears.", - "EventCode": "0xE6", + "BriefDescription": "Counts the number of cycles and allocation pi= peline is stalled and is waiting for a free MEC reservation station entry. = The cycles should be appropriately counted in case of the cracked ops e.g.= In case of a cracked load-op, the load portion is sent to M", "Counter": "0,1", - "UMask": "0x8", - "EventName": "BACLEARS.RETURN", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.MEC", + "PublicDescription": "Counts the number of cycles and allocation p= ipeline is stalled and is waiting for a free MEC reservation station entry.= The cycles should be appropriately counted in case of the cracked ops e.g= . In case of a cracked load-op, the load portion is sent to M.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of RETURN baclears" + "UMask": "0x1" }, { - "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.COND event counts the number of J= CC (Jump on Condtional Code) baclears.", - "EventCode": "0xE6", + "BriefDescription": "Micro-ops retired", "Counter": "0,1", - "UMask": "0x10", - "EventName": "BACLEARS.COND", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of JCC baclears" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "This event counts the number of micro-ops re= tired. The processor decodes complex macro instructions into a sequence of = simpler micro-ops. Most instructions are composed of one or two micro-ops. = Some instructions are decoded into longer sequences such as repeat instruct= ions, floating point transcendental instructions, and assists. In some case= s micro-op sequences are fused or whole instructions are fused into one mic= ro-op. See other UOPS_RETIRED events for differentiating retired fused and = non-fused micro-ops.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PEBS": "2", - "PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all = taken branch instructions retired. Branch prediction predicts the branch t= arget and enables the processor to begin executing instructions long before= the branch true execution path is known. All branches utilize the branch p= rediction unit (BPU) for prediction. This unit predicts the target address = not only based on the EIP of the branch but also based on the execution pat= h through which execution reached this EIP. The BPU can efficiently predict= the following branch types: conditional branches, direct calls and jumps, = indirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "MSROM micro-ops retired", "Counter": "0,1", - "UMask": "0x80", - "PEBScounters": "0,1", - "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of taken branch instruction= s retired" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PublicDescription": "This event counts the number of micro-ops re= tired that were supplied from MSROM.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json index ad31479f8f60..f4b8a1ef48f6 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json @@ -1,69 +1,69 @@ [ { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops ret= ired that had DTLB miss.", - "EventCode": "0x04", + "BriefDescription": "Loads missed DTLB", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops ret= ired that had DTLB miss.", "SampleAfterValue": "200003", - "BriefDescription": "Loads missed DTLB" + "UMask": "0x8" }, { - "PublicDescription": "This event counts when a data (D) page walk = is completed or started. Since a page walk implies a TLB miss, the number = of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "Total cycles for all the page walks. (I-side = and D-side)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "D-side page-walks", - "EdgeDetect": "1" + "EventCode": "0x05", + "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "This event counts every cycle when a data (D= ) page walk or instruction (I) page walk is in progress. Since a pagewalk = implies a TLB miss, the approximate cost of a TLB miss can be determined fr= om this event.", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "PublicDescription": "This event counts every cycle when a D-side = (walks due to a load) page walk is in progress. Page walk duration divided = by number of page walks is the average duration of page-walks.", - "EventCode": "0x05", + "BriefDescription": "Duration of D-side page-walks in core cycles", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when a D-side = (walks due to a load) page walk is in progress. Page walk duration divided = by number of page walks is the average duration of page-walks.", "SampleAfterValue": "200003", - "BriefDescription": "Duration of D-side page-walks in core cycles" + "UMask": "0x1" }, { - "PublicDescription": "This event counts when an instruction (I) pa= ge walk is completed or started. Since a page walk implies a TLB miss, the= number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "D-side page-walks", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "PublicDescription": "This event counts when a data (D) page walk = is completed or started. Since a page walk implies a TLB miss, the number = of TLB misses can be counted by counting the number of pagewalks.", "SampleAfterValue": "100003", - "BriefDescription": "I-side page-walks", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "PublicDescription": "This event counts every cycle when a I-side = (walks due to an instruction fetch) page walk is in progress. Page walk dur= ation divided by number of page walks is the average duration of page-walks= .", - "EventCode": "0x05", + "BriefDescription": "Duration of I-side page-walks in core cycles", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when a I-side = (walks due to an instruction fetch) page walk is in progress. Page walk dur= ation divided by number of page walks is the average duration of page-walks= .", "SampleAfterValue": "200003", - "BriefDescription": "Duration of I-side page-walks in core cycles" + "UMask": "0x2" }, { - "PublicDescription": "This event counts when a data (D) page walk = or an instruction (I) page walk is completed or started. Since a page walk= implies a TLB miss, the number of TLB misses can be counted by counting th= e number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "I-side page-walks", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "PublicDescription": "This event counts when an instruction (I) pa= ge walk is completed or started. Since a page walk implies a TLB miss, the= number of TLB misses can be counted by counting the number of pagewalks.", "SampleAfterValue": "100003", - "BriefDescription": "Total page walks that are completed (I-side a= nd D-side)", - "EdgeDetect": "1" + "UMask": "0x2" }, { - "PublicDescription": "This event counts every cycle when a data (D= ) page walk or instruction (I) page walk is in progress. Since a pagewalk = implies a TLB miss, the approximate cost of a TLB miss can be determined fr= om this event.", - "EventCode": "0x05", + "BriefDescription": "Total page walks that are completed (I-side a= nd D-side)", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Total cycles for all the page walks. (I-side = and D-side)" + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.WALKS", + "PublicDescription": "This event counts when a data (D) page walk = or an instruction (I) page walk is completed or started. Since a page walk= implies a TLB miss, the number of TLB misses can be counted by counting th= e number of pagewalks.", + "SampleAfterValue": "100003", + "UMask": "0x3" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E61C2C4332F for ; Tue, 1 Feb 2022 02:01:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232792AbiBACBt (ORCPT ); Mon, 31 Jan 2022 21:01:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232259AbiBACAT (ORCPT ); Mon, 31 Jan 2022 21:00:19 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91103C0613E3 for ; Mon, 31 Jan 2022 18:00:12 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id a88-20020a25a1e1000000b00615c588ab22so30285853ybi.3 for ; Mon, 31 Jan 2022 18:00:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=Kk4Zm5h/y0Yg3iILYAuGpcM5yA/WzW0Erq4NQKy/rfM=; b=LzDhk6W+cjeeH4p2Pvc08iVUhcS7+1/L9HWTD9su29q5FQus33PSJM4OAuaYhGTGS/ 1RSWkzAymalvAkwbl3bWxfHO0YXVeEZRgqUJpxbIAUQOe8qIidZ6ghmW2b5bjhU2NaeK zcmxFkL2lJGwal3RhxnZUbI4ySGeVI5DsJ/1e4Wv1y3XZZaOeG8SbTx4kzHh2K5USozt XSwkQ9krONbY+dIEKfVH9/5KbpmTfmqutO8/MXvQ4Ep1skwx01PE6eqSagsh+oSiBXfu wUxBb7LQlq0xWfk4ABt3DCMsLiCDLdAWtmiaMIU/Mps/PfXZGKh28Rya1MjK5u9J9EPq df8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=Kk4Zm5h/y0Yg3iILYAuGpcM5yA/WzW0Erq4NQKy/rfM=; b=Z5gorBEEFUeG+/ltkyIBtc8xCvuahLw1B+7RRHwfFDVhSWaulgyEhNMa6m6HsgJHF0 +PC4kAAN6zUMb2EYH/LwJ7IWI9POpBq4piS+fnuUH+m8QzMNuY9EmwcE4KMCMgvPf7Sg 7ljCGOgDeEqMGgG6cygRybaghmTpsO32XmQPgReKRLqA5Ft0Bghts/hpo15vv1U9DbPO 5CK4+zTz80E3CmmgK1LimODlmDpJ1ucZOTtK3Zrwynk9tqSk4MXbhyL94858p9718tf5 CH6TRu9/CPNI62hvfi7ZgLt69RlEaGz3/t7SH5Oz2//PPJrZXTJEzJGhLvkiRxWuvEii r34Q== X-Gm-Message-State: AOAM5303CDYF+tU9/uj3toGeIt2ESfNr3HQLS/+a0VmI1c1wo/H1O2Ud izZIxgZ+2bZVsuCHbX20x4QnH2Qc2UwZ X-Google-Smtp-Source: ABdhPJxaJZrnSw9mGTPVrOnVf2LTKL09b+8VwoZS2m97pTnHf4vWgdUj/1stZtsvPxclaPP0z8fG0bLszCFh X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a81:8348:: with SMTP id t69mr1684ywf.477.1643680810795; Mon, 31 Jan 2022 18:00:10 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:55 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-24-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 23/26] perf vendor events: Update Tigerlake From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Events are updated to version 1.06: https://download.01.org/perfmon/TGL Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Tigerlake, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/tigerlake/cache.json | 44 +++++++++++++++++-- .../arch/x86/tigerlake/floating-point.json | 11 ++++- .../arch/x86/tigerlake/frontend.json | 17 ++++++- .../arch/x86/tigerlake/pipeline.json | 37 +++++++++++++++- 4 files changed, 100 insertions(+), 9 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/tigerlake/cache.json index 8d767b8932b0..543a3298f86f 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json @@ -145,6 +145,17 @@ "SampleAfterValue": "200003", "UMask": "0x24" }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, { "BriefDescription": "All requests that miss L2 cache", "CollectPEBSRecord": "2", @@ -185,7 +196,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instruc= tions.", + "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", "SampleAfterValue": "200003", "UMask": "0xc8" }, @@ -196,7 +207,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instru= ctions.", + "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", "SampleAfterValue": "200003", "UMask": "0x28" }, @@ -222,6 +233,17 @@ "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, { "BriefDescription": "All retired load instructions.", "CollectPEBSRecord": "2", @@ -249,6 +271,20 @@ "SampleAfterValue": "1000003", "UMask": "0x82" }, + { + "BriefDescription": "All retired memory instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" + }, { "BriefDescription": "Retired load instructions with locked access.= ", "CollectPEBSRecord": "2", @@ -298,7 +334,7 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that true m= iss the STLB.", + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, @@ -312,7 +348,7 @@ "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that true = miss the STLB.", + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" }, diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b= /tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json index 402f01851313..de8eb2b34a3a 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json @@ -17,6 +17,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x4" }, @@ -27,7 +28,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of SSE/AVX computational 128-b= it packed single precision floating-point instructions retired; some instru= ctions will count twice as noted below. Each count represents 4 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MI= N MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions c= ount twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x8" }, @@ -38,6 +39,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x10" }, @@ -48,6 +50,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x20" }, @@ -58,16 +61,18 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", "SampleAfterValue": "100003", "UMask": "0x40" }, { - "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed double= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x80" }, @@ -78,6 +83,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -88,6 +94,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json b/tools= /perf/pmu-events/arch/x86/tigerlake/frontend.json index 24c736ac8f8e..2eaa33cc574e 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json @@ -39,12 +39,27 @@ "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", "MSRValue": "0x11", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/tigerlake/pipeline.json index d0d8a09bc470..4dc3a16e3da4 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json @@ -71,14 +71,14 @@ "UMask": "0x40" }, { - "BriefDescription": "All indirect branch instructions retired (exc= luding RETs. TSX aborts are considered indirect branch).", + "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions reti= red (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts near indirect branch instructions ret= ired excluding returns. TSX abort is an indirect branch.", "SampleAfterValue": "100003", "UMask": "0x80" }, @@ -442,6 +442,17 @@ "SampleAfterValue": "500009", "UMask": "0x1" }, + { + "BriefDescription": "Instruction decoders utilized in a cycle", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "INST_DECODED.DECODERS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", "CollectPEBSRecord": "2", @@ -464,6 +475,17 @@ "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", "CollectPEBSRecord": "2", @@ -689,6 +711,17 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, { "BriefDescription": "Number of uops executed on port 0", "CollectPEBSRecord": "2", --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B2BBC433F5 for ; Tue, 1 Feb 2022 02:01:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233224AbiBACBm (ORCPT ); Mon, 31 Jan 2022 21:01:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232287AbiBACAT (ORCPT ); Mon, 31 Jan 2022 21:00:19 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A4BDC0613E6 for ; Mon, 31 Jan 2022 18:00:15 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id c76-20020a25c04f000000b00613e2c514e2so29874657ybf.21 for ; Mon, 31 Jan 2022 18:00:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=CSFFPa9f8Mi16VnzV5BR4aScnoL9/WoilM+dMY6/MyQ=; b=lgLsvQzy7PaT2bgFoVPZWMtnER5+jIpnieN7OrWttHHXzgK7gDYHjf+bIuqghg0LwT fbIZYQU1CKf6W2X8dc7Xd+FWMaNC1IKjft/7Kr8YEMHOifeAgDgk3n6C9BAlb2Qks6tq fRKkLX+28FiGlBPGxlMPe0bj3Kxu6pCf2Lcm4n4aG2JNFRXGHrirzpwNyrqHoDaDi8n1 vNwmNY7NDpDDTau9GgGMzhUGbZ2Ka6Nw1xUsYc8FkIRatt6JWzOZ52qtLUeEzUNQf3rJ szKXuBgbeqSe7oJ7WGK7CzZTpATya3NpY73KNJ05pH55U90yG9v2DId6gjFojdOaUmA+ 5fCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=CSFFPa9f8Mi16VnzV5BR4aScnoL9/WoilM+dMY6/MyQ=; b=DRPjWRamM2pz6A4X+3jbU/e+Pe+C66xdVEypdbv0AU1hE/aU3/n5uJryyIcWyv25yw gynAwL/pTZpBWkS/iUabsgjHw2whh6LjrtbrZ2H4NB0zrdXfY8yn/rVITqFaWLU7z1lA FnnlRsaLOY+Va3rkxVGtxG45LBhiLXCYUDoW74R4m1QgQNSfQEpYyPPmVccWy48vs1NA /dR+4zhixvg7SZTpkfxPJqc79YLLmrN1xv5yqZTKRxWawV44HZS6O+BwlbzquCJTAjaT BZqy8slUpOabRxqBdVx0mq2mNRdMMKzZybEylM6e8Ih33DYg7MdiztVHsHxT4+mFmuGc hE2w== X-Gm-Message-State: AOAM532ZjPZ4SdnPoyuNIHsZQOo7q2IKo0Gqm/xuqtd7VSsNAOt8EDt7 +g45CANp0Q5CWeMliBTqYqZ4pcnoAfjT X-Google-Smtp-Source: ABdhPJxE/wrIckCS29mogB/iPb8tuP1ZYtpTywf2saJRjGfESQvOTpSI9VsrsczRllvkgr91Zk+4MMNpBlmb X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:6a55:: with SMTP id f82mr30180436ybc.1.1643680814545; Mon, 31 Jan 2022 18:00:14 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:56 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-25-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 24/26] perf vendor events: Update Westmere EP-SP From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Events are still at version 2: https://download.01.org/perfmon/WSM-EP-SP Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Westmere EP-SP, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../arch/x86/westmereep-sp/cache.json | 3142 ++++++++--------- .../x86/westmereep-sp/floating-point.json | 180 +- .../arch/x86/westmereep-sp/frontend.json | 18 +- .../arch/x86/westmereep-sp/memory.json | 670 ++-- .../arch/x86/westmereep-sp/other.json | 238 +- .../arch/x86/westmereep-sp/pipeline.json | 780 ++-- .../x86/westmereep-sp/virtual-memory.json | 120 +- 7 files changed, 2574 insertions(+), 2574 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tool= s/perf/pmu-events/arch/x86/westmereep-sp/cache.json index dad20f0e3cac..2ecd80f8fa67 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -1,3233 +1,3233 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0x8" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0x8" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0x80" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch reque= st" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" + "UMask": "0x10" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x20" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { + "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "UMask": "0xc0" + }, + { + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" + "UMask": "0x40" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch misses", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" + "UMask": "0x80" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xc" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO misses", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 transactions", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" - }, - { "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0x80" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0x8" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (= Precise Event)" + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "100", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)" + "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)" + "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "10000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)" + "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", + "SampleAfterValue": "5", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)" + "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "SampleAfterValue": "50", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)" + "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "500", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)" + "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "5000", + "UMask": "0x10" }, { + "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", + "SampleAfterValue": "3", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "50000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", + "SampleAfterValue": "20", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "200", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "20000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", + "SampleAfterValue": "10", + "UMask": "0x10" + }, + { + "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", - "EventCode": "0xF", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (= Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired with a data source = of local DRAM or locally homed remote hitm (Precise Event)" + "UMask": "0x10" }, { + "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", - "EventCode": "0xF", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)" + "UMask": "0x8" }, { + "BriefDescription": "Load instructions retired with a data source = of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load instructions retired remote cache HIT da= ta source (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired remote cache HIT da= ta source (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xF", + "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)" + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xF", + "BriefDescription": "Load instructions retired IO (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" + "UMask": "0x80" }, { - "EventCode": "0xB0", + "BriefDescription": "All offcore requests", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" + "UMask": "0x80" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore read requests", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" + "UMask": "0x8" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore RFO requests", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" + "UMask": "0x10" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand code read requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" + "UMask": "0x2" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand data read requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" + "UMask": "0x1" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" + "UMask": "0x4" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore L1 data cache writebacks", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" + "UMask": "0x40" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore uncached memory accesses", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", "SampleAfterValue": "100000", - "BriefDescription": "Offcore uncached memory accesses" + "UMask": "0x20" }, { + "BriefDescription": "Outstanding offcore reads", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" + "UMask": "0x8" }, { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" + "UMask": "0x8" }, { + "BriefDescription": "Outstanding offcore demand code reads", "EventCode": "0x60", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" + "UMask": "0x2" }, { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" - }, - { + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding offcore demand data reads", "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue f= ull" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", - "MSRIndex": "0x3F6", - "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)" + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)" + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)" + "BriefDescription": "Outstanding offcore demand RFOs", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "UMask": "0x4" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)" + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F11", + "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2711", + "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cach= e", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2744", + "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cach= e", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x27FF", + "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x27FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x58FF", + "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x58FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5808", + "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y location", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2780", + "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote c= ache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote c= ache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote = cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F50", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF50", + "BriefDescription": "All offcore prefetch data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8050", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x150", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x150", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x250", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x250", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x450", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x450", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x750", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x750", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2750", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2750", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1850", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5850", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1050", + "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x850", + "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.js= on b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "MMX Uops", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { + "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" + "UMask": "0x80" }, { - "EventCode": "0x10", + "BriefDescription": "SSE and SSE2 FP Uops", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP packed Uops", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP scalar Uops", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" + "UMask": "0x20" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP single precision Uops", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" + "UMask": "0x40" }, { - "EventCode": "0x10", + "BriefDescription": "Computational floating-point operations execu= ted", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations execu= ted" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transition= s", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transition= s" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instru= ctions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instru= ctions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operation= s" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/t= ools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/too= ls/perf/pmu-events/arch/x86/westmereep-sp/memory.json index 90eb6aac357b..623a0087c8f3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json @@ -1,739 +1,739 @@ [ { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by the local DRA= M", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by the local DRA= M", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that misse= d the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that misse= d the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the = LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the L= LC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4080", + "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6050", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF850", + "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2050", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4050", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the L= LC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the L= LC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC= ", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tool= s/perf/pmu-events/arch/x86/westmereep-sp/other.json index 85133d6a5ce0..23dcd554728c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json @@ -1,287 +1,287 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Loads that partially overlap an earlier store= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" + "UMask": "0x2" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address ali= asing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address ali= asing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Snoop code requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" + "UMask": "0x4" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" + "UMask": "0x1" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop invalidate requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding snoop code requests", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" + "UMask": "0x4" }, { + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Outstanding snoop data requests", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding snoop invalidate requests", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xF6", + "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Thread responded HITE to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/t= ools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json index f130510f7616..10140f460fbb 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json @@ -1,899 +1,899 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", + "BriefDescription": "Divide Operations executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", "EventName": "ARITH.DIV", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Divide Operations executed", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired near call instructions (Precise Event= )", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event= )" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted branches executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches execu= ted", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches execu= ted" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Even= t)" + "UMask": "0x2" }, { - "EventCode": "0x0", + "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed count= er)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed count= er)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", + "BriefDescription": "Total CPU cycles", "Counter": "0,1,2,3", - "UMask": "0x0", + "CounterMask": "2", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder = 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder = 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", + "EventCode": "0x17", + "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instru= ction queue" + "UMask": "0x1" }, { - "EventCode": "0x17", + "BriefDescription": "Cycles instructions are written to the instru= ction queue", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITES", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Ev= ent)" + "UMask": "0x2" }, { - "EventCode": "0x4C", + "BriefDescription": "Load operations conflicting with software pre= fetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software pre= fetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", + "BriefDescription": "Cycles no uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.INACTIVE", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction = queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction = queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)" + "UMask": "0x10" }, { - "EventCode": "0xDB", + "BriefDescription": "Stack pointer instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", + "BriefDescription": "Cycles no Uops are decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)= ", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" - }, - { + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on ports 0-4 (core count)", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x3f" }, { + "AnyThread": "1", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on any port (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", + "SampleAfterValue": "2000000", + "UMask": "0x3f" + }, + { "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", + "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x80", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT234_CORE", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", + "BriefDescription": "Cycles no Uops were issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles Uops are being retired", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Uop unfusions due to FP exceptions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json index 2153b3f5d7b0..0252f77a844b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json @@ -1,149 +1,149 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x4F", + "BriefDescription": "Extended Page Table walk cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" + "UMask": "0x10" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" + "UMask": "0x4" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", - "EventCode": "0xCB", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)" + "UMask": "0x1" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FC85C43217 for ; Tue, 1 Feb 2022 02:01:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232546AbiBACBw (ORCPT ); Mon, 31 Jan 2022 21:01:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232773AbiBACAU (ORCPT ); Mon, 31 Jan 2022 21:00:20 -0500 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05F43C06173E for ; Mon, 31 Jan 2022 18:00:18 -0800 (PST) Received: by mail-yb1-xb4a.google.com with SMTP id n198-20020a2540cf000000b00614c2ee23b7so30234389yba.9 for ; Mon, 31 Jan 2022 18:00:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=bEE/2QuH3ZEV1G5Lyi8qSStCaEQ1XiO9gMXy5WqXZdo=; b=gmKrLNGQV+MKVZCd8+ypgex/O0yLXSBWmK+yTNbhDbSJetGdOw5hG6ndxg5xh4qNHF k3fn77l2AKQSCrewppJVSGqvri35TvTYo00FoJVhGKamo27hMz0A04DLNW+kDgukgWoF uJMxLYMUi76SFKTa4grC8tKfh+GuMbDouMI5STPTweDlRzpY9rvvXbmjEsK22CaYbF6z OAeqbLSV/31IfSe6v0DEDIUKxQNU/48iiba186HhRSjHNLp3XjqnVmqBPlzsLTv5m7qG ix5Ebw4AKLANRGUgc77uolTxoYRwOlEKkDbgKurHOPJ/VHyXsWREaLhK0N9FD/8djZf5 BqKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=bEE/2QuH3ZEV1G5Lyi8qSStCaEQ1XiO9gMXy5WqXZdo=; b=zODTM+MQvgOtfhaapC5CzJvy1YORFYUNvWRQdsfsUC7OJ3gpsnFyo2+UL50S9QeeW8 DSaB24/3HhnKcfEJ2mXNADzOzcjAQ01fh2cemy4RUKAQzYqUITG9AZFgjSTkNlN/sJUs nFkfHWUJdkpGBDpoW7juKjhZvupHEWs4Ne2kgKNKEAYqEp+lvZmFalUqaIgb4xTgXJEq LFl0CFk41M+H4WCWUp+1YPPZEGhMKU2eSlrOcKrIXp358DpjFshnXC3pEaVDhwrXlQAM 84JKsWYYGgqw1vPKz95errGD4bIu8Azl0FlBBQ1szhz94DotFpHt5lH+lAPoKrwg+Osg 2dJQ== X-Gm-Message-State: AOAM532hN3ppTFuOj+PnrxzzpAhoK7IcHQwij5fBMTkUwLeQnD+DakFA XPd/Tk5kAwtlDKcTsyXcbqrKQxo/kGFK X-Google-Smtp-Source: ABdhPJz184D5Wi31PIDTVc6cnLNgAsgDhOdyFrJ8mNLtgYsP9R66FdfLNIovUQlaoQMOl+DQdwC8xZz4qTrt X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:b14e:bc64:b7f6:5d4b]) (user=irogers job=sendgmr) by 2002:a25:d855:: with SMTP id p82mr30274148ybg.575.1643680817134; Mon, 31 Jan 2022 18:00:17 -0800 (PST) Date: Mon, 31 Jan 2022 17:58:57 -0800 In-Reply-To: <20220201015858.1226914-1-irogers@google.com> Message-Id: <20220201015858.1226914-26-irogers@google.com> Mime-Version: 1.0 References: <20220201015858.1226914-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH v2 25/26] perf vendor events: Update Westmere EX From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Events are still at version 2: https://download.01.org/perfmon/WSM-EX Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Westmere EX, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/westmereex/cache.json | 3142 ++++++++--------- .../arch/x86/westmereex/floating-point.json | 180 +- .../arch/x86/westmereex/frontend.json | 18 +- .../arch/x86/westmereex/memory.json | 676 ++-- .../pmu-events/arch/x86/westmereex/other.json | 238 +- .../arch/x86/westmereex/pipeline.json | 784 ++-- .../arch/x86/westmereex/virtual-memory.json | 138 +- 7 files changed, 2584 insertions(+), 2592 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/p= erf/pmu-events/arch/x86/westmereex/cache.json index f9bc7fdd48d6..23de93ea347a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json @@ -1,3225 +1,3225 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0x8" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0x8" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0x80" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch reque= st" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" + "UMask": "0x10" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x20" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { + "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "UMask": "0xc0" + }, + { + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" + "UMask": "0x40" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch misses", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" + "UMask": "0x80" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xc" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO misses", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 transactions", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" - }, - { "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0x80" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0x8" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (= Precise Event)" + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "100", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)" + "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)" + "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "10000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)" + "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", + "SampleAfterValue": "5", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)" + "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "SampleAfterValue": "50", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)" + "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "500", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)" + "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "5000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", + "SampleAfterValue": "3", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "50000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", + "SampleAfterValue": "20", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "200", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "20000", + "UMask": "0x10" }, { + "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", + "SampleAfterValue": "10", + "UMask": "0x10" + }, + { + "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", - "EventCode": "0xF", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (= Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)" + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { + "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", - "EventCode": "0xF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired local dram and remo= te cache HIT data sources (Precise Event)" + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { + "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", - "EventCode": "0xF", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)" + "UMask": "0x10" }, { + "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", - "EventCode": "0xF", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", - "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" }, { + "BriefDescription": "Load instructions retired local dram and remo= te cache HIT data sources (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that hit remote socket in modif= ied state (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", + "PEBS": "1", "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit remote socket in modif= ied state (Precise Event)" + "UMask": "0x4" }, { - "EventCode": "0xB0", + "BriefDescription": "Load instructions retired IO (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", + "SampleAfterValue": "4000", + "UMask": "0x80" + }, + { + "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" + "UMask": "0x80" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore read requests", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" + "UMask": "0x8" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore RFO requests", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" + "UMask": "0x10" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand code read requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" + "UMask": "0x2" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand data read requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" + "UMask": "0x1" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore demand RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" + "UMask": "0x4" }, { - "EventCode": "0xB0", + "BriefDescription": "Offcore L1 data cache writebacks", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" + "UMask": "0x40" }, { + "BriefDescription": "Outstanding offcore reads", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" + "UMask": "0x8" }, { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" + "UMask": "0x8" }, { + "BriefDescription": "Outstanding offcore demand code reads", "EventCode": "0x60", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" + "UMask": "0x2" }, { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" - }, - { + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding offcore demand data reads", "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue f= ull" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", - "MSRIndex": "0x3F6", - "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)" + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)" + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)" + "BriefDescription": "Outstanding offcore demand RFOs", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "UMask": "0x4" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)" + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x4" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F11", + "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4711", + "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4744", + "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x47FF", + "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x47FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x38FF", + "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x38FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3808", + "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y location", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1A6", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1A6", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1A6", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1A6", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1A6", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1A6", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4780", + "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote c= ache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote c= ache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote = cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F30", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF30", + "BriefDescription": "All offcore prefetch data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8030", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x130", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x130", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x230", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x230", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x430", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x430", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x730", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4730", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1830", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3830", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1030", + "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x830", + "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json = b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "MMX Uops", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { + "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" + "UMask": "0x80" }, { - "EventCode": "0x10", + "BriefDescription": "SSE and SSE2 FP Uops", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP packed Uops", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP scalar Uops", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" + "UMask": "0x20" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP single precision Uops", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" + "UMask": "0x40" }, { - "EventCode": "0x10", + "BriefDescription": "Computational floating-point operations execu= ted", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations execu= ted" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transition= s", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transition= s" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instru= ctions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instru= ctions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operation= s" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tool= s/perf/pmu-events/arch/x86/westmereex/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/= perf/pmu-events/arch/x86/westmereex/memory.json index 3ba555e73cbd..a2132858b9c1 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json @@ -1,747 +1,747 @@ [ { - "EventCode": "0x5", + "BriefDescription": "Misaligned store references", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", - "BriefDescription": "Misaligned store references" + "UMask": "0x2" }, { - "EventCode": "0xB7", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by the local DRA= M", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by the local DRA= M", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that misse= d the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that misse= d the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2080", + "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6030", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF830", + "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4030", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2030", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/p= erf/pmu-events/arch/x86/westmereex/other.json index 85133d6a5ce0..23dcd554728c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json @@ -1,287 +1,287 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Loads that partially overlap an earlier store= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" + "UMask": "0x2" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address ali= asing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address ali= asing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Snoop code requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" + "UMask": "0x4" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" + "UMask": "0x1" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop invalidate requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding snoop code requests", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" + "UMask": "0x4" }, { + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Outstanding snoop data requests", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding snoop invalidate requests", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xF6", + "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Thread responded HITE to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tool= s/perf/pmu-events/arch/x86/westmereex/pipeline.json index 799c57d94c39..620d9084d860 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json @@ -1,905 +1,897 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", + "BriefDescription": "Divide Operations executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", "EventName": "ARITH.DIV", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Divide Operations executed", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired near call instructions (Precise Event= )", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event= )" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted branches executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches execu= ted", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches execu= ted" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Even= t)" + "UMask": "0x2" }, { - "EventCode": "0x0", + "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed count= er)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed count= er)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", + "BriefDescription": "Total CPU cycles", "Counter": "0,1,2,3", - "UMask": "0x0", + "CounterMask": "2", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder = 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder = 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", + "EventCode": "0x17", + "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instru= ction queue" + "UMask": "0x1" }, { - "EventCode": "0x17", + "BriefDescription": "Cycles instructions are written to the instru= ction queue", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITES", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Ev= ent)" + "UMask": "0x2" }, { - "EventCode": "0x4C", + "BriefDescription": "Load operations conflicting with software pre= fetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software pre= fetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", + "BriefDescription": "Cycles no uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.INACTIVE", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction = queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction = queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles thread is active" + "UMask": "0x10" }, { - "EventCode": "0xDB", + "BriefDescription": "Stack pointer instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", + "BriefDescription": "Cycles no Uops are decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)= ", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Uops executed on any port (core count)", "Counter": "0,1,2,3", - "UMask": "0x3f", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on any port (core count)", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Uops executed on ports 0-4 (core count)", "Counter": "0,1,2,3", - "UMask": "0x1f", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on ports 0-4 (core count)", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on any port (core count= )", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", + "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x80", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT234_CORE", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", + "BriefDescription": "Cycles no Uops were issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles Uops are being retired", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Uop unfusions due to FP exceptions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json index ad989207e8f8..5d1e017d1261 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -1,173 +1,173 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses caused by low part of address. Co= unt also includes 2M page references because 2M pages do not use the PDE.", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses caused by low part of address. Co= unt also includes 2M page references because 2M pages do not use the PDE." + "UMask": "0x20" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x4F", + "BriefDescription": "Extended Page Table walk cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" + "UMask": "0x10" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" + "UMask": "0x4" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", - "EventCode": "0xCB", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)" + "UMask": "0x1" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog From nobody Mon Jun 29 23:25:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8868C433FE for ; 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charset="utf-8" Note 01.org has no TremontX directory but in mapfile.csv the family and model: ... GenuineIntel-6-86,V1.17,/SNR/snowridgex_core_v1.17.json,core,,, GenuineIntel-6-86,V1.17,/SNR/snowridgex_uncore_v1.17.json,uncore,,, ... match TremontX in the perf mapfile.csv: ... GenuineIntel-6-86,v1,tremontx,core ... Events are at version 1.17: https://download.01.org/perfmon/SNR Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf floating-point.json is added. Tested: Not tested on a SnowridgeX/TremontX, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/tremontx/cache.json | 282 ++- .../arch/x86/tremontx/floating-point.json | 24 + .../arch/x86/tremontx/frontend.json | 97 +- .../pmu-events/arch/x86/tremontx/memory.json | 449 +++- .../pmu-events/arch/x86/tremontx/other.json | 1786 +++++++++++++- .../arch/x86/tremontx/pipeline.json | 341 ++- .../arch/x86/tremontx/uncore-memory.json | 156 +- .../arch/x86/tremontx/uncore-other.json | 2045 ++++++++++++++++- .../arch/x86/tremontx/virtual-memory.json | 320 ++- 9 files changed, 5262 insertions(+), 238 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/floating-point.= json diff --git a/tools/perf/pmu-events/arch/x86/tremontx/cache.json b/tools/per= f/pmu-events/arch/x86/tremontx/cache.json index f88040171b4d..615b516ea021 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/cache.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/cache.json @@ -1,111 +1,305 @@ [ { + "BriefDescription": "Counts the number of core requests (demand an= d L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of first level data cacheli= ne (dirty) evictions caused by misses, stores, and prefetches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "DL1.DIRTY_EVICTION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of first level data cachel= ine (dirty) evictions caused by misses, stores, and prefetches. Does not c= ount evictions or dirty writebacks caused by snoops. Does not count a repl= acement unless a (dirty) line was written back.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cacheable memory requests that miss i= n the the Last Level Cache. Requests include Demand Loads, Reads for Owner= ship(RFO), Instruction fetches and L1 HW prefetches. If the platform has an= L3 cache, last level cache is the L3, otherwise it is the L2.", - "EventCode": "0x2e", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). If the platform has an L3 cache= , the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per co= re basis.", "SampleAfterValue": "200003", - "BriefDescription": "Counts memory requests originating from the c= ore that miss in the last level cache. If the platform has an L3 cache, las= t level cache is the L3, otherwise it is the L2." + "UMask": "0x41" }, { + "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cacheable memory requests that access= the Last Level Cache. Requests include Demand Loads, Reads for Ownership(= RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 c= ache, last level cache is the L3, otherwise it is the L2.", + "Counter": "0,1,2,3", "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH", "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200003", + "UMask": "0x38" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles a core is stalle= d due to an instruction cache or translation lookaside buffer (TLB) access = which hit in DRAM or MMIO (non-DRAM).", "SampleAfterValue": "200003", - "BriefDescription": "Counts memory requests originating from the c= ore that reference a cache line in the last level cache. If the platform ha= s an L3 cache, last level cache is the L3, otherwise it is the L2." + "UMask": "0x20" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired. This= event is Precise Event capable", - "EventCode": "0xd0", "Counter": "0,1,2,3", - "UMask": "0x81", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "Counts the number of cycles a core is stalle= d due to an instruction cache or Translation Lookaside Buffer (TLB) access = which hit in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired.", - "Data_LA": "1" + "UMask": "0x8" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired. Thi= s event is Precise Event capable", - "EventCode": "0xd0", "Counter": "0,1,2,3", - "UMask": "0x82", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "Counts the number of cycles a core is stalle= d due to an instruction cache or Translation Lookaside Buffer (TLB) access = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of store uops retired.", - "Data_LA": "1" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", "CollectPEBSRecord": "2", - "EventCode": "0xd1", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that h= it the level 1 data cache", - "Data_LA": "1" + "UMask": "0x7" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the Last Level Cache (LLC) or other cor= e with HITE/F/M.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of cycles a core is stalled= due to a store buffer being full.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of load ops retired that hi= t in DRAM.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of retired loads that hit i= n the L3 cache, in which a snoop was required and modified data was forward= ed from another core.", "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of load uops retired that h= it in the L1 data cache.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that h= it in the level 2 cache", - "Data_LA": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of load uops retired that m= iss in the L1 data cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of load uops retired that m= iss in the L2 cache.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x4", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that m= iss in the level 3 cache" + "UMask": "0x4" }, { + "BriefDescription": "Counts the number of load uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of load uops retired= .", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Counts the number of store uops retired.", "CollectPEBSRecord": "2", - "EventCode": "0xd1", "Counter": "0,1,2,3", - "UMask": "0x8", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PublicDescription": "Counts the total number of store uops retire= d.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that m= iss in the level 1 data cache", - "Data_LA": "1" + "UMask": "0x82" }, { + "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x43" + }, + { + "BriefDescription": "Counts the number of retired split loads uops= .", "CollectPEBSRecord": "2", - "EventCode": "0xd1", "Counter": "0,1,2,3", - "UMask": "0x10", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that m= iss in the level 2 cache", - "Data_LA": "1" + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ICACHE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json b/= tools/perf/pmu-events/arch/x86/tremontx/floating-point.json new file mode 100644 index 000000000000..2515b9aa6e66 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json @@ -0,0 +1,24 @@ +[ + { + "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy. Does not imply a stall waiting for the divider.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcd", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/frontend.json b/tools/= perf/pmu-events/arch/x86/tremontx/frontend.json index 73b0a1ed5756..c752c52ba03e 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/frontend.json @@ -1,26 +1,105 @@ [ { + "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.MISSES", + "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of BACLEARS due to a condit= ional jump.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.COND", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", - "BriefDescription": "Counts requests to the Instruction Cache (ICa= che) for one or more bytes in a cache line and they do not hit in the ICach= e (miss)." + "UMask": "0x10" }, { + "BriefDescription": "Counts the number of BACLEARS due to an indir= ect branch.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.INDIRECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of BACLEARS due to a return= branch.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.RETURN", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of BACLEARS due to a direct= , unconditional jump.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.UNCOND", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a decode restricti= on reduces the decode throughput due to wrong instruction length prediction= .", "CollectPEBSRecord": "2", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xe9", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of instruction cache hits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of requests that hit in th= e instruction cache. The event only counts new cache line accesses, so tha= t multiple back to back fetches to the exact same cache line and byte chunk= count as one. Specifically, the event counts when accesses from sequentia= l code crosses the cache line boundary, or when a branch target is moved to= a new line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of instruction cache misses= .", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", - "BriefDescription": "Counts requests to the Instruction Cache (ICa= che) for one or more bytes cache Line." + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/memory.json b/tools/pe= rf/pmu-events/arch/x86/tremontx/memory.json index 65469e84f35b..4486f78035d8 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/memory.json @@ -1,26 +1,457 @@ [ { + "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000044", + "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", - "MSRValue": "0x000000003F04000001", + "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that was not supplie= d by the L3 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002184000000", + "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", - "MSRValue": "0x000000003F04000002", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all hardware and software prefetches t= hat were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PREFETCHES.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000470", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand reads for ownership (RFO) r= equests and software based prefetches for exclusive ownership (PREFETCHW) t= hat was not supplied by the L3 cache.", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/other.json b/tools/per= f/pmu-events/arch/x86/tremontx/other.json index 85bf3c8f3914..522eb795574d 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/other.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/other.json @@ -1,26 +1,1792 @@ [ { + "BriefDescription": "Counts the total number of BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe8", + "EventName": "BTCLEAR.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of BTCLEARS which oc= curs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.SELF_LOCKS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EdgeDetect": "1", + "EventCode": "0x63", + "EventName": "BUS_LOCK.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock issued by other cores.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.BLOCK_CYCLES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock issued by other cores. Counts on a per c= ore basis.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.BLOCK_CYCLES", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.LOCK_CYCLES", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock it issued.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.LOCK_CYCLES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock it issued. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of bus locks a core issued = its self (e.g. lock to UC or Split Lock) and does not include cache locks.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EdgeDetect": "1", + "EventCode": "0x63", + "EventName": "BUS_LOCK.SELF_LOCKS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of bus locks a core issued= its self (e.g. lock to UC or Split Lock) and does not include cache locks.= Counts on a per core basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "C0_STALLS.LOAD_DRAM_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_L2_HIT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "C0_STALLS.LOAD_L2_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_LLC_HIT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "C0_STALLS.LOAD_LLC_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of core cycles during which= interrupts are masked (disabled).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcb", + "EventName": "HW_INTERRUPTS.MASKED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of core cycles during which= there are pending interrupts while interrupts are masked (disabled).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcb", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during whic= h there are pending interrupts while interrupts are masked (disabled). Incr= ements by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending= (which means the APIC is telling the ROB to cause an INTR). This event doe= s not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt = Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR= ) because in these cases the interrupts would be held up in the APIC and w= ould not be pended to the ROB. This event does count when an interrupt is o= nly inhibited by MOV/POP SS state machines or the STI state machine. These = extra inhibits only last for a single instructions and would not be importa= nt.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of hardware interrupts rece= ived by the processor.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcb", + "EventName": "HW_INTERRUPTS.RECEIVED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "203", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that have any type of r= esponse.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and modified data was fo= rwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, but no data was forwarde= d.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and non-modified data wa= s forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000044", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3000000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3001F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8003000000000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and modi= fied data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, but no d= ata was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and non-= modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FW= D", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where no snoop was needed to satisfy the reques= t.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000040", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", - "MSRValue": "0x000000000000010001", + "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were supplied by the L3 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that have any respon= se type.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts all hardware and software prefetches t= hat have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PREFETCHES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10470", + "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", - "MSRValue": "0x000000000000010002", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and modif= ied data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, but no da= ta was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and non-m= odified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where no snoop was needed to satisfy the request= .", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that have any ty= pe of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and modified data= was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010003C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, but no data was f= orwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004003C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and non-modified = data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008003C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002003C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001003C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000100000000000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that have any t= ype of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200000010000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were suppl= ied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201F803C0000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand reads for ownership (RFO) r= equests and software based prefetches for exclusive ownership (PREFETCHW) t= hat have any response type.", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = TOPDOWN_BAD_SPECULATION.FASTNUKE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "This event is deprecated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to frontend bandwidth restricti= ons due to decode, predecode, cisc, and other limitations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8d" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to a latency related stalls inc= luding BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x72" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of consumed retiremen= t slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json b/tools/= perf/pmu-events/arch/x86/tremontx/pipeline.json index 05a8f6a7d9c0..200255c62249 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json @@ -1,111 +1,354 @@ [ { + "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of instructions in w= hich the instruction pointer (IP) of the processor is resteered due to a br= anch instruction and the branch instruction successfully retires. All bran= ch type instructions are accounted for.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of instructions that retir= e. For instructions that consist of multiple uops, this event counts the re= tirement of the last uop of the instruction. The counter continues counting= during hardware interrupts, traps, and inside interrupt handlers. This ev= ent uses fixed counter 0.", - "Counter": "32", - "UMask": "0x1", - "PEBScounters": "32", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of instructions retired. (F= ixed event)" + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xf9" }, { + "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. = This event uses fixed counter 1.", - "Counter": "33", - "UMask": "0x2", - "PEBScounters": "33", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xbf" + }, + { + "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfd" + }, + { + "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of mispredicted bran= ch instructions retired. All branch type instructions are accounted for. = Prediction of the branch target address enables the processor to begin exec= uting instructions before the non-speculative execution path is known. The = branch prediction unit (BPU) predicts the target address based on the instr= uction pointer (IP) of the branch and on the execution path through which e= xecution reached this IP. A branch misprediction occurs when the predict= ion is wrong, and results in discarding all instructions executed in the sp= eculative path and re-fetching from the correct path.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PDIR_COUNTER": "na", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. T= his event uses fixed counter 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)" + "UMask": "0x2" }, { + "BriefDescription": "Counts the number of unhalted core clock cycl= es.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. The core frequency may change from time. This= event is not affected by core frequency changes and at a fixed frequency. = This event uses fixed counter 2.", - "Counter": "34", - "UMask": "0x3", - "PEBScounters": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "Counter": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.CORE_P", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. T= his event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. = This event uses a programmable general purpose performance counter.", - "EventCode": "0x3c", "Counter": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PDIR_COUNTER": "na", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted core clock cycl= es." + "UMask": "0x3" }, { + "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts reference cycles (at TSC frequency) w= hen core is not halted. This event uses a programmable general purpose per= fmon counter.", + "Counter": "0,1,2,3", "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency c= hanges and increments at a fixed frequency that is also used for the Time S= tamp Counter (TSC). This event uses a programmable general purpose performa= nce counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xcd", + "EventName": "CYCLES_DIV_BUSY.ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of cycles the integer divid= er is busy. Does not imply a stall waiting for the divider.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcd", + "EventName": "CYCLES_DIV_BUSY.IDIV", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency." + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { + "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of instructions retir= ed.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a Programmabl= e general purpose perfmon counter. *This event is Precise Event capable: T= he EventingRIP field in the PEBS record is precise to the address of the in= struction which caused the event.", + "Counter": "0,1,2,3", "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of instructions retired." + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { + "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", "CollectPEBSRecord": "2", - "EventCode": "0xc3", "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "1", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003" + }, + { + "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", - "BriefDescription": "Counts all machine clears due to, but not lim= ited to memory ordering, memory disambiguation, SMC, page faults and FP ass= ist." + "UMask": "0x20" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of machine clears due typic= ally to program modifying data (self modifying code) within 1K of a recentl= y fetched code page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all b= ranch types. This event is Precise Event capable. This is an architectural = event.", - "EventCode": "0xc4", "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions reti= red for all branch types." + "SampleAfterValue": "20003", + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Counts the total number of uops retired.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red for all branch types. This event is Precise Event capable. This is an a= rchitectural event.", - "EventCode": "0xc5", "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired." + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Counts the number of integer divide uops reti= red.", "CollectPEBSRecord": "2", - "EventCode": "0xcd", "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.ANY", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MS", "PDIR_COUNTER": "na", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops that are from comp= lex flows issued by the Microcode Sequencer (MS). This includes uops from f= lows due to complex instructions, faults, assists, and inserted flows.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles the floating point divider or i= nteger divider or both are busy. Does not imply a stall waiting for either= divider." + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json index 15376f2cf052..0d342efae154 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json @@ -50,13 +50,79 @@ "Unit": "iMC" }, { - "BriefDescription": "Precharge due to read on page miss, write on = page miss or PGT", + "BriefDescription": "DRAM Activate Count : All Activates", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M_ACT_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "DRAM Activate Count : All Activates : Counts= the number of DRAM Activate commands sent on this channel. Activate comma= nds are issued to open up a page on the DRAM devices so that it can be read= or written to with a CAS. One can calculate the number of Page Misses by = subtracting the number of Page Miss precharges from the number of Activates= .", + "UMask": "0x0B", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of DRAM CAS commands= issued on this channel.", + "UMask": "0x3f", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the= number of refreshes issued.", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", + "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the= number of refreshes issued.", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the= number of refreshes issued.", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Half clockticks for IMC", + "Counter": "FIXED", + "CounterType": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_M_HCLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Half clockticks for IMC", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", - "UMask": "0x1c", + "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", + "UMask": "0x1C", "Unit": "iMC" }, { @@ -66,8 +132,92 @@ "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Precharge due to = page table : Counts the number of DRAM Precharge commands sent on this chan= nel.", + "PublicDescription": "DRAM Precharge commands. : Precharge due to = page table : Counts the number of DRAM Precharge commands sent on this chan= nel. : Prechages from Page Table", "UMask": "0x10", "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the = number of allocations into the Read Pending Queue. This queue is used to s= chedule reads out to the memory controller and to track the requests. Requ= ests allocate into the RPQ soon after they enter the memory controller, and= need credits for an entry in this buffer before being sent from the HA to = the iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the = number of allocations into the Read Pending Queue. This queue is used to s= chedule reads out to the memory controller and to track the requests. Requ= ests allocate into the RPQ soon after they enter the memory controller, and= need credits for an entry in this buffer before being sent from the HA to = the iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates t= he occupancies of the Read Pending Queue each cycle. This can then be used= to calculate both the average occupancy (in conjunction with the number of= cycles not empty) and the average latency (in conjunction with the number = of allocations). The RPQ is used to schedule reads out to the memory contr= oller and to track the requests. Requests allocate into the RPQ soon after= they enter the memory controller, and need credits for an entry in this bu= ffer before being sent from the HA to the iMC. They deallocate after the CA= S command has been issued to memory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates t= he occupancies of the Read Pending Queue each cycle. This can then be used= to calculate both the average occupancy (in conjunction with the number of= cycles not empty) and the average latency (in conjunction with the number = of allocations). The RPQ is used to schedule reads out to the memory contr= oller and to track the requests. Requests allocate into the RPQ soon after= they enter the memory controller, and need credits for an entry in this bu= ffer before being sent from the HA to the iMC. They deallocate after the CA= S command has been issued to memory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations : Counts the= number of allocations into the Write Pending Queue. This can then be used= to calculate the average queuing latency (in conjunction with the WPQ occu= pancy count). The WPQ is used to schedule write out to the memory controll= er and to track the writes. Requests allocate into the WPQ soon after they= enter the memory controller, and need credits for an entry in this buffer = before being sent from the CHA to the iMC. They deallocate after being iss= ued to DRAM. Write requests themselves are able to complete (from the pers= pective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations : Counts the= number of allocations into the Write Pending Queue. This can then be used= to calculate the average queuing latency (in conjunction with the WPQ occu= pancy count). The WPQ is used to schedule write out to the memory controll= er and to track the writes. Requests allocate into the WPQ soon after they= enter the memory controller, and need credits for an entry in this buffer = before being sent from the CHA to the iMC. They deallocate after being iss= ued to DRAM. Write requests themselves are able to complete (from the pers= pective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates = the occupancies of the Write Pending Queue each cycle. This can then be us= ed to calculate both the average queue occupancy (in conjunction with the n= umber of cycles not empty) and the average latency (in conjunction with the= number of allocations). The WPQ is used to schedule write out to the memo= ry controller and to track the writes. Requests allocate into the WPQ soon= after they enter the memory controller, and need credits for an entry in t= his buffer before being sent from the HA to the iMC. They deallocate after= being issued to DRAM. Write requests themselves are able to complete (fro= m the perspective of the rest of the system) as soon they have posted to th= e iMC. This is not to be confused with actually performing the write to DR= AM. Therefore, the average latency for this queue is actually not useful f= or deconstruction intermediate write latencies. So, we provide filtering b= ased on if the request has posted or not. By using the not posted filter, = we can track how long writes spent in the iMC before completions were sent = to the HA. The posted filter, on the other hand, provides information abou= t how much queueing is actually happenning in the iMC for writes before the= y are actually issued to memory. High average occupancies will generally c= oincide with high write major mode counts.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates = the occupancies of the Write Pending Queue each cycle. This can then be us= ed to calculate both the average queue occupancy (in conjunction with the n= umber of cycles not empty) and the average latency (in conjunction with the= number of allocations). The WPQ is used to schedule write out to the memo= ry controller and to track the writes. Requests allocate into the WPQ soon= after they enter the memory controller, and need credits for an entry in t= his buffer before being sent from the HA to the iMC. They deallocate after= being issued to DRAM. Write requests themselves are able to complete (fro= m the perspective of the rest of the system) as soon they have posted to th= e iMC. This is not to be confused with actually performing the write to DR= AM. Therefore, the average latency for this queue is actually not useful f= or deconstruction intermediate write latencies. So, we provide filtering b= ased on if the request has posted or not. By using the not posted filter, = we can track how long writes spent in the iMC before completions were sent = to the HA. The posted filter, on the other hand, provides information abou= t how much queueing is actually happenning in the iMC for writes before the= y are actually issued to memory. High average occupancies will generally c= oincide with high write major mode counts.", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/tremontx/uncore-other.json index 6deff1fe89e3..4e1a1c6faa63 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json @@ -69,6 +69,26 @@ "UMaskExt": "0xC001FE", "Unit": "CHA" }, + { + "BriefDescription": "read requests from home agent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from home agent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x0c", + "Unit": "CHA" + }, { "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", "Counter": "0,1", @@ -180,215 +200,1938 @@ "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; CRd misses from local IA", + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "CMS Clockticks", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read = is issued to any of the memory controller channels from the CHA.", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Lin= e Non-ISOCH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full = line write is issued from the CHA to any of the memory controller channels.= ", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1BC1FF", + "UMaskExt": "0x1BC1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : All Lines Victimized", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : All Lines Victimized : Co= unts the number of lines that were victimized on a fill. This can be filte= red by the state that the line was in.", + "UMask": "0x0F", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking exclusive lines in the cores? cache.? Snoop filter capacity= evictions occur when the snoop filter is full and evicts an existing entry= to track a new entry.? Does not count clean evictions such as when a core?= s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking modified lines in the cores? cache.? Snoop filter capacity = evictions occur when the snoop filter is full and evicts an existing entry = to track a new entry.? Does not count clean evictions such as when a core?s= cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking shared lines in the cores? cache.? Snoop filter capacity ev= ictions occur when the snoop filter is full and evicts an existing entry to= track a new entry.? Does not count clean evictions such as when a core?s c= ache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores : C= ounts the number of entries successfuly inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", + "UMask": "0xC001FF01", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores := Counts the number of entries successfuly inserted into the TOR that match = qualifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", + "UMask": "0xC8C7FF01", + "UMaskExt": "0xC8C7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Coun= ts the number of entries successfuly inserted into the TOR that match quali= fications specified by the subevent. Does not include addressless request= s such as locks and interrupts.", + "UMask": "0xC80FFF01", + "UMaskExt": "0xC80FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : = Counts the number of entries successfuly inserted into the TOR that match q= ualifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", + "UMask": "0xC827FF01", + "UMaskExt": "0xC827FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es : Counts the number of entries successfuly inserted into the TOR that ma= tch qualifications specified by the subevent. Does not include addressles= s requests such as locks and interrupts.", + "UMask": "0xC8A7FF01", + "UMaskExt": "0xC8A7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that= Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Hit the LLC : Counts the number of entries successfuly inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xC001FD01", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that H= it the LLC : Counts the number of entries successfuly inserted into the TOR= that match qualifications specified by the subevent. Does not include ad= dressless requests such as locks and interrupts.", + "UMask": "0xC80FFD01", + "UMaskExt": "0xC80FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat hit the LLC : Counts the number of entries successfuly inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xC88FFD01", + "UMaskExt": "0xC88FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores tha= t hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores th= at hit the LLC : Counts the number of entries successfuly inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0xC827FD01", + "UMaskExt": "0xC827FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es that hit the LLC : Counts the number of entries successfuly inserted int= o the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xC8A7FD01", + "UMaskExt": "0xC8A7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that H= it the LLC : Counts the number of entries successfuly inserted into the TOR= that match qualifications specified by the subevent. Does not include ad= dressless requests such as locks and interrupts.", + "UMask": "0xC807FD01", + "UMaskExt": "0xC807FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Hit the LLC : Counts the number of entries successfuly inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xC887FD01", + "UMaskExt": "0xC887FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read from local IA that mi= sses in the snoop filter", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfuly inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xC80FFE01", "UMaskExt": "0xC80FFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC : Counts the number of entries successfuly inserted into= the TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", "UMask": "0xC88FFE01", "UMaskExt": "0xC88FFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that= missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t misses in the snoop filter", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores tha= t missed the LLC : Counts the number of entries successfuly inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", "UMask": "0xC827FE01", "UMaskExt": "0xC827FE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local I= A", + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that misses in the snoop filter", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es that missed the LLC : Counts the number of entries successfuly inserted = into the TOR that match qualifications specified by the subevent. Does no= t include addressless requests such as locks and interrupts.", "UMask": "0xC8A7FE01", "UMaskExt": "0xC8A7FE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; RFO misses from local IA", + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", + "UMask": "0xc867fe01", + "UMaskExt": "0xc867fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", + "UMask": "0xc86ffe01", + "UMaskExt": "0xc86ffe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership from local I= A that misses in the snoop filter", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC : Counts the number of entries successfuly inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xC807FE01", "UMaskExt": "0xC807FE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; RFO pref misses from local IA", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch fro= m local IA that misses in the snoop filter", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Missed the LLC : Counts the number of entries successfuly inserted into= the TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", "UMask": "0xC887FE01", "UMaskExt": "0xC887FE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that= Missed LLC : Counts the number of entries successfuly inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0xC877DE01", + "UMaskExt": "0xC877DE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that = Missed the LLC : Counts the number of entries successfuly inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xC86FFE01", "UMaskExt": "0xC86FFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that = Missed the LLC : Counts the number of entries successfuly inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xC867FE01", "UMaskExt": "0xC867FE", "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_IIO_CLOCKTICKS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", - "PublicDescription": "Clockticks of the integrated IO (IIO) traffi= c controller", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that M= issed LLC : Counts the number of entries successfuly inserted into the TOR = that match qualifications specified by the subevent. Does not include add= ressless requests such as locks and interrupts.", + "UMask": "0xC87FDE01", + "UMaskExt": "0xC87FDE", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x16 = card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is = plugged in to slot 0", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Coun= ts the number of entries successfuly inserted into the TOR that match quali= fications specified by the subevent. Does not include addressless request= s such as locks and interrupts.", + "UMask": "0xC807FF01", + "UMaskExt": "0xC807FF", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 1", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores := Counts the number of entries successfuly inserted into the TOR that match = qualifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", + "UMask": "0xC887FF01", + "UMaskExt": "0xC887FF", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : All requests from IO Devices", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x8 c= ard plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : All requests from IO Devices := Counts the number of entries successfuly inserted into the TOR that match = qualifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", + "UMask": "0xC001FF04", + "UMaskExt": "0xC001FF", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : All requests from IO Devices th= at hit the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 3", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat hit the LLC : Counts the number of entries successfuly inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xC001FD04", + "UMaskExt": "0xC001FD", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= Hit the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x16 ca= rd plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is pl= ugged in to slot 0", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC : Counts the number of entries successfuly inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xCC43FD04", + "UMaskExt": "0xCC43FD", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 1", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that hit the LLC : Counts the number = of entries successfuly inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts.", + "UMask": "0xCD43FD04", + "UMaskExt": "0xCD43FD", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that hit the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x8 car= d plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that hit the LLC : Counts the number of entries successfuly inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FD04", + "UMaskExt": "0xC8F3FD", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : C= ounts the number of entries successfuly inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", + "UMask": "0xCC43FF04", + "UMaskExt": "0xCC43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices : Counts the number of entries succes= sfuly inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xCD43FF04", + "UMaskExt": "0xCD43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices th= at missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat missed the LLC : Counts the number of entries successfuly inserted into= the TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", + "UMask": "0xC001FE04", + "UMaskExt": "0xC001FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t missed the LLC : Counts the number of entries successfuly inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xCC43FE04", + "UMaskExt": "0xCC43FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC : Counts the numb= er of entries successfuly inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", + "UMask": "0xCD43FE04", + "UMaskExt": "0xCD43FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that missed the LLC : Counts the number of entries successfuly inserted in= to the TOR that match qualifications specified by the subevent. Does not = include addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FE04", + "UMaskExt": "0xC8F3FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= : Counts the number of entries successfuly inserted into the TOR that matc= h qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", + "UMask": "0xC8F3FF04", + "UMaskExt": "0xC8F3FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xC001FF01", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : Fo= r each cycle, this event accumulates the number of valid entries in the TOR= that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xC80FFF01", + "UMaskExt": "0xC80FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = : For each cycle, this event accumulates the number of valid entries in the= TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xC827FF01", + "UMaskExt": "0xC827FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores : For each cycle, this event accumulates the number of valid entries i= n the TOR that match qualifications specified by the subevent. Does not= include addressless requests such as locks and interrupts.", + "UMask": "0xC8A7FF01", + "UMaskExt": "0xC8A7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Hit the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FD01", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores t= hat hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = that hit the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FD01", + "UMaskExt": "0xC827FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that hit the LLC : For each cycle, this event accumulates the number o= f valid entries in the TOR that match qualifications specified by the subev= ent. Does not include addressless requests such as locks and interrupts= .", + "UMask": "0xC8A7FD01", + "UMaskExt": "0xC8A7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FE01", + "UMaskExt": "0xC001FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Missed the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC80FFE01", + "UMaskExt": "0xC80FFE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores th= at missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FE01", + "UMaskExt": "0xC827FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC807FE01", + "UMaskExt": "0xC807FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : Fo= r each cycle, this event accumulates the number of valid entries in the TOR= that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xC807FF01", + "UMaskExt": "0xC807FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xC001FF04", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices = that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= that hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FD04", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices = that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= that missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xC001FE04", + "UMaskExt": "0xC001FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC : For each cycle, this event accumulates the number = of valid entries in the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupt= s.", + "UMask": "0xc8f3fe04", + "UMaskExt": "0xc8f3fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FF04", + "UMaskExt": "0xC8F3FF", + "Unit": "CHA" + }, + { + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks of the integrated IO (IIO) traffi= c controller", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for IIO = clocktick", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xff", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 0-7", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 1", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 2", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 3", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 3", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 4", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 5", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 6", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugge= d in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged = in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugge= d in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged = in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or= x4 card is plugged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 3", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or= x4 card is plugged in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 7", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugge= d in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged = in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugge= d in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged = in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x16 = card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 c= ard is plugged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x8 c= ard plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x16 ca= rd plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 car= d is plugged in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x8 car= d plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 3", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 7", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : = All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die := All : Counts full PCIe requests before they're broken into a series of cac= he-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x16 card plu= gged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is p= lugged in to slot 0", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x8 card plug= ged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 3", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x16 card plu= gged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is p= lugged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x8 card plug= ged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x16 card plugg= ed in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plu= gged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x8 card plugge= d in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 3", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x16 card plugg= ed in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plu= gged in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x8 card plugge= d in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 7", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lan= e 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot = 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lan= e 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot = 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x16 card plugge= d in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plug= ged in to slot 0", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x8 card plugged= in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 3", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x16 card plugge= d in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plug= ged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x8 card plugged= in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x16 card plugged = in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugge= d in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x8 card plugged i= n to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 3", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x16 card plugged = in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugge= d in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x8 card plugged i= n to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 7", "UMask": "0x01", "Unit": "IIO" }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and writ= e requests to coherent memory. This is effectively the sum of read occupan= cy and write occupancy.", + "UMask": "0x04", + "Unit": "IRP" + }, { "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", "Counter": "0,1", @@ -399,6 +2142,112 @@ "PublicDescription": "Clockticks of the IO coherency tracker (IRP)= ", "Unit": "IRP" }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to th= e mesh with the intention of writing a full cacheline to coherent memory, w= ithout a RFO. PCIITOM is a speculative Invalidate to Modified command that= requests ownership of the cacheline and does not move data from the mesh t= o IRP cache.", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : WbMtoI", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of= coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "PublicDescription": "FAF RF full", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, re= ceived by the IRP and inserted into the Fire and Forget queue (FAF), a queu= e used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) q= ueue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "PublicDescription": "FAF allocation -- sent to ADQ", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "PublicDescription": ": All Inserts Inbound (p2p + faf + cset)", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop p= ulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to cohere= nt memory, received by the IRP resulting in write ownership requests issued= by IRP to the mesh.", + "UMask": "0x08", + "Unit": "IRP" + }, { "BriefDescription": "Clockticks of the mesh to memory (M2M)", "Counter": "0,1,2,3", @@ -408,6 +2257,16 @@ "PublicDescription": "Clockticks of the mesh to memory (M2M)", "Unit": "M2M" }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "CMS Clockticks", + "Unit": "M2M" + }, { "BriefDescription": "Clockticks of the mesh to PCI (M2P)", "Counter": "0,1,2,3", @@ -418,10 +2277,20 @@ "PublicDescription": "Clockticks of the mesh to PCI (M2P)", "Unit": "M2PCIe" }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "CMS Clockticks", + "Unit": "M2PCIe" + }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", "Counter": "FIXED", - "CounterType": "PGMABLE", + "CounterType": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json index 93e407a0f645..cb0784562bd1 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json @@ -1,86 +1,354 @@ [ { + "BriefDescription": "Counts the number of page walks due to loads = that miss the PDE (Page Directory Entry) cache.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 4K pages. The page walks can end with or wi= thout a page fault.", + "Counter": "0,1,2,3", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to loads that did not start a page walk. Account f= or all pages sizes. Will result in a DTLB write from STLB.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. = Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 4K page." + "UMask": "0x2" }, { + "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for loads every cycle.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 2M or 4M pages. The page walks can end with= or without a page fault.", + "Counter": "0,1,2,3", "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for loads every cycle. A page walk is outst= anding from start till PMH becomes idle again (ready to serve next walk). I= ncludes EPT-walk intervals.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of page walks due to stores= that miss the PDE (Page Directory Entry) cache.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts the number of page walks due to stors= e that miss the PDE (Page Directory Entry) cache.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Account = for all pages sizes. Will result in a DTLB write from STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 2M or 4M page." + "UMask": "0xe" }, { + "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that = page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page." + "UMask": "0x2" }, { + "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M or 4M pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A page walk is outs= tanding from start till PMH becomes idle again (ready to serve next walk). = Includes EPT-walk intervals.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory = Entry hits.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x4f", + "EventName": "EPT.EPDE_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts the number of Extended Page Directory= Entry hits. The Extended Page Directory cache is used by Virtual Machine = operating systems while the guest operating systems use the standard TLB ca= ches.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory = Entry misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.EPDE_MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number Extended Page Directory En= try misses. The Extended Page Directory cache is used by Virtual Machine o= perating systems while the guest operating systems use the standard TLB cac= hes.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M or 4M page." + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry hits.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and new translation was filled into the ITLB. The event is specula= tive in nature, but will not count translations (page walks) that are begun= and not finished, or translations that are finished but not filled into th= e ITLB.", - "EventCode": "0x81", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x4f", + "EventName": "EPT.EPDPE_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry hits. The Extended Page Directory cache is used by Virtual Mac= hine operating systems while the guest operating systems use the standard T= LB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.EPDPE_MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry misses. The Extended Page Directory cache is used by Virtual M= achine operating systems while the guest operating systems use the standard= TLB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks outstanding f= or an Extended Page table walk including GTLB hits per cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = for an Extended Page table walk including GTLB hits per cycle. The Extende= d Page Directory cache is used by Virtual Machine operating systems while t= he guest operating systems use the standard TLB caches.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x81", "EventName": "ITLB.FILLS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and a new translation was filled into the ITLB. The event is specul= ative in nature, but will not count translations (page walks) that are begu= n and not finished, or translations that are finished but not filled into t= he ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB." + "UMask": "0x4" }, { + "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.PDE_CACHE_MISS", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will results in a DTLB write from STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 4K page." + "UMask": "0x20" }, { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 2M or 4M pages. The page walks can end with or without a page fault.", + "Counter": "0,1,2,3", "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 1G page.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes pag= e walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 2M or 4M page." + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for instruction fetches every cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for instruction fetches every cycle. A page= walk is outstanding from start till PMH becomes idle again (ready to serve= next walk).", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of memory retired ops that = missed in the second level TLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x13" + }, + { + "BriefDescription": "Counts the number of load ops retired that mi= ss in the second Level TLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x11" + }, + { + "BriefDescription": "Counts the number of store ops retired that m= iss in the second level TLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x12" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog