From nobody Mon Jun 29 23:23:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0195C433EF for ; Mon, 31 Jan 2022 23:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235911AbiAaXBV (ORCPT ); Mon, 31 Jan 2022 18:01:21 -0500 Received: from mga03.intel.com ([134.134.136.65]:53702 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235389AbiAaXBT (ORCPT ); Mon, 31 Jan 2022 18:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643670079; x=1675206079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=quHtX6b2lWq0OCMDIPUYUvGCuDxHqCPbaufrchm5fIA=; b=JYPlpCiosiRymR2nVfeijrN8GsXhw6f+iUp2jCvpNOHAFhHz5cPBshTH kTyksJmx6ekJvHKCUk4cZiNnZt9AJrPbBLOMX0hqa/zpPUJim3/gfL+L+ DgYlKqJ2qGukiDwdpwK2rUw4ZBNnRRtgtAfqcwQAS5Rl1kE+QGWUWhrYu a6Y2gzmpufTnRFn2n+jM7Nd2ebPNB3fR8C0A5G1EHgIYZal2Rx15Ojgvw //qNN/j9TvUU7pvQXy+YGxoC0fkKuj5L+5E67oiaV19wZocM31WLPvKU/ W2bhOkL18vZzDYr8WAMVewQBl8ZanjYJHTCs5jJbqCSE7dRBSmvrARw60 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10244"; a="247521224" X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="247521224" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="522831337" Received: from agluck-desk2.sc.intel.com ([10.3.52.146]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 From: Tony Luck To: Borislav Petkov Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Smita Koralahalli Channabasappa , Wei Huang , Tom Lendacky , patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 1/5] x86/cpu: Merge Intel and AMD ppin_init() functions Date: Mon, 31 Jan 2022 15:01:07 -0800 Message-Id: <20220131230111.2004669-2-tony.luck@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220131230111.2004669-1-tony.luck@intel.com> References: <20220121174743.1875294-1-tony.luck@intel.com> <20220131230111.2004669-1-tony.luck@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The code to decide whether a system supports the PPIN (Protected Processor Inventory Number) MSR was cloned from the Intel implementation. Apart from the X86_FEATURE bit and the MSR numbers it is identical. Merge the two functions into common x86 code, but use x86_match_cpu() instead of the switch (c->x86_model) that was used by the old Intel code. No functional change. Signed-off-by: Tony Luck --- arch/x86/kernel/cpu/amd.c | 30 ------------- arch/x86/kernel/cpu/common.c | 74 +++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/intel.c | 42 ------------------- 3 files changed, 74 insertions(+), 72 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 4edb6f0f628c..bad0fa4c1779 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -394,35 +394,6 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->phys_proc_id; } =20 -static void amd_detect_ppin(struct cpuinfo_x86 *c) -{ - unsigned long long val; - - if (!cpu_has(c, X86_FEATURE_AMD_PPIN)) - return; - - /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */ - if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val)) - goto clear_ppin; - - /* PPIN is locked in disabled mode, clear feature bit */ - if ((val & 3UL) =3D=3D 1UL) - goto clear_ppin; - - /* If PPIN is disabled, try to enable it */ - if (!(val & 2UL)) { - wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL); - rdmsrl_safe(MSR_AMD_PPIN_CTL, &val); - } - - /* If PPIN_EN bit is 1, return from here; otherwise fall through */ - if (val & 2UL) - return; - -clear_ppin: - clear_cpu_cap(c, X86_FEATURE_AMD_PPIN); -} - u32 amd_get_nodes_per_socket(void) { return nodes_per_socket; @@ -947,7 +918,6 @@ static void init_amd(struct cpuinfo_x86 *c) amd_detect_cmp(c); amd_get_topology(c); srat_detect_node(c); - amd_detect_ppin(c); =20 init_amd_cacheinfo(c); =20 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 7b8382c11788..b0bd8a6b5beb 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -88,6 +88,78 @@ EXPORT_SYMBOL_GPL(get_llc_id); /* L2 cache ID of each logical CPU */ DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) =3D BAD_APICID; =20 +static struct ppin_info { + int feature; + int msr_ppin_ctl; +} ppin_info[] =3D { + [X86_VENDOR_INTEL] =3D { + .feature =3D X86_FEATURE_INTEL_PPIN, + .msr_ppin_ctl =3D MSR_PPIN_CTL, + }, + [X86_VENDOR_AMD] =3D { + .feature =3D X86_FEATURE_AMD_PPIN, + .msr_ppin_ctl =3D MSR_AMD_PPIN_CTL, + }, +}; + +static const struct x86_cpu_id ppin_cpuids[] =3D { + X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), + + /* Legacy models without CPUID enumeration */ + X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]= ), + X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), + X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), + + {} +}; + +static void ppin_init(struct cpuinfo_x86 *c) +{ + const struct x86_cpu_id *id; + unsigned long long val; + struct ppin_info *info; + + id =3D x86_match_cpu(ppin_cpuids); + if (!id) + return; + + /* + * Testing the presence of the MSR is not enough. Need to check + * that the PPIN_CTL allows reading of the PPIN. + */ + info =3D (struct ppin_info *)id->driver_data; + + if (rdmsrl_safe(info->msr_ppin_ctl, &val)) + goto clear_ppin; + + if ((val & 3UL) =3D=3D 1UL) { + /* PPIN locked in disabled mode */ + goto clear_ppin; + } + + /* If PPIN is disabled, try to enable */ + if (!(val & 2UL)) { + wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); + rdmsrl_safe(info->msr_ppin_ctl, &val); + } + + /* Is the enable bit set? */ + if (val & 2UL) { + set_cpu_cap(c, info->feature); + return; + } + +clear_ppin: + clear_cpu_cap(c, info->feature); +} + /* correctly size the local cpu masks */ void __init setup_cpu_local_masks(void) { @@ -1655,6 +1727,8 @@ static void identify_cpu(struct cpuinfo_x86 *c) c->x86_capability[i] |=3D boot_cpu_data.x86_capability[i]; } =20 + ppin_init(c); + /* Init Machine Check Exception if available. */ mcheck_cpu_init(c); =20 diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index baafbb37be67..95275a5e57e0 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -470,47 +470,6 @@ void intel_clear_lmce(void) wrmsrl(MSR_IA32_MCG_EXT_CTL, val); } =20 -static void intel_ppin_init(struct cpuinfo_x86 *c) -{ - unsigned long long val; - - /* - * Even if testing the presence of the MSR would be enough, we don't - * want to risk the situation where other models reuse this MSR for - * other purposes. - */ - switch (c->x86_model) { - case INTEL_FAM6_IVYBRIDGE_X: - case INTEL_FAM6_HASWELL_X: - case INTEL_FAM6_BROADWELL_D: - case INTEL_FAM6_BROADWELL_X: - case INTEL_FAM6_SKYLAKE_X: - case INTEL_FAM6_ICELAKE_X: - case INTEL_FAM6_ICELAKE_D: - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_XEON_PHI_KNL: - case INTEL_FAM6_XEON_PHI_KNM: - - if (rdmsrl_safe(MSR_PPIN_CTL, &val)) - return; - - if ((val & 3UL) =3D=3D 1UL) { - /* PPIN locked in disabled mode */ - return; - } - - /* If PPIN is disabled, try to enable */ - if (!(val & 2UL)) { - wrmsrl_safe(MSR_PPIN_CTL, val | 2UL); - rdmsrl_safe(MSR_PPIN_CTL, &val); - } - - /* Is the enable bit set? */ - if (val & 2UL) - set_cpu_cap(c, X86_FEATURE_INTEL_PPIN); - } -} - /* * Enable additional error logs from the integrated * memory controller on processors that support this. @@ -535,7 +494,6 @@ void mce_intel_feature_init(struct cpuinfo_x86 *c) { intel_init_cmci(); intel_init_lmce(); - intel_ppin_init(c); intel_imc_init(c); } =20 --=20 2.31.1 From nobody Mon Jun 29 23:23:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5175AC433F5 for ; Mon, 31 Jan 2022 23:01:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236107AbiAaXB0 (ORCPT ); Mon, 31 Jan 2022 18:01:26 -0500 Received: from mga03.intel.com ([134.134.136.65]:53704 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235529AbiAaXBT (ORCPT ); Mon, 31 Jan 2022 18:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643670079; x=1675206079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D5IxgMQQPsxXkTofIEcbAivuT+zDal3E4DIqU1/Lh7U=; b=iCIgDmkTlB8DyrMbKKp47u8joncKrkhUox8ApaIJECV1wswJfjN81DCA qQaZGNwEcTDY6W7Yl50rI25b35MNj+fx3MrsAC98YH/WIAj9+kdJXbtmg cmPoY5QhI+ScOYY0gC0a3brxRaOKDfp7/oCY+fccTX31WmGeSXTbFfK6t Cyljs9vCip+boB23GrSx9nQuMHPeLcjO7tGF0NKk2JyqCNNQjagm62fug r4PCmhrrKS6pJMrYzYnGHmXGuKlDlpUzV1dIsgbA/jVQpraGzXDLYsUvD WP6ipu+mzeC/JWsU9vv6lWgp/av3PMptrX1Op2WnSiKt7n0h0nltBSETy A==; X-IronPort-AV: E=McAfee;i="6200,9189,10244"; a="247521225" X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="247521225" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="522831341" Received: from agluck-desk2.sc.intel.com ([10.3.52.146]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 From: Tony Luck To: Borislav Petkov Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Smita Koralahalli Channabasappa , Wei Huang , Tom Lendacky , patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 2/5] x86/cpu: X86_FEATURE_INTEL_PPIN finally has a CPUID bit Date: Mon, 31 Jan 2022 15:01:08 -0800 Message-Id: <20220131230111.2004669-3-tony.luck@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220131230111.2004669-1-tony.luck@intel.com> References: <20220121174743.1875294-1-tony.luck@intel.com> <20220131230111.2004669-1-tony.luck@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" After nine generations of adding to model specific list of CPUs that support PPIN (Protected Processor Inventory Number) Intel allocated a CPUID bit to enumerate the MSRs. CPUID(EAX=3D7, ECX=3D1).EBX bit 0 enumerates presence of MSR_PPIN_CTL and MSR_PPIN. Add it to the "scattered" CPUID bits and add an entry to the ppin_cpuids[] x86_match_cpu() array to catch Intel CPUs that implement it. Signed-off-by: Tony Luck --- arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index b0bd8a6b5beb..0681c69a1f09 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -104,6 +104,7 @@ static struct ppin_info { =20 static const struct x86_cpu_id ppin_cpuids[] =3D { X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), + X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), =20 /* Legacy models without CPUID enumeration */ X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 21d1f062895a..4143b1e4c5c6 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -26,6 +26,7 @@ struct cpuid_bit { static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, + { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, --=20 2.31.1 From nobody Mon Jun 29 23:23:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EACA8C433F5 for ; Mon, 31 Jan 2022 23:01:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236489AbiAaXB3 (ORCPT ); Mon, 31 Jan 2022 18:01:29 -0500 Received: from mga03.intel.com ([134.134.136.65]:53702 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235638AbiAaXBT (ORCPT ); Mon, 31 Jan 2022 18:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643670079; x=1675206079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+9Xepbi4V3tZGWxD6uy9Ve7FiBq+R8pLyM5H5ykMw4U=; b=bHgHnT3/GoPK1VOdgDg4GFFCR/Gab90qT4sUyOG8v1UzoWXhgKa6Pcuo LG/GBMb1I+tNb7qz02wbSIef0Z/eHMIGdtQqO0v/AcFpeD2sgNvtltAS6 Zdjgd8zrPUfgozjNCnRIrsACpGC/ucD8YQ2la2vcoktdxJwV3fX9MILRb XO/rI+GAqe1dslneKsSXt3EaLHrUHvKC0yba6aJ5RSTD7AG14Gu7X/+Ll zxOdVFN1uAX1dx/0P7rW+AcChXzO87iHVywNM2c8m836GO6NVAUR2mgU5 0CfEDT6Tu2glnbVXTLMFLyba8eITDG9frjTPyHDIpxhdUiSAEtFgBQHwP w==; X-IronPort-AV: E=McAfee;i="6200,9189,10244"; a="247521228" X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="247521228" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="522831344" Received: from agluck-desk2.sc.intel.com ([10.3.52.146]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 From: Tony Luck To: Borislav Petkov Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Smita Koralahalli Channabasappa , Wei Huang , Tom Lendacky , patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 3/5] x86/cpu: Read/save PPIN MSR during initialization Date: Mon, 31 Jan 2022 15:01:09 -0800 Message-Id: <20220131230111.2004669-4-tony.luck@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220131230111.2004669-1-tony.luck@intel.com> References: <20220121174743.1875294-1-tony.luck@intel.com> <20220131230111.2004669-1-tony.luck@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently the PPIN (Protected Processor Inventory Number) MSR is read by every CPU that processes a machine check, CMCI, or just polls machine check banks from a periodic timer. This is not a "fast" MSR, so this adds to overhead of processing errors. Add a new "ppin" field to the cpuinfo_x86 structure. Read and save the PPIN during initialization. Use this copy in mce_setup() instead of reading the MSR. Signed-off-by: Tony Luck --- arch/x86/include/asm/processor.h | 2 ++ arch/x86/kernel/cpu/common.c | 4 ++++ arch/x86/kernel/cpu/mce/core.c | 7 +------ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 2c5f12ae7d04..a87e7c33d5ac 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -119,6 +119,8 @@ struct cpuinfo_x86 { int x86_cache_mbm_width_offset; int x86_power; unsigned long loops_per_jiffy; + /* protected processor identification number */ + u64 ppin; /* cpuid returned max cores value: */ u16 x86_max_cores; u16 apicid; diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0681c69a1f09..64deb7727d00 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -91,14 +91,17 @@ DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) =3D BAD_API= CID; static struct ppin_info { int feature; int msr_ppin_ctl; + int msr_ppin; } ppin_info[] =3D { [X86_VENDOR_INTEL] =3D { .feature =3D X86_FEATURE_INTEL_PPIN, .msr_ppin_ctl =3D MSR_PPIN_CTL, + .msr_ppin =3D MSR_PPIN }, [X86_VENDOR_AMD] =3D { .feature =3D X86_FEATURE_AMD_PPIN, .msr_ppin_ctl =3D MSR_AMD_PPIN_CTL, + .msr_ppin =3D MSR_AMD_PPIN }, }; =20 @@ -153,6 +156,7 @@ static void ppin_init(struct cpuinfo_x86 *c) =20 /* Is the enable bit set? */ if (val & 2UL) { + c->ppin =3D __rdmsr(info->msr_ppin); set_cpu_cap(c, info->feature); return; } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 5818b837fd4d..4f1e825033ce 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -138,12 +138,7 @@ void mce_setup(struct mce *m) m->socketid =3D cpu_data(m->extcpu).phys_proc_id; m->apicid =3D cpu_data(m->extcpu).initial_apicid; m->mcgcap =3D __rdmsr(MSR_IA32_MCG_CAP); - - if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) - m->ppin =3D __rdmsr(MSR_PPIN); - else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) - m->ppin =3D __rdmsr(MSR_AMD_PPIN); - + m->ppin =3D cpu_data(m->extcpu).ppin; m->microcode =3D boot_cpu_data.microcode; } =20 --=20 2.31.1 From nobody Mon Jun 29 23:23:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C318BC433F5 for ; Mon, 31 Jan 2022 23:01:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236372AbiAaXBd (ORCPT ); Mon, 31 Jan 2022 18:01:33 -0500 Received: from mga03.intel.com ([134.134.136.65]:53702 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235774AbiAaXBT (ORCPT ); Mon, 31 Jan 2022 18:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643670079; x=1675206079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IPbq71KTo4yhzvGZvTZl4Fs2bjq1kiEYwJBMLRbd8X0=; b=gA+nS1kcJEx0K+IDHNLIL0FV6ddXyXhmiK9/XeBR9zDEvQqLHAMQoMSS mvIpZVb0hWbGF+vOGTvArVhxelcyFYFtrhoUFEGQdAGmD1zk7lpifVyy5 xVyy7KHQIawJMnMCYwIgUAqZjrKbYAYSSrpavg6HeHGGiNeOMQxl+PuWj ljOiJWVyyYXtLvA7HDXdhXpqWf+R/pAskZO/p1fOPNtivI6JWhZpF25W2 LtYNBuNX/lRErVPAh5YlpkcWLRFfnNsijCOKfJa9LFjMfrjRW7+lwVXjr enD9hFPfjUfznKVarE2KwzPEOJYF1/7+JCfYfl2H+NP3ydD6PVegkTJGa A==; X-IronPort-AV: E=McAfee;i="6200,9189,10244"; a="247521231" X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="247521231" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="522831347" Received: from agluck-desk2.sc.intel.com ([10.3.52.146]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 From: Tony Luck To: Borislav Petkov Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Smita Koralahalli Channabasappa , Wei Huang , Tom Lendacky , patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 4/5] topology/sysfs: Add format parameter to macro defining "show" functions for proc Date: Mon, 31 Jan 2022 15:01:10 -0800 Message-Id: <20220131230111.2004669-5-tony.luck@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220131230111.2004669-1-tony.luck@intel.com> References: <20220121174743.1875294-1-tony.luck@intel.com> <20220131230111.2004669-1-tony.luck@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the simple (non-mask and non-list files in /sys/devices/system/cpu/cpu0/topology/ are currently printed as decimal integers. Refactor the macro that generates the "show" functions to take a format parameter to allow future files to display in other formats. No functional change. Acked-by: Greg Kroah-Hartman Signed-off-by: Tony Luck --- drivers/base/topology.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/base/topology.c b/drivers/base/topology.c index fc24e89f9592..044f3664f8f2 100644 --- a/drivers/base/topology.c +++ b/drivers/base/topology.c @@ -14,11 +14,11 @@ #include #include =20 -#define define_id_show_func(name) \ +#define define_id_show_func(name, fmt) \ static ssize_t name##_show(struct device *dev, \ struct device_attribute *attr, char *buf) \ { \ - return sysfs_emit(buf, "%d\n", topology_##name(dev->id)); \ + return sysfs_emit(buf, fmt "\n", topology_##name(dev->id)); \ } =20 #define define_siblings_read_func(name, mask) \ @@ -42,20 +42,20 @@ static ssize_t name##_list_read(struct file *file, stru= ct kobject *kobj, \ off, count); \ } =20 -define_id_show_func(physical_package_id); +define_id_show_func(physical_package_id, "%d"); static DEVICE_ATTR_RO(physical_package_id); =20 #ifdef TOPOLOGY_DIE_SYSFS -define_id_show_func(die_id); +define_id_show_func(die_id, "%d"); static DEVICE_ATTR_RO(die_id); #endif =20 #ifdef TOPOLOGY_CLUSTER_SYSFS -define_id_show_func(cluster_id); +define_id_show_func(cluster_id, "%d"); static DEVICE_ATTR_RO(cluster_id); #endif =20 -define_id_show_func(core_id); +define_id_show_func(core_id, "%d"); static DEVICE_ATTR_RO(core_id); =20 define_siblings_read_func(thread_siblings, sibling_cpumask); @@ -87,7 +87,7 @@ static BIN_ATTR_RO(package_cpus, 0); static BIN_ATTR_RO(package_cpus_list, 0); =20 #ifdef TOPOLOGY_BOOK_SYSFS -define_id_show_func(book_id); +define_id_show_func(book_id, "%d"); static DEVICE_ATTR_RO(book_id); define_siblings_read_func(book_siblings, book_cpumask); static BIN_ATTR_RO(book_siblings, 0); @@ -95,7 +95,7 @@ static BIN_ATTR_RO(book_siblings_list, 0); #endif =20 #ifdef TOPOLOGY_DRAWER_SYSFS -define_id_show_func(drawer_id); +define_id_show_func(drawer_id, "%d"); static DEVICE_ATTR_RO(drawer_id); define_siblings_read_func(drawer_siblings, drawer_cpumask); static BIN_ATTR_RO(drawer_siblings, 0); --=20 2.31.1 From nobody Mon Jun 29 23:23:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE343C433F5 for ; Mon, 31 Jan 2022 23:01:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235921AbiAaXBf (ORCPT ); Mon, 31 Jan 2022 18:01:35 -0500 Received: from mga03.intel.com ([134.134.136.65]:53704 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235781AbiAaXBT (ORCPT ); Mon, 31 Jan 2022 18:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643670079; x=1675206079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HY/bz+/rI+UbhijOVUtdDlgLNv9q2KmlLYwHNyBOdnk=; b=e/V8LuauKppi3gITygWYtUkUouiOo1oMW5dn24gixRmeES9l6vlcYkcv iu45naR0iuqlcHUE0gb4muoZyP066XSnStD2V9huEqOEgLo4qvMztM6Oa 8jk5q1WwSVLZavjsmO/CMnEpFjkm8G5069sYssemvier7YGpGVSwXcxAx G8ZepTRqFByKj/AxnZfb1bwJNV+Z7ynnk7jZPvwF4G5Kf4nJ6I8k//98Q 2T7M5OhqYomDUhdn/+NpX69gmkDcpLOLXcMS4HkLsYY73Aw9xWqAw8m3L Uz48BDv9fYnDzzMtv/u/0eA01upFtjYbJV29EoYVBFUvEjfNsc7kP8lLE Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10244"; a="247521233" X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="247521233" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:19 -0800 X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="522831350" Received: from agluck-desk2.sc.intel.com ([10.3.52.146]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 15:01:18 -0800 From: Tony Luck To: Borislav Petkov Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Smita Koralahalli Channabasappa , Wei Huang , Tom Lendacky , patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 5/5] topology/sysfs: Add PPIN in sysfs under cpu topology Date: Mon, 31 Jan 2022 15:01:11 -0800 Message-Id: <20220131230111.2004669-6-tony.luck@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220131230111.2004669-1-tony.luck@intel.com> References: <20220121174743.1875294-1-tony.luck@intel.com> <20220131230111.2004669-1-tony.luck@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PPIN is the Protected Processor Identification Number. This is used to identify the socket as a Field Replaceable Unit (FRU). Existing code only displays this when reporting errors. But this makes it inconvenient for large clusters to use it for its intended purpose of inventory control. Add ppin to /sys/devices/system/cpu/cpu*/topology to make what is already available using RDMSR more easily accessible. Make the file read only for root in case there are still people concerned about making a unique system "serial number" available. Acked-by: Greg Kroah-Hartman Signed-off-by: Tony Luck --- Documentation/ABI/stable/sysfs-devices-system-cpu | 4 ++++ Documentation/ABI/testing/sysfs-devices-system-cpu | 6 ++++++ arch/x86/include/asm/topology.h | 1 + drivers/base/topology.c | 4 ++++ include/linux/topology.h | 3 +++ 5 files changed, 18 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-devices-system-cpu b/Documentat= ion/ABI/stable/sysfs-devices-system-cpu index 3965ce504484..902392d7eddf 100644 --- a/Documentation/ABI/stable/sysfs-devices-system-cpu +++ b/Documentation/ABI/stable/sysfs-devices-system-cpu @@ -86,6 +86,10 @@ What: /sys/devices/system/cpu/cpuX/topology/di= e_cpus Description: internal kernel map of CPUs within the same die. Values: hexadecimal bitmask. =20 +What: /sys/devices/system/cpu/cpuX/topology/ppin +Description: per-socket protected processor inventory number +Values: hexadecimal. + What: /sys/devices/system/cpu/cpuX/topology/die_cpus_list Description: human-readable list of CPUs within the same die. The format is like 0-3, 8-11, 14,17. diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documenta= tion/ABI/testing/sysfs-devices-system-cpu index 61f5676a7429..74962c200790 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -73,6 +73,7 @@ What: /sys/devices/system/cpu/cpuX/topology/core_id /sys/devices/system/cpu/cpuX/topology/physical_package_id /sys/devices/system/cpu/cpuX/topology/thread_siblings /sys/devices/system/cpu/cpuX/topology/thread_siblings_list + /sys/devices/system/cpu/cpuX/topology/ppin Date: December 2008 Contact: Linux kernel mailing list Description: CPU topology files that describe a logical CPU's relationship @@ -103,6 +104,11 @@ Description: CPU topology files that describe a logica= l CPU's relationship thread_siblings_list: human-readable list of cpuX's hardware threads within the same core as cpuX =20 + ppin: human-readable Protected Processor Identification + Number of the socket the cpu# belongs to. There should be + one per physical_package_id. File is readable only to + admin. + See Documentation/admin-guide/cputopology.rst for more information. =20 =20 diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 2f0b6be8eaab..43a89476a522 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -110,6 +110,7 @@ extern const struct cpumask *cpu_clustergroup_mask(int = cpu); #define topology_logical_die_id(cpu) (cpu_data(cpu).logical_die_id) #define topology_die_id(cpu) (cpu_data(cpu).cpu_die_id) #define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) +#define topology_ppin(cpu) (cpu_data(cpu).ppin) =20 extern unsigned int __max_die_per_package; =20 diff --git a/drivers/base/topology.c b/drivers/base/topology.c index 044f3664f8f2..e9d1efcda89b 100644 --- a/drivers/base/topology.c +++ b/drivers/base/topology.c @@ -58,6 +58,9 @@ static DEVICE_ATTR_RO(cluster_id); define_id_show_func(core_id, "%d"); static DEVICE_ATTR_RO(core_id); =20 +define_id_show_func(ppin, "0x%llx"); +static DEVICE_ATTR_ADMIN_RO(ppin); + define_siblings_read_func(thread_siblings, sibling_cpumask); static BIN_ATTR_RO(thread_siblings, 0); static BIN_ATTR_RO(thread_siblings_list, 0); @@ -145,6 +148,7 @@ static struct attribute *default_attrs[] =3D { #ifdef TOPOLOGY_DRAWER_SYSFS &dev_attr_drawer_id.attr, #endif + &dev_attr_ppin.attr, NULL }; =20 diff --git a/include/linux/topology.h b/include/linux/topology.h index a6e201758ae9..f19bc3626297 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -211,6 +211,9 @@ static inline int cpu_to_mem(int cpu) #ifndef topology_drawer_id #define topology_drawer_id(cpu) ((void)(cpu), -1) #endif +#ifndef topology_ppin +#define topology_ppin(cpu) ((void)(cpu), 0ull) +#endif #ifndef topology_sibling_cpumask #define topology_sibling_cpumask(cpu) cpumask_of(cpu) #endif --=20 2.31.1