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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:17 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 1/7] riscv: Avoid unaligned access when relocating modules Date: Mon, 31 Jan 2022 19:21:39 +0100 Message-Id: <20220131182145.236005-2-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With the C-extension regular 32bit instructions are not necessarily aligned on 4-byte boundaries. RISC-V instructions are in fact an ordered list of 16bit native-endian "parcels", so access the instruction as such. This should also make the code work in case someone builds a big-endian RISC-V machine. Fix rcv -> rvc typo while we're at it. Signed-off-by: Emil Renner Berthing --- arch/riscv/kernel/module.c | 151 +++++++++++++++++++------------------ 1 file changed, 76 insertions(+), 75 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 68a9e3d1fe16..3d33442226e7 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -13,68 +13,86 @@ #include #include =20 -static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Add= r v) +static int riscv_insn_rmw(void *location, u32 keep, u32 set) +{ + u16 *parcel =3D location; + u32 insn =3D (u32)parcel[0] | (u32)parcel[1] << 16; + + insn &=3D keep; + insn |=3D set; + + parcel[0] =3D insn; + parcel[1] =3D insn >> 16; + return 0; +} + +static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set) +{ + u16 *parcel =3D location; + + *parcel =3D (*parcel & keep) | set; + return 0; +} + +static int apply_r_riscv_32_rela(struct module *me, void *location, Elf_Ad= dr v) { if (v !=3D (u32)v) { pr_err("%s: value %016llx out of range for 32-bit field\n", me->name, (long long)v); return -EINVAL; } - *location =3D v; + *(u32 *)location =3D v; return 0; } =20 -static int apply_r_riscv_64_rela(struct module *me, u32 *location, Elf_Add= r v) +static int apply_r_riscv_64_rela(struct module *me, void *location, Elf_Ad= dr v) { *(u64 *)location =3D v; return 0; } =20 -static int apply_r_riscv_branch_rela(struct module *me, u32 *location, +static int apply_r_riscv_branch_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u32 imm12 =3D (offset & 0x1000) << (31 - 12); u32 imm11 =3D (offset & 0x800) >> (11 - 7); u32 imm10_5 =3D (offset & 0x7e0) << (30 - 10); u32 imm4_1 =3D (offset & 0x1e) << (11 - 4); =20 - *location =3D (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; - return 0; + return riscv_insn_rmw(location, 0x1fff07f, imm12 | imm11 | imm10_5 | imm4= _1); } =20 -static int apply_r_riscv_jal_rela(struct module *me, u32 *location, +static int apply_r_riscv_jal_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u32 imm20 =3D (offset & 0x100000) << (31 - 20); u32 imm19_12 =3D (offset & 0xff000); u32 imm11 =3D (offset & 0x800) << (20 - 11); u32 imm10_1 =3D (offset & 0x7fe) << (30 - 10); =20 - *location =3D (*location & 0xfff) | imm20 | imm19_12 | imm11 | imm10_1; - return 0; + return riscv_insn_rmw(location, 0xfff, imm20 | imm19_12 | imm11 | imm10_1= ); } =20 -static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location, +static int apply_r_riscv_rvc_branch_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u16 imm8 =3D (offset & 0x100) << (12 - 8); u16 imm7_6 =3D (offset & 0xc0) >> (6 - 5); u16 imm5 =3D (offset & 0x20) >> (5 - 2); u16 imm4_3 =3D (offset & 0x18) << (12 - 5); u16 imm2_1 =3D (offset & 0x6) << (12 - 10); =20 - *(u16 *)location =3D (*(u16 *)location & 0xe383) | - imm8 | imm7_6 | imm5 | imm4_3 | imm2_1; - return 0; + return riscv_insn_rvc_rmw(location, 0xe383, + imm8 | imm7_6 | imm5 | imm4_3 | imm2_1); } =20 -static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, +static int apply_r_riscv_rvc_jump_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u16 imm11 =3D (offset & 0x800) << (12 - 11); u16 imm10 =3D (offset & 0x400) >> (10 - 8); u16 imm9_8 =3D (offset & 0x300) << (12 - 11); @@ -84,16 +102,14 @@ static int apply_r_riscv_rvc_jump_rela(struct module *= me, u32 *location, u16 imm4 =3D (offset & 0x10) << (12 - 5); u16 imm3_1 =3D (offset & 0xe) << (12 - 10); =20 - *(u16 *)location =3D (*(u16 *)location & 0xe003) | - imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1; - return 0; + return riscv_insn_rvc_rmw(location, 0xe003, + imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1); } =20 -static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_pcrel_hi20_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; - s32 hi20; + ptrdiff_t offset =3D (void *)v - location; =20 if (offset !=3D (s32)offset) { pr_err( @@ -102,23 +118,20 @@ static int apply_r_riscv_pcrel_hi20_rela(struct modul= e *me, u32 *location, return -EINVAL; } =20 - hi20 =3D (offset + 0x800) & 0xfffff000; - *location =3D (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); } =20 -static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, u32 *locatio= n, +static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, void *locati= on, Elf_Addr v) { /* * v is the lo12 value to fill. It is calculated before calling this * handler. */ - *location =3D (*location & 0xfffff) | ((v & 0xfff) << 20); - return 0; + return riscv_insn_rmw(location, 0xfffff, (v & 0xfff) << 20); } =20 -static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, u32 *locatio= n, +static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, void *locati= on, Elf_Addr v) { /* @@ -128,15 +141,12 @@ static int apply_r_riscv_pcrel_lo12_s_rela(struct mod= ule *me, u32 *location, u32 imm11_5 =3D (v & 0xfe0) << (31 - 11); u32 imm4_0 =3D (v & 0x1f) << (11 - 4); =20 - *location =3D (*location & 0x1fff07f) | imm11_5 | imm4_0; - return 0; + return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); } =20 -static int apply_r_riscv_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_hi20_rela(struct module *me, void *location, Elf_Addr v) { - s32 hi20; - if (IS_ENABLED(CONFIG_CMODEL_MEDLOW)) { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = =3D %p\n", @@ -144,22 +154,20 @@ static int apply_r_riscv_hi20_rela(struct module *me,= u32 *location, return -EINVAL; } =20 - hi20 =3D ((s32)v + 0x800) & 0xfffff000; - *location =3D (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, ((s32)v + 0x800) & 0xfffff000); } =20 -static int apply_r_riscv_lo12_i_rela(struct module *me, u32 *location, +static int apply_r_riscv_lo12_i_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ s32 hi20 =3D ((s32)v + 0x800) & 0xfffff000; s32 lo12 =3D ((s32)v - hi20); - *location =3D (*location & 0xfffff) | ((lo12 & 0xfff) << 20); - return 0; + + return riscv_insn_rmw(location, 0xfffff, (lo12 & 0xfff) << 20); } =20 -static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location, +static int apply_r_riscv_lo12_s_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ @@ -167,20 +175,18 @@ static int apply_r_riscv_lo12_s_rela(struct module *m= e, u32 *location, s32 lo12 =3D ((s32)v - hi20); u32 imm11_5 =3D (lo12 & 0xfe0) << (31 - 11); u32 imm4_0 =3D (lo12 & 0x1f) << (11 - 4); - *location =3D (*location & 0x1fff07f) | imm11_5 | imm4_0; - return 0; + + return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); } =20 -static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_got_hi20_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; - s32 hi20; + ptrdiff_t offset =3D (void *)v - location; =20 /* Always emit the got entry */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { - offset =3D module_emit_got_entry(me, v); - offset =3D (void *)offset - (void *)location; + offset =3D (void *)module_emit_got_entry(me, v) - location; } else { pr_err( "%s: can not generate the GOT entry for symbol =3D %016llx from PC =3D= %p\n", @@ -188,23 +194,20 @@ static int apply_r_riscv_got_hi20_rela(struct module = *me, u32 *location, return -EINVAL; } =20 - hi20 =3D (offset + 0x800) & 0xfffff000; - *location =3D (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); } =20 -static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, +static int apply_r_riscv_call_plt_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; s32 fill_v =3D offset; u32 hi20, lo12; =20 if (offset !=3D fill_v) { /* Only emit the plt entry if offset over 32-bit range */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { - offset =3D module_emit_plt_entry(me, v); - offset =3D (void *)offset - (void *)location; + offset =3D (void *)module_emit_plt_entry(me, v) - location; } else { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC= =3D %p\n", @@ -215,15 +218,14 @@ static int apply_r_riscv_call_plt_rela(struct module = *me, u32 *location, =20 hi20 =3D (offset + 0x800) & 0xfffff000; lo12 =3D (offset - hi20) & 0xfff; - *location =3D (*location & 0xfff) | hi20; - *(location + 1) =3D (*(location + 1) & 0xfffff) | (lo12 << 20); - return 0; + riscv_insn_rmw(location, 0xfff, hi20); + return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); } =20 -static int apply_r_riscv_call_rela(struct module *me, u32 *location, +static int apply_r_riscv_call_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; s32 fill_v =3D offset; u32 hi20, lo12; =20 @@ -236,18 +238,17 @@ static int apply_r_riscv_call_rela(struct module *me,= u32 *location, =20 hi20 =3D (offset + 0x800) & 0xfffff000; lo12 =3D (offset - hi20) & 0xfff; - *location =3D (*location & 0xfff) | hi20; - *(location + 1) =3D (*(location + 1) & 0xfffff) | (lo12 << 20); - return 0; + riscv_insn_rmw(location, 0xfff, hi20); + return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); } =20 -static int apply_r_riscv_relax_rela(struct module *me, u32 *location, +static int apply_r_riscv_relax_rela(struct module *me, void *location, Elf_Addr v) { return 0; } =20 -static int apply_r_riscv_align_rela(struct module *me, u32 *location, +static int apply_r_riscv_align_rela(struct module *me, void *location, Elf_Addr v) { pr_err( @@ -256,41 +257,41 @@ static int apply_r_riscv_align_rela(struct module *me= , u32 *location, return -EINVAL; } =20 -static int apply_r_riscv_add32_rela(struct module *me, u32 *location, +static int apply_r_riscv_add32_rela(struct module *me, void *location, Elf_Addr v) { *(u32 *)location +=3D (u32)v; return 0; } =20 -static int apply_r_riscv_add64_rela(struct module *me, u32 *location, +static int apply_r_riscv_add64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location +=3D (u64)v; return 0; } =20 -static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub32_rela(struct module *me, void *location, Elf_Addr v) { *(u32 *)location -=3D (u32)v; return 0; } =20 -static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location -=3D (u64)v; return 0; } =20 -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, +static int (*reloc_handlers_rela[]) (struct module *me, void *location, Elf_Addr v) =3D { [R_RISCV_32] =3D apply_r_riscv_32_rela, [R_RISCV_64] =3D apply_r_riscv_64_rela, [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rcv_branch_rela, + [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, @@ -314,9 +315,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *s= trtab, struct module *me) { Elf_Rela *rel =3D (void *) sechdrs[relsec].sh_addr; - int (*handler)(struct module *me, u32 *location, Elf_Addr v); + int (*handler)(struct module *me, void *location, Elf_Addr v); Elf_Sym *sym; - u32 *location; + void *location; unsigned int i, type; Elf_Addr v; int res; --=20 2.35.1 From nobody Mon Jun 29 23:03:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18EB5C433EF for ; Mon, 31 Jan 2022 18:22:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347931AbiAaSWa (ORCPT ); Mon, 31 Jan 2022 13:22:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347944AbiAaSWW (ORCPT ); Mon, 31 Jan 2022 13:22:22 -0500 Received: from mail-oi1-x236.google.com (mail-oi1-x236.google.com [IPv6:2607:f8b0:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B902C06173B for ; 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:21 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 2/7] riscv: Fix auipc+jalr relocation range checks Date: Mon, 31 Jan 2022 19:21:40 +0100 Message-Id: <20220131182145.236005-3-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISC-V can do PC-relative jumps with a 32bit range using the following two instructions: auipc t0, imm20 ; t0 =3D PC + imm20 * 2^12 jalr ra, t0, imm12 ; ra =3D PC + 4, PC =3D t0 + imm12, Crucially both the 20bit immediate imm20 and the 12bit immediate imm12 are treated as two's-complement signed values. For this reason the immediates are usually calculated like this: imm20 =3D (offset + 0x800) >> 12 imm12 =3D offset & 0xfff ..where offset is the signed offset from the auipc instruction. When the 11th bit of offset is 0 the addition of 0x800 doesn't change the top 20 bits and imm12 considered positive. When the 11th bit is 1 the carry of the addition by 0x800 means imm20 is one higher, but since imm12 is then considered negative the two's complement representation means it all cancels out nicely. However, this addition by 0x800 (2^11) means an offset greater than or equal to 2^31 - 2^11 would overflow so imm20 is considered negative and result in a backwards jump. Similarly the lower range of offset is also moved down by 2^11 and hence the true 32bit range is [-2^31 - 2^11, 2^31 - 2^11) Signed-off-by: Emil Renner Berthing --- arch/riscv/kernel/module.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 3d33442226e7..a75ccf3a6ce8 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -13,6 +13,18 @@ #include #include =20 +static inline bool riscv_insn_valid_32bit_offset(ptrdiff_t val) +{ + if (IS_ENABLED(CONFIG_32BIT)) + return true; + + /* + * auipc+jalr can reach any PC-relative offset in the range + * [-2^31 - 2^11, 2^31 - 2^11) + */ + return (-(1L << 31) - (1L << 11)) <=3D val && val < ((1L << 31) - (1L << = 11)); +} + static int riscv_insn_rmw(void *location, u32 keep, u32 set) { u16 *parcel =3D location; @@ -111,7 +123,7 @@ static int apply_r_riscv_pcrel_hi20_rela(struct module = *me, void *location, { ptrdiff_t offset =3D (void *)v - location; =20 - if (offset !=3D (s32)offset) { + if (!riscv_insn_valid_32bit_offset(offset)) { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = =3D %p\n", me->name, (long long)v, location); @@ -201,10 +213,9 @@ static int apply_r_riscv_call_plt_rela(struct module *= me, void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - s32 fill_v =3D offset; u32 hi20, lo12; =20 - if (offset !=3D fill_v) { + if (!riscv_insn_valid_32bit_offset(offset)) { /* Only emit the plt entry if offset over 32-bit range */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { offset =3D (void *)module_emit_plt_entry(me, v) - location; @@ -226,10 +237,9 @@ static int apply_r_riscv_call_rela(struct module *me, = void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - s32 fill_v =3D offset; u32 hi20, lo12; =20 - if (offset !=3D fill_v) { + if (!riscv_insn_valid_32bit_offset(offset)) { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = =3D %p\n", me->name, (long long)v, location); --=20 2.35.1 From nobody Mon Jun 29 23:03:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46995C433EF for ; Mon, 31 Jan 2022 18:22:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348454AbiAaSWg (ORCPT ); Mon, 31 Jan 2022 13:22:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348236AbiAaSW0 (ORCPT ); Mon, 31 Jan 2022 13:22:26 -0500 Received: from mail-oi1-x233.google.com (mail-oi1-x233.google.com [IPv6:2607:f8b0:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F6A4C061714 for ; Mon, 31 Jan 2022 10:22:26 -0800 (PST) Received: by mail-oi1-x233.google.com with SMTP id x193so28445095oix.0 for ; Mon, 31 Jan 2022 10:22:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6eMWCVmEcwxhKWA4X00yoLIXiWrdcmbrlYXjWFueDp8=; b=jqH6c0jEogoSGD5Ee/FcG2bn4Odrh9BtU928Z8acx2mqhmhtMj2i8/WcMVjxlyFVPl LjznNcOAEDBZugYf0ZQAz3MJGPFR+UnWBJUZKO17LQYeiPDOe6O7wtHh66HRmdJLKxEm 4ErPJfxLCKpW/K9WiNmWVLFK0beb2RpMRDY+b7Gp39anq6HDi4y4CetGZ4GbZokIlxIp mH6scYDJviVHAav55EkZAUD3eKVKa0inS5heTSxpSDs5IgSKpIuv1Tk5fTzXARW3RqBx K5+JVru1J3yKwEWQcaAlJ/LFBfMwZe9wwW00hlrJtbWKwiRYmjwtLP1HJWzQCL3IXGvg so2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6eMWCVmEcwxhKWA4X00yoLIXiWrdcmbrlYXjWFueDp8=; b=ZE3j9zLBkqm80iRE87B0BnZYvI0WKA9ubJj+ZTLYVUO7TCun6F8Gb/fNTYUrbRRHFj U2SM7fImFP02yDDM2IK0YHLLM8W6+vjOyHiwSTIiTntaDjJZqdHBxEnCqgog4sMU+OZR xnjCIC2WgTd5oEi66YP8hDeU/9qlxMaGBUYbHQr/OQaxeG/HXQRRFrO7uCOVInceDXei xg2wQ8/BTCtlKLxNfQ0Sxm+aC4Z5RPdmV63aet2nDMrg5NKapyQTnGZRd3phqPgqFt6s 3bQIcIdCpziK0JOzv93QQjONY2XyMJgTzLB+pG49jaDv46c1TZ4QloUV2EKllYMff6QK NAxA== X-Gm-Message-State: AOAM533iUybfQmMgLT83XQLZ6lCY0RML96FYf3XLtlY6BcJetj3u5oHp NK37f0QNuM2m1n8EF2999W4= X-Google-Smtp-Source: ABdhPJybuZ+l9IBa0oBBWeviE7Tlm1E07to/F3di8EpWk18bWxhozZwdNTmIkKHKqG1rE9RAGXz/Ag== X-Received: by 2002:a05:6808:8d:: with SMTP id s13mr8759735oic.227.1643653345887; Mon, 31 Jan 2022 10:22:25 -0800 (PST) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:25 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 3/7] riscv: Add asm/insn.h header Date: Mon, 31 Jan 2022 19:21:41 +0100 Message-Id: <20220131182145.236005-4-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add new asm/insn.h header to consolidate RISC-V instruction constants and inline helper functions. Signed-off-by: Emil Renner Berthing --- arch/riscv/include/asm/insn.h | 121 ++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/riscv/include/asm/insn.h diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h new file mode 100644 index 000000000000..2bdb089390f0 --- /dev/null +++ b/arch/riscv/include/asm/insn.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Emil Renner Berthing + */ +#ifndef __ASM_RISCV_INSN_H +#define __ASM_RISCV_INSN_H + +#include + +#define RISCV_INSN_LD _AC(0x00003003, U) +#define RISCV_INSN_ADDI _AC(0x00000013, U) +#define RISCV_INSN_NOP RISCV_INSN_ADDI +#define RISCV_INSN_AUIPC _AC(0x00000017, U) +#define RISCV_INSN_LUI _AC(0x00000037, U) +#define RISCV_INSN_JALR _AC(0x00000067, U) +#define RISCV_INSN_JAL _AC(0x0000006f, U) + +#define RISCV_INSN_RA _AC(0x1, U) +#define RISCV_INSN_T0 _AC(0x5, U) +#define RISCV_INSN_T1 _AC(0x6, U) + +#define RISCV_INSN_RD_POS 7 +#define RISCV_INSN_RD_RA (RISCV_INSN_RA << RISCV_INSN_RD_POS) +#define RISCV_INSN_RD_T0 (RISCV_INSN_T0 << RISCV_INSN_RD_POS) +#define RISCV_INSN_RD_T1 (RISCV_INSN_T1 << RISCV_INSN_RD_POS) + +#define RISCV_INSN_RS1_POS 15 +#define RISCV_INSN_RS1_RA (RISCV_INSN_RA << RISCV_INSN_RS1_POS) +#define RISCV_INSN_RS1_T0 (RISCV_INSN_T0 << RISCV_INSN_RS1_POS) +#define RISCV_INSN_RS1_T1 (RISCV_INSN_T1 << RISCV_INSN_RS1_POS) + +#define RISCV_INSN_I_IMM_MASK _AC(0xfff00000, U) +#define RISCV_INSN_S_IMM_MASK _AC(0xfe000f80, U) +#define RISCV_INSN_B_IMM_MASK _AC(0xfe000f80, U) +#define RISCV_INSN_U_IMM_MASK _AC(0xfffff000, U) +#define RISCV_INSN_J_IMM_MASK _AC(0xfffff000, U) + +#define RISCV_INSN_CI_IMM_MASK _AC(0x107c, U) +#define RISCV_INSN_CSS_IMM_MASK _AC(0x1f80, U) +#define RISCV_INSN_CIW_IMM_MASK _AC(0x1fe0, U) +#define RISCV_INSN_CL_IMM_MASK _AC(0x1c60, U) +#define RISCV_INSN_CS_IMM_MASK _AC(0x1c60, U) +#define RISCV_INSN_CB_IMM_MASK _AC(0x1c7c, U) +#define RISCV_INSN_CJ_IMM_MASK _AC(0x1ffc, U) + +#ifndef __ASSEMBLY__ +#include +#include + +static inline bool riscv_insn_valid_20bit_offset(ptrdiff_t val) +{ + return !(val & 1) && -(1L << 19) <=3D val && val < (1L << 19); +} + +static inline bool riscv_insn_valid_32bit_offset(ptrdiff_t val) +{ + if (IS_ENABLED(CONFIG_32BIT)) + return true; + + /* + * auipc+jalr can reach any PC-relative offset in the range + * [-2^31 - 2^11, 2^31 - 2^11) + */ + return (-(1L << 31) - (1L << 11)) <=3D val && val < ((1L << 31) - (1L << = 11)); +} + +static inline u32 riscv_insn_i_imm(u32 imm) +{ + return (imm & GENMASK(11, 0)) << 20; +} + +static inline u32 riscv_insn_s_imm(u32 imm) +{ + return (imm & GENMASK( 4, 0)) << ( 7 - 0) | + (imm & GENMASK(11, 5)) << (25 - 5); +} + +static inline u32 riscv_insn_b_imm(u32 imm) +{ + return (imm & GENMASK(11, 11)) >> (11 - 7) | + (imm & GENMASK( 4, 1)) << ( 8 - 1) | + (imm & GENMASK(10, 5)) << (25 - 5) | + (imm & GENMASK(12, 12)) << (31 - 12); +} + +static inline u32 riscv_insn_u_imm(u32 imm) +{ + return imm & GENMASK(31, 12); +} + +static inline u32 riscv_insn_j_imm(u32 imm) +{ + return (imm & GENMASK(19, 12)) << (12 - 12) | + (imm & GENMASK(11, 11)) << (20 - 11) | + (imm & GENMASK(10, 1)) << (21 - 1) | + (imm & GENMASK(20, 20)) << (31 - 20); +} + +static inline u16 riscv_insn_rvc_branch_imm(u16 imm) +{ + return (imm & GENMASK(5, 5)) >> ( 5 - 2) | + (imm & GENMASK(2, 1)) << ( 3 - 1) | + (imm & GENMASK(7, 6)) >> ( 6 - 5) | + (imm & GENMASK(4, 3)) << (10 - 3) | + (imm & GENMASK(8, 8)) << (12 - 8); +} + +static inline u16 riscv_insn_rvc_jump_imm(u16 imm) +{ + return (imm & GENMASK( 5, 5)) >> ( 5 - 2) | + (imm & GENMASK( 3, 1)) << ( 3 - 1) | + (imm & GENMASK( 7, 7)) >> ( 7 - 6) | + (imm & GENMASK( 6, 6)) << ( 7 - 6) | + (imm & GENMASK(10, 10)) >> (10 - 8) | + (imm & GENMASK( 9, 8)) << ( 9 - 8) | + (imm & GENMASK( 4, 4)) << (11 - 4) | + (imm & GENMASK(11, 11)) << (12 - 11); +} + +#endif +#endif --=20 2.35.1 From nobody Mon Jun 29 23:03:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFFF6C433EF for ; Mon, 31 Jan 2022 18:22:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349142AbiAaSWk (ORCPT ); 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:29 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 4/7] riscv: Use asm/insn.h for module relocations Date: Mon, 31 Jan 2022 19:21:42 +0100 Message-Id: <20220131182145.236005-5-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This converts the module relocations in kernel/module.c to use asm/insn.h for instruction manipulation. Also RISC-V has a number of instruction pairs to generate 32bit immediates or jump/call offsets. Eg.: lui rd, hi20 addi rd, rd, lo12 ..where hi20 is the upper 20bits to load into register rd and lo12 is the lower 12bits. However both immediates are interpreted as two's complement signed values. Hence the old code calculates hi20 and lo12 for 32bit immediates imm like this: hi20 =3D (imm + 0x800) & 0xfffff000; lo12 =3D (imm - hi20) & 0xfff; This patch simplifies it to: hi20 =3D (imm + 0x800) & 0xfffff000; lo12 =3D imm & 0xfff; ..which amounts to the same: imm - hi20 may be become negative/underflow, but it doesn't change the lower 12 bits. Signed-off-by: Emil Renner Berthing --- arch/riscv/kernel/module.c | 138 +++++++++++++++---------------------- 1 file changed, 56 insertions(+), 82 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index a75ccf3a6ce8..2212d88776e0 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -2,6 +2,7 @@ /* * * Copyright (C) 2017 Zihao Yu + * Copyright (C) 2020 Emil Renner Berthing */ =20 #include @@ -11,38 +12,27 @@ #include #include #include +#include #include =20 -static inline bool riscv_insn_valid_32bit_offset(ptrdiff_t val) -{ - if (IS_ENABLED(CONFIG_32BIT)) - return true; - - /* - * auipc+jalr can reach any PC-relative offset in the range - * [-2^31 - 2^11, 2^31 - 2^11) - */ - return (-(1L << 31) - (1L << 11)) <=3D val && val < ((1L << 31) - (1L << = 11)); -} - -static int riscv_insn_rmw(void *location, u32 keep, u32 set) +static int riscv_insn_rmw(void *location, u32 mask, u32 value) { u16 *parcel =3D location; u32 insn =3D (u32)parcel[0] | (u32)parcel[1] << 16; =20 - insn &=3D keep; - insn |=3D set; + insn &=3D ~mask; + insn |=3D value; =20 parcel[0] =3D insn; parcel[1] =3D insn >> 16; return 0; } =20 -static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set) +static int riscv_insn_rvc_rmw(void *location, u16 mask, u16 value) { u16 *parcel =3D location; =20 - *parcel =3D (*parcel & keep) | set; + *parcel =3D (*parcel & ~mask) | value; return 0; } =20 @@ -67,55 +57,40 @@ static int apply_r_riscv_branch_rela(struct module *me,= void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - u32 imm12 =3D (offset & 0x1000) << (31 - 12); - u32 imm11 =3D (offset & 0x800) >> (11 - 7); - u32 imm10_5 =3D (offset & 0x7e0) << (30 - 10); - u32 imm4_1 =3D (offset & 0x1e) << (11 - 4); =20 - return riscv_insn_rmw(location, 0x1fff07f, imm12 | imm11 | imm10_5 | imm4= _1); + return riscv_insn_rmw(location, + RISCV_INSN_B_IMM_MASK, + riscv_insn_b_imm(offset)); } =20 static int apply_r_riscv_jal_rela(struct module *me, void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - u32 imm20 =3D (offset & 0x100000) << (31 - 20); - u32 imm19_12 =3D (offset & 0xff000); - u32 imm11 =3D (offset & 0x800) << (20 - 11); - u32 imm10_1 =3D (offset & 0x7fe) << (30 - 10); =20 - return riscv_insn_rmw(location, 0xfff, imm20 | imm19_12 | imm11 | imm10_1= ); + return riscv_insn_rmw(location, + RISCV_INSN_J_IMM_MASK, + riscv_insn_j_imm(offset)); } =20 static int apply_r_riscv_rvc_branch_rela(struct module *me, void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - u16 imm8 =3D (offset & 0x100) << (12 - 8); - u16 imm7_6 =3D (offset & 0xc0) >> (6 - 5); - u16 imm5 =3D (offset & 0x20) >> (5 - 2); - u16 imm4_3 =3D (offset & 0x18) << (12 - 5); - u16 imm2_1 =3D (offset & 0x6) << (12 - 10); - - return riscv_insn_rvc_rmw(location, 0xe383, - imm8 | imm7_6 | imm5 | imm4_3 | imm2_1); + + return riscv_insn_rvc_rmw(location, + RISCV_INSN_CB_IMM_MASK, + riscv_insn_rvc_branch_imm(offset)); } =20 static int apply_r_riscv_rvc_jump_rela(struct module *me, void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - u16 imm11 =3D (offset & 0x800) << (12 - 11); - u16 imm10 =3D (offset & 0x400) >> (10 - 8); - u16 imm9_8 =3D (offset & 0x300) << (12 - 11); - u16 imm7 =3D (offset & 0x80) >> (7 - 6); - u16 imm6 =3D (offset & 0x40) << (12 - 11); - u16 imm5 =3D (offset & 0x20) >> (5 - 2); - u16 imm4 =3D (offset & 0x10) << (12 - 5); - u16 imm3_1 =3D (offset & 0xe) << (12 - 10); - - return riscv_insn_rvc_rmw(location, 0xe003, - imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1); + + return riscv_insn_rvc_rmw(location, + RISCV_INSN_CJ_IMM_MASK, + riscv_insn_rvc_jump_imm(offset)); } =20 static int apply_r_riscv_pcrel_hi20_rela(struct module *me, void *location, @@ -130,30 +105,27 @@ static int apply_r_riscv_pcrel_hi20_rela(struct modul= e *me, void *location, return -EINVAL; } =20 - return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); + return riscv_insn_rmw(location, + RISCV_INSN_U_IMM_MASK, + riscv_insn_u_imm(offset + 0x800)); } =20 static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, void *locati= on, Elf_Addr v) { - /* - * v is the lo12 value to fill. It is calculated before calling this - * handler. - */ - return riscv_insn_rmw(location, 0xfffff, (v & 0xfff) << 20); + /* v is already the relative offset */ + return riscv_insn_rmw(location, + RISCV_INSN_I_IMM_MASK, + riscv_insn_i_imm(v)); } =20 static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, void *locati= on, Elf_Addr v) { - /* - * v is the lo12 value to fill. It is calculated before calling this - * handler. - */ - u32 imm11_5 =3D (v & 0xfe0) << (31 - 11); - u32 imm4_0 =3D (v & 0x1f) << (11 - 4); - - return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); + /* v is already the relative offset */ + return riscv_insn_rmw(location, + RISCV_INSN_S_IMM_MASK, + riscv_insn_s_imm(v)); } =20 static int apply_r_riscv_hi20_rela(struct module *me, void *location, @@ -166,29 +138,27 @@ static int apply_r_riscv_hi20_rela(struct module *me,= void *location, return -EINVAL; } =20 - return riscv_insn_rmw(location, 0xfff, ((s32)v + 0x800) & 0xfffff000); + return riscv_insn_rmw(location, + RISCV_INSN_U_IMM_MASK, + riscv_insn_u_imm(v + 0x800)); } =20 static int apply_r_riscv_lo12_i_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ - s32 hi20 =3D ((s32)v + 0x800) & 0xfffff000; - s32 lo12 =3D ((s32)v - hi20); - - return riscv_insn_rmw(location, 0xfffff, (lo12 & 0xfff) << 20); + return riscv_insn_rmw(location, + RISCV_INSN_I_IMM_MASK, + riscv_insn_i_imm(v)); } =20 static int apply_r_riscv_lo12_s_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ - s32 hi20 =3D ((s32)v + 0x800) & 0xfffff000; - s32 lo12 =3D ((s32)v - hi20); - u32 imm11_5 =3D (lo12 & 0xfe0) << (31 - 11); - u32 imm4_0 =3D (lo12 & 0x1f) << (11 - 4); - - return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); + return riscv_insn_rmw(location, + RISCV_INSN_S_IMM_MASK, + riscv_insn_s_imm(v)); } =20 static int apply_r_riscv_got_hi20_rela(struct module *me, void *location, @@ -206,14 +176,15 @@ static int apply_r_riscv_got_hi20_rela(struct module = *me, void *location, return -EINVAL; } =20 - return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); + return riscv_insn_rmw(location, + RISCV_INSN_U_IMM_MASK, + riscv_insn_u_imm(offset + 0x800)); } =20 static int apply_r_riscv_call_plt_rela(struct module *me, void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - u32 hi20, lo12; =20 if (!riscv_insn_valid_32bit_offset(offset)) { /* Only emit the plt entry if offset over 32-bit range */ @@ -227,17 +198,18 @@ static int apply_r_riscv_call_plt_rela(struct module = *me, void *location, } } =20 - hi20 =3D (offset + 0x800) & 0xfffff000; - lo12 =3D (offset - hi20) & 0xfff; - riscv_insn_rmw(location, 0xfff, hi20); - return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); + riscv_insn_rmw(location, + RISCV_INSN_U_IMM_MASK, + riscv_insn_u_imm(offset + 0x800)); + return riscv_insn_rmw(location + 4, + RISCV_INSN_I_IMM_MASK, + riscv_insn_i_imm(offset)); } =20 static int apply_r_riscv_call_rela(struct module *me, void *location, Elf_Addr v) { ptrdiff_t offset =3D (void *)v - location; - u32 hi20, lo12; =20 if (!riscv_insn_valid_32bit_offset(offset)) { pr_err( @@ -246,10 +218,12 @@ static int apply_r_riscv_call_rela(struct module *me,= void *location, return -EINVAL; } =20 - hi20 =3D (offset + 0x800) & 0xfffff000; - lo12 =3D (offset - hi20) & 0xfff; - riscv_insn_rmw(location, 0xfff, hi20); - return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); + riscv_insn_rmw(location, + RISCV_INSN_U_IMM_MASK, + riscv_insn_u_imm(offset + 0x800)); + return riscv_insn_rmw(location + 4, + RISCV_INSN_I_IMM_MASK, + riscv_insn_i_imm(offset)); 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:33 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 5/7] riscv: Use asm/insn.h to generate plt entries Date: Mon, 31 Jan 2022 19:21:43 +0100 Message-Id: <20220131182145.236005-6-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This converts kernel/module-sections.c to use asm/insn.h to generate the instructions in the plt entries. Signed-off-by: Emil Renner Berthing --- arch/riscv/kernel/module-sections.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module= -sections.c index 39d4ac681c2a..cb73399c3603 100644 --- a/arch/riscv/kernel/module-sections.c +++ b/arch/riscv/kernel/module-sections.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 struct got_entry { unsigned long symbol_addr; /* the real variable address */ @@ -61,36 +62,16 @@ struct plt_entry { u32 insn_jr; /* jr t1 */ }; =20 -#define OPC_AUIPC 0x0017 -#define OPC_LD 0x3003 -#define OPC_JALR 0x0067 -#define REG_T0 0x5 -#define REG_T1 0x6 - static struct plt_entry emit_plt_entry(unsigned long val, unsigned long plt, unsigned long got_plt) { - /* - * U-Type encoding: - * +------------+----------+----------+ - * | imm[31:12] | rd[11:7] | opc[6:0] | - * +------------+----------+----------+ - * - * I-Type encoding: - * +------------+------------+--------+----------+----------+ - * | imm[31:20] | rs1[19:15] | funct3 | rd[11:7] | opc[6:0] | - * +------------+------------+--------+----------+----------+ - * - */ unsigned long offset =3D got_plt - plt; - u32 hi20 =3D (offset + 0x800) & 0xfffff000; - u32 lo12 =3D (offset - hi20); =20 return (struct plt_entry) { - OPC_AUIPC | (REG_T0 << 7) | hi20, - OPC_LD | (lo12 << 20) | (REG_T0 << 15) | (REG_T1 << 7), - OPC_JALR | (REG_T1 << 15) + RISCV_INSN_AUIPC | RISCV_INSN_RD_T0 | riscv_insn_u_imm(offset + 0x800), + RISCV_INSN_LD | RISCV_INSN_RD_T1 | RISCV_INSN_RS1_T0 | riscv_insn_i_i= mm(offset), + RISCV_INSN_JALR | RISCV_INSN_RS1_T1, }; } =20 --=20 2.35.1 From nobody Mon Jun 29 23:03:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B08C433F5 for ; Mon, 31 Jan 2022 18:23:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348652AbiAaSXB (ORCPT ); Mon, 31 Jan 2022 13:23:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348648AbiAaSWh (ORCPT ); Mon, 31 Jan 2022 13:22:37 -0500 Received: from mail-oi1-x235.google.com (mail-oi1-x235.google.com [IPv6:2607:f8b0:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6C71C06173B for ; Mon, 31 Jan 2022 10:22:37 -0800 (PST) Received: by mail-oi1-x235.google.com with SMTP id r27so6144866oiw.4 for ; Mon, 31 Jan 2022 10:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U2McVQuv53c33dZYwtuytrfr7zhfRHKf5OwpDdiji0Q=; b=GrPuCF7g8wuXvMFUhWNN1mhzoghD0PNgEzngwf2WvawQ8neFtZyyWFFWbrsLyvbhN0 1YLTZW9YmEf5d2WlRFTUJdnmChTV/PIDJd5JRx0YEC94UMjmjp0/5nD+7vFXklO6KAco tziDslat9YPXq77Ksu5JtauYUyr8ws1HKtftRCGmK2u+eUDCVSuPG81jrbVMgGBA5Xcj +cyDSjShDdJ2Mq7rljU0CX8f1UDknrJW/a7DqHadutRbyD+8xDe/3tCcKAy4a1V51tqq sGB/9BvZ8JZagsG2pE2fPv00MPEWXjT48ZAbEPc8Owmp35/GlcEaBsLshIZ7l/bJIj0s wOOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=U2McVQuv53c33dZYwtuytrfr7zhfRHKf5OwpDdiji0Q=; b=8QLZPavJ8zudhhebnzKfuABwY1+YfEPJkxcu56tYzj6aFjLIXtSuwkfJ/+R/oxIrAM L5kH7obAyaBp1p8i2bXThxH+J3fIEdNKWJ6FAk1MZMJ9Wqmo7KQLBch4amoyl4i7Mvhi r7wS8SifZP76TeMccErEdiNBxrxHPMsYNMmxyw9+zf5BnbNlCsrdZ/0+SlNDfE24e+dS 0xSKsdhKgZyU+G/CN1EKi5E9NoU2oLNuvJ9ify/AV9WXI4nZ6oQ1Gqvugm3seLqVxpkn Y2Hmgha9/0Cgdlqtc/nlggi0MKBvDP27nseCo4v/xVDFl5eC0b+rMKpAnAi6ariTX8AR OkFA== X-Gm-Message-State: AOAM530ypsMBJiFFM3Twp+V99CniRudPJvgByGR3xS7wPdrnZMt3LlDU rax9uM1rFheXtFSOhbbo6rY= X-Google-Smtp-Source: ABdhPJyXQjVGntX1OX0ZlbDOasHZ7YutyxmQFYeM96PygHpy3m+Tr5xZApjL6EcLrg2VuspYptU/SA== X-Received: by 2002:a05:6808:1644:: with SMTP id az4mr13575526oib.214.1643653357036; Mon, 31 Jan 2022 10:22:37 -0800 (PST) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:36 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 6/7] riscv: Use asm/insn.h for jump labels Date: Mon, 31 Jan 2022 19:21:44 +0100 Message-Id: <20220131182145.236005-7-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This converts kernel/jump_label.c to use asm/insn.h to generate the jump/nop instructions. Signed-off-by: Emil Renner Berthing --- arch/riscv/kernel/jump_label.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/jump_label.c b/arch/riscv/kernel/jump_label.c index 20e09056d141..b5b4892c3e9e 100644 --- a/arch/riscv/kernel/jump_label.c +++ b/arch/riscv/kernel/jump_label.c @@ -9,11 +9,9 @@ #include #include #include +#include #include =20 -#define RISCV_INSN_NOP 0x00000013U -#define RISCV_INSN_JAL 0x0000006fU - void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type type) { @@ -23,14 +21,10 @@ void arch_jump_label_transform(struct jump_entry *entry, if (type =3D=3D JUMP_LABEL_JMP) { long offset =3D jump_entry_target(entry) - jump_entry_code(entry); =20 - if (WARN_ON(offset & 1 || offset < -524288 || offset >=3D 524288)) + if (WARN_ON(!riscv_insn_valid_20bit_offset(offset))) return; =20 - insn =3D RISCV_INSN_JAL | - (((u32)offset & GENMASK(19, 12)) << (12 - 12)) | - (((u32)offset & GENMASK(11, 11)) << (20 - 11)) | - (((u32)offset & GENMASK(10, 1)) << (21 - 1)) | - (((u32)offset & GENMASK(20, 20)) << (31 - 20)); + insn =3D RISCV_INSN_JAL | riscv_insn_j_imm(offset); } else { insn =3D RISCV_INSN_NOP; } --=20 2.35.1 From nobody Mon Jun 29 23:03:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59AC1C433EF for ; Mon, 31 Jan 2022 18:23:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348448AbiAaSXF (ORCPT ); Mon, 31 Jan 2022 13:23:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349447AbiAaSWl (ORCPT ); Mon, 31 Jan 2022 13:22:41 -0500 Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82361C061714 for ; Mon, 31 Jan 2022 10:22:41 -0800 (PST) Received: by mail-ot1-x32c.google.com with SMTP id g15-20020a9d6b0f000000b005a062b0dc12so13825421otp.4 for ; Mon, 31 Jan 2022 10:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CCzMOkXflHmWMxX1XPAY7nKtPtpcp9g4eQAqLH2YIns=; b=cVK8q8IqPDBCtC4ivwSc3NI0vzhHzduPJmRPfeneeNFUbDsICRd+mkaStOSPBXhwS7 Yx81OYIDDpFzjBTNOXUaGn/MCdv/wSm3v8jx2LYnh3iCrOLoYMgisLM9s0zDdt3XYU0v 2+XHQyESKt6wXm0aFMHt1OxQBc5j1k0lnSxg2K2pmNugaNF/xBDjvMtxNwe8W25DoE5N HICPrAY5HXD+8fEfd3JVjEYXTgPSLkCAZWBw5gJQVhkwuRhuCECPzoVpuJWoJjbjFfGf bCWDU4WTLWSkNE1aquajGR2doEYuqN9JQ1XvjyD3VEgq6EyAfhfFbS2mcsffA4xD6Qu4 SBsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CCzMOkXflHmWMxX1XPAY7nKtPtpcp9g4eQAqLH2YIns=; b=mf16P1DBmowaOLHPzME3p9jnznH/EAPcUoJCgBUg3Ldn3l3izbLv3J6Hj/Sh2hVObs 8idFc3rjtucXOjV4byu+hOV8sNxdNylf3+xuCsFuiJyreXYG2mVOjb+nDNGZ0cbeisw0 s1RTUWqk8x0QnWTh4uFEXehd5yBdKN5wgKLbZfaP9gPPBlQr1XJIO/wW6AD2EUlBM1zx Fvy4lEIWr9l7cQq247UkhlF36VwUJDgUhxa7P8o4RBo98kK4s2wVQ433WPV2OA0cdwdD B5xIs83OtonPhgGW/zhmZAiQn3iJ0iWuBLgRA5YS6khTmrHAuTCEEV7xeR9a2PQamviR bxOg== X-Gm-Message-State: AOAM533JH859ZGS9r3VW2lm+KHEAhxxpIjcnQmZj9taURI8lGzT6DHGT ZVd14xLo6QkHhYeljq0Pumc= X-Google-Smtp-Source: ABdhPJyINXPwfY18wwXLDqhZ/f1W5qGuM2/i1IID9PGprXPfceL3GeaWq/hfJyqgBqtWWKNNWrltLA== X-Received: by 2002:a05:6830:30b6:: with SMTP id g22mr12237496ots.122.1643653360912; Mon, 31 Jan 2022 10:22:40 -0800 (PST) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t4sm12986340oie.14.2022.01.31.10.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 10:22:40 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Alexandre Ghiti , Jisheng Zhang , linux-kernel@vger.kernel.org Subject: [PATCH v1 7/7] riscv: kernel/modules.c simplification Date: Mon, 31 Jan 2022 19:21:45 +0100 Message-Id: <20220131182145.236005-8-kernel@esmil.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220131182145.236005-1-kernel@esmil.dk> References: <20220131182145.236005-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Emil Renner Berthing --- arch/riscv/kernel/module.c | 93 ++++++++++++++++---------------------- 1 file changed, 39 insertions(+), 54 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 2212d88776e0..e371977aecfd 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -298,24 +298,23 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char = *strtab, unsigned int symindex, unsigned int relsec, struct module *me) { - Elf_Rela *rel =3D (void *) sechdrs[relsec].sh_addr; - int (*handler)(struct module *me, void *location, Elf_Addr v); - Elf_Sym *sym; - void *location; - unsigned int i, type; - Elf_Addr v; - int res; + Elf_Rela *rel =3D (void *)sechdrs[relsec].sh_addr; + unsigned int entries =3D sechdrs[relsec].sh_size / sizeof(*rel); + unsigned int i; =20 pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); =20 - for (i =3D 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location =3D (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to */ - sym =3D (Elf_Sym *)sechdrs[symindex].sh_addr + for (i =3D 0; i < entries; i++) { + Elf_Sym *sym =3D (Elf_Sym *)sechdrs[symindex].sh_addr + ELF_RISCV_R_SYM(rel[i].r_info); + Elf_Addr loc =3D sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + unsigned int type =3D ELF_RISCV_R_TYPE(rel[i].r_info); + int (*handler)(struct module *me, void *location, Elf_Addr v); + Elf_Addr v; + int res; + if (IS_ERR_VALUE(sym->st_value)) { /* Ignore unresolved weak symbol */ if (ELF_ST_BIND(sym->st_info) =3D=3D STB_WEAK) @@ -325,8 +324,6 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *s= trtab, return -ENOENT; } =20 - type =3D ELF_RISCV_R_TYPE(rel[i].r_info); - if (type < ARRAY_SIZE(reloc_handlers_rela)) handler =3D reloc_handlers_rela[type]; else @@ -343,48 +340,36 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char = *strtab, if (type =3D=3D R_RISCV_PCREL_LO12_I || type =3D=3D R_RISCV_PCREL_LO12_S= ) { unsigned int j; =20 - for (j =3D 0; j < sechdrs[relsec].sh_size / sizeof(*rel); j++) { - unsigned long hi20_loc =3D - sechdrs[sechdrs[relsec].sh_info].sh_addr + /* find the corresponding HI20 entry */ + for (j =3D 0; j < entries; j++) { + Elf_Sym *hi20_sym =3D (Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_RISCV_R_SYM(rel[j].r_info); + Elf_Addr hi20_loc =3D sechdrs[sechdrs[relsec].sh_info].sh_addr + rel[j].r_offset; - u32 hi20_type =3D ELF_RISCV_R_TYPE(rel[j].r_info); - - /* Find the corresponding HI20 relocation entry */ - if (hi20_loc =3D=3D sym->st_value - && (hi20_type =3D=3D R_RISCV_PCREL_HI20 - || hi20_type =3D=3D R_RISCV_GOT_HI20)) { - s32 hi20, lo12; - Elf_Sym *hi20_sym =3D - (Elf_Sym *)sechdrs[symindex].sh_addr - + ELF_RISCV_R_SYM(rel[j].r_info); - unsigned long hi20_sym_val =3D - hi20_sym->st_value - + rel[j].r_addend; - - /* Calculate lo12 */ - size_t offset =3D hi20_sym_val - hi20_loc; - if (IS_ENABLED(CONFIG_MODULE_SECTIONS) - && hi20_type =3D=3D R_RISCV_GOT_HI20) { - offset =3D module_emit_got_entry( - me, hi20_sym_val); - offset =3D offset - hi20_loc; - } - hi20 =3D (offset + 0x800) & 0xfffff000; - lo12 =3D offset - hi20; - v =3D lo12; - - break; - } - } - if (j =3D=3D sechdrs[relsec].sh_size / sizeof(*rel)) { - pr_err( - "%s: Can not find HI20 relocation information\n", - me->name); - return -EINVAL; + unsigned int hi20_type =3D ELF_RISCV_R_TYPE(rel[j].r_info); + + if (hi20_loc !=3D sym->st_value || + (hi20_type !=3D R_RISCV_PCREL_HI20 && + hi20_type !=3D R_RISCV_GOT_HI20)) + continue; + + /* calculate relative offset */ + v =3D hi20_sym->st_value + rel[j].r_addend; + + if (IS_ENABLED(CONFIG_MODULE_SECTIONS) && + hi20_type =3D=3D R_RISCV_GOT_HI20) + v =3D module_emit_got_entry(me, v); + + v -=3D hi20_loc; + goto handle_reloc; } - } =20 - res =3D handler(me, location, v); + pr_err("%s: Cannot find HI20 relocation information\n", + me->name); + return -EINVAL; + } +handle_reloc: + res =3D handler(me, (void *)loc, v); if (res) return res; } --=20 2.35.1