From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D59C433FE for ; Fri, 28 Jan 2022 20:29:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351193AbiA1U30 (ORCPT ); Fri, 28 Jan 2022 15:29:26 -0500 Received: from mga02.intel.com ([134.134.136.20]:61402 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351179AbiA1U3X (ORCPT ); Fri, 28 Jan 2022 15:29:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401763; x=1674937763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qX917cPwwlO8dZZek3e7j9ci/IfNoJH+hK5O82lWRfk=; b=lWK/UtObQ4wVEdYtHdBwGWWLbfuEsZLiTJTTlQpHNS/J8yt4AZCqc40O yAc6oJzcfUVl7DBx7aXZ1WylchoHNx3cCkIGYqYBj60LkBLyt0L8TMF9V YCFqy+tYWzh8HaRPhUBCpXly7JAzKip1fPT7Y/OIx09GHCimg9VSgoZyV w+HjUs/ezar+qOE8se59CIe2ajYAuguc51s34oVTjrR7Q6ynEJyN02F6T /Bzo7cVc12wodUgeM9/p3D0CvPBigQWXOQYEf9w+dbz/19t9aceaIS/ll 02vJfhtIOWZV9HvnT3k7FHynsCfjhePG2GKSaeqztnFpToD1QE9LyqjjW A==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="234578000" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578000" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827688" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:21 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 01/11] iommu/sva: Rename CONFIG_IOMMU_SVA_LIB to CONFIG_IOMMU_SVA Date: Fri, 28 Jan 2022 12:28:55 -0800 Message-Id: <20220128202905.2274672-2-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This CONFIG option originally only referred to the Shared Virtual Address (SVA) library. But it is now also used for non-library portions of code. Drop the "_LIB" suffix so that there is just one configuration options for all code relating to SVA. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Reviewed-by: Thomas Gleixner --- v2: - Add this patch for more meaningful name CONFIG_IOMMU_SVA drivers/iommu/Kconfig | 6 +++--- drivers/iommu/Makefile | 2 +- drivers/iommu/intel/Kconfig | 2 +- drivers/iommu/iommu-sva-lib.h | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 3eb68fa1b8cc..c79a0df090c0 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -144,8 +144,8 @@ config IOMMU_DMA select IRQ_MSI_IOMMU select NEED_SG_DMA_LENGTH =20 -# Shared Virtual Addressing library -config IOMMU_SVA_LIB +# Shared Virtual Addressing +config IOMMU_SVA bool select IOASID =20 @@ -379,7 +379,7 @@ config ARM_SMMU_V3 config ARM_SMMU_V3_SVA bool "Shared Virtual Addressing support for the ARM SMMUv3" depends on ARM_SMMU_V3 - select IOMMU_SVA_LIB + select IOMMU_SVA select MMU_NOTIFIER help Support for sharing process address spaces with devices using the diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index bc7f730edbb0..44475a9b3eea 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -27,6 +27,6 @@ obj-$(CONFIG_FSL_PAMU) +=3D fsl_pamu.o fsl_pamu_domain.o obj-$(CONFIG_S390_IOMMU) +=3D s390-iommu.o obj-$(CONFIG_HYPERV_IOMMU) +=3D hyperv-iommu.o obj-$(CONFIG_VIRTIO_IOMMU) +=3D virtio-iommu.o -obj-$(CONFIG_IOMMU_SVA_LIB) +=3D iommu-sva-lib.o io-pgfault.o +obj-$(CONFIG_IOMMU_SVA) +=3D iommu-sva-lib.o io-pgfault.o obj-$(CONFIG_SPRD_IOMMU) +=3D sprd-iommu.o obj-$(CONFIG_APPLE_DART) +=3D apple-dart.o diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig index 247d0f2d5fdf..39a06d245f12 100644 --- a/drivers/iommu/intel/Kconfig +++ b/drivers/iommu/intel/Kconfig @@ -52,7 +52,7 @@ config INTEL_IOMMU_SVM select PCI_PRI select MMU_NOTIFIER select IOASID - select IOMMU_SVA_LIB + select IOMMU_SVA help Shared Virtual Memory (SVM) provides a facility for devices to access DMA resources through process address space by diff --git a/drivers/iommu/iommu-sva-lib.h b/drivers/iommu/iommu-sva-lib.h index 031155010ca8..95dc3ebc1928 100644 --- a/drivers/iommu/iommu-sva-lib.h +++ b/drivers/iommu/iommu-sva-lib.h @@ -17,7 +17,7 @@ struct device; struct iommu_fault; struct iopf_queue; =20 -#ifdef CONFIG_IOMMU_SVA_LIB +#ifdef CONFIG_IOMMU_SVA int iommu_queue_iopf(struct iommu_fault *fault, void *cookie); =20 int iopf_queue_add_device(struct iopf_queue *queue, struct device *dev); @@ -28,7 +28,7 @@ struct iopf_queue *iopf_queue_alloc(const char *name); void iopf_queue_free(struct iopf_queue *queue); int iopf_queue_discard_partial(struct iopf_queue *queue); =20 -#else /* CONFIG_IOMMU_SVA_LIB */ +#else /* CONFIG_IOMMU_SVA */ static inline int iommu_queue_iopf(struct iommu_fault *fault, void *cookie) { return -ENODEV; @@ -64,5 +64,5 @@ static inline int iopf_queue_discard_partial(struct iopf_= queue *queue) { return -ENODEV; } -#endif /* CONFIG_IOMMU_SVA_LIB */ +#endif /* CONFIG_IOMMU_SVA */ #endif /* _IOMMU_SVA_LIB_H */ --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E991C433EF for ; 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a="234578001" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578001" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827691" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:21 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 02/11] mm: Change CONFIG option for mm->pasid field Date: Fri, 28 Jan 2022 12:28:56 -0800 Message-Id: <20220128202905.2274672-3-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This currently depends on CONFIG_IOMMU_SUPPORT. But it is only needed when CONFIG_IOMMU_SVA option is enabled. Change the CONFIG guards around definition and initialization of mm->pasid field. Suggested-by: Jacob Pan Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change condition to more accurate CONFIG_IOMMU_SVA (Jacob and Tony) include/linux/mm_types.h | 2 +- kernel/fork.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index 9db36dc5d4cf..c959116abd95 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -630,7 +630,7 @@ struct mm_struct { #endif struct work_struct async_put_work; =20 -#ifdef CONFIG_IOMMU_SUPPORT +#ifdef CONFIG_IOMMU_SVA u32 pasid; #endif } __randomize_layout; diff --git a/kernel/fork.c b/kernel/fork.c index d75a528f7b21..6ee7551d3bd2 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1021,7 +1021,7 @@ static void mm_init_owner(struct mm_struct *mm, struc= t task_struct *p) =20 static void mm_init_pasid(struct mm_struct *mm) { -#ifdef CONFIG_IOMMU_SUPPORT +#ifdef CONFIG_IOMMU_SVA mm->pasid =3D INIT_PASID; #endif } --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3D5BC4332F for ; Fri, 28 Jan 2022 20:29:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351270AbiA1U3a (ORCPT ); Fri, 28 Jan 2022 15:29:30 -0500 Received: from mga02.intel.com ([134.134.136.20]:61402 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351189AbiA1U3X (ORCPT ); Fri, 28 Jan 2022 15:29:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401763; x=1674937763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Bqxtojtmx5tWusYvxR//2iaQnYjgCUiRMbM+LXacmWg=; b=XKs8FwdYe8GPtgq0CZ8O01d/+EKkABzUde4lnEz6PGPxuQfnazpATNZv BrECuxMoBLHPO2EdOfojyv4sRYFmEslYfDCmOyItPnkyE3A/anbHidQXK vMidY0Jw/wq3+HSdRgfCNy7ZQXvS2oZxudy9DqCIKrQzbznw4U+fwySRj kdDGjJMoUhpcBoyYFdgW2aA+PZzpGmvFI+6/kO/LFPvAvNqtUwARWVIQ6 /rZfYFFlEM6O8l0z8zNLB3ZmQti4cfEVKI5VKqcJTxLoN82n+7u4csg+f +LY3ngU5ASO5lPY5tzejYXv+W3+HSvm6BjSDsWQ9K3/j74PRj3NAd+eEd g==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="234578002" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578002" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827694" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:22 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 03/11] iommu/ioasid: Introduce a helper to check for valid PASIDs Date: Fri, 28 Jan 2022 12:28:57 -0800 Message-Id: <20220128202905.2274672-4-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" pasid_valid() is defined to check if a given PASID is valid. Suggested-by: Ashok Raj Suggested-by: Jacob Pan Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Define a helper pasid_valid() (Ashok, Jacob, Thomas, Tony) include/linux/ioasid.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/ioasid.h b/include/linux/ioasid.h index e9dacd4b9f6b..2237f64dbaae 100644 --- a/include/linux/ioasid.h +++ b/include/linux/ioasid.h @@ -41,6 +41,10 @@ void *ioasid_find(struct ioasid_set *set, ioasid_t ioasi= d, int ioasid_register_allocator(struct ioasid_allocator_ops *allocator); void ioasid_unregister_allocator(struct ioasid_allocator_ops *allocator); int ioasid_set_data(ioasid_t ioasid, void *data); +static inline bool pasid_valid(ioasid_t ioasid) +{ + return ioasid !=3D INVALID_IOASID; +} =20 #else /* !CONFIG_IOASID */ static inline ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, @@ -78,5 +82,10 @@ static inline int ioasid_set_data(ioasid_t ioasid, void = *data) return -ENOTSUPP; } =20 +static inline bool pasid_valid(ioasid_t ioasid) +{ + return false; +} + #endif /* CONFIG_IOASID */ #endif /* __LINUX_IOASID_H */ --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2FC0C433F5 for ; Fri, 28 Jan 2022 20:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245393AbiA1U3i (ORCPT ); Fri, 28 Jan 2022 15:29:38 -0500 Received: from mga02.intel.com ([134.134.136.20]:61403 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351196AbiA1U3Y (ORCPT ); Fri, 28 Jan 2022 15:29:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401764; x=1674937764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h/z7DIvY0MTiK7Nx1uAnK2xPJLWu1xE6aEWz78v/hWE=; b=UI3rfCINPt8wQugche2sIllP2YHlCcxOlmc+i8eapq1Bji/VaBqR2DaV zb4QufbSW3p57Kj1egO9LdZgSz5+bHhX9w9d1Li1QaODAVI5/mrzLs4Tq 51QdEJOa1tZ8woHv8844Kc14QMNOf4M6xJtYAqPzSod1ncdTUXNefKhl1 EHizSqcgCJ0matFtVrlu3lAU8453apKDfupIYhELH1HiwebiYDLgJT6bh cLvY7x5cG3igmDYUMH20vFKizs2pVxw2Au6iLIJWp1nD+1y5ACtmzb2zI yAB6Q78M0l28mzWNpo/P8O2xl6BrDC2TLXyJjgLOPzWFCnDlaSeKA6yb6 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="234578005" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578005" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827697" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:22 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 04/11] kernel/fork: Initialize mm's PASID Date: Fri, 28 Jan 2022 12:28:58 -0800 Message-Id: <20220128202905.2274672-5-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" A new mm doesn't have a PASID yet when it's created. Initialize the mm's PASID on fork() or for init_mm to INVALID_IOASID (-1). Suggested-by: Dave Hansen Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change condition to more accurate CONFIG_IOMMU_SVA (Jacob) include/linux/sched/mm.h | 10 ++++++++++ kernel/fork.c | 10 ++-------- mm/init-mm.c | 4 ++++ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h index aa5f09ca5bcf..c74d1edbac2f 100644 --- a/include/linux/sched/mm.h +++ b/include/linux/sched/mm.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 /* * Routines for handling mm_structs @@ -433,4 +434,13 @@ static inline void membarrier_update_current_mm(struct= mm_struct *next_mm) } #endif =20 +#ifdef CONFIG_IOMMU_SVA +static inline void mm_pasid_init(struct mm_struct *mm) +{ + mm->pasid =3D INVALID_IOASID; +} +#else +static inline void mm_pasid_init(struct mm_struct *mm) {} +#endif + #endif /* _LINUX_SCHED_MM_H */ diff --git a/kernel/fork.c b/kernel/fork.c index 6ee7551d3bd2..deacd2c17a7f 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -97,6 +97,7 @@ #include #include #include +#include =20 #include #include @@ -1019,13 +1020,6 @@ static void mm_init_owner(struct mm_struct *mm, stru= ct task_struct *p) #endif } =20 -static void mm_init_pasid(struct mm_struct *mm) -{ -#ifdef CONFIG_IOMMU_SVA - mm->pasid =3D INIT_PASID; -#endif -} - static void mm_init_uprobes_state(struct mm_struct *mm) { #ifdef CONFIG_UPROBES @@ -1054,7 +1048,7 @@ static struct mm_struct *mm_init(struct mm_struct *mm= , struct task_struct *p, mm_init_cpumask(mm); mm_init_aio(mm); mm_init_owner(mm, p); - mm_init_pasid(mm); + mm_pasid_init(mm); RCU_INIT_POINTER(mm->exe_file, NULL); mmu_notifier_subscriptions_init(mm); init_tlb_flush_pending(mm); diff --git a/mm/init-mm.c b/mm/init-mm.c index b4a6f38fb51d..fbe7844d0912 100644 --- a/mm/init-mm.c +++ b/mm/init-mm.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include =20 #ifndef INIT_MM_CONTEXT @@ -38,6 +39,9 @@ struct mm_struct init_mm =3D { .mmlist =3D LIST_HEAD_INIT(init_mm.mmlist), .user_ns =3D &init_user_ns, .cpu_bitmap =3D CPU_BITS_NONE, +#ifdef CONFIG_IOMMU_SVA + .pasid =3D INVALID_IOASID, +#endif INIT_MM_CONTEXT(init_mm) }; =20 --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 377B7C433EF for ; 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a="234578006" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578006" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827700" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:22 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 05/11] iommu/sva: Assign a PASID to mm on PASID allocation and free it on mm exit Date: Fri, 28 Jan 2022 12:28:59 -0800 Message-Id: <20220128202905.2274672-6-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To avoid complexity of updating each thread's PASID status (e.g. sending IPI to update IA32_PASID MSR) on allocating and freeing PASID, once allocated and assigned to an mm, the PASID stays with the mm for the rest of the mm's lifetime. A reference to the PASID is taken on allocating the PASID. Binding/unbinding the PASID won't change refcount. The reference is dropped on mm exit and thus the PASID is freed. Two helpers mm_pasid_set() and mm_pasid_drop() are defined in mm because the PASID operations handle the pasid member in mm_struct and should be part of mm operations. Because IOASID's reference count is not used any more and removed, unused ioasid_get() and iommu_sva_free_pasid() are deleted and ioasid_put() is renamed to ioasid_free(). 20-bit PASID allows up to 1M processes bound to PASIDs at the same time. With cgroups and other controls that might limit the number of process creation, the limited number of PASIDs is not a realistic issue for lazy PASID free. Suggested-by: Dave Hansen Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v3: - Rename mm_pasid_get() to mm_pasid_set() (Thomas). - Remove ioasid_get() because it's not used any more when the IOASID is freed on mm exit (Thomas). - Remove PASID's refcount exercise in ioasid_put() and rename ioasid_put() to ioasid_free() (Thomas). v2: - Free PASID on mm exit instead of in exit(2) or unbind() (Thomas, AndyL, PeterZ) - Add mm_pasid_init(), mm_pasid_get(), and mm_pasid_drop() functions in mm. So the mm's PASID operations are generic for both X86 and ARM (Dave Hansen) .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +-- drivers/iommu/intel/iommu.c | 4 +- drivers/iommu/intel/svm.c | 9 ----- drivers/iommu/ioasid.c | 38 ++---------------- drivers/iommu/iommu-sva-lib.c | 39 ++++++------------- drivers/iommu/iommu-sva-lib.h | 1 - include/linux/ioasid.h | 12 +----- include/linux/sched/mm.h | 16 ++++++++ kernel/fork.c | 1 + 9 files changed, 38 insertions(+), 87 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index a737ba5f727e..22ddd05bbdcd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -340,14 +340,12 @@ __arm_smmu_sva_bind(struct device *dev, struct mm_str= uct *mm) bond->smmu_mn =3D arm_smmu_mmu_notifier_get(smmu_domain, mm); if (IS_ERR(bond->smmu_mn)) { ret =3D PTR_ERR(bond->smmu_mn); - goto err_free_pasid; + goto err_free_bond; } =20 list_add(&bond->list, &master->bonds); return &bond->sva; =20 -err_free_pasid: - iommu_sva_free_pasid(mm); err_free_bond: kfree(bond); return ERR_PTR(ret); @@ -377,7 +375,6 @@ void arm_smmu_sva_unbind(struct iommu_sva *handle) if (refcount_dec_and_test(&bond->refs)) { list_del(&bond->list); arm_smmu_mmu_notifier_put(bond->smmu_mn); - iommu_sva_free_pasid(bond->mm); kfree(bond); } mutex_unlock(&sva_lock); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 92fea3fbbb11..ef03b2176bbd 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4781,7 +4781,7 @@ static int aux_domain_add_dev(struct dmar_domain *dom= ain, link_failed: spin_unlock_irqrestore(&device_domain_lock, flags); if (list_empty(&domain->subdevices) && domain->default_pasid > 0) - ioasid_put(domain->default_pasid); + ioasid_free(domain->default_pasid); =20 return ret; } @@ -4811,7 +4811,7 @@ static void aux_domain_remove_dev(struct dmar_domain = *domain, spin_unlock_irqrestore(&device_domain_lock, flags); =20 if (list_empty(&domain->subdevices) && domain->default_pasid > 0) - ioasid_put(domain->default_pasid); + ioasid_free(domain->default_pasid); } =20 static int prepare_domain_attach_device(struct iommu_domain *domain, diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 5b5d69b04fcc..51ac2096b3da 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -514,11 +514,6 @@ static int intel_svm_alloc_pasid(struct device *dev, s= truct mm_struct *mm, return iommu_sva_alloc_pasid(mm, PASID_MIN, max_pasid - 1); } =20 -static void intel_svm_free_pasid(struct mm_struct *mm) -{ - iommu_sva_free_pasid(mm); -} - static struct iommu_sva *intel_svm_bind_mm(struct intel_iommu *iommu, struct device *dev, struct mm_struct *mm, @@ -662,8 +657,6 @@ static int intel_svm_unbind_mm(struct device *dev, u32 = pasid) kfree(svm); } } - /* Drop a PASID reference and free it if no reference. */ - intel_svm_free_pasid(mm); } out: return ret; @@ -1047,8 +1040,6 @@ struct iommu_sva *intel_svm_bind(struct device *dev, = struct mm_struct *mm, void } =20 sva =3D intel_svm_bind_mm(iommu, dev, mm, flags); - if (IS_ERR_OR_NULL(sva)) - intel_svm_free_pasid(mm); mutex_unlock(&pasid_mutex); =20 return sva; diff --git a/drivers/iommu/ioasid.c b/drivers/iommu/ioasid.c index 50ee27bbd04e..a786c034907c 100644 --- a/drivers/iommu/ioasid.c +++ b/drivers/iommu/ioasid.c @@ -2,7 +2,7 @@ /* * I/O Address Space ID allocator. There is one global IOASID space, split= into * subsets. Users create a subset with DECLARE_IOASID_SET, then allocate a= nd - * free IOASIDs with ioasid_alloc and ioasid_put. + * free IOASIDs with ioasid_alloc() and ioasid_free(). */ #include #include @@ -15,7 +15,6 @@ struct ioasid_data { struct ioasid_set *set; void *private; struct rcu_head rcu; - refcount_t refs; }; =20 /* @@ -315,7 +314,6 @@ ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t = min, ioasid_t max, =20 data->set =3D set; data->private =3D private; - refcount_set(&data->refs, 1); =20 /* * Custom allocator needs allocator data to perform platform specific @@ -348,34 +346,11 @@ ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_= t min, ioasid_t max, EXPORT_SYMBOL_GPL(ioasid_alloc); =20 /** - * ioasid_get - obtain a reference to the IOASID - */ -void ioasid_get(ioasid_t ioasid) -{ - struct ioasid_data *ioasid_data; - - spin_lock(&ioasid_allocator_lock); - ioasid_data =3D xa_load(&active_allocator->xa, ioasid); - if (ioasid_data) - refcount_inc(&ioasid_data->refs); - else - WARN_ON(1); - spin_unlock(&ioasid_allocator_lock); -} -EXPORT_SYMBOL_GPL(ioasid_get); - -/** - * ioasid_put - Release a reference to an ioasid + * ioasid_free - Free an ioasid * @ioasid: the ID to remove - * - * Put a reference to the IOASID, free it when the number of references dr= ops to - * zero. - * - * Return: %true if the IOASID was freed, %false otherwise. */ -bool ioasid_put(ioasid_t ioasid) +void ioasid_free(ioasid_t ioasid) { - bool free =3D false; struct ioasid_data *ioasid_data; =20 spin_lock(&ioasid_allocator_lock); @@ -385,10 +360,6 @@ bool ioasid_put(ioasid_t ioasid) goto exit_unlock; } =20 - free =3D refcount_dec_and_test(&ioasid_data->refs); - if (!free) - goto exit_unlock; - active_allocator->ops->free(ioasid, active_allocator->ops->pdata); /* Custom allocator needs additional steps to free the xa element */ if (active_allocator->flags & IOASID_ALLOCATOR_CUSTOM) { @@ -398,9 +369,8 @@ bool ioasid_put(ioasid_t ioasid) =20 exit_unlock: spin_unlock(&ioasid_allocator_lock); - return free; } -EXPORT_SYMBOL_GPL(ioasid_put); +EXPORT_SYMBOL_GPL(ioasid_free); =20 /** * ioasid_find - Find IOASID data diff --git a/drivers/iommu/iommu-sva-lib.c b/drivers/iommu/iommu-sva-lib.c index bd41405d34e9..106506143896 100644 --- a/drivers/iommu/iommu-sva-lib.c +++ b/drivers/iommu/iommu-sva-lib.c @@ -18,8 +18,7 @@ static DECLARE_IOASID_SET(iommu_sva_pasid); * * Try to allocate a PASID for this mm, or take a reference to the existin= g one * provided it fits within the [@min, @max] range. On success the PASID is - * available in mm->pasid, and must be released with iommu_sva_free_pasid(= ). - * @min must be greater than 0, because 0 indicates an unused mm->pasid. + * available in mm->pasid and will be available for the lifetime of the mm. * * Returns 0 on success and < 0 on error. */ @@ -33,38 +32,24 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_= t min, ioasid_t max) return -EINVAL; =20 mutex_lock(&iommu_sva_lock); - if (mm->pasid) { - if (mm->pasid >=3D min && mm->pasid <=3D max) - ioasid_get(mm->pasid); - else + /* Is a PASID already associated with this mm? */ + if (pasid_valid(mm->pasid)) { + if (mm->pasid < min || mm->pasid >=3D max) ret =3D -EOVERFLOW; - } else { - pasid =3D ioasid_alloc(&iommu_sva_pasid, min, max, mm); - if (pasid =3D=3D INVALID_IOASID) - ret =3D -ENOMEM; - else - mm->pasid =3D pasid; + goto out; } + + pasid =3D ioasid_alloc(&iommu_sva_pasid, min, max, mm); + if (!pasid_valid(pasid)) + ret =3D -ENOMEM; + else + mm_pasid_set(mm, pasid); +out: mutex_unlock(&iommu_sva_lock); return ret; } EXPORT_SYMBOL_GPL(iommu_sva_alloc_pasid); =20 -/** - * iommu_sva_free_pasid - Release the mm's PASID - * @mm: the mm - * - * Drop one reference to a PASID allocated with iommu_sva_alloc_pasid() - */ -void iommu_sva_free_pasid(struct mm_struct *mm) -{ - mutex_lock(&iommu_sva_lock); - if (ioasid_put(mm->pasid)) - mm->pasid =3D 0; - mutex_unlock(&iommu_sva_lock); -} -EXPORT_SYMBOL_GPL(iommu_sva_free_pasid); - /* ioasid_find getter() requires a void * argument */ static bool __mmget_not_zero(void *mm) { diff --git a/drivers/iommu/iommu-sva-lib.h b/drivers/iommu/iommu-sva-lib.h index 95dc3ebc1928..8909ea1094e3 100644 --- a/drivers/iommu/iommu-sva-lib.h +++ b/drivers/iommu/iommu-sva-lib.h @@ -9,7 +9,6 @@ #include =20 int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max= ); -void iommu_sva_free_pasid(struct mm_struct *mm); struct mm_struct *iommu_sva_find(ioasid_t pasid); =20 /* I/O Page fault */ diff --git a/include/linux/ioasid.h b/include/linux/ioasid.h index 2237f64dbaae..af1c9d62e642 100644 --- a/include/linux/ioasid.h +++ b/include/linux/ioasid.h @@ -34,8 +34,7 @@ struct ioasid_allocator_ops { #if IS_ENABLED(CONFIG_IOASID) ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max, void *private); -void ioasid_get(ioasid_t ioasid); -bool ioasid_put(ioasid_t ioasid); +void ioasid_free(ioasid_t ioasid); void *ioasid_find(struct ioasid_set *set, ioasid_t ioasid, bool (*getter)(void *)); int ioasid_register_allocator(struct ioasid_allocator_ops *allocator); @@ -53,14 +52,7 @@ static inline ioasid_t ioasid_alloc(struct ioasid_set *s= et, ioasid_t min, return INVALID_IOASID; } =20 -static inline void ioasid_get(ioasid_t ioasid) -{ -} - -static inline bool ioasid_put(ioasid_t ioasid) -{ - return false; -} +static inline void ioasid_free(ioasid_t ioasid) { } =20 static inline void *ioasid_find(struct ioasid_set *set, ioasid_t ioasid, bool (*getter)(void *)) diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h index c74d1edbac2f..a80356e9dc69 100644 --- a/include/linux/sched/mm.h +++ b/include/linux/sched/mm.h @@ -439,8 +439,24 @@ static inline void mm_pasid_init(struct mm_struct *mm) { mm->pasid =3D INVALID_IOASID; } + +/* Associate a PASID with an mm_struct: */ +static inline void mm_pasid_set(struct mm_struct *mm, u32 pasid) +{ + mm->pasid =3D pasid; +} + +static inline void mm_pasid_drop(struct mm_struct *mm) +{ + if (pasid_valid(mm->pasid)) { + ioasid_free(mm->pasid); + mm->pasid =3D INVALID_IOASID; + } +} #else static inline void mm_pasid_init(struct mm_struct *mm) {} +static inline void mm_pasid_set(struct mm_struct *mm, u32 pasid) {} +static inline void mm_pasid_drop(struct mm_struct *mm) {} #endif =20 #endif /* _LINUX_SCHED_MM_H */ diff --git a/kernel/fork.c b/kernel/fork.c index deacd2c17a7f..c03c6682464c 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1115,6 +1115,7 @@ static inline void __mmput(struct mm_struct *mm) } if (mm->binfmt) module_put(mm->binfmt->module); + mm_pasid_drop(mm); mmdrop(mm); } =20 --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9710FC433F5 for ; Fri, 28 Jan 2022 20:29:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351302AbiA1U3t (ORCPT ); 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28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827703" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:22 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 06/11] x86/fpu: Clear PASID when copying fpstate Date: Fri, 28 Jan 2022 12:29:00 -0800 Message-Id: <20220128202905.2274672-7-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kernel must allocate a Process Address Space ID (PASID) on behalf of each process which will use ENQCMD and program it into the new MSR to communicate the process identity to platform hardware. ENQCMD uses the PASID stored in this MSR to tag requests from this process. The PASID state must be cleared on fork() since fork creates a new address space. For clone(), it would be functionally OK to copy the PASID. However, clearing it is _also_ functionally OK since any PASID use will trigger the #GP handler to populate the MSR. Copying the PASID state has two main downsides: * It requires differentiating fork() and clone() in the code, both in the FPU code and keeping tsk->pasid_activated consistent. * It guarantees that the PASID is out of its init state, which incurs small but non-zero cost on every XSAVE/XRSTOR. The main downside of clearing the PASID at fpstate copy is the future, one-time #GP for the thread. Use the simplest approach: clear the PASID state both on clone() and fork(). Rely on the #GP handler for MSR population in children. Also, just clear the PASID bit from xfeatures if XSAVE is supported. This will have no effect on systems that do not have PASID support. It is virtually zero overhead because 'dst_fpu' was just written and the whole thing is cache hot. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Rewrite changelog (Dave Hansen). - Move xfeature tweaking into fpu_clone() and make it unconditional if XSAVE is supported (Dave Hansen). arch/x86/kernel/fpu/core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 8dea01ffc5c1..19821f027cb3 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -612,6 +612,13 @@ int fpu_clone(struct task_struct *dst, unsigned long c= lone_flags) fpu_inherit_perms(dst_fpu); fpregs_unlock(); =20 + /* + * Children never inherit PASID state. + * Force it to have its init value: + */ + if (use_xsave()) + dst_fpu->fpstate->regs.xsave.header.xfeatures &=3D ~XFEATURE_MASK_PASID; + trace_x86_fpu_copy_src(src_fpu); trace_x86_fpu_copy_dst(dst_fpu); =20 --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9247C433EF for ; Fri, 28 Jan 2022 20:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351404AbiA1U3w (ORCPT ); Fri, 28 Jan 2022 15:29:52 -0500 Received: from mga02.intel.com ([134.134.136.20]:61402 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351204AbiA1U3Y (ORCPT ); Fri, 28 Jan 2022 15:29:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401764; x=1674937764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xDQdQWuDTNQebXOoM6D02Rc8q/BYhAiS+q/XkCoK6F4=; b=i1plt4OhLMJ85KzTGU/cGGwV3DNaKV8y9OKSg4pFdsWApLmErHvUVBIK 20l75JR5tLv3iYg7ldj+5TPl7zJG9uK23q5Knz26JtBwYWDaEk5qSMNbf lwFCA2PazYn7iRsTvSS9gnxLxp1jg7sfiCPGxhTDUJI3NSzLUj7aeKwQu bX5vOE+TwxxErQ+yfS9+QAQ7kxIzEsaLYW2w28h4lfj3KvdsCmNsZ1Pww OGHSHZ3d5XYWt6sMDDXLenQbYfDb4rvkxmd1dPgQCdM6wgZk3wRYx4Gqg lyQGTsj04kQ2bvmMXb/nUZJXhA3TlNV8R3FBSekm/YcCS6BOTDvKzUqll A==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="234578010" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578010" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827707" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:22 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 07/11] sched: Define and initialize a flag to identify valid PASID in the task Date: Fri, 28 Jan 2022 12:29:01 -0800 Message-Id: <20220128202905.2274672-8-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Peter Zijlstra Add a new single bit field to the task structure to track whether this task has initialized the IA32_PASID MSR to the mm's PASID. Initialize the field to zero when creating a new task with fork/clone. Signed-off-by: Peter Zijlstra Co-developed-by: Fenghua Yu Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change condition to more accurate CONFIG_IOMMU_SVA (Jacob) include/linux/sched.h | 3 +++ kernel/fork.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/include/linux/sched.h b/include/linux/sched.h index f5b2be39a78c..812e40c5bde5 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -938,6 +938,9 @@ struct task_struct { /* Recursion prevention for eventfd_signal() */ unsigned in_eventfd_signal:1; #endif +#ifdef CONFIG_IOMMU_SVA + unsigned pasid_activated:1; +#endif =20 unsigned long atomic_flags; /* Flags requiring atomic access. */ =20 diff --git a/kernel/fork.c b/kernel/fork.c index c03c6682464c..51fd1df994b7 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -968,6 +968,10 @@ static struct task_struct *dup_task_struct(struct task= _struct *orig, int node) tsk->use_memdelay =3D 0; #endif =20 +#ifdef CONFIG_IOMMU_SVA + tsk->pasid_activated =3D 0; +#endif + #ifdef CONFIG_MEMCG tsk->active_memcg =3D NULL; #endif --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16F7BC433EF for ; Fri, 28 Jan 2022 20:29:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351421AbiA1U3y (ORCPT ); Fri, 28 Jan 2022 15:29:54 -0500 Received: from mga02.intel.com ([134.134.136.20]:61407 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351190AbiA1U3Y (ORCPT ); Fri, 28 Jan 2022 15:29:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401764; x=1674937764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jUmhLCHJPiqhmaaqrTsN4KWS/+AZ+jsPvivdmM8ieFY=; b=nAqBN1pFHjse/39b2n6f6r9bvy79h2qiKtkuEsdfh8d5CpTFp13oHDIK sCkX0hRoElRg1pDbkoMNrgE47FRJM9/RshKIwT1w5qzC/20I4uj3Rqo+d J1u7OTcFML/WcPkMFSLAs1tXmPr/hJf1wSrMvhjsNn91v9u61zrLt65Dk 1SyG2YO/cd8ost5bGCzYtLUpFacbNC/8skIurICFbccy+j4WII+VzHqIv MK/RjE/oM4EM6YuxKYC9lJYFxGvGLWzNoz4Uc2KYx8mbU/s9Y9/XCs9IF VxNxfTE7UTC0rPX+SJig13LMZ4vfZUG0lHB88tdKkvai4NDn8VxvL5NF1 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="234578012" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578012" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827709" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:23 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 08/11] x86/traps: Demand-populate PASID MSR via #GP Date: Fri, 28 Jan 2022 12:29:02 -0800 Message-Id: <20220128202905.2274672-9-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All tasks start with PASID state disabled. This means that the first time they execute an ENQCMD instruction they will take a #GP fault. Modify the #GP fault handler to check if the "mm" for the task has already been allocated a PASID. If so, try to fix the #GP fault by loading the IA32_PASID MSR. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Directly write IA32_PASID MSR in fixup while local IRQ is still disabled (Thomas) - Move #ifdef over to CONFIG_IOMMU_SVA since it is what defines mm->pasid and ->pasid_activated (Dave Hansen). - Rename try_fixup_pasid() -> try_fixup_enqcmd_gp(). This code really is highly specific to ENQCMD, not PASIDs (Dave Hansen). - Add lockdep assert and comment about context (Dave Hansen). - Re-flow the if() mess (Dave Hansen). arch/x86/kernel/traps.c | 55 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c9d566dcf89a..7ef00dee35be 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -39,6 +39,7 @@ #include #include #include +#include =20 #include #include @@ -559,6 +560,57 @@ static bool fixup_iopl_exception(struct pt_regs *regs) return true; } =20 +/* + * The unprivileged ENQCMD instruction generates #GPs if the + * IA32_PASID MSR has not been populated. If possible, populate + * the MSR from a PASID previously allocated to the mm. + */ +static bool try_fixup_enqcmd_gp(void) +{ +#ifdef CONFIG_IOMMU_SVA + u32 pasid; + + /* + * MSR_IA32_PASID is managed using XSAVE. Directly + * writing to the MSR is only possible when fpregs + * are valid and the fpstate is not. This is + * guaranteed when handling a userspace exception + * in *before* interrupts are re-enabled. + */ + lockdep_assert_irqs_disabled(); + + /* + * Hardware without ENQCMD will not generate + * #GPs that can be fixed up here. + */ + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) + return false; + + pasid =3D current->mm->pasid; + + /* + * If the mm has not been allocated a + * PASID, the #GP can not be fixed up. + */ + if (!pasid_valid(pasid)) + return false; + + /* + * Did this thread already have its PASID activated? + * If so, the #GP must be from something else. + */ + if (current->pasid_activated) + return false; + + wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); + current->pasid_activated =3D 1; + + return true; +#else + return false; +#endif +} + DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) { char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] =3D GPFSTR; @@ -567,6 +619,9 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) unsigned long gp_addr; int ret; =20 + if (user_mode(regs) && try_fixup_enqcmd_gp()) + return; + cond_local_irq_enable(regs); =20 if (static_cpu_has(X86_FEATURE_UMIP)) { --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53571C433FE for ; Fri, 28 Jan 2022 20:29:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351312AbiA1U3f (ORCPT ); Fri, 28 Jan 2022 15:29:35 -0500 Received: from mga03.intel.com ([134.134.136.65]:63494 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351160AbiA1U3X (ORCPT ); Fri, 28 Jan 2022 15:29:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401763; x=1674937763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fB10nwZMIIkZgxpaLbu+h5IIsCNWZL2euG5C+O9nJak=; b=JoPRlVt1GWrH0oV/Zq43OasnIoKS1nfQeWAB6q3tDgTJugvBsKenVnbl pdR4MoI8eZNkIP0naawh2o1Tqerj1UzpSx/VoK2MnsbhYjW7olXiLjWqH CaTvd4RqnAhZFZhoDFCyJtXdebVImFONSezpOXAOlh7bcqpuvHX2sG+hA AkKfFvjIxc+QfsF8Qn6W7QcYeziso/dzuM1mlcRaLq0D8EK7wCAoCAuFF aUITJLYi4Ui84Ty6P0vdybaDzaIk0T2NdP+o3GvnXktp8x9KXgWd3HFZu S25dLxzO/kk9uX8GdM7JaLDPwBTukm3aN/GrGQp1GIlQHXLQU1/ACfzG/ Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="247142797" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="247142797" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827712" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:23 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 09/11] x86/cpufeatures: Re-enable ENQCMD Date: Fri, 28 Jan 2022 12:29:03 -0800 Message-Id: <20220128202905.2274672-10-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since ENQCMD is handled by #GP fix up, it can be re-enabled. The ENQCMD feature can only be used if CONFIG_INTEL_IOMMU_SVM is set. Add X86_FEATURE_ENQCMD to the disabled features mask as appropriate so that cpu_feature_enabled() can be used to check the feature. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Update the commit message (Tony). arch/x86/include/asm/disabled-features.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/as= m/disabled-features.h index 8f28fafa98b3..1231d63f836d 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -56,8 +56,11 @@ # define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) #endif =20 -/* Force disable because it's broken beyond repair */ -#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) +#ifdef CONFIG_INTEL_IOMMU_SVM +# define DISABLE_ENQCMD 0 +#else +# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) +#endif =20 #ifdef CONFIG_X86_SGX # define DISABLE_SGX 0 --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F646C433FE for ; Fri, 28 Jan 2022 20:29:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243563AbiA1U3o (ORCPT ); Fri, 28 Jan 2022 15:29:44 -0500 Received: from mga12.intel.com ([192.55.52.136]:39617 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351198AbiA1U3Y (ORCPT ); Fri, 28 Jan 2022 15:29:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401763; x=1674937763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zs6a0hud3tcEUziiNk3cD8a/Ewh7oEDNlHJ8E4IWhEw=; b=SmQjAXmaU8M4b4WAcvLSJTRQeRq47gv114QE8uzb5yEYNb9iPiXUj3pg 6aDY7tdOo+WgCh4PvY1GfZcJFThhQN7JCznwLpLXpgsXx2Kh1Mlxi8eg8 zhjFT7czIuQAsf62Kz9JLeRH0bfwQVheWHH/R3/rLPkKdT+N+XwwTqnGz mJ9xNq61jSUlnOEWzhfxP7eQoPYrThL2G01AwV4syoj5VGVeN1pC6QewI +U3rQZBILCof2G/FO4fXnfQ3PmqapXYvlBrXLuxZbDzYIuMog1ZgKG9tD dCmZ4ZmdvsX10V+bt8dfeE0YpZ12lP+6m4kY9+8lar5RGeORqO8WfDNim g==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="227170807" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="227170807" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827715" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:23 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 10/11] tools/objtool: Check for use of the ENQCMD instruction in the kernel Date: Fri, 28 Jan 2022 12:29:04 -0800 Message-Id: <20220128202905.2274672-11-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ENQCMD implicitly accesses the PASID_MSR to fill in the pasid field of the descriptor being submitted to an accelerator. But there is no precise (and stable across kernel changes) point at which the PASID_MSR is updated from the value for one task to the next. Kernel code that uses accelerators must always use the ENQCMDS instruction which does not access the PASID_MSR. Check for use of the ENQCMD instruction in the kernel and warn on its usage. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck Acked-by: Josh Poimboeuf --- v3: - Add Acked-by: Josh Poimboeuf v2: - Simplify handling ENQCMD (PeterZ and Josh) tools/objtool/arch/x86/decode.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decod= e.c index c10ef78df050..479e769ca324 100644 --- a/tools/objtool/arch/x86/decode.c +++ b/tools/objtool/arch/x86/decode.c @@ -112,7 +112,7 @@ int arch_decode_instruction(struct objtool_file *file, = const struct section *sec const struct elf *elf =3D file->elf; struct insn insn; int x86_64, ret; - unsigned char op1, op2, + unsigned char op1, op2, op3, rex =3D 0, rex_b =3D 0, rex_r =3D 0, rex_w =3D 0, rex_x =3D 0, modrm =3D 0, modrm_mod =3D 0, modrm_rm =3D 0, modrm_reg =3D 0, sib =3D 0, /* sib_scale =3D 0, */ sib_index =3D 0, sib_base =3D 0; @@ -139,6 +139,7 @@ int arch_decode_instruction(struct objtool_file *file, = const struct section *sec =20 op1 =3D insn.opcode.bytes[0]; op2 =3D insn.opcode.bytes[1]; + op3 =3D insn.opcode.bytes[2]; =20 if (insn.rex_prefix.nbytes) { rex =3D insn.rex_prefix.bytes[0]; @@ -491,6 +492,14 @@ int arch_decode_instruction(struct objtool_file *file,= const struct section *sec /* nopl/nopw */ *type =3D INSN_NOP; =20 + } else if (op2 =3D=3D 0x38 && op3 =3D=3D 0xf8) { + if (insn.prefixes.nbytes =3D=3D 1 && + insn.prefixes.bytes[0] =3D=3D 0xf2) { + /* ENQCMD cannot be used in the kernel. */ + WARN("ENQCMD instruction at %s:%lx", sec->name, + offset); + } + } else if (op2 =3D=3D 0xa0 || op2 =3D=3D 0xa8) { =20 /* push fs/gs */ --=20 2.35.0 From nobody Tue Jun 30 00:48:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED38BC433F5 for ; Fri, 28 Jan 2022 20:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351385AbiA1U3s (ORCPT ); Fri, 28 Jan 2022 15:29:48 -0500 Received: from mga12.intel.com ([192.55.52.136]:39617 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351203AbiA1U3Y (ORCPT ); Fri, 28 Jan 2022 15:29:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401764; x=1674937764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qFGT50wtzxZn0pd/mKB4aYLdN6vzUrpmDy6Ee1GufQU=; b=MyVHjF3IQmBgQUnxxJT+xsh1UWM5/hb83VseagQE0K+XgrsCOjtq+pd0 jEdG8KTEJG4uIsEArs7HpvatIVJ83yhHyMNL7OjNsjgBScfOvq7xPc9Lm Bpv9A4CyLzjyHlxIUWMEUroncjw5gAv+goE3IyqWJ2nhGnEgbg5aKBwRf jKq9rerqh6kfD+m2x8oy2c8NYWvE/1oNXZ9Yq7rr05l0GE3uT4c1xJl9c qGPsiI8sxceAHN2NaIQ3yjXBOWTE2a33oJrYf92/p4yYafVi18i+wJlzv 0F4g+nF3uyThdfftv/RysPcuf3vKchMQvnbIEOvNMsAEwpYXNc1j890D0 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="227170810" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="227170810" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827718" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:23 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 11/11] docs: x86: Change documentation for SVA (Shared Virtual Addressing) Date: Fri, 28 Jan 2022 12:29:05 -0800 Message-Id: <20220128202905.2274672-12-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since allocating, freeing and fixing up PASID are changed, the documentation is updated to reflect the changes. Originally-by: Ashok Raj Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v3: - Remove PASID refcount description (Thomas). v2: - Update life cycle info (Tony and Thomas). - Update initial PASID value to INVALID_IOASID on fork(). Documentation/x86/sva.rst | 53 ++++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 12 deletions(-) diff --git a/Documentation/x86/sva.rst b/Documentation/x86/sva.rst index 076efd51ef1f..1a22020735a3 100644 --- a/Documentation/x86/sva.rst +++ b/Documentation/x86/sva.rst @@ -104,18 +104,47 @@ The MSR must be configured on each logical CPU before= any application thread can interact with a device. Threads that belong to the same process share the same page tables, thus the same MSR value. =20 -PASID is cleared when a process is created. The PASID allocation and MSR -programming may occur long after a process and its threads have been creat= ed. -One thread must call iommu_sva_bind_device() to allocate the PASID for the -process. If a thread uses ENQCMD without the MSR first being populated, a = #GP -will be raised. The kernel will update the PASID MSR with the PASID for all -threads in the process. A single process PASID can be used simultaneously -with multiple devices since they all share the same address space. - -One thread can call iommu_sva_unbind_device() to free the allocated PASID. -The kernel will clear the PASID MSR for all threads belonging to the proce= ss. - -New threads inherit the MSR value from the parent. +PASID Life Cycle Management +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +PASID is initialized as INVALID_IOASID (-1) when a process is created. + +Only processes that access SVA-capable devices need to have a PASID +allocated. This allocation happens when a process opens/binds an SVA-capab= le +device but finds no PASID for this process. Subsequent binds of the same, = or +other devices will share the same PASID. + +Although the PASID is allocated to the process by opening a device, +it is not active in any of the threads of that process. It's loaded to the +IA32_PASID MSR lazily when a thread tries to submit a work descriptor +to a device using the ENQCMD. + +That first access will trigger a #GP fault because the IA32_PASID MSR +has not been initialized with the PASID value assigned to the process +when the device was opened. The Linux #GP handler notes that a PASID has +been allocated for the process, and so initializes the IA32_PASID MSR +and returns so that the ENQCMD instruction is re-executed. + +On fork(2) or exec(2) the PASID is removed from the process as it no +longer has the same address space that it had when the device was opened. + +On clone(2) the new task shares the same address space, so will be +able to use the PASID allocated to the process. The IA32_PASID is not +preemptively initialized as the PASID value might not be allocated yet or +the kernel does not know whether this thread is going to access the device +and the cleared IA32_PASID MSR reduces context switch overhead by xstate +init optimization. Since #GP faults have to be handled on any threads that +were created before the PASID was assigned to the mm of the process, newly +created threads might as well be treated in a consistent way. + +Due to complexity of freeing the PASID and clearing all IA32_PASID MSRs in +all threads in unbind, free the PASID lazily only on mm exit. + +If a process does a close(2) of the device file descriptor and munmap(2) +of the device MMIO portal, then the driver will unbind the device. The +PASID is still marked VALID in the PASID_MSR for any threads in the +process that accessed the device. But this is harmless as without the +MMIO portal they cannot submit new work to the device. =20 Relationships =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.35.0