From nobody Tue Jun 30 01:42:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B7C2C433F5 for ; Fri, 28 Jan 2022 05:25:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243561AbiA1FZw (ORCPT ); Fri, 28 Jan 2022 00:25:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231458AbiA1FZv (ORCPT ); Fri, 28 Jan 2022 00:25:51 -0500 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE76FC061714 for ; Thu, 27 Jan 2022 21:25:50 -0800 (PST) Received: by mail-pg1-x531.google.com with SMTP id g20so4250872pgn.10 for ; Thu, 27 Jan 2022 21:25:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0e9yogaMLiWmOvC9vxOUuPR1xHD22ef7smp5tanFg+4=; b=hQLDE2JK5PLVwi5sPyGY3DuU3dDGa+74zauWKpxlzHdPT/TGezkvqGqSvfuD595csv kqNMjLttFs5lGF0n40ZTpPmdfB7fyDVhneRr8/zMOG20QU+ULpLB+yWRJ096c9si7nZ7 J0Q6Vy+zuuguvNEh5x7jlj+AXFceYt6nu2rm5gfL81v0+yBVkBZXcuhyrY/k9HxAQoZq tDuE/GqS01lp1JlXU1HPzR7mDQn7AjdBc5sfNbqOQ2Rz2Em1n6COI/3OIjiD15nPcB4i L1OH95QNZKCBNHHgBStcVEgwoHHuU/Jnme5yW4Psn6X9Oma1m6LPdbOwvYDpMRkSNHnD Cf6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0e9yogaMLiWmOvC9vxOUuPR1xHD22ef7smp5tanFg+4=; b=lCXp6k+FQh8qxAVGuwYjzPYY9L1OcdUxVAkOv++UTmq16yXVFKEtIwdB8Tzw3U0+jH ZsV46hSSwM1+cZ6Jnevbxhbc9RIaoDnL4rbOh2RCFXQrlSfdF0bRv4+Py9tcsUa/F2zq n5im7A+muCU6xdiSRg/pZq+gYydSgeNp95jIMb/zWq7iLjokFgN/Zj1tx40Y4jhC8eUJ 6qze8PzszM+GtqiBTIPr98vd6PA4CwIxXdkVcHWcabxiAK7EKQmAGpm/seIBoYs007Rj W+s2lrAHzBAVWnvE66g1QRZ7xWQVxr5vr+Mcef5tOIRMzsEljfGUgvtl+C1IDY+vViL7 hMqw== X-Gm-Message-State: AOAM532mYcgGdbRhvvTyZTcy+IDta/qJ7MugMj4BewLKteJK+DASoJ9A DPjCW3Ij7Mg5TUs2QlvuLCvmhg== X-Google-Smtp-Source: ABdhPJyDPeruoVE6AI2zH5VGYkjVLdK85RQIuEj5RjEPrwpWiMZ2TMq+S9dZ8srKOXbrkEivf38XXw== X-Received: by 2002:a65:68c3:: with SMTP id k3mr5390261pgt.353.1643347550561; Thu, 27 Jan 2022 21:25:50 -0800 (PST) Received: from localhost.localdomain ([122.171.184.231]) by smtp.gmail.com with ESMTPSA id b20sm7731744pfv.134.2022.01.27.21.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 21:25:50 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Bin Meng Subject: [PATCH v2 1/6] RISC-V: Clear SIP bit only when using SBI IPI operations Date: Fri, 28 Jan 2022 10:55:00 +0530 Message-Id: <20220128052505.859518-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The software interrupt pending (i.e. [M|S]SIP) bit is writeable for S-mode but read-only for M-mode so we clear this bit only when using SBI IPI operations. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/kernel/sbi.c | 8 +++++++- arch/riscv/kernel/smp.c | 2 -- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index f72527fcb347..9786fc641436 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -621,8 +621,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask = *target) sbi_send_ipi(target); } =20 +static void sbi_ipi_clear(void) +{ + csr_clear(CSR_IP, IE_SIE); +} + static const struct riscv_ipi_ops sbi_ipi_ops =3D { - .ipi_inject =3D sbi_send_cpumask_ipi + .ipi_inject =3D sbi_send_cpumask_ipi, + .ipi_clear =3D sbi_ipi_clear }; =20 void __init sbi_init(void) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b5d30ea92292..6fd8b3cbec1b 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,8 +89,6 @@ void riscv_clear_ipi(void) { if (ipi_ops && ipi_ops->ipi_clear) ipi_ops->ipi_clear(); - - csr_clear(CSR_IP, IE_SIE); } EXPORT_SYMBOL_GPL(riscv_clear_ipi); =20 --=20 2.25.1 From nobody Tue Jun 30 01:42:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82DC4C433EF for ; Fri, 28 Jan 2022 05:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346121AbiA1FZ5 (ORCPT ); Fri, 28 Jan 2022 00:25:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242293AbiA1FZz (ORCPT ); Fri, 28 Jan 2022 00:25:55 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A142C061714 for ; Thu, 27 Jan 2022 21:25:55 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id r59so5470700pjg.4 for ; Thu, 27 Jan 2022 21:25:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f6Dhv5CqQOYQndQIhDjH4EYISmVCA9GVd9cSSXcZ/p4=; b=GaXc22d/Oeuw/Z0L7w4JWWMIkz1bLJPPEfpeg6Gv42VmaRtNwHriEPd8k353vLwaM5 /b3sM7LdNeYkP7s1RGP+dZJ0s06OwUnAhb9X2ckTffHlVyL1ovu97uvbHZLjCYY/k2yB mimEKZwdRi7ScdWTGQf8zD4VLVnwIJn9HOlsMgr2+2CQ2wOs1/nT7a57f2n8W64pLsH6 V4duYC6ZqwlaEgiKNCSHgxnUgMCwh4jV8vBEhLkn6cCooycRyqhjQ7oWgoZY1+IA5M3H b8b2A4Edt584wG2igCvwKDEPlyq9AJFnqZwz1PiwV5I7eXSFZa6CbJLmSSMNWOBESVPY mZ5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f6Dhv5CqQOYQndQIhDjH4EYISmVCA9GVd9cSSXcZ/p4=; b=Quv8Bzbl6FzpWOhCs4oXFoodRiV2gGfY7lgYfsKuQd4aPMksypWARDMmjf/lPi9l1X CzpKA2OG8tPk7Y4enlC9wxRw+h68ZIag9pWvIMp3jsZo6ae9swNZPb3HHKyQfcriqGJk IGL27SCpo6RS3HWy9Vi9rZcvr1logae2L/pTUfvMKwA4yQSDPWB0P4oH3YNlF3Ti/HS0 49Sseov1qUvkRYYgg1Tso8DWpB0hlOa748BtyMPPrxSQbObM9yY5JuipkFlaOdZYwPYF QBa+XDZfoKIIc0USC+jn2ulepoQ1QhFgvzQ7RT7DnvDcmtpTU9A1743XskbtEO7YzTIr G1Xg== X-Gm-Message-State: AOAM531Fctf0309lytlJW9UAV4mE6FXvfLgMNhvnzrEqBKCfmece5E00 eRSd6d+sQGmPUG6UUiZcPg0YNg== X-Google-Smtp-Source: ABdhPJz2/UsyxAXmlYhVZjgHVyydrJYSa6gO05OevE7Cy5PSp7fuRDkxOdQScASf9qei8T7dD657+Q== X-Received: by 2002:a17:90a:39c6:: with SMTP id k6mr17979017pjf.194.1643347555092; Thu, 27 Jan 2022 21:25:55 -0800 (PST) Received: from localhost.localdomain ([122.171.184.231]) by smtp.gmail.com with ESMTPSA id b20sm7731744pfv.134.2022.01.27.21.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 21:25:54 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode Date: Fri, 28 Jan 2022 10:55:01 +0530 Message-Id: <20220128052505.859518-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should create INTC domain using a synthetic fwnode which will allow drivers (such as RISC-V SBI IPI driver, RISC-V timer driver, RISC-V PMU driver, etc) not having dedicated DT/ACPI node to directly create interrupt mapping for standard local interrupt numbers defined by the RISC-V privileged specification. Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 2 ++ arch/riscv/kernel/irq.c | 13 +++++++++++++ drivers/clocksource/timer-clint.c | 13 +++++++------ drivers/clocksource/timer-riscv.c | 11 ++--------- drivers/irqchip/irq-riscv-intc.c | 12 ++++++++++-- drivers/irqchip/irq-sifive-plic.c | 19 +++++++++++-------- 6 files changed, 45 insertions(+), 25 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..f85ebaf07505 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,8 @@ =20 #include =20 +extern struct fwnode_handle *riscv_intc_fwnode(void); + extern void __init init_IRQ(void); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..f2fed78ab659 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,22 @@ =20 #include #include +#include +#include #include #include =20 +static struct fwnode_handle *intc_fwnode; + +struct fwnode_handle *riscv_intc_fwnode(void) +{ + if (!intc_fwnode) + intc_fwnode =3D irq_domain_alloc_named_fwnode("RISCV-INTC"); + + return intc_fwnode; +} +EXPORT_SYMBOL_GPL(riscv_intc_fwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 6cfe2ab73eb0..6e5624989525 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -149,6 +149,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) int rc; u32 i, nr_irqs; void __iomem *base; + struct irq_domain *domain; struct of_phandle_args oirq; =20 /* @@ -169,14 +170,14 @@ static int __init clint_timer_init_dt(struct device_n= ode *np) np, i, oirq.args[0]); return -ENODEV; } - - /* Find parent irq domain and map timer irq */ - if (!clint_timer_irq && - oirq.args[0] =3D=3D RV_IRQ_TIMER && - irq_find_host(oirq.np)) - clint_timer_irq =3D irq_of_parse_and_map(np, i); } =20 + /* Find parent irq domain and map timer irq */ + domain =3D irq_find_matching_fwnode(riscv_intc_fwnode(), + DOMAIN_BUS_ANY); + if (!clint_timer_irq && domain) + clint_timer_irq =3D irq_create_mapping(domain, RV_IRQ_TIMER); + /* If CLINT timer irq not found then fail */ if (!clint_timer_irq) { pr_err("%pOFP: timer irq not found\n", np); diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 1767f8bf2013..a98f5d18bab9 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -102,7 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void = *dev_id) static int __init riscv_timer_init_dt(struct device_node *n) { int cpuid, hartid, error; - struct device_node *child; struct irq_domain *domain; =20 hartid =3D riscv_of_processor_hartid(n); @@ -121,14 +120,8 @@ static int __init riscv_timer_init_dt(struct device_no= de *n) if (cpuid !=3D smp_processor_id()) return 0; =20 - domain =3D NULL; - child =3D of_get_compatible_child(n, "riscv,cpu-intc"); - if (!child) { - pr_err("Failed to find INTC node [%pOF]\n", n); - return -ENODEV; - } - domain =3D irq_find_host(child); - of_node_put(child); + domain =3D irq_find_matching_fwnode(riscv_intc_fwnode(), + DOMAIN_BUS_ANY); if (!domain) { pr_err("Failed to find IRQ domain for node [%pOF]\n", n); return -ENODEV; diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index b65bd8878d4f..26ed62c11768 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -112,8 +112,16 @@ static int __init riscv_intc_init(struct device_node *= node, if (riscv_hartid_to_cpuid(hartid) !=3D smp_processor_id()) return 0; =20 - intc_domain =3D irq_domain_add_linear(node, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + /* + * Create INTC domain using a synthetic fwnode which will allow + * drivers (such as RISC-V SBI IPI driver, RISC-V timer driver, + * RISC-V PMU driver, etc) not having dedicated DT/ACPI node to + * directly create interrupt mapping for standard local interrupt + * numbers defined by the RISC-V privileged specification. + */ + intc_domain =3D irq_domain_create_linear(riscv_intc_fwnode(), + BITS_PER_LONG, + &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 259065d271ef..2c43ab77c014 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -284,6 +284,7 @@ static int __init plic_init(struct device_node *node, u32 nr_irqs; struct plic_priv *priv; struct plic_handler *handler; + struct irq_domain *domain; =20 priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -339,14 +340,6 @@ static int __init plic_init(struct device_node *node, continue; } =20 - /* Find parent domain and register chained handler */ - if (!plic_parent_irq && irq_find_host(parent.np)) { - plic_parent_irq =3D irq_of_parse_and_map(node, i); - if (plic_parent_irq) - irq_set_chained_handler(plic_parent_irq, - plic_handle_irq); - } - /* * When running in M-mode we need to ignore the S-mode handler. * Here we assume it always comes later, but that might be a @@ -373,6 +366,16 @@ static int __init plic_init(struct device_node *node, nr_handlers++; } =20 + /* Find parent domain and register chained handler */ + domain =3D irq_find_matching_fwnode(riscv_intc_fwnode(), + DOMAIN_BUS_ANY); + if (!plic_parent_irq && domain) { + plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); + if (plic_parent_irq) + irq_set_chained_handler(plic_parent_irq, + plic_handle_irq); + } + /* * We can have multiple PLIC instances so setup cpuhp state only * when context handler for current/boot CPU is present. --=20 2.25.1 From nobody Tue Jun 30 01:42:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8723DC433F5 for ; Fri, 28 Jan 2022 05:26:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346148AbiA1F0E (ORCPT ); Fri, 28 Jan 2022 00:26:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243094AbiA1F0B (ORCPT ); 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Thu, 27 Jan 2022 21:26:00 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 3/6] RISC-V: Treat IPIs as normal Linux IRQs Date: Fri, 28 Jan 2022 10:55:02 +0530 Message-Id: <20220128052505.859518-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the RISC-V kernel provides arch specific hooks (i.e. struct riscv_ipi_ops) to register IPI handling methods. The stats gathering of IPIs is also arch specific in the RISC-V kernel. Other architectures (such as ARM, ARM64, and MIPS) have moved away from custom arch specific IPI handling methods. Currently, these architectures have Linux irqchip drivers providing a range of Linux IRQ numbers to be used as IPIs and IPI triggering is done using generic IPI APIs. This approach allows architectures to treat IPIs as normal Linux IRQs and IPI stats gathering is done by the generic Linux IRQ subsystem. We extend the RISC-V IPI handling as-per above approach so that arch specific IPI handling methods (struct riscv_ipi_ops) can be removed and the IPI handling is totally contained within Linux irqchip drivers. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/ipi-mux.h | 43 ++++++ arch/riscv/include/asm/sbi.h | 2 + arch/riscv/include/asm/smp.h | 35 +++-- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/ipi-mux.c | 222 ++++++++++++++++++++++++++++++ arch/riscv/kernel/irq.c | 3 +- arch/riscv/kernel/sbi.c | 13 +- arch/riscv/kernel/smp.c | 153 ++++++++++---------- arch/riscv/kernel/smpboot.c | 5 +- drivers/clocksource/timer-clint.c | 8 +- drivers/irqchip/irq-riscv-intc.c | 55 ++++---- 13 files changed, 405 insertions(+), 139 deletions(-) create mode 100644 arch/riscv/include/asm/ipi-mux.h create mode 100644 arch/riscv/kernel/ipi-mux.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5adcbd9b5e88..167681d6d3f8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -54,6 +54,7 @@ config RISCV select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP if MMU + select GENERIC_IRQ_IPI select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-= mux.h new file mode 100644 index 000000000000..988e2bba372a --- /dev/null +++ b/arch/riscv/include/asm/ipi-mux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#ifndef _ASM_RISCV_IPI_MUX_H +#define _ASM_RISCV_IPI_MUX_H + +struct cpumask; + +#ifdef CONFIG_SMP + +/* Handle muxed IPIs */ +void riscv_ipi_mux_handle_irq(void); + +/* Create irq_domain for muxed IPIs */ +struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + void (*clear_ipi)(void), + void (*send_ipi)(const struct cpumask *mask)); + +/* Destroy irq_domain for muxed IPIs */ +void riscv_ipi_mux_destroy(struct irq_domain *d); + +#else + +static inline void riscv_ipi_mux_handle_irq(void) +{ +} + +static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + void (*clear_ipi)(void), + void (*send_ipi)(const struct cpumask *mask)) +{ + return NULL; +} + +static inline void riscv_ipi_mux_destroy(struct irq_domain *d) +{ +} + +#endif + +#endif /* _ASM_RISCV_IPI_MUX_H */ diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d1c37479d828..1e9aa7941960 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -116,6 +116,7 @@ struct sbiret { }; =20 void sbi_init(void); +void sbi_ipi_init(void); struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, @@ -185,6 +186,7 @@ static inline unsigned long sbi_mk_version(unsigned lon= g major, int sbi_err_map_linux_errno(int err); #else /* CONFIG_RISCV_SBI */ static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { ret= urn -1; } +static inline void sbi_ipi_init(void) { } static inline void sbi_init(void) {} #endif /* CONFIG_RISCV_SBI */ #endif /* _ASM_RISCV_SBI_H */ diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 23170c933d73..178fe4ada592 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -15,11 +15,6 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 -struct riscv_ipi_ops { - void (*ipi_inject)(const struct cpumask *target); - void (*ipi_clear)(void); -}; - #ifdef CONFIG_SMP /* * Mapping between linux logical cpu index and hartid. @@ -33,9 +28,6 @@ void show_ipi_stats(struct seq_file *p, int prec); /* SMP initialization hook for setup_arch */ void __init setup_smp(void); =20 -/* Called from C code, this handles an IPI. */ -void handle_IPI(struct pt_regs *regs); - /* Hook for the generic smp_call_function_many() routine. */ void arch_send_call_function_ipi_mask(struct cpumask *mask); =20 @@ -44,11 +36,17 @@ void arch_send_call_function_single_ipi(int cpu); =20 int riscv_hartid_to_cpuid(int hartid); =20 -/* Set custom IPI operations */ -void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); +/* Enable IPI for CPU hotplug */ +void riscv_ipi_enable(void); + +/* Disable IPI for CPU hotplug */ +void riscv_ipi_disable(void); =20 -/* Clear IPI for current CPU */ -void riscv_clear_ipi(void); +/* Check if IPI interrupt numbers are available */ +bool riscv_ipi_have_virq_range(void); + +/* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ +void riscv_ipi_set_virq_range(int virq, int nr_irqs); =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -82,11 +80,20 @@ static inline unsigned long cpuid_to_hartid_map(int cpu) return boot_cpu_hartid; } =20 -static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) +static inline void riscv_ipi_enable(void) { } =20 -static inline void riscv_clear_ipi(void) +static inline void riscv_ipi_disable(void) +{ +} + +static inline bool riscv_ipi_have_virq_range(void) +{ + return false; +} + +static inline void riscv_ipi_set_virq_range(int virq, int nr) { } =20 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 612556faa527..e3cd63a8709a 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o +obj-$(CONFIG_SMP) +=3D ipi-mux.o obj-$(CONFIG_SMP) +=3D cpu_ops.o =20 obj-$(CONFIG_RISCV_BOOT_SPINWAIT) +=3D cpu_ops_spinwait.o diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplu= g.c index be7f05b542bb..d375bfeb08df 100644 --- a/arch/riscv/kernel/cpu-hotplug.c +++ b/arch/riscv/kernel/cpu-hotplug.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include =20 bool cpu_has_hotplug(unsigned int cpu) { @@ -41,6 +41,7 @@ int __cpu_disable(void) =20 remove_cpu_topology(cpu); set_cpu_online(cpu, false); + riscv_ipi_disable(); irq_migrate_all_off_this_cpu(); =20 return ret; diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c new file mode 100644 index 000000000000..93835355dccf --- /dev/null +++ b/arch/riscv/kernel/ipi-mux.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Multiplex several IPIs over a single HW IPI. + * + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-ipi-mux: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ipi_mux { + struct irq_domain *domain; + int parent_virq; + void (*clear_ipi)(void); + void (*send_ipi)(const struct cpumask *mask); +}; + +static struct ipi_mux ipi_mux_priv; +static DEFINE_PER_CPU(unsigned long, ipi_mux_bits); + +static void ipi_mux_dummy(struct irq_data *d) +{ +} + +static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *ma= sk) +{ + int cpu; + + /* Barrier before doing atomic bit update to IPI bits */ + smp_mb__before_atomic(); + + for_each_cpu(cpu, mask) + set_bit(d->hwirq, per_cpu_ptr(&ipi_mux_bits, cpu)); + + /* Barrier after doing atomic bit update to IPI bits */ + smp_mb__after_atomic(); + + if (ipi_mux_priv.send_ipi) + ipi_mux_priv.send_ipi(mask); +} + +static struct irq_chip ipi_mux_chip =3D { + .name =3D "RISC-V IPI Mux", + .irq_mask =3D ipi_mux_dummy, + .irq_unmask =3D ipi_mux_dummy, + .ipi_send_mask =3D ipi_mux_send_mask, +}; + +static int ipi_mux_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_percpu_devid(irq); + irq_domain_set_info(d, irq, hwirq, &ipi_mux_chip, d->host_data, + handle_percpu_devid_irq, NULL, NULL); + + return 0; +} + +static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + + ret =3D irq_domain_translate_onecell(d, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + ret =3D ipi_mux_domain_map(d, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + +static const struct irq_domain_ops ipi_mux_domain_ops =3D { + .translate =3D irq_domain_translate_onecell, + .alloc =3D ipi_mux_domain_alloc, + .free =3D irq_domain_free_irqs_top, +}; + +void riscv_ipi_mux_handle_irq(void) +{ + int err; + unsigned long irqs, *bits =3D this_cpu_ptr(&ipi_mux_bits); + irq_hw_number_t hwirq; + + while (true) { + if (ipi_mux_priv.clear_ipi) + ipi_mux_priv.clear_ipi(); + + /* Order bit clearing and data access. */ + mb(); + + irqs =3D xchg(bits, 0); + if (!irqs) + break; + + for_each_set_bit(hwirq, &irqs, BITS_PER_LONG) { + err =3D generic_handle_domain_irq(ipi_mux_priv.domain, + hwirq); + if (unlikely(err)) + pr_warn_ratelimited( + "can't find mapping for hwirq %lu\n", + hwirq); + } + } +} + +static void ipi_mux_handle_irq(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + riscv_ipi_mux_handle_irq(); + chained_irq_exit(chip, desc); +} + +static int ipi_mux_dying_cpu(unsigned int cpu) +{ + if (ipi_mux_priv.parent_virq) + disable_percpu_irq(ipi_mux_priv.parent_virq); + return 0; +} + +static int ipi_mux_starting_cpu(unsigned int cpu) +{ + if (ipi_mux_priv.parent_virq) + enable_percpu_irq(ipi_mux_priv.parent_virq, + irq_get_trigger_type(ipi_mux_priv.parent_virq)); + return 0; +} + +struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + void (*clear_ipi)(void), + void (*send_ipi)(const struct cpumask *mask)) +{ + int virq, parent_virq =3D 0; + struct irq_domain *domain; + struct irq_fwspec ipi; + + if (ipi_mux_priv.domain || riscv_ipi_have_virq_range()) + return NULL; + + if (use_soft_irq) { + domain =3D irq_find_matching_fwnode(riscv_intc_fwnode(), + DOMAIN_BUS_ANY); + if (!domain) { + pr_err("unable to find INTC IRQ domain\n"); + return NULL; + } + + parent_virq =3D irq_create_mapping(domain, RV_IRQ_SOFT); + if (!parent_virq) { + pr_err("unable to create INTC IRQ mapping\n"); + return NULL; + } + } + + domain =3D irq_domain_add_linear(NULL, BITS_PER_LONG, + &ipi_mux_domain_ops, NULL); + if (!domain) { + pr_err("unable to add IPI Mux domain\n"); + goto fail_dispose_mapping; + } + + ipi.fwnode =3D domain->fwnode; + ipi.param_count =3D 1; + ipi.param[0] =3D 0; + virq =3D __irq_domain_alloc_irqs(domain, -1, BITS_PER_LONG, + NUMA_NO_NODE, &ipi, false, NULL); + if (virq <=3D 0) { + pr_err("unable to alloc IRQs from IPI Mux domain\n"); + goto fail_domain_remove; + } + + ipi_mux_priv.domain =3D domain; + ipi_mux_priv.parent_virq =3D parent_virq; + ipi_mux_priv.clear_ipi =3D clear_ipi; + ipi_mux_priv.send_ipi =3D send_ipi; + + if (parent_virq) + irq_set_chained_handler(parent_virq, ipi_mux_handle_irq); + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/ipi-mux:starting", + ipi_mux_starting_cpu, ipi_mux_dying_cpu); + + riscv_ipi_set_virq_range(virq, BITS_PER_LONG); + + return ipi_mux_priv.domain; + +fail_domain_remove: + irq_domain_remove(domain); +fail_dispose_mapping: + if (parent_virq) + irq_dispose_mapping(parent_virq); + return NULL; +} + +void riscv_ipi_mux_destroy(struct irq_domain *d) +{ + if (!d || ipi_mux_priv.domain !=3D d) + return; + + irq_domain_remove(ipi_mux_priv.domain); + if (ipi_mux_priv.parent_virq) + irq_dispose_mapping(ipi_mux_priv.parent_virq); + memset(&ipi_mux_priv, 0, sizeof(ipi_mux_priv)); +} diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index f2fed78ab659..f2cfeb3a9f5c 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include =20 static struct fwnode_handle *intc_fwnode; =20 @@ -34,4 +34,5 @@ void __init init_IRQ(void) irqchip_init(); if (!handle_arch_irq) panic("No interrupt controller found."); + sbi_ipi_init(); } diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 9786fc641436..fa3d92fce9f8 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -5,9 +5,11 @@ * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ =20 +#define pr_fmt(fmt) "riscv: " fmt #include #include #include +#include #include #include =20 @@ -626,10 +628,11 @@ static void sbi_ipi_clear(void) csr_clear(CSR_IP, IE_SIE); } =20 -static const struct riscv_ipi_ops sbi_ipi_ops =3D { - .ipi_inject =3D sbi_send_cpumask_ipi, - .ipi_clear =3D sbi_ipi_clear -}; +void __init sbi_ipi_init(void) +{ + if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi)) + pr_info("providing IPIs using SBI IPI extension\n"); +} =20 void __init sbi_init(void) { @@ -677,6 +680,4 @@ void __init sbi_init(void) __sbi_send_ipi =3D __sbi_send_ipi_v01; __sbi_rfence =3D __sbi_rfence_v01; } - - riscv_set_ipi_ops(&sbi_ipi_ops); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 6fd8b3cbec1b..a9f1aca38358 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -17,9 +17,9 @@ #include #include #include +#include #include =20 -#include #include #include =20 @@ -41,11 +41,9 @@ void __init smp_setup_processor_id(void) cpuid_to_hartid_map(0) =3D boot_cpu_hartid; } =20 -/* A collection of single bit ipi messages. */ -static struct { - unsigned long stats[IPI_MAX] ____cacheline_aligned; - unsigned long bits ____cacheline_aligned; -} ipi_data[NR_CPUS] __cacheline_aligned; +static int ipi_virq_base __ro_after_init; +static int nr_ipi __ro_after_init =3D IPI_MAX; +static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly; =20 int riscv_hartid_to_cpuid(int hartid) { @@ -77,46 +75,14 @@ static void ipi_stop(void) wait_for_interrupt(); } =20 -static const struct riscv_ipi_ops *ipi_ops __ro_after_init; - -void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) -{ - ipi_ops =3D ops; -} -EXPORT_SYMBOL_GPL(riscv_set_ipi_ops); - -void riscv_clear_ipi(void) -{ - if (ipi_ops && ipi_ops->ipi_clear) - ipi_ops->ipi_clear(); -} -EXPORT_SYMBOL_GPL(riscv_clear_ipi); - static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_typ= e op) { - int cpu; - - smp_mb__before_atomic(); - for_each_cpu(cpu, mask) - set_bit(op, &ipi_data[cpu].bits); - smp_mb__after_atomic(); - - if (ipi_ops && ipi_ops->ipi_inject) - ipi_ops->ipi_inject(mask); - else - pr_warn("SMP: IPI inject method not available\n"); + __ipi_send_mask(ipi_desc[op], mask); } =20 static void send_ipi_single(int cpu, enum ipi_message_type op) { - smp_mb__before_atomic(); - set_bit(op, &ipi_data[cpu].bits); - smp_mb__after_atomic(); - - if (ipi_ops && ipi_ops->ipi_inject) - ipi_ops->ipi_inject(cpumask_of(cpu)); - else - pr_warn("SMP: IPI inject method not available\n"); + __ipi_send_mask(ipi_desc[op], cpumask_of(cpu)); } =20 #ifdef CONFIG_IRQ_WORK @@ -126,55 +92,88 @@ void arch_irq_work_raise(void) } #endif =20 -void handle_IPI(struct pt_regs *regs) +static irqreturn_t handle_IPI(int irq, void *data) +{ + int ipi =3D irq - ipi_virq_base; + + switch (ipi) { + case IPI_RESCHEDULE: + scheduler_ipi(); + break; + case IPI_CALL_FUNC: + generic_smp_call_function_interrupt(); + break; + case IPI_CPU_STOP: + ipi_stop(); + break; + case IPI_IRQ_WORK: + irq_work_run(); + break; +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST + case IPI_TIMER: + tick_receive_broadcast(); + break; +#endif + default: + pr_warn("CPU%d: unhandled IPI%d\n", smp_processor_id(), ipi); + break; + }; + + return IRQ_HANDLED; +} + +void riscv_ipi_enable(void) { - unsigned long *pending_ipis =3D &ipi_data[smp_processor_id()].bits; - unsigned long *stats =3D ipi_data[smp_processor_id()].stats; + int i; =20 - riscv_clear_ipi(); + if (WARN_ON_ONCE(!ipi_virq_base)) + return; =20 - while (true) { - unsigned long ops; + for (i =3D 0; i < nr_ipi; i++) + enable_percpu_irq(ipi_virq_base + i, 0); +} =20 - /* Order bit clearing and data access. */ - mb(); +void riscv_ipi_disable(void) +{ + int i; =20 - ops =3D xchg(pending_ipis, 0); - if (ops =3D=3D 0) - return; + if (WARN_ON_ONCE(!ipi_virq_base)) + return; =20 - if (ops & (1 << IPI_RESCHEDULE)) { - stats[IPI_RESCHEDULE]++; - scheduler_ipi(); - } + for (i =3D 0; i < nr_ipi; i++) + disable_percpu_irq(ipi_virq_base + i); +} =20 - if (ops & (1 << IPI_CALL_FUNC)) { - stats[IPI_CALL_FUNC]++; - generic_smp_call_function_interrupt(); - } +bool riscv_ipi_have_virq_range(void) +{ + return (ipi_virq_base) ? true : false; +} =20 - if (ops & (1 << IPI_CPU_STOP)) { - stats[IPI_CPU_STOP]++; - ipi_stop(); - } +void riscv_ipi_set_virq_range(int virq, int nr) +{ + int i, err; =20 - if (ops & (1 << IPI_IRQ_WORK)) { - stats[IPI_IRQ_WORK]++; - irq_work_run(); - } + if (WARN_ON(ipi_virq_base)) + return; =20 -#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST - if (ops & (1 << IPI_TIMER)) { - stats[IPI_TIMER]++; - tick_receive_broadcast(); - } -#endif - BUG_ON((ops >> IPI_MAX) !=3D 0); + WARN_ON(nr < IPI_MAX); + nr_ipi =3D min(nr, IPI_MAX); + ipi_virq_base =3D virq; + + /* Request IPIs */ + for (i =3D 0; i < nr_ipi; i++) { + err =3D request_percpu_irq(ipi_virq_base + i, handle_IPI, + "IPI", &ipi_virq_base); + WARN_ON(err); =20 - /* Order data access and bit testing. */ - mb(); + ipi_desc[i] =3D irq_to_desc(ipi_virq_base + i); + irq_set_status_flags(ipi_virq_base + i, IRQ_HIDDEN); } + + /* Enabled IPIs for boot CPU immediately */ + riscv_ipi_enable(); } +EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 static const char * const ipi_names[] =3D { [IPI_RESCHEDULE] =3D "Rescheduling interrupts", @@ -192,7 +191,7 @@ void show_ipi_stats(struct seq_file *p, int prec) seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >=3D 4 ? " " : ""); for_each_online_cpu(cpu) - seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]); + seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); seq_printf(p, " %s\n", ipi_names[i]); } } diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..e37036e779bb 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include =20 @@ -159,12 +158,12 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm =3D &init_mm; unsigned int curr_cpuid =3D smp_processor_id(); =20 - riscv_clear_ipi(); - /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm =3D mm; =20 + riscv_ipi_enable(); + notify_cpu_starting(curr_cpuid); numa_add_cpu(curr_cpuid); update_siblings_masks(curr_cpuid); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 6e5624989525..d20c093c5564 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #ifndef CONFIG_RISCV_M_MODE #include @@ -54,11 +55,6 @@ static void clint_clear_ipi(void) writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); } =20 -static struct riscv_ipi_ops clint_ipi_ops =3D { - .ipi_inject =3D clint_send_ipi, - .ipi_clear =3D clint_clear_ipi, -}; - #ifdef CONFIG_64BIT #define clint_get_cycles() readq_relaxed(clint_timer_val) #else @@ -229,7 +225,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) goto fail_free_irq; } =20 - riscv_set_ipi_ops(&clint_ipi_ops); + riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi); clint_clear_ipi(); =20 return 0; diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 26ed62c11768..16a56d8fd36e 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -26,20 +26,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) if (unlikely(cause >=3D BITS_PER_LONG)) panic("unexpected interrupt cause"); =20 - switch (cause) { -#ifdef CONFIG_SMP - case RV_IRQ_SOFT: - /* - * We only use software interrupts to pass IPIs, so if a - * non-SMP system gets one, then we don't know what to do. - */ - handle_IPI(regs); - break; -#endif - default: - generic_handle_domain_irq(intc_domain, cause); - break; - } + generic_handle_domain_irq(intc_domain, cause); } =20 /* @@ -59,18 +46,6 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } =20 -static int riscv_intc_cpu_starting(unsigned int cpu) -{ - csr_set(CSR_IE, BIT(RV_IRQ_SOFT)); - return 0; -} - -static int riscv_intc_cpu_dying(unsigned int cpu) -{ - csr_clear(CSR_IE, BIT(RV_IRQ_SOFT)); - return 0; -} - static struct irq_chip riscv_intc_chip =3D { .name =3D "RISC-V INTC", .irq_mask =3D riscv_intc_irq_mask, @@ -87,9 +62,32 @@ static int riscv_intc_domain_map(struct irq_domain *d, u= nsigned int irq, return 0; } =20 +static int riscv_intc_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + + ret =3D irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + ret =3D riscv_intc_domain_map(domain, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + static const struct irq_domain_ops riscv_intc_domain_ops =3D { .map =3D riscv_intc_domain_map, .xlate =3D irq_domain_xlate_onecell, + .alloc =3D riscv_intc_domain_alloc }; =20 static int __init riscv_intc_init(struct device_node *node, @@ -133,11 +131,6 @@ static int __init riscv_intc_init(struct device_node *= node, return rc; } =20 - cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, - "irqchip/riscv/intc:starting", - riscv_intc_cpu_starting, - riscv_intc_cpu_dying); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); =20 return 0; --=20 2.25.1 From nobody Tue Jun 30 01:42:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C3C8C433F5 for ; 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Thu, 27 Jan 2022 21:26:04 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 4/6] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Fri, 28 Jan 2022 10:55:03 +0530 Message-Id: <20220128052505.859518-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the RISC-V kernel instead of using SBI calls. The upcoming ACLINT [M|S]SWI devices and AIA IMSIC devices allow direct IPI injection from the RISC-V kernel. To support this, we extend the riscv_ipi_set_virq_range() function so that irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/include/asm/ipi-mux.h | 2 ++ arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/ipi-mux.c | 3 ++- arch/riscv/kernel/sbi.c | 3 ++- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 6 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-= mux.h index 988e2bba372a..3a5acbf51806 100644 --- a/arch/riscv/include/asm/ipi-mux.h +++ b/arch/riscv/include/asm/ipi-mux.h @@ -15,6 +15,7 @@ void riscv_ipi_mux_handle_irq(void); =20 /* Create irq_domain for muxed IPIs */ struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)); =20 @@ -28,6 +29,7 @@ static inline void riscv_ipi_mux_handle_irq(void) } =20 static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 178fe4ada592..ddd3be1c77b6 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); =20 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr_irqs); +void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } =20 -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } =20 +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ =20 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c index 93835355dccf..501b20aed179 100644 --- a/arch/riscv/kernel/ipi-mux.c +++ b/arch/riscv/kernel/ipi-mux.c @@ -144,6 +144,7 @@ static int ipi_mux_starting_cpu(unsigned int cpu) } =20 struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { @@ -198,7 +199,7 @@ struct irq_domain *riscv_ipi_mux_create(bool use_soft_i= rq, "irqchip/riscv/ipi-mux:starting", ipi_mux_starting_cpu, ipi_mux_dying_cpu); =20 - riscv_ipi_set_virq_range(virq, BITS_PER_LONG); + riscv_ipi_set_virq_range(virq, BITS_PER_LONG, use_for_rfence); =20 return ipi_mux_priv.domain; =20 diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index fa3d92fce9f8..210d23524771 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -630,7 +630,8 @@ static void sbi_ipi_clear(void) =20 void __init sbi_ipi_init(void) { - if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi)) + if (riscv_ipi_mux_create(true, false, + sbi_ipi_clear, sbi_send_cpumask_ipi)) pr_info("providing IPIs using SBI IPI extension\n"); } =20 diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index a9f1aca38358..b98d9c319f6f 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -149,7 +149,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } =20 -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; =20 @@ -172,6 +175,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) =20 /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index d20c093c5564..bc9be091a732 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -225,7 +225,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) goto fail_free_irq; } =20 - riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi); + riscv_ipi_mux_create(true, true, clint_clear_ipi, clint_send_ipi); clint_clear_ipi(); =20 return 0; --=20 2.25.1 From nobody Tue Jun 30 01:42:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E724C433F5 for ; Fri, 28 Jan 2022 05:26:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346152AbiA1F0V (ORCPT ); Fri, 28 Jan 2022 00:26:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346165AbiA1F0N (ORCPT ); Fri, 28 Jan 2022 00:26:13 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F472C06173B for ; Thu, 27 Jan 2022 21:26:13 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id g11-20020a17090a7d0b00b001b2c12c7273so6581863pjl.0 for ; Thu, 27 Jan 2022 21:26:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ANfiyTNuLH3K34lM7cYA66sM88G94rOT/TdSDWy1dfM=; b=Crn4O48Svbt1cMbrPm7OHVBzSfhmNPVV3P249sWbI5HBVMyMc+pvPClrZ0o6EjfLph HUldc8hL9NTHUzUGhir89D6lA/g3X0JRboyB2QPEmJXXJjNnwE3KStUUpC//gznpTwcg oGD6hC2x3PFQFC7p8cOTkHwT/vZKFLwq8pwaRJTxvL60g2DZ5vOzPw+ITsTMcbWdDyY7 Q9asyWMfNZrc0Ux2X2aXoNvTjtsvKorMS4h2JyVfke43yekRUsuQdvOsQdrZf95PK38j VhCr++061HQ7l0d+zLT7g+jGvWRmAXqo/CQqT/c8h/0I+SxpuVWsUfb4/p2o2VCIgqjN 61ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ANfiyTNuLH3K34lM7cYA66sM88G94rOT/TdSDWy1dfM=; b=utcx6UVHcmIG6Xa1aAuNNRFaMk3CyFdpex4ROYetAa4332eaNKi2SFujbq99hkmOQJ 3S5UwpdO1sWR6iuovDeDksjLym39y3F09lG3TrLCDyj2e7gyr8g3i39lPNVNbRfteZ0I tMOkpZUzDjVE6y6Z0ffJ91fiAKuCxtHpnBk2I4h9XofP24BNa5cWJpQMmr8rzARA58OU SjRK8GRMACB6Y9Cm202LLsRvOVfd4+KsOXJP1KcbWroARL+JuNteDWM+TgpudRpnaVQP kOSHmEibVCwMy158kwB1jFxtIfmdEN86+W9zZOopOhjhVOp1yPCsYM0yll8QlvUpGCrt NlMg== X-Gm-Message-State: AOAM530REJe+730TpZarfqJjzSbw2pO8RJKvC2h4p7dSTEfqKG3xh4uv T34e85ML8tT/CJTt5z3qt6hmYA== X-Google-Smtp-Source: ABdhPJyDLxw4MubXIt3YIL+ZCfqKBbp7+zx+PtBCHQxqP5+pBRyrAHI6xLWEqB+rVHCtbi4GmMEiOQ== X-Received: by 2002:a17:902:e0c9:: with SMTP id e9mr7177806pla.56.1643347573119; Thu, 27 Jan 2022 21:26:13 -0800 (PST) Received: from localhost.localdomain ([122.171.184.231]) by smtp.gmail.com with ESMTPSA id b20sm7731744pfv.134.2022.01.27.21.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 21:26:10 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 5/6] RISC-V: Use IPIs for remote TLB flush when possible Date: Fri, 28 Jan 2022 10:55:04 +0530 Message-Id: <20220128052505.859518-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If IPI calls are injected using SBI IPI calls then remote TLB flush using SBI RFENCE calls is much faster because using IPIs for remote TLB flush would still endup as SBI IPI calls with extra processing on kernel side. It is now possible to have specialized hardware (such as RISC-V AIA and RISC-V ACLINT) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote TLB flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 37ed760d007c..27a7db8eb2c4 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned l= ong addr, : "memory"); } =20 +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <=3D stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <=3D stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range(d->start, d->size, d->stride); } =20 -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long star= t, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *cmask =3D mm_cpumask(mm); unsigned int cpuid; bool broadcast; @@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm,= unsigned long start, unsigned long asid =3D atomic_long_read(&mm->context.id); =20 if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <=3D stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D asid; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <=3D stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D 0; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } =20 @@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm= , unsigned long start, =20 void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } =20 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } =20 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif --=20 2.25.1 From nobody Tue Jun 30 01:42:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B5B8C433EF for ; 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Thu, 27 Jan 2022 21:26:16 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 6/6] RISC-V: Use IPIs for remote icache flush when possible Date: Fri, 28 Jan 2022 10:55:05 +0530 Message-Id: <20220128052505.859518-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If IPI calls are injected using SBI IPI calls then remote icache flush using SBI RFENCE calls is much faster because using IPIs for remote icache flush would still endup as SBI IPI calls with extra processing on the kernel side. It is now possible to have specialized hardware (such as RISC-V AIA and RISC-V ACLINT) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote icache flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/mm/cacheflush.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..7c7e44aaf791 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -18,7 +18,7 @@ void flush_icache_all(void) { local_flush_icache_all(); =20 - if (IS_ENABLED(CONFIG_RISCV_SBI)) + if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) sbi_remote_fence_i(NULL); else on_each_cpu(ipi_remote_fence_i, NULL, 1); @@ -66,7 +66,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local) * with flush_icache_deferred(). */ smp_mb(); - } else if (IS_ENABLED(CONFIG_RISCV_SBI)) { + } else if (IS_ENABLED(CONFIG_RISCV_SBI) && + !riscv_use_ipi_for_rfence()) { sbi_remote_fence_i(&others); } else { on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); --=20 2.25.1