From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 421B7C4167B for ; Thu, 27 Jan 2022 23:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245626AbiA0XIe (ORCPT ); Thu, 27 Jan 2022 18:08:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245105AbiA0XI1 (ORCPT ); Thu, 27 Jan 2022 18:08:27 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F6F6C06173B for ; Thu, 27 Jan 2022 15:08:27 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id d187so4354887pfa.10 for ; Thu, 27 Jan 2022 15:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GtcaqeEbUVEF7c8CD//RjEQZFEd6SVIiY4Z9OyKXmWI=; b=lxBc+gjDYGe2Mf7EobWimq1wSjqT7NtWINtmYB+xJSBl9seqnK1ApP1sILvOY0tkEr Xi95R+XAyOC+iBeqmTAZlKIWaw2vAMLnKx2w71b4tSeP4Ulrt+67uxUDTHhIE5IeKU7Y IDmwb8usJ4BfyJyyGe7PsK59Fa2oivcSmfDIw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GtcaqeEbUVEF7c8CD//RjEQZFEd6SVIiY4Z9OyKXmWI=; b=pvFHVKPRgHSYA7PU+o8T/g/i0FtUgShEJyOF6TVcJ6DmecOSRpqHNNuLQr1K+eR+1G MDGfUMa8XoFGhSsotPpRNU8NMaWUSEo3P2rur5GVWwkHhzPVKqE4KP3odBP7qNtHceNa uQLbCy3cBIHbb4SAtCKq/oqJPCFQFseE+xeTc7wAYUqMZpN1aY5jf+k0W4Fc1YIgEvM9 nawyu46JgcB+AE4X9ze7vmwYsKnMnlg02XIPyB2mtpqmSTaVX8ovLixL4q82/2ziRG24 YQPZIxTq65dVSWydmuDllpsGSMhH05uMVuYxOFw+CQJjaP5IrWH2BhzENRBMOk6uHW0c 7wfg== X-Gm-Message-State: AOAM531IJfyGOuRerIpGsf97jxO5POMeAi4B0SzmxkRtj2ygjq4QAYmb 5duggEWy6FMcN0fgvdo94JYFIw== X-Google-Smtp-Source: ABdhPJzWGpvg4uNE5zJeyh0Irrt/6NjcrPgkgR6BPqESbVN1+SG4fAJaZoXo0MC+4P4sXl54UFF72g== X-Received: by 2002:a05:6a00:c86:: with SMTP id a6mr5448671pfv.78.1643324906733; Thu, 27 Jan 2022 15:08:26 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id b5sm20269263pgl.22.2022.01.27.15.08.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:26 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 01/15] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Date: Thu, 27 Jan 2022 15:07:12 -0800 Message-Id: <20220127150615.v2.1.I875ab8f28c5155a7d2f103316191954d4b07ac13@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" I want to add, deprecate, and bugfix some properties, as well as add the first users. This is easier with a proper schema. The transformation is mostly straightforward, plus a few notable tweaks: * Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The driver code and the example matched, but the description was different. I went with the implementation. * Drop upthreshold and downdifferential properties from the example. These were undocumented (so, wouldn't pass validation), but were representing software properties (governor tweaks). I drop them from the driver in subsequent patches. * Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example, and all downstream users matched -- the binding definition was the exception. Anyway, "dmc_clk" is a more appropriately generic name. Signed-off-by: Brian Norris --- Changes in v2: * rename to 'memory-controller' in example * place 'required' after properties * drop superluous free-form references and repetitions of other bindings * fix for yamllint .../bindings/devfreq/rk3399_dmc.txt | 212 ------------- .../bindings/devfreq/rk3399_dmc.yaml | 293 ++++++++++++++++++ 2 files changed, 293 insertions(+), 212 deletions(-) delete mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.ya= ml diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Doc= umentation/devicetree/bindings/devfreq/rk3399_dmc.txt deleted file mode 100644 index 58fc8a6cebc7..000000000000 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ /dev/null @@ -1,212 +0,0 @@ -* Rockchip rk3399 DMC (Dynamic Memory Controller) device - -Required properties: -- compatible: Must be "rockchip,rk3399-dmc". -- devfreq-events: Node to get DDR loading, Refer to - Documentation/devicetree/bindings/devfreq/event/ - rockchip-dfi.txt -- clocks: Phandles for clock specified in "clock-names" property -- clock-names : The name of clock used by the DFI, must be - "pclk_ddr_mon"; -- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp= -v2.yaml - for details. -- center-supply: DMC supply node. -- status: Marks the node enabled/disabled. -- rockchip,pmu: Phandle to the syscon managing the "PMU general register - files". - -Optional properties: -- interrupts: The CPU interrupt number. The interrupt specifier - format depends on the interrupt controller. - It should be a DCF interrupt. When DDR DVFS finishes - a DCF interrupt is triggered. -- rockchip,pmu: Phandle to the syscon managing the "PMU general register - files". - -Following properties relate to DDR timing: - -- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk= 3399-ddr.h, - it selects the DDR3 cl-trp-trcd type. It must be - set according to "Speed Bin" in DDR3 datasheet, - DO NOT use a smaller "Speed Bin" than specified - for the DDR3 being used. - -- rockchip,pd_idle : Configure the PD_IDLE value. Defines the - power-down idle period in which memories are - placed into power-down mode if bus is idle - for PD_IDLE DFI clock cycles. - -- rockchip,sr_idle : Configure the SR_IDLE value. Defines the - self-refresh idle period in which memories are - placed into self-refresh mode if bus is idle - for SR_IDLE * 1024 DFI clock cycles (DFI - clocks freq is half of DRAM clock), default - value is "0". - -- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and control= ler - clock gating idle period. Memories are placed - into self-refresh mode and memory controller - clock arg gating started if bus is idle for - sr_mc_gate_idle*1024 DFI clock cycles. - -- rockchip,srpd_lite_idle : Defines the self-refresh power down idle - period in which memories are placed into - self-refresh power down mode if bus is idle - for srpd_lite_idle * 1024 DFI clock cycles. - This parameter is for LPDDR4 only. - -- rockchip,standby_idle : Defines the standby idle period in which - memories are placed into self-refresh mode. - The controller, pi, PHY and DRAM clock will - be gated if bus is idle for standby_idle * DFI - clock cycles. - -- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in = MHz. - When DDR frequency is less than DRAM_DLL_DISB_FREQ, - DDR3 DLL will be bypassed. Note: if DLL was bypassed, - the odt will also stop working. - -- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in - MHz (Mega Hz). When DDR frequency is less than - DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. - Note: PHY DLL and PHY ODT are independent. - -- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this paramete= r defines - the ODT disable frequency in MHz (Mega Hz). - when the DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines - the DRAM side driver strength in ohms. Default - value is 40. - -- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines - the DRAM side ODT strength in ohms. Default value - is 120. - -- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter = defines - the phy side CA line (incluing command line, - address line and clock line) driver strength. - Default value is 40. - -- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter = defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 40. - -- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter de= fines - the PHY side ODT strength. Default value is 240. - -- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parame= ter defines - then ODT disable frequency in MHz (Mega Hz). - When DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter de= fines - the DRAM side driver strength in ohms. Default - value is 34. - -- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter de= fines - the DRAM side ODT strength in ohms. Default value - is 240. - -- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parame= ter defines - the PHY side CA line (including command line, - address line and clock line) driver strength. - Default value is 40. - -- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parame= ter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 40. - -- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter de= fine - the phy side odt strength, default value is 240. - -- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parame= ter - defines the ODT disable frequency in - MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and - controller side are both disabled. - -- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter de= fines - the DRAM side driver strength in ohms. Default - value is 60. - -- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter= defines - the DRAM side ODT on DQS/DQ line strength in ohms. - Default value is 40. - -- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter = defines - the DRAM side ODT on CA line strength in ohms. - Default value is 40. - -- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parame= ter defines - the PHY side CA line (including command address - line) driver strength. Default value is 40. - -- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this param= eter defines - the PHY side clock line and CS line driver - strength. Default value is 80. - -- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parame= ter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 80. - -- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter= defines - the PHY side ODT strength. Default value is 60. - -Example: - dmc_opp_table: dmc_opp_table { - compatible =3D "operating-points-v2"; - - opp00 { - opp-hz =3D /bits/ 64 <300000000>; - opp-microvolt =3D <900000>; - }; - opp01 { - opp-hz =3D /bits/ 64 <666000000>; - opp-microvolt =3D <900000>; - }; - }; - - dmc: dmc { - compatible =3D "rockchip,rk3399-dmc"; - devfreq-events =3D <&dfi>; - interrupts =3D ; - clocks =3D <&cru SCLK_DDRC>; - clock-names =3D "dmc_clk"; - operating-points-v2 =3D <&dmc_opp_table>; - center-supply =3D <&ppvar_centerlogic>; - upthreshold =3D <15>; - downdifferential =3D <10>; - rockchip,ddr3_speed_bin =3D <21>; - rockchip,pd_idle =3D <0x40>; - rockchip,sr_idle =3D <0x2>; - rockchip,sr_mc_gate_idle =3D <0x3>; - rockchip,srpd_lite_idle =3D <0x4>; - rockchip,standby_idle =3D <0x2000>; - rockchip,dram_dll_dis_freq =3D <300>; - rockchip,phy_dll_dis_freq =3D <125>; - rockchip,auto_pd_dis_freq =3D <666>; - rockchip,ddr3_odt_dis_freq =3D <333>; - rockchip,ddr3_drv =3D <40>; - rockchip,ddr3_odt =3D <120>; - rockchip,phy_ddr3_ca_drv =3D <40>; - rockchip,phy_ddr3_dq_drv =3D <40>; - rockchip,phy_ddr3_odt =3D <240>; - rockchip,lpddr3_odt_dis_freq =3D <333>; - rockchip,lpddr3_drv =3D <34>; - rockchip,lpddr3_odt =3D <240>; - rockchip,phy_lpddr3_ca_drv =3D <40>; - rockchip,phy_lpddr3_dq_drv =3D <40>; - rockchip,phy_lpddr3_odt =3D <240>; - rockchip,lpddr4_odt_dis_freq =3D <333>; - rockchip,lpddr4_drv =3D <60>; - rockchip,lpddr4_dq_odt =3D <40>; - rockchip,lpddr4_ca_odt =3D <40>; - rockchip,phy_lpddr4_ca_drv =3D <40>; - rockchip,phy_lpddr4_ck_cs_drv =3D <80>; - rockchip,phy_lpddr4_dq_drv =3D <80>; - rockchip,phy_lpddr4_odt =3D <60>; - }; diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Do= cumentation/devicetree/bindings/devfreq/rk3399_dmc.yaml new file mode 100644 index 000000000000..467a7b5b374b --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -0,0 +1,293 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# %YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/rk3399_dmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3399 DMC (Dynamic Memory Controller) device + +maintainers: + - Brian Norris + +properties: + compatible: + enum: + - rockchip,rk3399-dmc + + devfreq-events: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + description: + Node to get DDR loading. Refer to + Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt. + + clocks: + maxItems: 1 + + clock-names: + items: + - const: dmc_clk + + operating-points-v2: true + + center-supply: + description: + DMC regulator supply. + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "PMU general register files". + + interrupts: + maxItems: 1 + description: + The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS + finishes, a DCF interrupt is triggered. + + rockchip,ddr3_speed_bin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + For values, reference include/dt-bindings/clock/rk3399-ddr.h. Select= s the + DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DD= R3 + datasheet; DO NOT use a smaller "Speed Bin" than specified for the D= DR3 + being used. + + rockchip,pd_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure the PD_IDLE value. Defines the power-down idle period in w= hich + memories are placed into power-down mode if bus is idle for PD_IDLE = DFI + clock cycles. + + rockchip,sr_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure the SR_IDLE value. Defines the self-refresh idle period in + which memories are placed into self-refresh mode if bus is idle for + SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clo= ck). + Default value is "0". + + rockchip,sr_mc_gate_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the memory self-refresh and controller clock gating idle per= iod. + Memories are placed into self-refresh mode and memory controller clo= ck + arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock + cycles. + + rockchip,srpd_lite_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh power down idle period in which memories are + placed into self-refresh power down mode if bus is idle for + srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4 + only. + + rockchip,standby_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the standby idle period in which memories are placed into + self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted + if bus is idle for standby_idle * DFI clock cycles. + + rockchip,dram_dll_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is = less + than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed. + Note: if DLL was bypassed, the odt will also stop working. + + rockchip,phy_dll_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR freq= uency + is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. + Note: PHY DLL and PHY ODT are independent. + + rockchip,auto_pd_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the auto PD disable frequency in MHz. + + rockchip,ddr3_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the ODT disable + frequency in MHz (Mega Hz). When the DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both + disabled. + + rockchip,ddr3_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the DRAM side dri= ve + strength in ohms. Default value is 40. + + rockchip,ddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the DRAM side ODT + strength in ohms. Default value is 120. + + rockchip,phy_ddr3_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the phy side CA l= ine + (incluing command line, address line and clock line) drive strength. + Default value is 40. + + rockchip,phy_ddr3_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the PHY side DQ l= ine + (including DQS/DQ/DM line) drive strength. Default value is 40. + + rockchip,phy_ddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the PHY side ODT + strength. Default value is 240. + + rockchip,lpddr3_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines then ODT disable + frequency in MHz (Mega Hz). When DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both + disabled. + + rockchip,lpddr3_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the DRAM side d= rive + strength in ohms. Default value is 34. + + rockchip,lpddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the DRAM side O= DT + strength in ohms. Default value is 240. + + rockchip,phy_lpddr3_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the PHY side CA= line + (including command line, address line and clock line) drive strength. + Default value is 40. + + rockchip,phy_lpddr3_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the PHY side DQ= line + (including DQS/DQ/DM line) drive strength. Default value is 40. + + rockchip,phy_lpddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When dram type is LPDDR3, this parameter define the phy side odt + strength, default value is 240. + + rockchip,lpddr4_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the ODT disable + frequency in MHz (Mega Hz). When the DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both + disabled. + + rockchip,lpddr4_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side d= rive + strength in ohms. Default value is 60. + + rockchip,lpddr4_dq_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on + DQS/DQ line strength in ohms. Default value is 40. + + rockchip,lpddr4_ca_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on + CA line strength in ohms. Default value is 40. + + rockchip,phy_lpddr4_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side CA= line + (including command address line) drive strength. Default value is 40. + + rockchip,phy_lpddr4_ck_cs_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side cl= ock + line and CS line drive strength. Default value is 80. + + rockchip,phy_lpddr4_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side DQ= line + (including DQS/DQ/DM line) drive strength. Default value is 80. + + rockchip,phy_lpddr4_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side ODT + strength. Default value is 60. + +required: + - compatible + - devfreq-events + - clocks + - clock-names + - operating-points-v2 + - center-supply + +additionalProperties: false + +examples: + - | + #include + #include + memory-controller { + compatible =3D "rockchip,rk3399-dmc"; + devfreq-events =3D <&dfi>; + rockchip,pmu =3D <&pmu>; + interrupts =3D ; + clocks =3D <&cru SCLK_DDRC>; + clock-names =3D "dmc_clk"; + operating-points-v2 =3D <&dmc_opp_table>; + center-supply =3D <&ppvar_centerlogic>; + rockchip,ddr3_speed_bin =3D <21>; + rockchip,pd_idle =3D <0x40>; + rockchip,sr_idle =3D <0x2>; + rockchip,sr_mc_gate_idle =3D <0x3>; + rockchip,srpd_lite_idle =3D <0x4>; + rockchip,standby_idle =3D <0x2000>; + rockchip,dram_dll_dis_freq =3D <300>; + rockchip,phy_dll_dis_freq =3D <125>; + rockchip,auto_pd_dis_freq =3D <666>; + rockchip,ddr3_odt_dis_freq =3D <333>; + rockchip,ddr3_drv =3D <40>; + rockchip,ddr3_odt =3D <120>; + rockchip,phy_ddr3_ca_drv =3D <40>; + rockchip,phy_ddr3_dq_drv =3D <40>; + rockchip,phy_ddr3_odt =3D <240>; + rockchip,lpddr3_odt_dis_freq =3D <333>; + rockchip,lpddr3_drv =3D <34>; + rockchip,lpddr3_odt =3D <240>; + rockchip,phy_lpddr3_ca_drv =3D <40>; + rockchip,phy_lpddr3_dq_drv =3D <40>; + rockchip,phy_lpddr3_odt =3D <240>; + rockchip,lpddr4_odt_dis_freq =3D <333>; + rockchip,lpddr4_drv =3D <60>; + rockchip,lpddr4_dq_odt =3D <40>; + rockchip,lpddr4_ca_odt =3D <40>; + rockchip,phy_lpddr4_ca_drv =3D <40>; + rockchip,phy_lpddr4_ck_cs_drv =3D <80>; + rockchip,phy_lpddr4_dq_drv =3D <80>; + rockchip,phy_lpddr4_odt =3D <60>; + }; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DCF4C4332F for ; Thu, 27 Jan 2022 23:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343899AbiA0XIg (ORCPT ); Thu, 27 Jan 2022 18:08:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245539AbiA0XI3 (ORCPT ); Thu, 27 Jan 2022 18:08:29 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 169B7C06174A for ; Thu, 27 Jan 2022 15:08:29 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id c3so4214631pls.5 for ; Thu, 27 Jan 2022 15:08:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ji/SQVVMeTn1tROVJbE5IrSuQIV7umlG4sAb9DJ1rd4=; b=GJM/8zOZW0jPtcOYOaNBWtQ+KSUyKvUuXiUYQWTAO1rDvzd7irsrnCeZWw+gY+dvAC H3rxT/8/ZAQ/SJDJWN7wVaxvIf4kTQZTn0JjyYXNgPVS470n10NfGh5KQRpfBL4P9EfB SdBUplDn/Oxn1fbUeU8O1CKRon/hgYYO7VUyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ji/SQVVMeTn1tROVJbE5IrSuQIV7umlG4sAb9DJ1rd4=; b=u1HAqQ4uZcXSsel6kX24iBgYaR+YE4YRetIN1CKgjNVZLpaePpl92aGS6RFbgD9vef 2u1X33MaurwbKNpN1uTWIjs0PPxDAW06O5wDr8EXkp/ZFBQeY5djQ7N/eK5chpNAPgGZ WHeH7SWKSIJQ19bac4CLVitaOVVIKDgIQOTbVkHOa3OhK/fTf29AC58cb5NJejxKNTBY Xvz2hq/z1tse9tFG6+1OYInYYAqGt+CcqkeAkz9DgiTsAdOxnzShtDP1BEQHxEPowh7b B0C8ldZxw9WDr1fE0MzDyGpwBQfw3c3DY7yoMpA2jdH1fgSc/ssmIDG0qdUcOPbhsOez sGDQ== X-Gm-Message-State: AOAM530SwR6cPqQGHlJDTcLulGsTOwadGM4+/qAKxdxNYab+xeBoadN7 2KB3sBY96RGKPKa8ksa5IbRWhw== X-Google-Smtp-Source: ABdhPJx9wiK9xm45b/dDJyYOFbrCKmg/tP7sUb2cWXUt03ZZJppWUeBaQOtvpMF6ShLXjrrfnTWJFw== X-Received: by 2002:a17:902:c10c:: with SMTP id 12mr5903890pli.158.1643324908569; Thu, 27 Jan 2022 15:08:28 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id f12sm517852pfj.37.2022.01.27.15.08.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:28 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 02/15] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Date: Thu, 27 Jan 2022 15:07:13 -0800 Message-Id: <20220127150615.v2.2.I5ba582cd678d34c03d647e5500db8e33b7524d66@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These DRAM configuration properties are all handled in ARM Trusted Firmware (and have been since the early days of this SoC), and there are no in-tree users of the DMC binding yet. It's better to just defer to firmware instead of maintaining this large list of properties. There's also some confusion about units: many of these are specified in MHz, but the downstream users and driver code are treating them as Hz, I believe. Rather than straighten all that out, I just drop them. Signed-off-by: Brian Norris --- (no changes since v1) .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Do= cumentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 467a7b5b374b..fd62a8cd62d5 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -46,6 +46,7 @@ properties: finishes, a DCF interrupt is triggered. =20 rockchip,ddr3_speed_bin: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: For values, reference include/dt-bindings/clock/rk3399-ddr.h. Select= s the @@ -92,6 +93,7 @@ properties: if bus is idle for standby_idle * DFI clock cycles. =20 rockchip,dram_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is = less @@ -99,6 +101,7 @@ properties: Note: if DLL was bypassed, the odt will also stop working. =20 rockchip,phy_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR freq= uency @@ -106,6 +109,7 @@ properties: Note: PHY DLL and PHY ODT are independent. =20 rockchip,auto_pd_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the auto PD disable frequency in MHz. @@ -119,18 +123,21 @@ properties: disabled. =20 rockchip,ddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side dri= ve strength in ohms. Default value is 40. =20 rockchip,ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 120. =20 rockchip,phy_ddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the phy side CA l= ine @@ -138,12 +145,14 @@ properties: Default value is 40. =20 rockchip,phy_ddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side DQ l= ine (including DQS/DQ/DM line) drive strength. Default value is 40. =20 rockchip,phy_ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side ODT @@ -158,18 +167,21 @@ properties: disabled. =20 rockchip,lpddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side d= rive strength in ohms. Default value is 34. =20 rockchip,lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side O= DT strength in ohms. Default value is 240. =20 rockchip,phy_lpddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side CA= line @@ -177,12 +189,14 @@ properties: Default value is 40. =20 rockchip,phy_lpddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side DQ= line (including DQS/DQ/DM line) drive strength. Default value is 40. =20 rockchip,phy_lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When dram type is LPDDR3, this parameter define the phy side odt @@ -197,42 +211,49 @@ properties: disabled. =20 rockchip,lpddr4_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side d= rive strength in ohms. Default value is 60. =20 rockchip,lpddr4_dq_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on DQS/DQ line strength in ohms. Default value is 40. =20 rockchip,lpddr4_ca_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on CA line strength in ohms. Default value is 40. =20 rockchip,phy_lpddr4_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side CA= line (including command address line) drive strength. Default value is 40. =20 rockchip,phy_lpddr4_ck_cs_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side cl= ock line and CS line drive strength. Default value is 80. =20 rockchip,phy_lpddr4_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side DQ= line (including DQS/DQ/DM line) drive strength. Default value is 80. =20 rockchip,phy_lpddr4_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT @@ -261,33 +282,12 @@ examples: clock-names =3D "dmc_clk"; operating-points-v2 =3D <&dmc_opp_table>; center-supply =3D <&ppvar_centerlogic>; - rockchip,ddr3_speed_bin =3D <21>; rockchip,pd_idle =3D <0x40>; rockchip,sr_idle =3D <0x2>; rockchip,sr_mc_gate_idle =3D <0x3>; rockchip,srpd_lite_idle =3D <0x4>; rockchip,standby_idle =3D <0x2000>; - rockchip,dram_dll_dis_freq =3D <300>; - rockchip,phy_dll_dis_freq =3D <125>; - rockchip,auto_pd_dis_freq =3D <666>; rockchip,ddr3_odt_dis_freq =3D <333>; - rockchip,ddr3_drv =3D <40>; - rockchip,ddr3_odt =3D <120>; - rockchip,phy_ddr3_ca_drv =3D <40>; - rockchip,phy_ddr3_dq_drv =3D <40>; - rockchip,phy_ddr3_odt =3D <240>; rockchip,lpddr3_odt_dis_freq =3D <333>; - rockchip,lpddr3_drv =3D <34>; - rockchip,lpddr3_odt =3D <240>; - rockchip,phy_lpddr3_ca_drv =3D <40>; - rockchip,phy_lpddr3_dq_drv =3D <40>; - rockchip,phy_lpddr3_odt =3D <240>; rockchip,lpddr4_odt_dis_freq =3D <333>; - rockchip,lpddr4_drv =3D <60>; - rockchip,lpddr4_dq_odt =3D <40>; - rockchip,lpddr4_ca_odt =3D <40>; - rockchip,phy_lpddr4_ca_drv =3D <40>; - rockchip,phy_lpddr4_ck_cs_drv =3D <80>; - rockchip,phy_lpddr4_dq_drv =3D <80>; - rockchip,phy_lpddr4_odt =3D <60>; }; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E35EAC433EF for ; Thu, 27 Jan 2022 23:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344313AbiA0XIn (ORCPT ); Thu, 27 Jan 2022 18:08:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245691AbiA0XIb (ORCPT ); Thu, 27 Jan 2022 18:08:31 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC6DEC06173B for ; Thu, 27 Jan 2022 15:08:30 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id r59so4757942pjg.4 for ; Thu, 27 Jan 2022 15:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7h2TqwoqXaEMfjPzv9SF6ZGc4nNnV1XaxjSg49pOxCw=; b=DPUvXSj4gGoUi2PZpwiU9r2MGTNKqUgmF4dU8QpNs/blxOChn/Dp4X5P6uc34QaFaV DOvAxI8yXqbH/50nNHY73T7e0MH2ScJuvKPL2U+RdqfwtNhtdml4RTg/ip02fDK4yYwO +/wg5JzxvX29Bfht/wS7TUy2EGdWPpsb4iBTk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7h2TqwoqXaEMfjPzv9SF6ZGc4nNnV1XaxjSg49pOxCw=; b=OTp0qQVba7JvJUOmcSjZ9hza+WwNaZydGNFxjAaadAQQ1p9EPHu0j1a9FDlk1OhOPr JIbApgWTjsS+feHG6IXcchw1z3K2aF5nF2cCN+5LfkMeG43EtrUWDtEQA4CO3JmnY47J /17j8xeyjnY+3ohooTRnyLACNaJeXnkxF6EYJeEc1qnIPHGuxGJ3IIqZubguKDHA+Ykb HLDf5ATG5228U9nsAzfYdvRueZvkBBirrKIvVtPT+ajxemk5YfKS58f7/TR9OJNSziHL 5PVc+jz1s4faUaPbXAVd3pKeHfUag1o8CGICMU+Wt5Namsg9sILt/vTHM6gR7lA2rHx/ VVPg== X-Gm-Message-State: AOAM531Em20TX4qz0Y0VAhe6El6kMl9P9g9kIgUrZ2UO4ibbWxuMrmw9 WXfoh+Vyq0jgil4E38siEHJ+SQ== X-Google-Smtp-Source: ABdhPJwF8ZK0wYylhQqNtZ4M2mQnejXec2VevUUW76yQtWHtCIpE5oy0RcA49p/AmsG5dRO59F5mzg== X-Received: by 2002:a17:90b:33c6:: with SMTP id lk6mr6586908pjb.213.1643324910342; Thu, 27 Jan 2022 15:08:30 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id h6sm6933258pfc.35.2022.01.27.15.08.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:29 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 03/15] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Date: Thu, 27 Jan 2022 15:07:14 -0800 Message-Id: <20220127150615.v2.3.I9341269171c114d0e04e41d48037fd32816e2d8c@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The driver and all downstream device trees [1] are using Hz units, but the document claims MHz. DRAM frequency for these systems can't possibly exceed 2^32-1 Hz, so the choice of unit doesn't really matter than much. Rather than add unnecessary risk in getting the units wrong, let's just go with the unofficial convention and make the docs match reality. A sub-1MHz frequency is extremely unlikely, so include a minimum in the schema, to help catch anybody who might have believed this was MHz. [1] And notably, also those trying to upstream them: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.o= rg/ Signed-off-by: Brian Norris Acked-by: Chanwoo Choi Reviewed-by: Rob Herring --- (no changes since v1) .../bindings/devfreq/rk3399_dmc.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Do= cumentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index fd62a8cd62d5..8bb778df92ae 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -116,11 +116,11 @@ properties: =20 rockchip,ddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is DDR3, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_fr= eq, + the ODT on the DRAM side and controller side are both disabled. =20 rockchip,ddr3_drv: deprecated: true @@ -160,11 +160,11 @@ properties: =20 rockchip,lpddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR3, this parameter defines then ODT disable - frequency in MHz (Mega Hz). When DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both - disabled. + frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, = the + ODT on the DRAM side and controller side are both disabled. =20 rockchip,lpddr3_drv: deprecated: true @@ -204,11 +204,11 @@ properties: =20 rockchip,lpddr4_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR4, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_fr= eq, + the ODT on the DRAM side and controller side are both disabled. =20 rockchip,lpddr4_drv: deprecated: true @@ -287,7 +287,7 @@ examples: rockchip,sr_mc_gate_idle =3D <0x3>; rockchip,srpd_lite_idle =3D <0x4>; rockchip,standby_idle =3D <0x2000>; - rockchip,ddr3_odt_dis_freq =3D <333>; - rockchip,lpddr3_odt_dis_freq =3D <333>; - rockchip,lpddr4_odt_dis_freq =3D <333>; + rockchip,ddr3_odt_dis_freq =3D <333000000>; + rockchip,lpddr3_odt_dis_freq =3D <333000000>; + rockchip,lpddr4_odt_dis_freq =3D <333000000>; }; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1876C433F5 for ; Thu, 27 Jan 2022 23:08:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344158AbiA0XIk (ORCPT ); Thu, 27 Jan 2022 18:08:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239780AbiA0XIc (ORCPT ); Thu, 27 Jan 2022 18:08:32 -0500 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9922C061747 for ; Thu, 27 Jan 2022 15:08:32 -0800 (PST) Received: by mail-pf1-x432.google.com with SMTP id 128so4337872pfe.12 for ; Thu, 27 Jan 2022 15:08:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZfhvZdFs5TObb5S4eewDrBMOltALFoSNTdZ7kqpym+w=; b=npEbe3pKve6T0stjeDsyP2hlb1l9yn6TxS2m1sa+3SXZ04FPuvMdfmzsTIJNsLSdxi t6w0LMTqu1IkNqXOqN4942uEw/i8X5WRoVPoa8nM8w6m7VUaLVyx4MINNlIxcDmTvOQd xGhmHBDLy9pUDKcWGknlP0bT+XZ24P1uaSnpY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZfhvZdFs5TObb5S4eewDrBMOltALFoSNTdZ7kqpym+w=; b=OhRiz7bkKbwcFQ+zNbfZDhuxEWWDeGBSKbp61bWp/8e3I+Doa4fUICko/+IcggN4wZ U3OASP6XTI8mHReEtMq+o8/VCYuJFUuQ1VRQV4lfqE6iPX6/Ohgsl43WNUIvSCgSO3ot T982WPC1KHgZENSqxFnzQXEtxRAhagdELWAtuwZ6XchxTudAB+BY5D1mycnTpFQnebyJ lpfEEklX0yXCGm9TEPhLHYe9fgYvlX13lcHDAHehjo5zVarNWgzTAi6Z2/1fYWTJTTiZ dBA35tBscZEMxppvQJfHg8dt0HtE04hsM4hZSp52ESa+s+o63ZXHsWdhrNNqc5VYsZPW MgSg== X-Gm-Message-State: AOAM531Ku8TjhHJEqQGdr/rD3UQexIOXINZvzlKJWw6g+vyVuIPwi76g zzXVHtRA9f+PoIairXNAckXNPg== X-Google-Smtp-Source: ABdhPJzWfp15WA+agQIDXTl8cUPnuwXcqyV2WF4QJ4q1xpLKzz6EakugAmhaPwx/3rCjwXSRJkmH8Q== X-Received: by 2002:a05:6a00:b42:: with SMTP id p2mr5377425pfo.50.1643324912230; Thu, 27 Jan 2022 15:08:32 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id r14sm339902pjo.39.2022.01.27.15.08.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:31 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 04/15] dt-bindings: devfreq: rk3399_dmc: Specify idle params in nanoseconds Date: Thu, 27 Jan 2022 15:07:15 -0800 Message-Id: <20220127150615.v2.4.I01c6a2b2db578136686b42d463af985cfdff2fd9@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's inefficient to use the same number of cycles for all OPPs, since lower frequencies make for longer idle times. Let's specify the idle time instead, so software can pick the optimal number of cycles on its own. NB: these bindings aren't used anywhere yet. Signed-off-by: Brian Norris --- Changes in v2: - New patch .../bindings/devfreq/rk3399_dmc.yaml | 50 +++++++++++++++++-- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Do= cumentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 8bb778df92ae..8786b7fa9b28 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -55,42 +55,52 @@ properties: being used. =20 rockchip,pd_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Configure the PD_IDLE value. Defines the power-down idle period in w= hich memories are placed into power-down mode if bus is idle for PD_IDLE = DFI clock cycles. + See also rockchip,pd-idle-ns. =20 rockchip,sr_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Configure the SR_IDLE value. Defines the self-refresh idle period in which memories are placed into self-refresh mode if bus is idle for SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clo= ck). Default value is "0". + See also rockchip,sr-idle-ns. =20 rockchip,sr_mc_gate_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the memory self-refresh and controller clock gating idle per= iod. Memories are placed into self-refresh mode and memory controller clo= ck arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock cycles. + See also rockchip,sr-mc-gate-idle-ns. =20 rockchip,srpd_lite_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the self-refresh power down idle period in which memories are placed into self-refresh power down mode if bus is idle for srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4 only. + See also rockchip,srpd-lite-idle-ns. =20 rockchip,standby_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the standby idle period in which memories are placed into self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted if bus is idle for standby_idle * DFI clock cycles. + See also rockchip,standby-idle-ns. =20 rockchip,dram_dll_dis_freq: deprecated: true @@ -259,6 +269,36 @@ properties: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT strength. Default value is 60. =20 + rockchip,pd-idle-ns: + description: + Configure the PD_IDLE value in nanoseconds. Defines the power-down i= dle + period in which memories are placed into power-down mode if bus is i= dle + for PD_IDLE nanoseconds. + + rockchip,sr-idle-ns: + description: + Configure the SR_IDLE value in nanoseconds. Defines the self-refresh= idle + period in which memories are placed into self-refresh mode if bus is= idle + for SR_IDLE nanoseconds. Default value is "0". + + rockchip,sr-mc-gate-idle-ns: + description: + Defines the memory self-refresh and controller clock gating idle per= iod in nanoseconds. + Memories are placed into self-refresh mode and memory controller clo= ck + arg gating started if bus is idle for sr_mc_gate_idle nanoseconds. + + rockchip,srpd-lite-idle-ns: + description: + Defines the self-refresh power down idle period in which memories are + placed into self-refresh power down mode if bus is idle for + srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only. + + rockchip,standby-idle-ns: + description: + Defines the standby idle period in which memories are placed into + self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted + if bus is idle for standby_idle nanoseconds. + required: - compatible - devfreq-events @@ -282,11 +322,11 @@ examples: clock-names =3D "dmc_clk"; operating-points-v2 =3D <&dmc_opp_table>; center-supply =3D <&ppvar_centerlogic>; - rockchip,pd_idle =3D <0x40>; - rockchip,sr_idle =3D <0x2>; - rockchip,sr_mc_gate_idle =3D <0x3>; - rockchip,srpd_lite_idle =3D <0x4>; - rockchip,standby_idle =3D <0x2000>; + rockchip,pd-idle-ns =3D <160>; + rockchip,sr-idle-ns =3D <10240>; + rockchip,sr-mc-gate-idle-ns =3D <40960>; + rockchip,srpd-lite-idle-ns =3D <61440>; + rockchip,standby-idle-ns =3D <81920>; rockchip,ddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr4_odt_dis_freq =3D <333000000>; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 114FEC4332F for ; Thu, 27 Jan 2022 23:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344467AbiA0XIq (ORCPT ); Thu, 27 Jan 2022 18:08:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245300AbiA0XIe (ORCPT ); Thu, 27 Jan 2022 18:08:34 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 876DBC06173B for ; Thu, 27 Jan 2022 15:08:34 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id o64so4777529pjo.2 for ; Thu, 27 Jan 2022 15:08:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PIXY+sEGqfziH4n+3nglkYpU71hUD2jbkDapelJUYx4=; b=VHdpreI16umQb0mYgJNYwcpXLMOYb9t5rWTJ5lF4m9dkAlOLQJbt8IUssF2/vzGhhu P2J4/IhQS1aBIC7OrTZ1rtXRz+BfKAgWlbPsQXOeqn/lbT032Hn/Q9FuFAS2EqI91NEL qkeLOxEtvhwyVPeocb+jYET3MYH1WQ8LLra/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PIXY+sEGqfziH4n+3nglkYpU71hUD2jbkDapelJUYx4=; b=4+iESeOg2gyp9nu1YCXtxDBHQNX+fWfJb+hOI5KS2HiVpwKRWBeAXVFc//XUjDoTRq huaJelvJeRjZDkhn/5MRlXA0j7Hp0gbyTguJQx37/NJMJaczJU1TdPN44m0B5SZYwf/0 7NgBs2LuQKIH/McfDEhni4zzzv+tc4n5du+FcxO3J7mLICcBRRGW+EtzN7JP6ZKe35XJ h/ItPIW05kq7pOgaLeF39oY2kOuKHafTkf4ZG94CS7YXw7/ir4BofRr88WO94m0U1xJS Zin1c+nmO5dkjzsQJOvEliMhQ9P9vKHAIcx7Ew/bWvzdGzCuwpp5bu+TctpnGsM/XVEv gAXw== X-Gm-Message-State: AOAM53072imIWrGTdk8svNjy8unLCItZGTktEx1tCz9xj4divYBSgIbq 6xC6j9jfE03CQAzNlPRsJS2E1Q== X-Google-Smtp-Source: ABdhPJyOEdExuVH8zC2uGNPOjViFehIsUDjflPA1+PxmuS5k/khzsp0p8n9ZntEMyywxRWObRePXqQ== X-Received: by 2002:a17:90b:1983:: with SMTP id mv3mr6659930pjb.222.1643324914114; Thu, 27 Jan 2022 15:08:34 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id h10sm4000716pfv.31.2022.01.27.15.08.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:33 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 05/15] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Date: Thu, 27 Jan 2022 15:07:16 -0800 Message-Id: <20220127150615.v2.5.I382d4de737198ea52deb118c9bdc4d93d76e009e@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DDR DVFS tuning has found that several power-saving features don't have good tradeoffs at higher frequencies -- at higher frequencies, we'll see glitches or other errors. Provide tuning controls so these can be disabled at higher OPPs, and left active only at the lower ones. Signed-off-by: Brian Norris Reviewed-by: Rob Herring --- Changes in v2: - hyphens, not underscores - *-hz units, and drop the types definition .../bindings/devfreq/rk3399_dmc.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Do= cumentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 8786b7fa9b28..afa058c52c0b 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -299,6 +299,38 @@ properties: self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted if bus is idle for standby_idle nanoseconds. =20 + rockchip,pd-idle-dis-freq-hz: + description: + Defines the power-down idle disable frequency in Hz. When the DDR + frequency is greater than pd-idle-dis-freq, power-down idle is disab= led. + See also rockchip,pd-idle-ns. + + rockchip,sr-idle-dis-freq-hz: + description: + Defines the self-refresh idle disable frequency in Hz. When the DDR + frequency is greater than sr-idle-dis-freq, self-refresh idle is + disabled. See also rockchip,sr-idle-ns. + + rockchip,sr-mc-gate-idle-dis-freq-hz: + description: + Defines the self-refresh and memory-controller clock gating disable + frequency in Hz. When the DDR frequency is greater than + sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See= also + rockchip,sr-mc-gate-idle-ns. + + rockchip,srpd-lite-idle-dis-freq-hz: + description: + Defines the self-refresh power down idle disable frequency in Hz. Wh= en + the DDR frequency is greater than srpd-lite-idle-dis-freq, memory wi= ll + not be placed into self-refresh power down mode when idle. See also + rockchip,srpd-lite-idle-ns. + + rockchip,standby-idle-dis-freq-hz: + description: + Defines the standby idle disable frequency in Hz. When the DDR frequ= ency + is greater than standby-idle-dis-freq, standby idle is disabled. See= also + rockchip,standby-idle-ns. + required: - compatible - devfreq-events @@ -330,4 +362,9 @@ examples: rockchip,ddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr4_odt_dis_freq =3D <333000000>; + rockchip,pd-idle-dis-freq-hz =3D <1000000000>; + rockchip,sr-idle-dis-freq-hz =3D <1000000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz =3D <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz =3D <0>; + rockchip,standby-idle-dis-freq-hz =3D <928000000>; }; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CEB3C433FE for ; Thu, 27 Jan 2022 23:08:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344522AbiA0XIt (ORCPT ); Thu, 27 Jan 2022 18:08:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344174AbiA0XIk (ORCPT ); Thu, 27 Jan 2022 18:08:40 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 538EFC061751 for ; Thu, 27 Jan 2022 15:08:36 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id e9so3680426pgb.3 for ; Thu, 27 Jan 2022 15:08:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S7JkzSF7lxJgCpd6ZXDkhdvjrfqNJJ5Wge2dT4ZFw7o=; b=QkHrDYVuucq5tGrwY+7ofVKvafE8N1vG6K7wssS8MFOLQ8A+qT44Pw8OkxznULsPLE fU0ppcxIbnnoe3DkKlONgnWitZdR6bHPjT1zDXJKdypl9iivtwyPlKX/9eCq/YqaK+Iu BWm6b0pbXYtrWPXRj7GPsRq0ghVWt5Gr/dEag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S7JkzSF7lxJgCpd6ZXDkhdvjrfqNJJ5Wge2dT4ZFw7o=; b=mUKcIbNdfjR0LNA2BV8Jrd/Mi8E89+l6plr1LyyqoCI7h29KbnsEOmH1jfyIMFuRc/ TiqzmHMvGE6TdmMPF4R4hXW3dEPTQPlPS1SwOMxgauBSRyET+vGrCvarmMws+pFNWpS+ 1M0EHkca96HQUYsToZ3iognZWwxngWwIZ+4iQWbA0bDIBUcbBfl2YNB18vLO/cHFYwfI 5BMij0J7INr0TGzCC/9NWErZCzT2z94yq3Cw8ZWn0BD2bquyrlbL3KcicrvG0NpteBoG ghVaiQQuivwhyWssYpkjQ7o6s7nKmdnlY+qv28FdryJLh2tvX2mCqxDaHxB6WJuHhtqJ Zr+g== X-Gm-Message-State: AOAM532khKOzRs+P2GzO7K8UK+o6BzOALXr9KYnh+2iiOdVYBxDJVsTL 6cX8zsdKp1eyArLgt0PReb8yiA== X-Google-Smtp-Source: ABdhPJxGSe8Or1J7VdvMjjKei+W+lXlkhGyA7m0Vzqh1YDxZLw6gaRpY1PqHnE/am+HMGfaQbFydiw== X-Received: by 2002:a63:6c44:: with SMTP id h65mr4438729pgc.100.1643324915912; Thu, 27 Jan 2022 15:08:35 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id f8sm4740841pfe.204.2022.01.27.15.08.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:35 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 06/15] PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props Date: Thu, 27 Jan 2022 15:07:17 -0800 Message-Id: <20220127150615.v2.6.I4bd77eb751d5bfce8346bfed576bcacb28e4550f@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These properties are: * undocumented * directly representing software properties, not hardware properties * unused (no in-tree users, yet; this IP block has so far only been used in downstream kernels) Let's just stick the values that downstream users have been using directly in the driver and call it a day. Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 293857ebfd75..e982862f6ac2 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -430,10 +430,8 @@ static int rk3399_dmcfreq_probe(struct platform_device= *pdev) goto err_edev; } =20 - of_property_read_u32(np, "upthreshold", - &data->ondemand_data.upthreshold); - of_property_read_u32(np, "downdifferential", - &data->ondemand_data.downdifferential); + data->ondemand_data.upthreshold =3D 25; + data->ondemand_data.downdifferential =3D 15; =20 data->rate =3D clk_get_rate(data->dmc_clk); =20 --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC164C4321E for ; Thu, 27 Jan 2022 23:08:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344488AbiA0XIv (ORCPT ); Thu, 27 Jan 2022 18:08:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344228AbiA0XIk (ORCPT ); Thu, 27 Jan 2022 18:08:40 -0500 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57E76C061759 for ; Thu, 27 Jan 2022 15:08:38 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id c3so4215006pls.5 for ; Thu, 27 Jan 2022 15:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wF8asFGVt+AtZyFXw9AJs8JGc2Au97BqBwJjLVvGTGk=; b=m1bskz9VGSEPkl+OYySs5FbJ0mDYlowRn5rLoqv7/j6elQ7bap/Bl2Lgxr6a94SOop lzEZ4ix7y92Izu0CGTiXbfiphyDiAhP2/5B9WpdaSvqtFSf7Ua5RzfQ7t92rhlyx3Jdc ygqdBWCu8Qh55p5yPlpF07c7hEwg/gZwTC38c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wF8asFGVt+AtZyFXw9AJs8JGc2Au97BqBwJjLVvGTGk=; b=3CL/WHrWfjnIUFBT2ICsDCxyx1BcaR9JR7kXKzHDJ4aIUqvY3Oe6HUPidMEKCkf7O7 IcM1XjAGlx8h9Kp3cT+6nsa6XziQdgiRnm8D/JTMOmwfCb8f5DEtuZtJG6KcFP2RjN4Q XHCFUKLa5HmReQ3gL6UNA3TgpQmMxveRFOaIZpfTirxQiAoVN0NA8q3J0AfElonm5PmS XAzdcNLOwvLKkFDVUiKWGCRKUV+irybCdhLqd/UPAbBgVbhryQEs+Md554DmzVc/Uac7 jmRFJj+MyNEUCz0TEJy2GprIg4MWva0sBlgMqxTmoJVxKjNehRcvMk7w6NCNzO1EQbBq BhQw== X-Gm-Message-State: AOAM530JBLGaH9+iqMSljFQxn848anoQkEzvm8Hcer6Lv6FOzxXNtub4 sLdVdfC/1UrGpXRa/HD6Ei094w== X-Google-Smtp-Source: ABdhPJyXiZZXus/1gKOLq7YPh4vsv9pI+aiSXDErCp0/kRJCwY8CjMJMvtJ9PdkOAN7io+dQpIvUKA== X-Received: by 2002:a17:90a:ec0b:: with SMTP id l11mr16387805pjy.200.1643324917848; Thu, 27 Jan 2022 15:08:37 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id d8sm7421810pfv.64.2022.01.27.15.08.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:37 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 07/15] PM / devfreq: rk3399_dmc: Drop excess timing properties Date: Thu, 27 Jan 2022 15:07:18 -0800 Message-Id: <20220127150615.v2.7.Ia0f7d6168a71ba4a4fd0519972a8dfd4c681fc25@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of these properties are initialized by ARM Trusted Firmware, and have been since the early days of this chip. It's redundant (and possibly wrong) to do this here now. What's more, there seems to be some confusion about the units and some of the definitions of this timing struct: the DT docs say MHz for many of these, but downstream users were in Hz (and therefore, the ATF interface was Hz). Also, the in-driver usage for some of these (e.g., for comparing to target frequency) were in Hz too. So doubly wrong. We can avoid thinking about who got the right units by dropping the unnecessary code and properties. They are marked deprecated in the binding schema. Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 144 +++++++---------------------------- 1 file changed, 29 insertions(+), 115 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index e982862f6ac2..8f447217303f 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -23,38 +23,6 @@ #include #include =20 -struct dram_timing { - unsigned int ddr3_speed_bin; - unsigned int pd_idle; - unsigned int sr_idle; - unsigned int sr_mc_gate_idle; - unsigned int srpd_lite_idle; - unsigned int standby_idle; - unsigned int auto_pd_dis_freq; - unsigned int dram_dll_dis_freq; - unsigned int phy_dll_dis_freq; - unsigned int ddr3_odt_dis_freq; - unsigned int ddr3_drv; - unsigned int ddr3_odt; - unsigned int phy_ddr3_ca_drv; - unsigned int phy_ddr3_dq_drv; - unsigned int phy_ddr3_odt; - unsigned int lpddr3_odt_dis_freq; - unsigned int lpddr3_drv; - unsigned int lpddr3_odt; - unsigned int phy_lpddr3_ca_drv; - unsigned int phy_lpddr3_dq_drv; - unsigned int phy_lpddr3_odt; - unsigned int lpddr4_odt_dis_freq; - unsigned int lpddr4_drv; - unsigned int lpddr4_dq_odt; - unsigned int lpddr4_ca_odt; - unsigned int phy_lpddr4_ca_drv; - unsigned int phy_lpddr4_ck_cs_drv; - unsigned int phy_lpddr4_dq_drv; - unsigned int phy_lpddr4_odt; -}; - struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; @@ -62,13 +30,21 @@ struct rk3399_dmcfreq { struct clk *dmc_clk; struct devfreq_event_dev *edev; struct mutex lock; - struct dram_timing timing; struct regulator *vdd_center; struct regmap *regmap_pmu; unsigned long rate, target_rate; unsigned long volt, target_volt; unsigned int odt_dis_freq; int odt_pd_arg0, odt_pd_arg1; + + unsigned int pd_idle; + unsigned int sr_idle; + unsigned int sr_mc_gate_idle; + unsigned int srpd_lite_idle; + unsigned int standby_idle; + unsigned int ddr3_odt_dis_freq; + unsigned int lpddr3_odt_dis_freq; + unsigned int lpddr4_odt_dis_freq; }; =20 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, @@ -238,69 +214,27 @@ static __maybe_unused int rk3399_dmcfreq_resume(struc= t device *dev) static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, rk3399_dmcfreq_resume); =20 -static int of_get_ddr_timings(struct dram_timing *timing, - struct device_node *np) +static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data, + struct device_node *np) { int ret =3D 0; =20 - ret =3D of_property_read_u32(np, "rockchip,ddr3_speed_bin", - &timing->ddr3_speed_bin); ret |=3D of_property_read_u32(np, "rockchip,pd_idle", - &timing->pd_idle); + &data->pd_idle); ret |=3D of_property_read_u32(np, "rockchip,sr_idle", - &timing->sr_idle); + &data->sr_idle); ret |=3D of_property_read_u32(np, "rockchip,sr_mc_gate_idle", - &timing->sr_mc_gate_idle); + &data->sr_mc_gate_idle); ret |=3D of_property_read_u32(np, "rockchip,srpd_lite_idle", - &timing->srpd_lite_idle); + &data->srpd_lite_idle); ret |=3D of_property_read_u32(np, "rockchip,standby_idle", - &timing->standby_idle); - ret |=3D of_property_read_u32(np, "rockchip,auto_pd_dis_freq", - &timing->auto_pd_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,dram_dll_dis_freq", - &timing->dram_dll_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,phy_dll_dis_freq", - &timing->phy_dll_dis_freq); + &data->standby_idle); ret |=3D of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", - &timing->ddr3_odt_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,ddr3_drv", - &timing->ddr3_drv); - ret |=3D of_property_read_u32(np, "rockchip,ddr3_odt", - &timing->ddr3_odt); - ret |=3D of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv", - &timing->phy_ddr3_ca_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv", - &timing->phy_ddr3_dq_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_ddr3_odt", - &timing->phy_ddr3_odt); + &data->ddr3_odt_dis_freq); ret |=3D of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", - &timing->lpddr3_odt_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,lpddr3_drv", - &timing->lpddr3_drv); - ret |=3D of_property_read_u32(np, "rockchip,lpddr3_odt", - &timing->lpddr3_odt); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv", - &timing->phy_lpddr3_ca_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv", - &timing->phy_lpddr3_dq_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr3_odt", - &timing->phy_lpddr3_odt); + &data->lpddr3_odt_dis_freq); ret |=3D of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", - &timing->lpddr4_odt_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,lpddr4_drv", - &timing->lpddr4_drv); - ret |=3D of_property_read_u32(np, "rockchip,lpddr4_dq_odt", - &timing->lpddr4_dq_odt); - ret |=3D of_property_read_u32(np, "rockchip,lpddr4_ca_odt", - &timing->lpddr4_ca_odt); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv", - &timing->phy_lpddr4_ca_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv", - &timing->phy_lpddr4_ck_cs_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv", - &timing->phy_lpddr4_dq_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_odt", - &timing->phy_lpddr4_odt); + &data->lpddr4_odt_dis_freq); =20 return ret; } @@ -311,8 +245,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D pdev->dev.of_node, *node; struct rk3399_dmcfreq *data; - int ret, index, size; - uint32_t *timing; + int ret; struct dev_pm_opp *opp; u32 ddr_type; u32 val; @@ -343,26 +276,7 @@ static int rk3399_dmcfreq_probe(struct platform_device= *pdev) return ret; } =20 - /* - * Get dram timing and pass it to arm trust firmware, - * the dram driver in arm trust firmware will get these - * timing and to do dram initial. - */ - if (!of_get_ddr_timings(&data->timing, np)) { - timing =3D &data->timing.ddr3_speed_bin; - size =3D sizeof(struct dram_timing) / 4; - for (index =3D 0; index < size; index++) { - arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, - ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM, - 0, 0, 0, 0, &res); - if (res.a0) { - dev_err(dev, "Failed to set dram param: %ld\n", - res.a0); - ret =3D -EINVAL; - goto err_edev; - } - } - } + rk3399_dmcfreq_of_props(data, np); =20 node =3D of_parse_phandle(np, "rockchip,pmu", 0); if (!node) @@ -381,13 +295,13 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) =20 switch (ddr_type) { case RK3399_PMUGRF_DDRTYPE_DDR3: - data->odt_dis_freq =3D data->timing.ddr3_odt_dis_freq; + data->odt_dis_freq =3D data->ddr3_odt_dis_freq; break; case RK3399_PMUGRF_DDRTYPE_LPDDR3: - data->odt_dis_freq =3D data->timing.lpddr3_odt_dis_freq; + data->odt_dis_freq =3D data->lpddr3_odt_dis_freq; break; case RK3399_PMUGRF_DDRTYPE_LPDDR4: - data->odt_dis_freq =3D data->timing.lpddr4_odt_dis_freq; + data->odt_dis_freq =3D data->lpddr4_odt_dis_freq; break; default: ret =3D -EINVAL; @@ -414,11 +328,11 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) * arg2: * bit[0] : odt enable */ - data->odt_pd_arg0 =3D (data->timing.sr_idle & 0xff) | - ((data->timing.sr_mc_gate_idle & 0xff) << 8) | - ((data->timing.standby_idle & 0xffff) << 16); - data->odt_pd_arg1 =3D (data->timing.pd_idle & 0xfff) | - ((data->timing.srpd_lite_idle & 0xfff) << 16); + data->odt_pd_arg0 =3D (data->sr_idle & 0xff) | + ((data->sr_mc_gate_idle & 0xff) << 8) | + ((data->standby_idle & 0xffff) << 16); + data->odt_pd_arg1 =3D (data->pd_idle & 0xfff) | + ((data->srpd_lite_idle & 0xfff) << 16); =20 /* * We add a devfreq driver to our parent since it has a device tree node --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4689C433FE for ; Thu, 27 Jan 2022 23:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344545AbiA0XIx (ORCPT ); Thu, 27 Jan 2022 18:08:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344260AbiA0XIn (ORCPT ); Thu, 27 Jan 2022 18:08:43 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28283C06175E for ; Thu, 27 Jan 2022 15:08:40 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id i1so4185178pla.9 for ; Thu, 27 Jan 2022 15:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P0joUK/pdUbQ+tkRTC3slVsYBufXst0qResCEw1GAIA=; b=BnDRXk0/6EBRLVuizHHpYzMVT205phm4z1vtVYFekaSNBBGlmSe7dnC89KkP+OZt1G siu7id/3fNo2OQJWUz2DUH2Qqu3hNfEMPvBy0PFOSDsE0iX3SBC8JOdtXPCvtW9Er8p0 4nBNdSrt4WvJktSG23xNKi00oMJoBAbhFo92w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P0joUK/pdUbQ+tkRTC3slVsYBufXst0qResCEw1GAIA=; b=4Pmt7U0vnMC5E7wmLeJjnN8DeURBJdc1m/qrVPJdXyde+NpARPRHOmnz+cQ/JyHuuE kDb46vJCt8xK/KZD0Fu06NyB/rioSKyBVI0/6CWLD8PDx8KUPxM/MSupnVRqqNXulB7j A9xJhZCo+ivXBXVXO928rpb6fYJgrHovoFhoYA/aiI9L1vuvySuGGKrfWRHCrDa9J3Ga o0M2mDRzIV/eBgnt28N11bBbQZQx09UdBY1V8bbOq44I2xsoVcFYWFVD3Ma7Ag/tt/DS 2QcKcagYKPumiGcqToD6PNxgOy7Wtm7+FfsWfL1ovDPrayuo7rURnQj82GYjch8DKDXT WYdA== X-Gm-Message-State: AOAM530Xt/KCYAnncb8QPgVSI8guOXoXdaqQPCimaeFJe6wDfvjVP1Q5 KoRfBl9FQ3AAIVNO/gNax4FLnP05Ofzuww== X-Google-Smtp-Source: ABdhPJygQAI1P2SOa4Oto5BDHOx+X35TmrwOGXC/s5RZcVPqZCFxYS6m1xx9ePbYZiM/Z5xhtIElww== X-Received: by 2002:a17:90b:4b83:: with SMTP id lr3mr16431459pjb.42.1643324919686; Thu, 27 Jan 2022 15:08:39 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id s6sm369704pjg.22.2022.01.27.15.08.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:39 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 08/15] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD Date: Thu, 27 Jan 2022 15:07:19 -0800 Message-Id: <20220127150615.v2.8.I0f36da588afd01d0dc9ce5866240efa34bd91e21@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We're going to add new usages, and it's cleaner to work with macros instead of comments and magic numbers. Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 43 ++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 8f447217303f..c4efbc15cbb1 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -23,6 +24,15 @@ #include #include =20 +#define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0) +#define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8) +#define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16) + +#define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0) +#define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16) + +#define RK3399_SET_ODT_PD_2_ODT_ENABLE BIT(0) + struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; @@ -55,7 +65,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsi= gned long *freq, unsigned long old_clk_rate =3D dmcfreq->rate; unsigned long target_volt, target_rate; struct arm_smccc_res res; - bool odt_enable =3D false; int err; =20 opp =3D devfreq_recommended_opp(dev, freq, flags); @@ -72,8 +81,10 @@ static int rk3399_dmcfreq_target(struct device *dev, uns= igned long *freq, mutex_lock(&dmcfreq->lock); =20 if (dmcfreq->regmap_pmu) { + unsigned int odt_pd_arg2 =3D 0; + if (target_rate >=3D dmcfreq->odt_dis_freq) - odt_enable =3D true; + odt_pd_arg2 |=3D RK3399_SET_ODT_PD_2_ODT_ENABLE; =20 /* * This makes a SMC call to the TF-A to set the DDR PD @@ -83,7 +94,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsi= gned long *freq, arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, dmcfreq->odt_pd_arg1, ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, - odt_enable, 0, 0, 0, &res); + odt_pd_arg2, 0, 0, 0, &res); } =20 /* @@ -316,23 +327,17 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) /* * In TF-A there is a platform SIP call to set the PD (power-down) * timings and to enable or disable the ODT (on-die termination). - * This call needs three arguments as follows: - * - * arg0: - * bit[0-7] : sr_idle - * bit[8-15] : sr_mc_gate_idle - * bit[16-31] : standby idle - * arg1: - * bit[0-11] : pd_idle - * bit[16-27] : srpd_lite_idle - * arg2: - * bit[0] : odt enable */ - data->odt_pd_arg0 =3D (data->sr_idle & 0xff) | - ((data->sr_mc_gate_idle & 0xff) << 8) | - ((data->standby_idle & 0xffff) << 16); - data->odt_pd_arg1 =3D (data->pd_idle & 0xfff) | - ((data->srpd_lite_idle & 0xfff) << 16); + data->odt_pd_arg0 =3D + FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE, + data->sr_mc_gate_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE, + data->standby_idle); + data->odt_pd_arg1 =3D + FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE, + data->srpd_lite_idle); =20 /* * We add a devfreq driver to our parent since it has a device tree node --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FE3CC433FE for ; Thu, 27 Jan 2022 23:09:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344714AbiA0XJN (ORCPT ); Thu, 27 Jan 2022 18:09:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344303AbiA0XIn (ORCPT ); Thu, 27 Jan 2022 18:08:43 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E64CC061749 for ; Thu, 27 Jan 2022 15:08:42 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id l24-20020a17090aec1800b001b55738f633so6043025pjy.1 for ; Thu, 27 Jan 2022 15:08:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2CpJvXPo2f7MRYObSqB2TPJqiUKrFA3vxItu5+XYK4E=; b=RMywaGeGSUmwaERdUZXc9MuVTXOPqFgSFhHBitMJ8rd4ASs7kZQ022V1CUjjIYErrP 1+LuIQdQlFuLiG+S0snlh+YJwpNbeCQv9GxVu8jX9W/6cq9Tx5JKPMsE5HDiBxywBrkn +LKU1Wi7Afnuc9KbFJYSnjvTkkmfduZqVbbW0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2CpJvXPo2f7MRYObSqB2TPJqiUKrFA3vxItu5+XYK4E=; b=02fRmD2nppB1B+c0tQstJwUIbYKCvSXPAikguLPFcBeJnqUkXV3dAW67NFrBWw1LK5 FNmMpMEVsy94a4kZTJfbiCEFrWFWdZUHBvzPn2C/p+lqjjgBX+QkWl8ihoQ2YsPyaGO1 t3QoPD6WV5Tkkg6wTq0A630fDPHo45Azf4ed6sSl5LDDLwjVGiyG7mN+RzK4N38o435r a28/wzeRaayQwlH3xIqFMxnagirDuxND0xuVwqAlkbOkgGFBrWTg0HOUeevAWP0+xjgd bYIHSUJ68/KRxyTcp27q/1RGxAAJptnxZ2yJPZrHCb0pM8G5cZxWAnqwiBsHMecQzX2k Da0w== X-Gm-Message-State: AOAM531W+0gBKyb1qyAB7p5ufGmsu+bLrY8zETPDiSsB6b4i/GnClQPA 4Ohv1JolOzScPfLr/+QEDftotA== X-Google-Smtp-Source: ABdhPJy7XLBtJwlwzqij9tbWm9vhWkNj4dblv+pYuN1DbddFkcM4t+BTJNdAAI3cfZtgWDwaQAdXxA== X-Received: by 2002:a17:90a:de98:: with SMTP id n24mr6656488pjv.87.1643324921749; Thu, 27 Jan 2022 15:08:41 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id ck21sm338858pjb.51.2022.01.27.15.08.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:41 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 09/15] PM / devfreq: rk3399_dmc: Support new disable-freq properties Date: Thu, 27 Jan 2022 15:07:20 -0800 Message-Id: <20220127150615.v2.9.I08d654522b8a1ae92ecb8d2e2a74511f778f61e5@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the newly-defined properties to allow disabling certain power-saving-at-idle features at higher frequencies. This is a rewritten version of work by Lin Huang . Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 51 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index c4efbc15cbb1..fc740c1f6747 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -55,6 +55,12 @@ struct rk3399_dmcfreq { unsigned int ddr3_odt_dis_freq; unsigned int lpddr3_odt_dis_freq; unsigned int lpddr4_odt_dis_freq; + + unsigned int pd_idle_dis_freq; + unsigned int sr_idle_dis_freq; + unsigned int sr_mc_gate_idle_dis_freq; + unsigned int srpd_lite_idle_dis_freq; + unsigned int standby_idle_dis_freq; }; =20 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, @@ -81,8 +87,25 @@ static int rk3399_dmcfreq_target(struct device *dev, uns= igned long *freq, mutex_lock(&dmcfreq->lock); =20 if (dmcfreq->regmap_pmu) { + unsigned int odt_pd_arg0 =3D dmcfreq->odt_pd_arg0; + unsigned int odt_pd_arg1 =3D dmcfreq->odt_pd_arg1; unsigned int odt_pd_arg2 =3D 0; =20 + if (target_rate >=3D dmcfreq->sr_idle_dis_freq) + odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_SR_IDLE; + + if (target_rate >=3D dmcfreq->sr_mc_gate_idle_dis_freq) + odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE; + + if (target_rate >=3D dmcfreq->standby_idle_dis_freq) + odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_STANDBY_IDLE; + + if (target_rate >=3D dmcfreq->pd_idle_dis_freq) + odt_pd_arg1 &=3D ~RK3399_SET_ODT_PD_1_PD_IDLE; + + if (target_rate >=3D dmcfreq->srpd_lite_idle_dis_freq) + odt_pd_arg1 &=3D ~RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE; + if (target_rate >=3D dmcfreq->odt_dis_freq) odt_pd_arg2 |=3D RK3399_SET_ODT_PD_2_ODT_ENABLE; =20 @@ -91,10 +114,9 @@ static int rk3399_dmcfreq_target(struct device *dev, un= signed long *freq, * (power-down) timings and to enable or disable the * ODT (on-die termination) resistors. */ - arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, - dmcfreq->odt_pd_arg1, - ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, - odt_pd_arg2, 0, 0, 0, &res); + arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, odt_pd_arg0, odt_pd_arg1, + ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, odt_pd_arg2, + 0, 0, 0, &res); } =20 /* @@ -230,6 +252,16 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfr= eq *data, { int ret =3D 0; =20 + /* + * These are all optional, and serve as minimum bounds. Give them large + * (i.e., never "disabled") values if the DT doesn't specify one. + */ + data->pd_idle_dis_freq =3D + data->sr_idle_dis_freq =3D + data->sr_mc_gate_idle_dis_freq =3D + data->srpd_lite_idle_dis_freq =3D + data->standby_idle_dis_freq =3D UINT_MAX; + ret |=3D of_property_read_u32(np, "rockchip,pd_idle", &data->pd_idle); ret |=3D of_property_read_u32(np, "rockchip,sr_idle", @@ -247,6 +279,17 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfr= eq *data, ret |=3D of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", &data->lpddr4_odt_dis_freq); =20 + ret |=3D of_property_read_u32(np, "rockchip,pd-idle-dis-freq-hz", + &data->pd_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,sr-idle-dis-freq-hz", + &data->sr_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,sr-mc-gate-idle-dis-freq-hz", + &data->sr_mc_gate_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,srpd-lite-idle-dis-freq-hz", + &data->srpd_lite_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,standby-idle-dis-freq-hz", + &data->standby_idle_dis_freq); + return ret; } =20 --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B50F9C43217 for ; Thu, 27 Jan 2022 23:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344579AbiA0XI6 (ORCPT ); Thu, 27 Jan 2022 18:08:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344472AbiA0XIq (ORCPT ); Thu, 27 Jan 2022 18:08:46 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39AC3C061756 for ; Thu, 27 Jan 2022 15:08:44 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id x11so4210498plg.6 for ; Thu, 27 Jan 2022 15:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O9UUBFHvbSrtJMfZR9HJLLl/uTdLWsiae0TVMvt6HWo=; b=WZ5WVi8R+bmMgknUpN9mtZuAUztF0PXl5q1MvKtTVVlbJV/nokfuBkGkbupYK/bjnL MghDXT89x7o7pz8erRgPiNB1tbJj41LzolRQRLknKPj794F0YYWiyV18zLsEjpknXcpC S6m4H9JZkY4Vq1lFjVzu3Ona8/l/63mH45q5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O9UUBFHvbSrtJMfZR9HJLLl/uTdLWsiae0TVMvt6HWo=; b=u3avOX9f34Ype660yoI0FYTfH47KDN/uEWy1PRlrCo3sl5aIMWyLMIocEb3KaQdR+J jzhPJXAUDGkjVuFPq3bxGWlqRft5mZk/73uIHg++yAicOYjlcodZFvYmhXz4p3BiWzkA DR0iWP02tN2Rd43sSLjK6ag7FnzZrDZX9DaUpOHRwygXs84Pl+2pizL+O5VnMMJo1J7R 7modjYNQdvB0wWmNSpCnqZbNswQjYqMqNRgeUyk3sXvSu+wvpJBQQfkDeddmBkJM9I6w fH/EDlOaWnGKrx+PYiXnE+eI82HJYwCWSDwhNKaQNwLf0/bs7T2vevKE0gImPyad54IF KPyg== X-Gm-Message-State: AOAM531Kn0vD6XtoBvP2cQ7CaTcjENYovmBNBRkYnWhwsIMuiFFpl5Ka DX4eWVYlxDB+opkNs5sFuA/c1w== X-Google-Smtp-Source: ABdhPJwLYXBQbIhC3AWRQacZGe/+yRBB0PUOR8RSC8ozjMA3n/Xb0G8ifymvRon0Yc8CnrtIKg+b9A== X-Received: by 2002:a17:902:ba98:: with SMTP id k24mr5444084pls.44.1643324923796; Thu, 27 Jan 2022 15:08:43 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id k15sm6933107pff.39.2022.01.27.15.08.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:43 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 10/15] PM / devfreq: rk3399_dmc: Support new *-ns properties Date: Thu, 27 Jan 2022 15:07:21 -0800 Message-Id: <20220127150615.v2.10.I4e01e243ea11e9f95295b40b44a9eaa3a883a0dd@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We want to keep the idle time fixed, so compute based on the current DDR frequency. The old properties were deprecated and never used, so we can safely drop them from the driver. This is a rewritten version of work by Lin Huang . Signed-off-by: Brian Norris --- Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 85 +++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 35 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index fc740c1f6747..f778564cab49 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -24,6 +24,8 @@ #include #include =20 +#define NS_TO_CYCLE(NS, MHz) (((NS) * (MHz)) / NSEC_PER_USEC) + #define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0) #define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8) #define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16) @@ -45,13 +47,12 @@ struct rk3399_dmcfreq { unsigned long rate, target_rate; unsigned long volt, target_volt; unsigned int odt_dis_freq; - int odt_pd_arg0, odt_pd_arg1; =20 - unsigned int pd_idle; - unsigned int sr_idle; - unsigned int sr_mc_gate_idle; - unsigned int srpd_lite_idle; - unsigned int standby_idle; + unsigned int pd_idle_ns; + unsigned int sr_idle_ns; + unsigned int sr_mc_gate_idle_ns; + unsigned int srpd_lite_idle_ns; + unsigned int standby_idle_ns; unsigned int ddr3_odt_dis_freq; unsigned int lpddr3_odt_dis_freq; unsigned int lpddr4_odt_dis_freq; @@ -70,9 +71,14 @@ static int rk3399_dmcfreq_target(struct device *dev, uns= igned long *freq, struct dev_pm_opp *opp; unsigned long old_clk_rate =3D dmcfreq->rate; unsigned long target_volt, target_rate; + unsigned int ddrcon_mhz; struct arm_smccc_res res; int err; =20 + u32 odt_pd_arg0 =3D 0; + u32 odt_pd_arg1 =3D 0; + u32 odt_pd_arg2 =3D 0; + opp =3D devfreq_recommended_opp(dev, freq, flags); if (IS_ERR(opp)) return PTR_ERR(opp); @@ -86,11 +92,35 @@ static int rk3399_dmcfreq_target(struct device *dev, un= signed long *freq, =20 mutex_lock(&dmcfreq->lock); =20 - if (dmcfreq->regmap_pmu) { - unsigned int odt_pd_arg0 =3D dmcfreq->odt_pd_arg0; - unsigned int odt_pd_arg1 =3D dmcfreq->odt_pd_arg1; - unsigned int odt_pd_arg2 =3D 0; + /* + * Some idle parameters may be based on the DDR controller clock, which + * is half of the DDR frequency. + * pd_idle and standby_idle are based on the controller clock cycle. + * sr_idle_cycle, sr_mc_gate_idle_cycle, and srpd_lite_idle_cycle + * are based on the 1024 controller clock cycle + */ + ddrcon_mhz =3D target_rate / USEC_PER_SEC / 2; + + u32p_replace_bits(&odt_pd_arg1, + NS_TO_CYCLE(dmcfreq->pd_idle_ns, ddrcon_mhz), + RK3399_SET_ODT_PD_1_PD_IDLE); + u32p_replace_bits(&odt_pd_arg0, + NS_TO_CYCLE(dmcfreq->standby_idle_ns, ddrcon_mhz), + RK3399_SET_ODT_PD_0_STANDBY_IDLE); + u32p_replace_bits(&odt_pd_arg0, + DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_idle_ns, + ddrcon_mhz), 1024), + RK3399_SET_ODT_PD_0_SR_IDLE); + u32p_replace_bits(&odt_pd_arg0, + DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_mc_gate_idle_ns, + ddrcon_mhz), 1024), + RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE); + u32p_replace_bits(&odt_pd_arg1, + DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->srpd_lite_idle_ns, + ddrcon_mhz), 1024), + RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE); =20 + if (dmcfreq->regmap_pmu) { if (target_rate >=3D dmcfreq->sr_idle_dis_freq) odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_SR_IDLE; =20 @@ -262,16 +292,16 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcf= req *data, data->srpd_lite_idle_dis_freq =3D data->standby_idle_dis_freq =3D UINT_MAX; =20 - ret |=3D of_property_read_u32(np, "rockchip,pd_idle", - &data->pd_idle); - ret |=3D of_property_read_u32(np, "rockchip,sr_idle", - &data->sr_idle); - ret |=3D of_property_read_u32(np, "rockchip,sr_mc_gate_idle", - &data->sr_mc_gate_idle); - ret |=3D of_property_read_u32(np, "rockchip,srpd_lite_idle", - &data->srpd_lite_idle); - ret |=3D of_property_read_u32(np, "rockchip,standby_idle", - &data->standby_idle); + ret |=3D of_property_read_u32(np, "rockchip,pd-idle-ns", + &data->pd_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,sr-idle-ns", + &data->sr_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,sr-mc-gate-idle-ns", + &data->sr_mc_gate_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,srpd-lite-idle-ns", + &data->srpd_lite_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,standby-idle-ns", + &data->standby_idle_ns); ret |=3D of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", &data->ddr3_odt_dis_freq); ret |=3D of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", @@ -367,21 +397,6 @@ static int rk3399_dmcfreq_probe(struct platform_device= *pdev) ROCKCHIP_SIP_CONFIG_DRAM_INIT, 0, 0, 0, 0, &res); =20 - /* - * In TF-A there is a platform SIP call to set the PD (power-down) - * timings and to enable or disable the ODT (on-die termination). - */ - data->odt_pd_arg0 =3D - FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) | - FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE, - data->sr_mc_gate_idle) | - FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE, - data->standby_idle); - data->odt_pd_arg1 =3D - FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) | - FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE, - data->srpd_lite_idle); - /* * We add a devfreq driver to our parent since it has a device tree node * with operating points. --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EBEEC433F5 for ; Thu, 27 Jan 2022 23:09:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344595AbiA0XJA (ORCPT ); Thu, 27 Jan 2022 18:09:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344504AbiA0XIr (ORCPT ); Thu, 27 Jan 2022 18:08:47 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32DE5C06176C for ; Thu, 27 Jan 2022 15:08:46 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id q75so3658268pgq.5 for ; Thu, 27 Jan 2022 15:08:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fXezxkg2kGuWbB36YJn2JEHiHCC80Um0xlTyospu4bE=; b=W52+ysBtqCsUepS7IJiVv6MqZt+QdNIY980EbuHquIW6109/e0+n0y9mwaOPmdVytS uRAk7qC1DiU/CwNi49mc4RvLPdUna1Oqj5Qgt0jPuWkra+DTqe1xx5fnNx2rjw/SO5hh qVqkuZdKSeug7aH608jY9tfD7Q/F1d9LkblPo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fXezxkg2kGuWbB36YJn2JEHiHCC80Um0xlTyospu4bE=; b=b9eIoOdGPN6yQMhGwKWWqgc2H/SPq1D0IQvIsppQHlOX8ASsOGv8az58a5M46q9Jrp C3FtfIOhkfLrucb6AIQWXHMznfQNQVTYR8HTuriO6Cxqi6PFsyPXis791XXnFMFjmbO/ QHeXBiPScGqE/wkrHK1HFMu/jNqpb+bL4U5tQ4yD1cJZ/gmVb03/q/NKpD39Bgsw9GWK xmyFSeuFXWHr0Z06m1WElHmouZxitzZHvq++/YOTe2unNr3uhxFR7gC1Dh/JGg0GDyHG o8gkAxkucSS4k5RqJnlr8iqgBpAOY8m99yJfw5BckH8hoYH8qNFD9VQVEu6jKfDXfJW/ Ljgg== X-Gm-Message-State: AOAM5325066xGQCfvvCvdMPY4cWr3Hrw8sxStxGBGkCdLrsdVrU8BaP1 mnuT55oFq1JGn5ZDIGombQHYyA== X-Google-Smtp-Source: ABdhPJzIjPFzmvY95upLY8umBbY8uqvVIvgVAGp2b3szXo3MoWikHuPQAGZ4kG2PB8Y9F89T9NfEvQ== X-Received: by 2002:a62:1cc9:: with SMTP id c192mr4895534pfc.70.1643324925797; Thu, 27 Jan 2022 15:08:45 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id n22sm6497884pfu.77.2022.01.27.15.08.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:45 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Enric Balletbo i Serra , =?UTF-8?q?Ga=C3=ABl=20PORTAY?= , Daniel Lezcano , Brian Norris Subject: [PATCH v2 11/15] arm64: dts: rk3399: Add dfi and dmc nodes Date: Thu, 27 Jan 2022 15:07:22 -0800 Message-Id: <20220127150615.v2.11.Ie97993621975c5463d7928a8646f3737c9f2921d@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lin Huang These are required to support DDR DVFS on RK3399 platforms. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Ga=C3=ABl PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Change since Daniel's posting: reordered by unit address, per existing style --- Changes in v2: - rename dmc to memory-controller Changes in v1: This is based on a v5 posting from various authors: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.o= rg/ Much of that series was already merged, so I start over with the numbering. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts= /rockchip/rk3399.dtsi index d3cdf6f42a30..4096ef6f7b72 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1295,6 +1295,25 @@ pwm3: pwm@ff420030 { status =3D "disabled"; }; =20 + dfi: dfi@ff630000 { + reg =3D <0x00 0xff630000 0x00 0x4000>; + compatible =3D "rockchip,rk3399-dfi"; + rockchip,pmu =3D <&pmugrf>; + interrupts =3D ; + clocks =3D <&cru PCLK_DDR_MON>; + clock-names =3D "pclk_ddr_mon"; + status =3D "disabled"; + }; + + dmc: memory-controller { + compatible =3D "rockchip,rk3399-dmc"; + rockchip,pmu =3D <&pmugrf>; + devfreq-events =3D <&dfi>; + clocks =3D <&cru SCLK_DDRC>; + clock-names =3D "dmc_clk"; + status =3D "disabled"; + }; + vpu: video-codec@ff650000 { compatible =3D "rockchip,rk3399-vpu"; reg =3D <0x0 0xff650000 0x0 0x800>; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CB95C433F5 for ; Thu, 27 Jan 2022 23:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344650AbiA0XJH (ORCPT ); Thu, 27 Jan 2022 18:09:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344513AbiA0XIs (ORCPT ); Thu, 27 Jan 2022 18:08:48 -0500 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55A49C06175C for ; Thu, 27 Jan 2022 15:08:48 -0800 (PST) Received: by mail-pf1-x42f.google.com with SMTP id n32so4343960pfv.11 for ; Thu, 27 Jan 2022 15:08:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H3WPdl8RHDSD1wX3WYrqIIpaKS0otWy1CXBFRdtFIp0=; b=MI68bzzOlftwsLGrBYAOzyCTdVT7/DjY0G28T/dktb1p+eyNQg3lJ38XqA+02nrBSc MlpQ+bwattyukKMVxifDcCRAefoXuFGzT6ODOCQjr3VmwTb1WTYp7pMoDJmFVXvaU0gx GIYMCkunM9HKsSMPediCjBTpAmV/CiExCjGxo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H3WPdl8RHDSD1wX3WYrqIIpaKS0otWy1CXBFRdtFIp0=; b=enXPd6OSTXQtvMBxiQgLE0w1zgi4LLI9SLQU+X8rJKMrdi0r9ys0sA1OhEcJ6X41+B MzweUj+vODc4+DUaTwELuiB+kf0qBo+2eOLrdUJ6DZsmnKynR3CDW55dRxDyz8kPz4xO sVOIkw9R2RwnxYy2C4UW024viikv9zSQblrnPZ/KRwBlIaSWIDB9r7GUETV2LnEHFdcq WBSbp15SZ2TgH2Q1SFatGOqwAGB02Eop2A2H1wVZL+6+kVFD9gIZ4b2++1AfwtZ9dzhL a9/oQ1U/2N9EX6m7u2KHSpsuZwnPTPrnrcyFyMkSoCbRW/vCBsdxIP8abiGNfWht/bNA /8qA== X-Gm-Message-State: AOAM532kGUE+zTDCaJktViw1U9ZNRgQlLawl1Subg0waiV6Eow2kEPT2 KUk5bTMJ/S2fGwjOjOK9dr2ksQ== X-Google-Smtp-Source: ABdhPJxHGKBFiprBfzF/G3/1M/XaUir6+M8cdNjBdHlepR+kl6Wvt2iHAswSxIZ9FoocWQX1BCjKkw== X-Received: by 2002:a63:245:: with SMTP id 66mr2604212pgc.349.1643324927837; Thu, 27 Jan 2022 15:08:47 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id z124sm6396253pfb.166.2022.01.27.15.08.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:47 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Enric Balletbo i Serra , =?UTF-8?q?Ga=C3=ABl=20PORTAY?= , Daniel Lezcano , Brian Norris Subject: [PATCH v2 12/15] arm64: dts: rockchip: Enable dmc and dfi nodes on gru Date: Thu, 27 Jan 2022 15:07:23 -0800 Message-Id: <20220127150615.v2.12.I3a5c7f21ecd8221b42c2dbcd618386bce7b3e9a6@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lin Huang Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Ga=C3=ABl PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Updates since the old series: - reordered alphabetically by phandle name, per style - drop a ton of deprecated/unused properties - add required center-supply for scarlet - add new *_idle_dis_freq properties - drop the lowest (200 MHz) OPP; this was never stabilized for production - bump the voltage (0.9V -> 0.925V) for the highest OPP on Chromebook models; later (tablet) models were more stable, with a fixed DDR regulator - bump odt_dis_freq to 666 MHz; early versions used 333 MHz, but stabilization efforts landed on 666 MHz for production --- Changes in v2: - Adapt to new properties Changes in v1: This was part of a previous series, at: https://lore.kernel.org/r/20210308233858.24741-3-daniel.lezcano@linaro.org I've picked up a bunch of changes and fixes, so I've restarted the patch series numbering. .../dts/rockchip/rk3399-gru-chromebook.dtsi | 7 +++++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++ 4 files changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch= /arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9b2c679f5eca..cc8950046d94 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -234,6 +234,13 @@ &cdn_dp { extcon =3D <&usbc_extcon0>, <&usbc_extcon1>; }; =20 +&dmc { + center-supply =3D <&ppvar_centerlogic>; + rockchip,pd-idle-dis-freq-hz =3D <800000000>; + rockchip,sr-idle-dis-freq-hz =3D <800000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz =3D <800000000>; +}; + &edp { status =3D "okay"; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/ar= m64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index a9817b3d7edc..913d845eb51a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -391,6 +391,18 @@ &cru { <400000000>; }; =20 +/* The center supply is fixed to .9V on scarlet */ +&dmc { + center-supply =3D <&pp900_s0>; +}; + +/* We don't need .925 V for 928 MHz on scarlet */ +&dmc_opp_table { + opp03 { + opp-microvolt =3D <900000>; + }; +}; + &gpio0 { gpio-line-names =3D /* GPIO0 A 0-7 */ "CLK_32K_AP", diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..23bfba86daab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -373,6 +373,34 @@ &cru { <200000000>; }; =20 +&dfi { + status =3D "okay"; +}; + +&dmc { + status =3D "okay"; + + rockchip,pd-idle-ns =3D <160>; + rockchip,sr-idle-ns =3D <10240>; + rockchip,sr-mc-gate-idle-ns =3D <40960>; + rockchip,srpd-lite-idle-ns =3D <61440>; + rockchip,standby-idle-ns =3D <81920>; + + rockchip,ddr3_odt_dis_freq =3D <666000000>; + rockchip,lpddr3_odt_dis_freq =3D <666000000>; + rockchip,lpddr4_odt_dis_freq =3D <666000000>; + + rockchip,sr-mc-gate-idle-dis-freq-hz =3D <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz =3D <0>; + rockchip,standby-idle-dis-freq-hz =3D <928000000>; +}; + +&dmc_opp_table { + opp03 { + opp-suspend; + }; +}; + &emmc_phy { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/= boot/dts/rockchip/rk3399-op1-opp.dtsi index 2180e0f75003..6e29e74f6fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,27 @@ opp05 { opp-microvolt =3D <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible =3D "operating-points-v2"; + + opp00 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <900000>; + }; + opp01 { + opp-hz =3D /bits/ 64 <666000000>; + opp-microvolt =3D <900000>; + }; + opp02 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <900000>; + }; + opp03 { + opp-hz =3D /bits/ 64 <928000000>; + opp-microvolt =3D <925000>; + }; + }; }; =20 &cpu_l0 { @@ -136,6 +157,10 @@ &cpu_b1 { operating-points-v2 =3D <&cluster1_opp>; }; =20 +&dmc { + operating-points-v2 =3D <&dmc_opp_table>; +}; + &gpu { operating-points-v2 =3D <&gpu_opp_table>; }; --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96197C433F5 for ; Thu, 27 Jan 2022 23:09:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245539AbiA0XJK (ORCPT ); Thu, 27 Jan 2022 18:09:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344400AbiA0XIu (ORCPT ); Thu, 27 Jan 2022 18:08:50 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94967C06174A for ; Thu, 27 Jan 2022 15:08:50 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id u130so4372414pfc.2 for ; Thu, 27 Jan 2022 15:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EE6yOukYiRv5t8m4wLbwnB8xsnP3xhP8Res4dSCKaao=; b=nmRFGuUfVGO1KN+i396jwFdqW3ji1pT8oIqYTB5EuvvDuDjJ4JLEpzIqppQ63Ye9oy hIC7Gfe2HCmAYKlFN7ntRE0NoWVXbgljdPNyr9JIyCzAFu3DbwqJUQ5DfovNWtpqnxdG 58KCpRNpof8Q2dQeySnSxQSVVVH/YetiHbpPM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EE6yOukYiRv5t8m4wLbwnB8xsnP3xhP8Res4dSCKaao=; b=R5KtuG9LdOPvYUvNXBtspx4+mE03EntfIkGr1YWFKsWSdx5YmjszPhni7S2AN/2dRg RNzYwvMawfiNxDXy4xEXsXTmgX/iILR5IF8p2qIbRhvxkM9EOKtevsLSBfhGQWHsj5N4 SpW/OnYdQa4MLTeYwA1SXigVp4wRc493KAUscHpdhpkP/8/P4CPcJIeJvfPFinO/4/Fh TltK0v0+P7BmNTz2drAhoEG2aF/zM7zQxOSg9225SwNJi98bA8BG/DcbD2fZdd+xL8n/ gdooRWS4S4icEe2URlB2T92DWmbS2OH6tPhxDm0icAyG6Wo8wQFBW4hiXCfJ7cJPqb83 z1rQ== X-Gm-Message-State: AOAM5308wuMQJ/0gCLTEMi7KE/pQ+GEznQr9hWUz2Qw+UxhvUnYCjjs8 l4ERqOGNZ/05iX1IjLLQmWK2mg== X-Google-Smtp-Source: ABdhPJz2hxjAYMq7nKYFqCN7bLNZ95pkrVKsFwO5nn2OivAjhokfFleQHjW/LAwoP5kPOvqwcxld4Q== X-Received: by 2002:a65:6951:: with SMTP id w17mr4482809pgq.108.1643324930151; Thu, 27 Jan 2022 15:08:50 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id v20sm5384419pfu.155.2022.01.27.15.08.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:49 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 13/15] PM / devfreq: rk3399_dmc: Disable edev on remove() Date: Thu, 27 Jan 2022 15:07:24 -0800 Message-Id: <20220127150615.v2.13.I1476960b2586441beaef21dca4feb3ecc067f768@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Otherwise we hit an unablanced enable-count when unbinding the DFI device: [ 1279.659119] ------------[ cut here ]------------ [ 1279.659179] WARNING: CPU: 2 PID: 5638 at drivers/devfreq/devfreq-event.c= :360 devfreq_event_remove_edev+0x84/0x8c ... [ 1279.659352] Hardware name: Google Kevin (DT) [ 1279.659363] pstate: 80400005 (Nzcv daif +PAN -UAO -TCO BTYPE=3D--) [ 1279.659371] pc : devfreq_event_remove_edev+0x84/0x8c [ 1279.659380] lr : devm_devfreq_event_release+0x1c/0x28 ... [ 1279.659571] Call trace: [ 1279.659582] devfreq_event_remove_edev+0x84/0x8c [ 1279.659590] devm_devfreq_event_release+0x1c/0x28 [ 1279.659602] release_nodes+0x1cc/0x244 [ 1279.659611] devres_release_all+0x44/0x60 [ 1279.659621] device_release_driver_internal+0x11c/0x1ac [ 1279.659629] device_driver_detach+0x20/0x2c [ 1279.659641] unbind_store+0x7c/0xb0 [ 1279.659650] drv_attr_store+0x2c/0x40 [ 1279.659663] sysfs_kf_write+0x44/0x58 [ 1279.659672] kernfs_fop_write_iter+0xf4/0x190 [ 1279.659684] vfs_write+0x2b0/0x2e4 [ 1279.659693] ksys_write+0x80/0xec [ 1279.659701] __arm64_sys_write+0x24/0x30 [ 1279.659714] el0_svc_common+0xf0/0x1d8 [ 1279.659724] do_el0_svc_compat+0x28/0x3c [ 1279.659738] el0_svc_compat+0x10/0x1c [ 1279.659746] el0_sync_compat_handler+0xa8/0xcc [ 1279.659758] el0_sync_compat+0x188/0x1c0 [ 1279.659768] ---[ end trace cec200e5094155b4 ]--- Signed-off-by: Brian Norris --- Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index f778564cab49..fca9fcbd4249 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -452,6 +452,8 @@ static int rk3399_dmcfreq_remove(struct platform_device= *pdev) { struct rk3399_dmcfreq *dmcfreq =3D dev_get_drvdata(&pdev->dev); =20 + devfreq_event_disable_edev(dmcfreq->edev); + /* * Before remove the opp table we need to unregister the opp notifier. */ --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3912C4332F for ; Thu, 27 Jan 2022 23:09:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344735AbiA0XJQ (ORCPT ); Thu, 27 Jan 2022 18:09:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344417AbiA0XIx (ORCPT ); Thu, 27 Jan 2022 18:08:53 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E56DEC06175A for ; Thu, 27 Jan 2022 15:08:52 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id oa14-20020a17090b1bce00b001b61aed4a03so3414519pjb.5 for ; Thu, 27 Jan 2022 15:08:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TgvyNELvg3Sp7eq/kP6ZXmVUFjIF8jXZbUQbHyXbYEA=; b=ksWYFpunD8F/POefDSacV+EHnA/Ob+b1C5cIWM4AR/RdicdiwkskZr6IkLTPvIAGlx jzRkBKTSZajM3cDG91qrW1bTBuFeklxmwp2NSoSV28l53EIxjzc01BDxznvW5DWUvycM r+wZn7zVndV2p4K+H9hIjyzSRx3eZWLf/U1Xc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TgvyNELvg3Sp7eq/kP6ZXmVUFjIF8jXZbUQbHyXbYEA=; b=cYrMf6826hc91Sd9XkeRgcdy71DuiFv9qRGhpX0ln2ZwKWgVfxX7RC+9DDqfENwdPf DZ2PaacAPhZ3LdjqWG2FtSmbfbvqRXnbZTbIW5MDzEJmFFuaZMuUwWIYbQrw8wpYpxCV O2TxPQdcN/uGL3RSfT5fKAZjvlx8r3yePaT0uqnryG33wfWHXZnpo8gkt/btiPALrwHi ViuGaQl4Nnhc70llEVW9RuPYQaNRdwFpKkRWfxeuYza6YihT9uE4UBuYUH/j5j+I8oba SPOGJpHq9lTnf5oXU/Wj0H/44LgDTaHy4haOcrIGt09O78OwRx/mREIqJJyCniF/DeCY 6PkQ== X-Gm-Message-State: AOAM530PV8h+kdNQecNde/EzB72fhBoahPKPAKxwAv9md1DpKIDicoCl Xx/64JNY71rYASUwt6M5RtQWGg== X-Google-Smtp-Source: ABdhPJxGTgGsf17+kFpx/sl5BjhXHh6BcmwIuThMSQoz/ECA3RxkZOf4C40gfM6CZkmpTwdQkKj4Mw== X-Received: by 2002:a17:902:c946:: with SMTP id i6mr5502608pla.74.1643324932282; Thu, 27 Jan 2022 15:08:52 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id 5sm367869pjf.34.2022.01.27.15.08.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:51 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 14/15] PM / devfreq: rk3399_dmc: Use devm_pm_opp_of_add_table() Date: Thu, 27 Jan 2022 15:07:25 -0800 Message-Id: <20220127150615.v2.14.I3df48ceacbf299549501a44433039d46e0a275ea@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This simplifies error-cleanup and remove(). Signed-off-by: Brian Norris --- Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index fca9fcbd4249..9615658d04ae 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -401,7 +401,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) * We add a devfreq driver to our parent since it has a device tree node * with operating points. */ - if (dev_pm_opp_of_add_table(dev)) { + if (devm_pm_opp_of_add_table(dev)) { dev_err(dev, "Invalid operating-points in device tree.\n"); ret =3D -EINVAL; goto err_edev; @@ -415,7 +415,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) opp =3D devfreq_recommended_opp(dev, &data->rate, 0); if (IS_ERR(opp)) { ret =3D PTR_ERR(opp); - goto err_free_opp; + goto err_edev; } =20 data->rate =3D dev_pm_opp_get_freq(opp); @@ -430,7 +430,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) &data->ondemand_data); if (IS_ERR(data->devfreq)) { ret =3D PTR_ERR(data->devfreq); - goto err_free_opp; + goto err_edev; } =20 devm_devfreq_register_opp_notifier(dev, data->devfreq); @@ -440,8 +440,6 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) =20 return 0; =20 -err_free_opp: - dev_pm_opp_of_remove_table(&pdev->dev); err_edev: devfreq_event_disable_edev(data->edev); =20 @@ -454,12 +452,6 @@ static int rk3399_dmcfreq_remove(struct platform_devic= e *pdev) =20 devfreq_event_disable_edev(dmcfreq->edev); =20 - /* - * Before remove the opp table we need to unregister the opp notifier. - */ - devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); - dev_pm_opp_of_remove_table(dmcfreq->dev); - return 0; } =20 --=20 2.35.0.rc0.227.g00780c9af4-goog From nobody Tue Jun 30 01:45:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7AC2C433FE for ; Thu, 27 Jan 2022 23:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343824AbiA0XJR (ORCPT ); Thu, 27 Jan 2022 18:09:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344555AbiA0XIz (ORCPT ); Thu, 27 Jan 2022 18:08:55 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E401EC061768 for ; Thu, 27 Jan 2022 15:08:54 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id s61-20020a17090a69c300b001b4d0427ea2so9266940pjj.4 for ; Thu, 27 Jan 2022 15:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Go5UOmrJA+s7smi2h52lD2tDLTL92TO4mF/3kSWc9Mw=; b=BD2hpR7jg+O2kVPF1qJXnuIpWgp1ScyjuAwtsYLAXOQDA3zbUFoCnVJJqrfqpylj9I WkldlnM7rS/nrlYZPEzyeNmMen8h5zRRumXIFqTs1NeKmEQvzAbFd1RxgdxH6oG+WCK3 A4qUAHhNqs6bC9yAGwD49KrJgLsgRsUQsKBig= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Go5UOmrJA+s7smi2h52lD2tDLTL92TO4mF/3kSWc9Mw=; b=kIUQ0HY5IplySaG4pOaTDrwJCv7F4ni01486NTXydxphIvhXxNRsw1bjaad1tEja7N 9LGR10+hX+G1f9MemDIers2WFqezTYi4QGQpDKpdpeJ2zeDHf/UC1bPDD00tSj5Hhuu9 snWud0YedUebQ8ogerxLazjNtnHFCHZPyE7On1yiFVnfnH9A61q/vbsXX0EmLc9eoEhl EKa7NGf1lb+T8PYF0/vr9bDqMF4HrPLhRiZslFWevE5JdP769fWSjM3RkqqjnDTq3/vT jk1uUq+W49ntJWcqdNwUZgkgtbz0fIMwKYHrTZz6FNQq0UPF4u827uJMcMqLuIsZo0o4 61Xg== X-Gm-Message-State: AOAM533OJoiEr0Why3nW9yCHBZTtnY0WqceBWYCE+x2OvoOijAqtxZJe Zw6vmIfCQZ6EES1oIa2GsPGTaQ== X-Google-Smtp-Source: ABdhPJzC64/S0pZWwwbAFZsH3pw2HjjqvrdmyZAjA0v0ob2Yy/chyC08JNhUoQmIoBfblbLksdOALg== X-Received: by 2002:a17:902:d4c5:: with SMTP id o5mr5877723plg.116.1643324934496; Thu, 27 Jan 2022 15:08:54 -0800 (PST) Received: from localhost ([2620:15c:202:201:723d:38a9:9e7f:3435]) by smtp.gmail.com with UTF8SMTPSA id 17sm7074374pfl.175.2022.01.27.15.08.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jan 2022 15:08:53 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Lin Huang , linux-arm-kernel@lists.infradead.org, Derek Basehore , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Brian Norris Subject: [PATCH v2 15/15] PM / devfreq: rk3399_dmc: Avoid static (reused) profile Date: Thu, 27 Jan 2022 15:07:26 -0800 Message-Id: <20220127150615.v2.15.I8d71e9555aca1fa7e532d22dd1ef27976f21799d@changeid> X-Mailer: git-send-email 2.35.0.rc0.227.g00780c9af4-goog In-Reply-To: <20220127230727.3369358-1-briannorris@chromium.org> References: <20220127230727.3369358-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This static struct can get reused if the device gets removed/reprobed, and that causes use-after-free in its ->freq_table. Let's just move the struct to our dynamic allocation. Signed-off-by: Brian Norris --- Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 9615658d04ae..e494d1497d60 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -38,6 +38,7 @@ struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; + struct devfreq_dev_profile profile; struct devfreq_simple_ondemand_data ondemand_data; struct clk *dmc_clk; struct devfreq_event_dev *edev; @@ -228,13 +229,6 @@ static int rk3399_dmcfreq_get_cur_freq(struct device *= dev, unsigned long *freq) return 0; } =20 -static struct devfreq_dev_profile rk3399_devfreq_dmc_profile =3D { - .polling_ms =3D 200, - .target =3D rk3399_dmcfreq_target, - .get_dev_status =3D rk3399_dmcfreq_get_dev_status, - .get_cur_freq =3D rk3399_dmcfreq_get_cur_freq, -}; - static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) { struct rk3399_dmcfreq *dmcfreq =3D dev_get_drvdata(dev); @@ -422,10 +416,16 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) data->volt =3D dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); =20 - rk3399_devfreq_dmc_profile.initial_freq =3D data->rate; + data->profile =3D (struct devfreq_dev_profile) { + .polling_ms =3D 200, + .target =3D rk3399_dmcfreq_target, + .get_dev_status =3D rk3399_dmcfreq_get_dev_status, + .get_cur_freq =3D rk3399_dmcfreq_get_cur_freq, + .initial_freq =3D data->rate, + }; =20 data->devfreq =3D devm_devfreq_add_device(dev, - &rk3399_devfreq_dmc_profile, + &data->profile, DEVFREQ_GOV_SIMPLE_ONDEMAND, &data->ondemand_data); if (IS_ERR(data->devfreq)) { --=20 2.35.0.rc0.227.g00780c9af4-goog