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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id lr8sm7511912pjb.11.2022.01.27.09.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 09:10:45 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Rob Clark , Sean Paul , Abhinav Kumar , David Airlie , Daniel Vetter , Jonathan Marek , Jordan Crouse , Sai Prakash Ranjan , Akhil P Oommen , Yangtao Li , AngeloGioacchino Del Regno , Bjorn Andersson , Vladimir Lypak , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/2] drm/msm/gpu: Add ctx to get_param() Date: Thu, 27 Jan 2022 09:10:38 -0800 Message-Id: <20220127171045.541341-2-robdclark@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220127171045.541341-1-robdclark@gmail.com> References: <20220127171045.541341-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rob Clark Prep work for next patch. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 ++- drivers/gpu/drm/msm/msm_drv.c | 3 ++- drivers/gpu/drm/msm/msm_gpu.h | 3 ++- drivers/gpu/drm/msm/msm_rd.c | 6 ++++-- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index f33cfa4ef1c8..caa9076197de 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -227,7 +227,8 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, return aspace; } =20 -int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) +int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, + uint32_t param, uint64_t *value) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index cffabe7d33c1..432590036b31 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -279,7 +279,8 @@ static inline int adreno_is_a650_family(struct adreno_g= pu *gpu) adreno_is_a660_family(gpu); } =20 -int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); +int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, + uint32_t param, uint64_t *value); const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname); struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 555666e3f960..72060247e43c 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -763,7 +763,8 @@ static int msm_ioctl_get_param(struct drm_device *dev, = void *data, if (!gpu) return -ENXIO; =20 - return gpu->funcs->get_param(gpu, args->param, &args->value); + return gpu->funcs->get_param(gpu, file->driver_priv, + args->param, &args->value); } =20 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 92aa1e9196c6..ba8407231340 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -42,7 +42,8 @@ struct msm_gpu_config { * + z180_gpu */ struct msm_gpu_funcs { - int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); + int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx, + uint32_t param, uint64_t *value); int (*hw_init)(struct msm_gpu *gpu); int (*pm_suspend)(struct msm_gpu *gpu); int (*pm_resume)(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c index 7e4d6460719e..dd3605b46264 100644 --- a/drivers/gpu/drm/msm/msm_rd.c +++ b/drivers/gpu/drm/msm/msm_rd.c @@ -197,13 +197,15 @@ static int rd_open(struct inode *inode, struct file *= file) =20 /* the parsing tools need to know gpu-id to know which * register database to load. + * + * Note: These particular param does not require a context */ - gpu->funcs->get_param(gpu, MSM_PARAM_GPU_ID, &val); + gpu->funcs->get_param(gpu, NULL, MSM_PARAM_GPU_ID, &val); gpu_id =3D val; =20 rd_write_section(rd, RD_GPU_ID, &gpu_id, sizeof(gpu_id)); =20 - gpu->funcs->get_param(gpu, MSM_PARAM_CHIP_ID, &val); + gpu->funcs->get_param(gpu, NULL, MSM_PARAM_CHIP_ID, &val); rd_write_section(rd, RD_CHIP_ID, &val, sizeof(val)); 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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id mm24sm3390444pjb.20.2022.01.27.09.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 09:10:49 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Rob Clark , Sean Paul , Abhinav Kumar , David Airlie , Daniel Vetter , Jonathan Marek , Jordan Crouse , Sai Prakash Ranjan , =?UTF-8?q?Christian=20K=C3=B6nig?= , Yangtao Li , Stephen Boyd , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] drm/msm/gpu: Add param to get address space faults Date: Thu, 27 Jan 2022 09:10:39 -0800 Message-Id: <20220127171045.541341-3-robdclark@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220127171045.541341-1-robdclark@gmail.com> References: <20220127171045.541341-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rob Clark Add a param so that userspace can query the fault count for faults that might effect them (ie. any context sharing the same address space). Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ drivers/gpu/drm/msm/msm_drv.c | 1 + drivers/gpu/drm/msm/msm_gem.h | 3 +++ drivers/gpu/drm/msm/msm_gpu.c | 1 + include/uapi/drm/msm_drm.h | 3 ++- 5 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index caa9076197de..05899c77ca38 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -271,6 +271,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_fi= le_private *ctx, case MSM_PARAM_FAULTS: *value =3D gpu->global_faults; return 0; + case MSM_PARAM_AS_FAULTS: + *value =3D ctx->aspace->faults; + return 0; case MSM_PARAM_SUSPENDS: *value =3D gpu->suspend_count; return 0; diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 72060247e43c..39ab9a361d7f 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -41,6 +41,7 @@ * - 1.6.0 - Syncobj support * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) + * - 1.9.0 - Add MSM_PARAM_AS_FAULTS */ #define MSM_VERSION_MAJOR 1 #define MSM_VERSION_MINOR 8 diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 54ca0817d807..af612add5264 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -35,6 +35,9 @@ struct msm_gem_address_space { * will be non-NULL: */ struct pid *pid; + + /* @faults: the number of GPU hangs associated with this address space */ + int faults; }; =20 struct msm_gem_vma { diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 2c1049c0ea14..1029a51cb016 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -372,6 +372,7 @@ static void recover_worker(struct kthread_work *work) /* Increment the fault counts */ gpu->global_faults++; submit->queue->faults++; + submit->aspace->faults++; =20 task =3D get_pid_task(submit->pid, PIDTYPE_PID); if (task) { diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 6b8fffc28a50..b7d92868b945 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -75,8 +75,9 @@ struct drm_msm_timespec { #define MSM_PARAM_GMEM_BASE 0x06 #define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */ #define MSM_PARAM_PP_PGTABLE 0x08 /* =3D> 1 for per-process pagetables, e= lse 0 */ -#define MSM_PARAM_FAULTS 0x09 +#define MSM_PARAM_FAULTS 0x09 /* global fault count */ #define MSM_PARAM_SUSPENDS 0x0a +#define MSM_PARAM_AS_FAULTS 0x0b /* faults in any context sharing same a= ddress space */ =20 /* For backwards compat. The original support for preemption was based on * a single ring per priority level so # of priority levels equals the # --=20 2.34.1