From nobody Tue Jun 30 01:46:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8F83C433F5 for ; Thu, 27 Jan 2022 15:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243211AbiA0Pu2 (ORCPT ); Thu, 27 Jan 2022 10:50:28 -0500 Received: from mail.emtrion.de ([87.139.198.129]:55005 "EHLO mail3.emtrion.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S243190AbiA0Pu0 (ORCPT ); Thu, 27 Jan 2022 10:50:26 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Thu, 27 Jan 2022 10:50:24 EST Received: from emtrion-yocto-comrzn1d.emtrion.local (2003:f9:5824:1:20c:29ff:fe08:43c4) by EMT-KA-S004.emtrion.local (2003:f9:5824:1:c59f:32f4:72e5:b9e1) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.20; Thu, 27 Jan 2022 16:35:19 +0100 From: To: CC: , , , , , , , Subject: [RESEND PATCH v5 1/2] dt-bindings: arm: Add emtrion hardware emCON-MX8M Mini Date: Thu, 27 Jan 2022 16:34:59 +0100 Message-ID: <20220127153500.9236-2-reinhold.mueller@emtrion.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127153500.9236-1-reinhold.mueller@emtrion.com> References: <20220127153500.9236-1-reinhold.mueller@emtrion.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2003:f9:5824:1:20c:29ff:fe08:43c4] X-ClientProxiedBy: EMT-KA-S004.emtrion.local (2003:f9:5824:1:c59f:32f4:72e5:b9e1) To EMT-KA-S004.emtrion.local (2003:f9:5824:1:c59f:32f4:72e5:b9e1) X-C2ProcessedOrg: 5b249fcb-306f-4927-9982-5d11b1d300ce Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Reinhold Mueller This patch presents the yaml patch for the emtrion GmbH emCON-MX8M Mini. Signed-off-by: Reinhold Mueller Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 0b595b26061f..e2c70c87baef 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -723,6 +723,7 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board + - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development = Kit --=20 2.20.1 From nobody Tue Jun 30 01:46:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A48CC433EF for ; Thu, 27 Jan 2022 15:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243225AbiA0Pua (ORCPT ); Thu, 27 Jan 2022 10:50:30 -0500 Received: from mail.emtrion.de ([87.139.198.129]:55005 "EHLO mail3.emtrion.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S242908AbiA0Pu2 (ORCPT ); Thu, 27 Jan 2022 10:50:28 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Thu, 27 Jan 2022 10:50:24 EST Received: from emtrion-yocto-comrzn1d.emtrion.local (2003:f9:5824:1:20c:29ff:fe08:43c4) by EMT-KA-S004.emtrion.local (2003:f9:5824:1:c59f:32f4:72e5:b9e1) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.20; Thu, 27 Jan 2022 16:35:20 +0100 From: To: CC: , , , , , , , Subject: [RESEND PATCH v5 2/2] arm64: dts: imx8mm: Add support for emtrion emCON-MX8M Mini Date: Thu, 27 Jan 2022 16:35:00 +0100 Message-ID: <20220127153500.9236-3-reinhold.mueller@emtrion.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127153500.9236-1-reinhold.mueller@emtrion.com> References: <20220127153500.9236-1-reinhold.mueller@emtrion.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2003:f9:5824:1:20c:29ff:fe08:43c4] X-ClientProxiedBy: EMT-KA-S004.emtrion.local (2003:f9:5824:1:c59f:32f4:72e5:b9e1) To EMT-KA-S004.emtrion.local (2003:f9:5824:1:c59f:32f4:72e5:b9e1) X-C2ProcessedOrg: 5b249fcb-306f-4927-9982-5d11b1d300ce Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Reinhold Mueller This patch adds support for the emtrion GmbH emCON-MX8M Mini modules. They are available with NXP i.MX 8M Mini equipped with 2 or 4 GB Memory. The devicetree imx8mm-emcon.dtsi is the common part providing all module components and the basic support for the SoC. The support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files. Signed-off-by: Reinhold Mueller Reviewed-by: Fabio Estevam --- arch/arm64/boot/dts/freescale/Makefile | 3 +- .../boot/dts/freescale/imx8mm-emcon-avari.dts | 23 + .../dts/freescale/imx8mm-emcon-avari.dtsi | 139 ++++ .../boot/dts/freescale/imx8mm-emcon.dtsi | 627 ++++++++++++++++++ 4 files changed, 791 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index a14a6173b765..a09b5e4d5a45 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -34,8 +34,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-lx2162a-qds.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-beacon-kit.dtb -dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-emcon-avari.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-n801x-s.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts b/arch/ar= m64/boot/dts/freescale/imx8mm-emcon-avari.dts new file mode 100644 index 000000000000..b2e8967e9687 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Frank Erdrich +// + +/dts-v1/; + +#include "imx8mm-emcon.dtsi" +#include "imx8mm-emcon-avari.dtsi" + +/ { + model =3D "emtrion SoM emCON-MX8M mini on Avari"; + compatible =3D "emtrion,emcon-mx8mm-avari", "fsl,imx8mm"; +}; + +&lvds_backlight { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi b/arch/a= rm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi new file mode 100644 index 000000000000..5028f232b6bd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2021 emtrion GmbH +// Author: Frank Erdrich +// + +/ { + aliases { + boardid =3D &boardID; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + }; + + chosen { + stdout-path =3D &uart1; + }; + + reg_wall_5p0: regulator-wall5p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "Main-Supply"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base3p3: regulator-base3p3 { + compatible =3D "regulator-fixed"; + vin-supply =3D <®_wall_5p0>; + regulator-name =3D "3V3-avari"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base1p5: regulator-base1p5 { + compatible =3D "regulator-fixed"; + vin-supply =3D <®_base3p3>; + regulator-name =3D "1V5-avari"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: regulator-otgvbus { + compatible =3D "regulator-fixed"; + vin-supply =3D <®_wall_5p0>; + regulator-name =3D "OTG_VBUS"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + clk_codec: clock-codec { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12000000>; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "SGTL5000-Card"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&sgtl5000>; + }; + }; +}; + +&ecspi1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <100000>; + status =3D "okay"; + + sgtl5000: audio-codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&clk_codec>; + VDDA-supply =3D <®_base3p3>; + VDDIO-supply =3D <®_base3p3>; + }; + + boardID: gpio@3a { + compatible =3D "nxp,pca8574"; + reg =3D <0x3a>; + gpio-controller; + #gpio-cells =3D <1>; + }; +}; + +&sai2 { + status =3D "okay"; +}; + +&uart2 { + uart-has-rtscts; + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +&usbotg1 { + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + status =3D "disabled"; +}; + +&usdhc2 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/b= oot/dts/freescale/imx8mm-emcon.dtsi new file mode 100644 index 000000000000..7c4af71baab9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright 2018 NXP +// Copyright (C) 2021 emtrion GmbH +// + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path =3D &uart1; + }; + + som_leds: leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + green { + label =3D "som:green"; + gpios =3D <&gpio3 4 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + linux,default-trigger =3D "heartbeat"; + }; + + red { + label =3D "som:red"; + gpios =3D <&gpio5 10 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + }; + }; + + lvds_backlight: lvds-backlight { + compatible =3D "pwm-backlight"; + enable-gpios =3D <&gpio3 23 GPIO_ACTIVE_HIGH>; + pwms =3D <&pwm1 0 50000 0>; + brightness-levels =3D < + 0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level =3D <9>; + status =3D "disabled"; + }; + + reg_usdhc1_vmmc: regulator-emmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "eMMC"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "sdcard_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2_reg>; +}; + +&ecspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio5 13 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + }; + }; +}; + +&flexspi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexspi0>; + pinctrl-1 =3D <&pinctrl_flexspi1>; + status =3D "okay"; + + flash0: spi-flash@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + spi-max-frequency =3D <40000000>; + }; +}; + +&iomuxc { + pinctrl-names =3D "default"; + + pinctrl_csi_pwn: csi-pwn-grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1-cs { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0-grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 + >; + }; + + pinctrl_flexspi1: flexspi1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + >; + }; + + pinctrl_gpio_led: gpio-led-grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_lvds: lvds-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06 + >; + }; + + pinctrl_pcie0: pcie0-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41 + >; + }; + + pinctrl_pmic: pmic-irq { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + >; + }; + + pinctrl_spdif1: spdif1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + + /* rts and cts */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpio-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + /* no reset for sdhc2 interface */ + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + bd71847: pmic@4b { + compatible =3D "rohm,bd71847"; + reg =3D <0x4b>; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <2 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <1250>; + rohm,dvs-run-voltage =3D <1000000>; + rohm,dvs-idle-voltage =3D <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name =3D "BUCK3"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <1605000>; + regulator-max-microvolt =3D <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name =3D "LDO6"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + rv1805: rtc@69 { + compatible =3D "abracon,ab1805"; + reg =3D <0x69>; + }; +}; + +&mu { + status =3D "okay"; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm1>; +}; + +&sai2 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + assigned-clocks =3D <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents =3D <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates =3D <12000000>; + status =3D "disabled"; +}; + +&spdif1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spdif1>; + assigned-clocks =3D <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents =3D <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates =3D <24576000>; + clocks =3D <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names =3D "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status =3D "disabled"; +}; + +&uart1 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + assigned-clocks =3D <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL1_80M>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + assigned-clocks =3D <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL1_80M>; + status =3D "okay"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + assigned-clocks =3D <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL1_80M>; + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; + assigned-clocks =3D <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL1_80M>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + over-current-active-low; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + disable-over-current; + status =3D "disabled"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width =3D <8>; + vmmc-supply =3D <®_usdhc1_vmmc>; + keep-power-in-suspend; + non-removable; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios =3D <&gpio2 20 GPIO_ACTIVE_HIGH>; + bus-width =3D <4>; + vmmc-supply =3D <®_usdhc2_vmmc>; + no-1-8-v; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; --=20 2.20.1