From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2A8CC433FE for ; Thu, 27 Jan 2022 01:59:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234846AbiA0B7L (ORCPT ); Wed, 26 Jan 2022 20:59:11 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:47288 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234734AbiA0B7G (ORCPT ); Wed, 26 Jan 2022 20:59:06 -0500 X-UUID: 029557a3844b41de882aae9a7dd40965-20220127 X-UUID: 029557a3844b41de882aae9a7dd40965-20220127 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1442677135; Thu, 27 Jan 2022 09:59:02 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 27 Jan 2022 09:59:00 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:58:59 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 1/9] net: ethernet: mtk-star-emac: store bit_clk_div in compat structure Date: Thu, 27 Jan 2022 09:58:49 +0800 Message-ID: <20220127015857.9868-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Not all the SoC are using the same clock divider. Move the divider into a compat structure specific to the SoCs. Signed-off-by: Biao Huang Signed-off-by: Fabien Parent Reviewed-by: Macpaul Lin --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 1d5dd2015453..7fd8ec0fc636 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -232,6 +233,10 @@ struct mtk_star_ring { unsigned int tail; }; =20 +struct mtk_star_compat { + unsigned char bit_clk_div; +}; + struct mtk_star_priv { struct net_device *ndev; =20 @@ -257,6 +262,8 @@ struct mtk_star_priv { int duplex; int pause; =20 + const struct mtk_star_compat *compat_data; + /* Protects against concurrent descriptor access. */ spinlock_t lock; =20 @@ -899,7 +906,7 @@ static void mtk_star_init_config(struct mtk_star_priv *= priv) regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val); regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF, MTK_STAR_MSK_MAC_CLK_CONF, - MTK_STAR_BIT_CLK_DIV_10); + priv->compat_data->bit_clk_div); } =20 static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) @@ -1461,6 +1468,7 @@ static int mtk_star_probe(struct platform_device *pde= v) =20 priv =3D netdev_priv(ndev); priv->ndev =3D ndev; + priv->compat_data =3D of_device_get_match_data(&pdev->dev); SET_NETDEV_DEV(ndev, dev); platform_set_drvdata(pdev, ndev); =20 @@ -1556,10 +1564,17 @@ static int mtk_star_probe(struct platform_device *p= dev) return devm_register_netdev(dev, ndev); } =20 +static const struct mtk_star_compat mtk_star_mt8516_compat =3D { + .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_10, +}; + static const struct of_device_id mtk_star_of_match[] =3D { - { .compatible =3D "mediatek,mt8516-eth", }, - { .compatible =3D "mediatek,mt8518-eth", }, - { .compatible =3D "mediatek,mt8175-eth", }, + { .compatible =3D "mediatek,mt8516-eth", + .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8518-eth", + .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8175-eth", + .data =3D &mtk_star_mt8516_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48F72C4332F for ; Thu, 27 Jan 2022 01:59:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234818AbiA0B7K (ORCPT ); Wed, 26 Jan 2022 20:59:10 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:41354 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234726AbiA0B7F (ORCPT ); Wed, 26 Jan 2022 20:59:05 -0500 X-UUID: a1b522c76a374cd2a21daa328e31f79a-20220127 X-UUID: a1b522c76a374cd2a21daa328e31f79a-20220127 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1994771345; Thu, 27 Jan 2022 09:59:03 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 27 Jan 2022 09:59:01 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:00 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 2/9] net: ethernet: mtk-star-emac: modify IRQ trigger flags Date: Thu, 27 Jan 2022 09:58:50 +0800 Message-ID: <20220127015857.9868-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the flags in request_irq() is IRQF_TRIGGER_NONE, the trigger method is determined by "interrupt" property in dts. So, modify the flag from IRQF_TRIGGER_FALLING to IRQF_TRIGGER_NONE. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Reviewed-by: Bartosz Golaszewski --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 7fd8ec0fc636..a8fbbbcd185b 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -959,7 +959,7 @@ static int mtk_star_enable(struct net_device *ndev) =20 /* Request the interrupt */ ret =3D request_irq(ndev->irq, mtk_star_handle_irq, - IRQF_TRIGGER_FALLING, ndev->name, ndev); + IRQF_TRIGGER_NONE, ndev->name, ndev); if (ret) goto err_free_skbs; =20 --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19551C4167D for ; Thu, 27 Jan 2022 01:59:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234959AbiA0B7S (ORCPT ); Wed, 26 Jan 2022 20:59:18 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:47366 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234762AbiA0B7I (ORCPT ); Wed, 26 Jan 2022 20:59:08 -0500 X-UUID: 73b44d43192b403691a828cb5ee19fee-20220127 X-UUID: 73b44d43192b403691a828cb5ee19fee-20220127 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 28216442; Thu, 27 Jan 2022 09:59:04 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 27 Jan 2022 09:59:03 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:01 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC Date: Thu, 27 Jan 2022 09:58:51 +0800 Message-ID: <20220127015857.9868-4-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet driver support for MT8365 SoC. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: Fabien Parent Reviewed-by: Macpaul Lin --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++--- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index a8fbbbcd185b..a3884beaa3fe 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -151,6 +151,7 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_STAR_REG_MAC_CLK_CONF 0x00ac #define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0) #define MTK_STAR_BIT_CLK_DIV_10 0x0a +#define MTK_STAR_BIT_CLK_DIV_50 0x32 =20 /* Counter registers. */ #define MTK_STAR_REG_C_RXOKPKT 0x0100 @@ -183,9 +184,11 @@ static const char *const mtk_star_clk_names[] =3D { "c= ore", "reg", "trans" }; #define MTK_STAR_REG_C_RX_TWIST 0x0218 =20 /* Ethernet CFG Control */ -#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4 -#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0) -#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0) +#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4 +#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 +#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 +#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 =20 /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, o= nly @@ -234,6 +237,7 @@ struct mtk_star_ring { }; =20 struct mtk_star_compat { + int (*set_interface_mode)(struct net_device *ndev); unsigned char bit_clk_div; }; =20 @@ -909,13 +913,6 @@ static void mtk_star_init_config(struct mtk_star_priv = *priv) priv->compat_data->bit_clk_div); } =20 -static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) -{ - regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON, - MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII, - MTK_PERICFG_BIT_NIC_CFG_CON_RMII); -} - static int mtk_star_enable(struct net_device *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); @@ -1531,7 +1528,13 @@ static int mtk_star_probe(struct platform_device *pd= ev) return -ENODEV; } =20 - mtk_star_set_mode_rmii(priv); + if (priv->compat_data->set_interface_mode) { + ret =3D priv->compat_data->set_interface_mode(ndev); + if (ret) { + dev_err(dev, "Failed to set phy interface, err =3D %d\n", ret); + return -EINVAL; + } + } =20 ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { @@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *p= dev) return devm_register_netdev(dev, ndev); } =20 +static int mt8516_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv =3D netdev_priv(ndev); + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int intf_val; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG0_CON, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); +} + +static int mt8365_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv =3D netdev_priv(ndev); + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int intf_val; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG_CON_V2, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); +} + static const struct mtk_star_compat mtk_star_mt8516_compat =3D { + .set_interface_mode =3D mt8516_set_interface_mode, .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_10, }; =20 +static const struct mtk_star_compat mtk_star_mt8365_compat =3D { + .set_interface_mode =3D mt8365_set_interface_mode, + .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_50, +}; + static const struct of_device_id mtk_star_of_match[] =3D { { .compatible =3D "mediatek,mt8516-eth", .data =3D &mtk_star_mt8516_compat }, @@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = =3D { .data =3D &mtk_star_mt8516_compat }, { .compatible =3D "mediatek,mt8175-eth", .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8365-eth", + .data =3D &mtk_star_mt8365_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 345D9C433FE for ; Thu, 27 Jan 2022 01:59:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234806AbiA0B7Y (ORCPT ); Wed, 26 Jan 2022 20:59:24 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:41500 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234687AbiA0B7K (ORCPT ); Wed, 26 Jan 2022 20:59:10 -0500 X-UUID: 186c714561cb433a939c0ea94fac20f3-20220127 X-UUID: 186c714561cb433a939c0ea94fac20f3-20220127 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1198502311; Thu, 27 Jan 2022 09:59:05 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 27 Jan 2022 09:59:04 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:03 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 4/9] dt-bindings: net: mtk-star-emac: add support for MT8365 Date: Thu, 27 Jan 2022 09:58:52 +0800 Message-ID: <20220127015857.9868-5-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding document for Ethernet on MT8365. Signed-off-by: Biao Huang Reviewed-by: Bartosz Golaszewski Acked-by: Rob Herring --- Documentation/devicetree/bindings/net/mediatek,star-emac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml = b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml index e6a5ff208253..87a8b25b03a6 100644 --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt8516-eth - mediatek,mt8518-eth - mediatek,mt8175-eth + - mediatek,mt8365-eth =20 reg: maxItems: 1 --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4268FC433FE for ; Thu, 27 Jan 2022 01:59:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235016AbiA0B7V (ORCPT ); Wed, 26 Jan 2022 20:59:21 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:41548 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234786AbiA0B7K (ORCPT ); Wed, 26 Jan 2022 20:59:10 -0500 X-UUID: efa5da12b9f54990af1a8fe571c71682-20220127 X-UUID: efa5da12b9f54990af1a8fe571c71682-20220127 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1421973521; Thu, 27 Jan 2022 09:59:07 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 27 Jan 2022 09:59:05 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:04 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 5/9] net: ethernet: mtk-star-emac: add clock pad selection for RMII Date: Thu, 27 Jan 2022 09:58:53 +0800 Message-ID: <20220127015857.9868-6-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add a new dts property named "mediatek,rmii-rxc" parsing in driver, which will configure MAC to select which pin the RMII reference clock is connected to, TXC or RXC. TXC pad is the default reference clock pin. If user wants to use RXC pad instead, add "mediatek,rmii-rxc" to corresponding device node. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index a3884beaa3fe..d69f75661e75 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -189,6 +189,8 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) =20 /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, o= nly @@ -265,6 +267,7 @@ struct mtk_star_priv { int speed; int duplex; int pause; + bool rmii_rxc; =20 const struct mtk_star_compat *compat_data; =20 @@ -1528,6 +1531,8 @@ static int mtk_star_probe(struct platform_device *pde= v) return -ENODEV; } =20 + priv->rmii_rxc =3D of_property_read_bool(of_node, "mediatek,rmii-rxc"); + if (priv->compat_data->set_interface_mode) { ret =3D priv->compat_data->set_interface_mode(ndev); if (ret) { @@ -1571,17 +1576,25 @@ static int mt8516_set_interface_mode(struct net_dev= ice *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); struct device *dev =3D mtk_star_get_dev(priv); - unsigned int intf_val; + unsigned int intf_val, ret, rmii_rxc; =20 switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + rmii_rxc =3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; break; default: dev_err(dev, "This interface not supported\n"); return -EINVAL; } =20 + ret =3D regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG1_CON, + MTK_PERICFG_BIT_NIC_CFG_CON_CLK, + rmii_rxc); + if (ret) + return ret; + return regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG0_CON, MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, @@ -1597,6 +1610,7 @@ static int mt8365_set_interface_mode(struct net_devic= e *ndev) switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + intf_val |=3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; break; default: dev_err(dev, "This interface not supported\n"); @@ -1605,7 +1619,8 @@ static int mt8365_set_interface_mode(struct net_devic= e *ndev) =20 return regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON_V2, - MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF | + MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2, intf_val); } =20 --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8A9CC433F5 for ; Thu, 27 Jan 2022 01:59:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234881AbiA0B71 (ORCPT ); Wed, 26 Jan 2022 20:59:27 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:47510 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234831AbiA0B7M (ORCPT ); Wed, 26 Jan 2022 20:59:12 -0500 X-UUID: ce175f520511464798346547ed2f56e7-20220127 X-UUID: ce175f520511464798346547ed2f56e7-20220127 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 652676736; Thu, 27 Jan 2022 09:59:08 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 27 Jan 2022 09:59:06 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:05 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 6/9] net: ethernet: mtk-star-emac: add timing adjustment support Date: Thu, 27 Jan 2022 09:58:54 +0800 Message-ID: <20220127015857.9868-7-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add simple clock inversion for timing adjustment in driver. Add property "mediatek,txc-inverse" or "mediatek,rxc-inverse" to device node when necessary. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index d69f75661e75..d5e974e0db6d 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -131,6 +131,11 @@ static const char *const mtk_star_clk_names[] =3D { "c= ore", "reg", "trans" }; #define MTK_STAR_REG_INT_MASK 0x0054 #define MTK_STAR_BIT_INT_MASK_FNRC BIT(6) =20 +/* Delay-Macro Register */ +#define MTK_STAR_REG_TEST0 0x0058 +#define MTK_STAR_BIT_INV_RX_CLK BIT(30) +#define MTK_STAR_BIT_INV_TX_CLK BIT(31) + /* Misc. Config Register */ #define MTK_STAR_REG_TEST1 0x005c #define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31) @@ -268,6 +273,8 @@ struct mtk_star_priv { int duplex; int pause; bool rmii_rxc; + bool rx_inv; + bool tx_inv; =20 const struct mtk_star_compat *compat_data; =20 @@ -1450,6 +1457,25 @@ static void mtk_star_clk_disable_unprepare(void *dat= a) clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); } =20 +static int mtk_star_set_timing(struct mtk_star_priv *priv) +{ + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int delay_val =3D 0; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); + delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val); + + return 0; +} static int mtk_star_probe(struct platform_device *pdev) { struct device_node *of_node; @@ -1532,6 +1558,8 @@ static int mtk_star_probe(struct platform_device *pde= v) } =20 priv->rmii_rxc =3D of_property_read_bool(of_node, "mediatek,rmii-rxc"); + priv->rx_inv =3D of_property_read_bool(of_node, "mediatek,rxc-inverse"); + priv->tx_inv =3D of_property_read_bool(of_node, "mediatek,txc-inverse"); =20 if (priv->compat_data->set_interface_mode) { ret =3D priv->compat_data->set_interface_mode(ndev); @@ -1541,6 +1569,12 @@ static int mtk_star_probe(struct platform_device *pd= ev) } } =20 + ret =3D mtk_star_set_timing(priv); + if (ret) { + dev_err(dev, "Failed to set timing, err =3D %d\n", ret); + return -EINVAL; + } + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { dev_err(dev, "unsupported DMA mask\n"); --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B76ABC433F5 for ; Thu, 27 Jan 2022 01:59:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235037AbiA0B7e (ORCPT ); Wed, 26 Jan 2022 20:59:34 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:47472 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234764AbiA0B7K (ORCPT ); Wed, 26 Jan 2022 20:59:10 -0500 X-UUID: eb86f13d169746a69ed4f6e86e4a64ce-20220127 X-UUID: eb86f13d169746a69ed4f6e86e4a64ce-20220127 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 299950623; Thu, 27 Jan 2022 09:59:09 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 27 Jan 2022 09:59:07 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:06 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 7/9] dt-bindings: net: mtk-star-emac: add description for new properties Date: Thu, 27 Jan 2022 09:58:55 +0800 Message-ID: <20220127015857.9868-8-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add description for new properties which will be parsed in driver. Signed-off-by: Biao Huang --- .../bindings/net/mediatek,star-emac.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml = b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml index 87a8b25b03a6..41b1b1dd562c 100644 --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml @@ -48,6 +48,22 @@ properties: Phandle to the device containing the PERICFG register range. This is= used to control the MII mode. =20 + mediatek,rmii-rxc: + type: boolean + description: + If present, indicates that the RMII reference clock, which is from e= xternal + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. + + mediatek,rxc-inverse: + type: boolean + description: + If present, indicates that clock on RXC pad will be inversed. + + mediatek,txc-inverse: + type: boolean + description: + If present, indicates that clock on TXC pad will be inversed. + mdio: type: object description: --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FA5AC433FE for ; Thu, 27 Jan 2022 01:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234902AbiA0B73 (ORCPT ); Wed, 26 Jan 2022 20:59:29 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:41698 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234871AbiA0B7O (ORCPT ); Wed, 26 Jan 2022 20:59:14 -0500 X-UUID: f2440afa94ab4dbdb97b1d034aabda0d-20220127 X-UUID: f2440afa94ab4dbdb97b1d034aabda0d-20220127 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 259980265; Thu, 27 Jan 2022 09:59:10 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 27 Jan 2022 09:59:09 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:08 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 8/9] net: ethernet: mtk-star-emac: add support for MII interface Date: Thu, 27 Jan 2022 09:58:56 +0800 Message-ID: <20220127015857.9868-9-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for MII interface. If user wants to use MII, assign "MII" to "phy-mode" property in dts. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index d5e974e0db6d..167a019fd8f5 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -193,6 +193,7 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_MII 0 #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 #define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) #define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) @@ -1463,6 +1464,7 @@ static int mtk_star_set_timing(struct mtk_star_priv *= priv) unsigned int delay_val =3D 0; =20 switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_RMII: delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); @@ -1545,7 +1547,8 @@ static int mtk_star_probe(struct platform_device *pde= v) ret =3D of_get_phy_mode(of_node, &priv->phy_intf); if (ret) { return ret; - } else if (priv->phy_intf !=3D PHY_INTERFACE_MODE_RMII) { + } else if (priv->phy_intf !=3D PHY_INTERFACE_MODE_RMII && + priv->phy_intf !=3D PHY_INTERFACE_MODE_MII) { dev_err(dev, "unsupported phy mode: %s\n", phy_modes(priv->phy_intf)); return -EINVAL; @@ -1610,9 +1613,12 @@ static int mt8516_set_interface_mode(struct net_devi= ce *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); struct device *dev =3D mtk_star_get_dev(priv); - unsigned int intf_val, ret, rmii_rxc; + unsigned int intf_val, ret, rmii_rxc =3D 0; =20 switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_MII; + break; case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; rmii_rxc =3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; @@ -1642,6 +1648,9 @@ static int mt8365_set_interface_mode(struct net_devic= e *ndev) unsigned int intf_val; =20 switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_MII; + break; case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; intf_val |=3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; --=20 2.25.1 From nobody Sun Sep 22 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98AAEC433F5 for ; Thu, 27 Jan 2022 01:59:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234804AbiA0B7b (ORCPT ); Wed, 26 Jan 2022 20:59:31 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:47610 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234884AbiA0B7P (ORCPT ); Wed, 26 Jan 2022 20:59:15 -0500 X-UUID: 7f7c1dd9e9a04fa3a135138c70f32705-20220127 X-UUID: 7f7c1dd9e9a04fa3a135138c70f32705-20220127 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1475301584; Thu, 27 Jan 2022 09:59:12 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 27 Jan 2022 09:59:10 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:59:09 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 9/9] net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs Date: Thu, 27 Jan 2022 09:58:57 +0800 Message-ID: <20220127015857.9868-10-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current driver may lost tx interrupts under bidirectional test with iperf3, which leads to some unexpected issues. This patch let rx/tx interrupt enable/disable separately, and rx/tx are handled in different NAPIs. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 317 ++++++++++-------- 1 file changed, 181 insertions(+), 136 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 167a019fd8f5..e5bcf851511a 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -229,7 +229,7 @@ struct mtk_star_ring_desc_data { struct sk_buff *skb; }; =20 -#define MTK_STAR_RING_NUM_DESCS 128 +#define MTK_STAR_RING_NUM_DESCS 512 #define MTK_STAR_NUM_TX_DESCS MTK_STAR_RING_NUM_DESCS #define MTK_STAR_NUM_RX_DESCS MTK_STAR_RING_NUM_DESCS #define MTK_STAR_NUM_DESCS_TOTAL (MTK_STAR_RING_NUM_DESCS * 2) @@ -264,7 +264,8 @@ struct mtk_star_priv { struct mtk_star_ring rx_ring; =20 struct mii_bus *mii; - struct napi_struct napi; + struct napi_struct tx_napi; + struct napi_struct rx_napi; =20 struct device_node *phy_node; phy_interface_t phy_intf; @@ -380,19 +381,16 @@ mtk_star_ring_push_head_tx(struct mtk_star_ring *ring, mtk_star_ring_push_head(ring, desc_data, flags); } =20 -static unsigned int mtk_star_ring_num_used_descs(struct mtk_star_ring *rin= g) +static unsigned int mtk_star_tx_ring_avail(struct mtk_star_ring *ring) { - return abs(ring->head - ring->tail); -} + u32 avail; =20 -static bool mtk_star_ring_full(struct mtk_star_ring *ring) -{ - return mtk_star_ring_num_used_descs(ring) =3D=3D MTK_STAR_RING_NUM_DESCS; -} + if (ring->tail > ring->head) + avail =3D ring->tail - ring->head - 1; + else + avail =3D MTK_STAR_RING_NUM_DESCS - ring->head + ring->tail - 1; =20 -static bool mtk_star_ring_descs_available(struct mtk_star_ring *ring) -{ - return mtk_star_ring_num_used_descs(ring) > 0; + return avail; } =20 static dma_addr_t mtk_star_dma_map_rx(struct mtk_star_priv *priv, @@ -415,7 +413,7 @@ static void mtk_star_dma_unmap_rx(struct mtk_star_priv = *priv, } =20 static dma_addr_t mtk_star_dma_map_tx(struct mtk_star_priv *priv, - struct sk_buff *skb) + struct sk_buff *skb) { struct device *dev =3D mtk_star_get_dev(priv); =20 @@ -437,6 +435,36 @@ static void mtk_star_nic_disable_pd(struct mtk_star_pr= iv *priv) MTK_STAR_BIT_MAC_CFG_NIC_PD); } =20 +static void mtk_star_enable_dma_irq(struct mtk_star_priv *priv, + bool rx, bool tx) +{ + u32 value; + + regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); + + if (tx) + value &=3D ~MTK_STAR_BIT_INT_STS_TNTC; + if (rx) + value &=3D ~MTK_STAR_BIT_INT_STS_FNRC; + + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); +} + +static void mtk_star_disable_dma_irq(struct mtk_star_priv *priv, + bool rx, bool tx) +{ + u32 value; + + regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); + + if (tx) + value |=3D MTK_STAR_BIT_INT_STS_TNTC; + if (rx) + value |=3D MTK_STAR_BIT_INT_STS_FNRC; + + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); +} + /* Unmask the three interrupts we care about, mask all others. */ static void mtk_star_intr_enable(struct mtk_star_priv *priv) { @@ -452,20 +480,11 @@ static void mtk_star_intr_disable(struct mtk_star_pri= v *priv) regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~0); } =20 -static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv) -{ - unsigned int val; - - regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); - - return val; -} - static unsigned int mtk_star_intr_ack_all(struct mtk_star_priv *priv) { unsigned int val; =20 - val =3D mtk_star_intr_read(priv); + regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); regmap_write(priv->regs, MTK_STAR_REG_INT_STS, val); =20 return val; @@ -737,25 +756,46 @@ static void mtk_star_free_tx_skbs(struct mtk_star_pri= v *priv) mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_tx); } =20 -/* All processing for TX and RX happens in the napi poll callback. - * - * FIXME: The interrupt handling should be more fine-grained with each - * interrupt enabled/disabled independently when needed. Unfortunatly this - * turned out to impact the driver's stability and until we have something - * working properly, we're disabling all interrupts during TX & RX process= ing - * or when resetting the counter registers. +/* mtk_star_handle_irq - Interrupt Handler. + * @irq: interrupt number. + * @data: pointer to a network interface device structure. + * Description : this is the driver interrupt service routine. + * it mainly handles: + * 1. tx complete interrupt for frame transmission. + * 2. rx complete interrupt for frame reception. + * 3. MAC Management Counter interrupt to avoid counter overflow. */ static irqreturn_t mtk_star_handle_irq(int irq, void *data) { - struct mtk_star_priv *priv; - struct net_device *ndev; + struct net_device *ndev =3D data; + struct mtk_star_priv *priv =3D netdev_priv(ndev); + unsigned int intr_status =3D mtk_star_intr_ack_all(priv); + unsigned long flags =3D 0; + + if (intr_status & MTK_STAR_BIT_INT_STS_FNRC) { + if (napi_schedule_prep(&priv->rx_napi)) { + spin_lock_irqsave(&priv->lock, flags); + /* mask Rx Complete interrupt */ + mtk_star_disable_dma_irq(priv, true, false); + spin_unlock_irqrestore(&priv->lock, flags); + __napi_schedule_irqoff(&priv->rx_napi); + } + } =20 - ndev =3D data; - priv =3D netdev_priv(ndev); + if (intr_status & MTK_STAR_BIT_INT_STS_TNTC) { + if (napi_schedule_prep(&priv->tx_napi)) { + spin_lock_irqsave(&priv->lock, flags); + /* mask Tx Complete interrupt */ + mtk_star_disable_dma_irq(priv, false, true); + spin_unlock_irqrestore(&priv->lock, flags); + __napi_schedule_irqoff(&priv->tx_napi); + } + } =20 - if (netif_running(ndev)) { - mtk_star_intr_disable(priv); - napi_schedule(&priv->napi); + /* interrupt is triggered once any counters reach 0x8000000 */ + if (intr_status & MTK_STAR_REG_INT_STS_MIB_CNT_TH) { + mtk_star_update_stats(priv); + mtk_star_reset_counters(priv); } =20 return IRQ_HANDLED; @@ -971,7 +1011,8 @@ static int mtk_star_enable(struct net_device *ndev) if (ret) goto err_free_skbs; =20 - napi_enable(&priv->napi); + napi_enable(&priv->tx_napi); + napi_enable(&priv->rx_napi); =20 mtk_star_intr_ack_all(priv); mtk_star_intr_enable(priv); @@ -1004,7 +1045,8 @@ static void mtk_star_disable(struct net_device *ndev) struct mtk_star_priv *priv =3D netdev_priv(ndev); =20 netif_stop_queue(ndev); - napi_disable(&priv->napi); + napi_disable(&priv->tx_napi); + napi_disable(&priv->rx_napi); mtk_star_intr_disable(priv); mtk_star_dma_disable(priv); mtk_star_intr_ack_all(priv); @@ -1043,6 +1085,17 @@ static int mtk_star_netdev_start_xmit(struct sk_buff= *skb, struct mtk_star_ring *ring =3D &priv->tx_ring; struct device *dev =3D mtk_star_get_dev(priv); struct mtk_star_ring_desc_data desc_data; + int nfrags =3D skb_shinfo(skb)->nr_frags; + + if (unlikely(mtk_star_tx_ring_avail(ring) < nfrags + 1)) { + if (!netif_queue_stopped(ndev)) { + netif_stop_queue(ndev); + /* This is a hard error, log it. */ + netdev_err(priv->ndev, "%s: Tx Ring full when queue awake\n", + __func__); + } + return NETDEV_TX_BUSY; + } =20 desc_data.dma_addr =3D mtk_star_dma_map_tx(priv, skb); if (dma_mapping_error(dev, desc_data.dma_addr)) @@ -1050,18 +1103,10 @@ static int mtk_star_netdev_start_xmit(struct sk_buf= f *skb, =20 desc_data.skb =3D skb; desc_data.len =3D skb->len; - - spin_lock_bh(&priv->lock); - mtk_star_ring_push_head_tx(ring, &desc_data); =20 netdev_sent_queue(ndev, skb->len); =20 - if (mtk_star_ring_full(ring)) - netif_stop_queue(ndev); - - spin_unlock_bh(&priv->lock); - mtk_star_dma_resume_tx(priv); =20 return NETDEV_TX_OK; @@ -1092,23 +1137,31 @@ static int mtk_star_tx_complete_one(struct mtk_star= _priv *priv) return ret; } =20 -static void mtk_star_tx_complete_all(struct mtk_star_priv *priv) +static int mtk_star_tx_poll(struct napi_struct *napi, int budget) { - struct mtk_star_ring *ring =3D &priv->tx_ring; - struct net_device *ndev =3D priv->ndev; - int ret, pkts_compl, bytes_compl; + int ret, pkts_compl =3D 0, bytes_compl =3D 0, count =3D 0; + struct mtk_star_priv *priv; + struct mtk_star_ring *ring; + struct net_device *ndev; + unsigned long flags =3D 0; + unsigned int entry; bool wake =3D false; =20 - spin_lock(&priv->lock); + priv =3D container_of(napi, struct mtk_star_priv, tx_napi); + ndev =3D priv->ndev; =20 - for (pkts_compl =3D 0, bytes_compl =3D 0;; + __netif_tx_lock_bh(netdev_get_tx_queue(priv->ndev, 0)); + ring =3D &priv->tx_ring; + entry =3D ring->tail; + for (pkts_compl =3D 0, bytes_compl =3D 0; + (entry !=3D ring->head) && (count < budget); pkts_compl++, bytes_compl +=3D ret, wake =3D true) { - if (!mtk_star_ring_descs_available(ring)) - break; =20 ret =3D mtk_star_tx_complete_one(priv); if (ret < 0) break; + count++; + entry =3D ring->tail; } =20 netdev_completed_queue(ndev, pkts_compl, bytes_compl); @@ -1116,7 +1169,16 @@ static void mtk_star_tx_complete_all(struct mtk_star= _priv *priv) if (wake && netif_queue_stopped(ndev)) netif_wake_queue(ndev); =20 - spin_unlock(&priv->lock); + __netif_tx_unlock_bh(netdev_get_tx_queue(priv->ndev, 0)); + + count =3D min(count, budget); + if (count < budget && napi_complete_done(napi, count)) { + spin_lock_irqsave(&priv->lock, flags); + mtk_star_enable_dma_irq(priv, false, true); + spin_unlock_irqrestore(&priv->lock, flags); + } + + return count; } =20 static void mtk_star_netdev_get_stats64(struct net_device *ndev, @@ -1196,7 +1258,7 @@ static const struct ethtool_ops mtk_star_ethtool_ops = =3D { .set_link_ksettings =3D phy_ethtool_set_link_ksettings, }; =20 -static int mtk_star_receive_packet(struct mtk_star_priv *priv) +static int mtk_star_rx(struct mtk_star_priv *priv, int budget) { struct mtk_star_ring *ring =3D &priv->rx_ring; struct device *dev =3D mtk_star_get_dev(priv); @@ -1204,107 +1266,86 @@ static int mtk_star_receive_packet(struct mtk_star= _priv *priv) struct net_device *ndev =3D priv->ndev; struct sk_buff *curr_skb, *new_skb; dma_addr_t new_dma_addr; - int ret; + int ret, count =3D 0; =20 - spin_lock(&priv->lock); - ret =3D mtk_star_ring_pop_tail(ring, &desc_data); - spin_unlock(&priv->lock); - if (ret) - return -1; + while (count < budget) { + ret =3D mtk_star_ring_pop_tail(ring, &desc_data); + if (ret) + return -1; =20 - curr_skb =3D desc_data.skb; + curr_skb =3D desc_data.skb; =20 - if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || - (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { - /* Error packet -> drop and reuse skb. */ - new_skb =3D curr_skb; - goto push_new_skb; - } + if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || + (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { + /* Error packet -> drop and reuse skb. */ + new_skb =3D curr_skb; + goto push_new_skb; + } =20 - /* Prepare new skb before receiving the current one. Reuse the current - * skb if we fail at any point. - */ - new_skb =3D mtk_star_alloc_skb(ndev); - if (!new_skb) { - ndev->stats.rx_dropped++; - new_skb =3D curr_skb; - goto push_new_skb; - } + /* Prepare new skb before receiving the current one. + * Reuse the current skb if we fail at any point. + */ + new_skb =3D mtk_star_alloc_skb(ndev); + if (!new_skb) { + ndev->stats.rx_dropped++; + new_skb =3D curr_skb; + goto push_new_skb; + } =20 - new_dma_addr =3D mtk_star_dma_map_rx(priv, new_skb); - if (dma_mapping_error(dev, new_dma_addr)) { - ndev->stats.rx_dropped++; - dev_kfree_skb(new_skb); - new_skb =3D curr_skb; - netdev_err(ndev, "DMA mapping error of RX descriptor\n"); - goto push_new_skb; - } + new_dma_addr =3D mtk_star_dma_map_rx(priv, new_skb); + if (dma_mapping_error(dev, new_dma_addr)) { + ndev->stats.rx_dropped++; + dev_kfree_skb(new_skb); + new_skb =3D curr_skb; + netdev_err(ndev, "DMA mapping error of RX descriptor\n"); + goto push_new_skb; + } =20 - /* We can't fail anymore at this point: it's safe to unmap the skb. */ - mtk_star_dma_unmap_rx(priv, &desc_data); + /* We can't fail anymore at this point: + * it's safe to unmap the skb. + */ + mtk_star_dma_unmap_rx(priv, &desc_data); =20 - skb_put(desc_data.skb, desc_data.len); - desc_data.skb->ip_summed =3D CHECKSUM_NONE; - desc_data.skb->protocol =3D eth_type_trans(desc_data.skb, ndev); - desc_data.skb->dev =3D ndev; - netif_receive_skb(desc_data.skb); + skb_put(desc_data.skb, desc_data.len); + desc_data.skb->ip_summed =3D CHECKSUM_NONE; + desc_data.skb->protocol =3D eth_type_trans(desc_data.skb, ndev); + desc_data.skb->dev =3D ndev; + netif_receive_skb(desc_data.skb); =20 - /* update dma_addr for new skb */ - desc_data.dma_addr =3D new_dma_addr; + /* update dma_addr for new skb */ + desc_data.dma_addr =3D new_dma_addr; =20 push_new_skb: - desc_data.len =3D skb_tailroom(new_skb); - desc_data.skb =3D new_skb; - - spin_lock(&priv->lock); - mtk_star_ring_push_head_rx(ring, &desc_data); - spin_unlock(&priv->lock); - - return 0; -} =20 -static int mtk_star_process_rx(struct mtk_star_priv *priv, int budget) -{ - int received, ret; + count++; =20 - for (received =3D 0, ret =3D 0; received < budget && ret =3D=3D 0; receiv= ed++) - ret =3D mtk_star_receive_packet(priv); + desc_data.len =3D skb_tailroom(new_skb); + desc_data.skb =3D new_skb; + mtk_star_ring_push_head_rx(ring, &desc_data); + } =20 mtk_star_dma_resume_rx(priv); =20 - return received; + return count; } =20 -static int mtk_star_poll(struct napi_struct *napi, int budget) +static int mtk_star_rx_poll(struct napi_struct *napi, int budget) { struct mtk_star_priv *priv; - unsigned int status; - int received =3D 0; + unsigned long flags =3D 0; + int work_done =3D 0; =20 - priv =3D container_of(napi, struct mtk_star_priv, napi); + priv =3D container_of(napi, struct mtk_star_priv, rx_napi); =20 - status =3D mtk_star_intr_read(priv); - mtk_star_intr_ack_all(priv); - - if (status & MTK_STAR_BIT_INT_STS_TNTC) - /* Clean-up all TX descriptors. */ - mtk_star_tx_complete_all(priv); - - if (status & MTK_STAR_BIT_INT_STS_FNRC) - /* Receive up to $budget packets. */ - received =3D mtk_star_process_rx(priv, budget); - - if (unlikely(status & MTK_STAR_REG_INT_STS_MIB_CNT_TH)) { - mtk_star_update_stats(priv); - mtk_star_reset_counters(priv); + work_done =3D mtk_star_rx(priv, budget); + if (work_done < budget) { + napi_complete_done(napi, work_done); + spin_lock_irqsave(&priv->lock, flags); + mtk_star_enable_dma_irq(priv, true, false); + spin_unlock_irqrestore(&priv->lock, flags); } =20 - if (received < budget) - napi_complete_done(napi, received); - - mtk_star_intr_enable(priv); - - return received; + return work_done; } =20 static void mtk_star_mdio_rwok_clear(struct mtk_star_priv *priv) @@ -1478,6 +1519,7 @@ static int mtk_star_set_timing(struct mtk_star_priv *= priv) =20 return 0; } + static int mtk_star_probe(struct platform_device *pdev) { struct device_node *of_node; @@ -1604,7 +1646,10 @@ static int mtk_star_probe(struct platform_device *pd= ev) ndev->netdev_ops =3D &mtk_star_netdev_ops; ndev->ethtool_ops =3D &mtk_star_ethtool_ops; =20 - netif_napi_add(ndev, &priv->napi, mtk_star_poll, MTK_STAR_NAPI_WEIGHT); + netif_napi_add(ndev, &priv->rx_napi, + mtk_star_rx_poll, MTK_STAR_NAPI_WEIGHT); + netif_tx_napi_add(ndev, &priv->tx_napi, + mtk_star_tx_poll, MTK_STAR_NAPI_WEIGHT); =20 return devm_register_netdev(dev, ndev); } --=20 2.25.1